FPGA BASED VGA DRIVER AND ARCADE GAME

ARMANDAS JARUSAUSKAS THIRD YEAR INDIVIDUAL PROJECT 2009/2010

SCHOOL OF ENGINEERING & DESIGN UNIVERSITY OF SUSSEX

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Abstract
Field-Programmable Gate-Array (FPGA) technology is gaining popularity among Application-Specific Integrated Circuit (ASIC) designers. Ease of development and maintenance makes FPGAs an attractive solution to many speed and efficiency-critical applications. The purpose of this project is to explore the world of FPGAs by implementing an arcade game on top of a VGA driver. The project was implemented on Xilinx Spartan-3E development board using VHDL hardware description language. The project was started by learning VHDL as well as familiarising with the Spartan-3E development board and Xilinx ISE WebPACK design software. A number of simple applications were developed in order to comfortably proceed on to investigation of working principles of a VGA driver. It turned out that the synchronisation logic was rather trivial and that the custom implementation would not add much value to the project. VHDL implementation of the classic Pong game was the first major task of the project. Plong, as it was named, is a two-player game, where each player tries to to hit a ball towards the opponent. A number of basic features, such as acceleration of the ball, sound output and textual information display, have been implemented. As this game was developed in the early stage of the project, complexity was consciously avoided. The objectives the second game, on the other hand, were focused on technical features and other improvements. Still monochrome images were exchanged for colourful animations, sound output was made more sophisticated by adding a tune player, Nintendo game pads replaced on-board switches as a user input interface and a number of other modules were developed. The theme was chosen to resemble the Space Invaders game, but all graphic elements were designed from scratch. To make the project more complete and self contained, the two games were combined into a single application, with a menu screen to allow user to choose which game to play. Lastly, an adaptor board, for connecting NES game pads to the development board, was designed and built. It facilitates the communication between the controllers and the FPGA. The board also hosts a piezoelectric buzzer for sound output and a reset switch. The project was complete and fully functional before the deadline. While there is still a lot of room for improvement, all set objectives, and more, were met.

or which have been accepted for the award of any degree or diploma at any educational institution. . except where due acknowledgement is made in the report itself.Statement of originality I hereby declare that this report is my own work and to the best of my knowledge it contains no materials previously published or written by another person.

. for his excellent work on a plastic case for my adaptor board. Sam Beardsmore-Rust for general support and help with project proposal. Martin Nock for help with PCB manufacture. from the mechanical workshop.Acknowledgements First supervisor: Dr Ahmet Aydin Second supervisor: Dr Christopher Harland I would like to thank the following people for all the help and support: • • • • • Ahmet Aydin for his time and support during the project and for letting me borrow the FPGA development board. David Smith. Philip Watson for 100-pin connector design files and other help.

.................................................................................................................................. 10 2........................................... 12 3 IMPLEMENTATION 13 3................................................................................................................. 14 3...................................... 11 2..16 3........................................................... 12 Objects ........................................................................................................4 Text generation ................ 14 Storing images ............................................. 9 1............................................ 12 Logic blocks ........................................................ 16 Colour image storage .............3 Development board ..............................................................................................................2 Hardware description languages ............................ 14 Code ........................................................ 10 VHDL .....................................................................................................................................................................................4 VGA .................1 About this report.............................17 ........................................................................................................................................................................................................................................... 15 Getting the pixels .. 9 Xilinx versus Altera.............................................................................................................................................................................................................................. 10 Digital systems theory ......................................................................................................................................................................................................................................................................................................................................Table of Contents 1 INTRODUCTION 9 1...... 13 Code .........................................................................10 Other HDLs ................ 17 3.................................................................................................................................................................................2 Project aims and plan ............................................................................................................................................. 9 2 BACKGROUND 9 2........................................................................................................................................ 17 Font .........................................................................................................1 Field-Programmable Gate Arrays .... 13 3..............17 Grid .................................... 9 2....1 VGA ....................................................................................................................................................2 NES controller interface ..................................................................................................................................... 17 Theory ............................................................................ 15 Moving images ............................................................................................................................................14 Results...............................................................................................................................................................................................................................................................13 Results.........................................................................................................................................................................5 Nintendo controllers . 12 2.......3 Graphics .................5 Binary to BCD conversion ........................................................................................................................................................................................... 10 2........ 11 Hardware ................................................6 Principles of game implementation ...........................11 Timing ..

............... 23 7 ADAPTOR BOARD 23 7....................................................................................................................................24 Manufacture .20 Ball logic .1 Structure ...............................................................................................................................................................................................................................................................................................................................................................................................................24 Shift register to FPGA ...3 Board design.................1 Game selection menu .....................................................................2 Graphics ........................................ 21 5 SPACE SHOOTER 21 5...................................................19 Paddle logic.........................................22 Spaceship and missile ..................................... 24 FPGA to Shift register.. 24 7.............. 23 6..................................... 24 PCB layout design ....................... 22 Main logic .............................................................................................................................................................................................1 Reverse engineering the controllers .................................................................................20 4........................................ 24 8 DISCUSSION 25 ................................................................................................................................................................................................................................... 23 7......................................................................................................................................................................................................................................................18 Sound ROM.................................................3 Sounds & User input .....................................................................................................20 Scores...2 Combining the applications............................................................................................................ 23 6 COMPLETING THE PROJECT 23 6........... 19 4................................................ 19 Main logic .......................................................................................................................................................................................................................6 Sound ................................................................... 21 5................... 22 Explosion logic ......................................................1 Gameplay ..................................................................................................................................................................................................................................2 Graphics ............................................................................................................................................................................... 18 Frequency generator ...........................................................................................................................................................18 3......................... 18 Player .................................22 Aliens ......................... 24 Schematic capture...........................................VHDL implementation ...................................................................................................................................................................................................................................................................2 TTL / CMOS level conversion ....................................................21 User input .................................... 21 Sounds ....................................................18 4 PONG 19 4............................................................................................................................................................................................................................22 Score and level display..................................

....................... 31 APPENDIX E 32 Python script for generating VHDL ROM from images ..2 Further work ........................................................................................................................................................................................... 26 8........................................................... 32 APPENDIX F 33 Adaptor board schematic diagram ............................................... 30 APPENDIX D 31 NES Controller: equivalent schematic diagram ................................ 25 Synchronisation problems ............................................ 29 APPENDIX C 30 Project plan .................................................................................................................1 Issues .................................................................................... 26 Binary-to-BCD conversion ................................................................... 25 Adaptor board ............................................................................................................................................................................................................................................................................................... 26 9 CONCLUSION REFERENCES BIBLIOGRAPHY APPENDIX A 26 27 27 28 Initial technical proposal ............. 34 APPENDIX H 35 Photographs ...................8............................................................................................................................................................................... 33 APPENDIX G 34 Adaptor board PCB: top and bottom layer masks ..........................28 APPENDIX B 29 Project parts list.. 35 ....................... 25 Pong ball acceleration............................................................................................................................................

Block RAM – memory used for data storage. with Altera being a close second. Xilinx is a current market share leader.vhd It is a pointer to a relative source file. An introduction to core concepts relating to the project is given in Chapter 2 section. that uses a VGA driver to display graphics on a computer monitor. Spartan-3E series FPGAs. • • • A plan. The report is accompanied by a printed VHDL code listing and a Compact Disc. you will see notes like this: Project . This report covers the work done during the course of the project. a number of objectives were set. Chapter 3 describes how the main building blocks. as described in [1]: • Configurable Logic Block – logic and basic storage elements are implemented using the Look-UP Tables (LUTs).1 About this report and milestones was created to give a rough estimate of duration of each part of the project. Create a more advanced game. therefore. Create a simple game. 2 BACKGROUND 2. • • 1. that can be used as logic or storage elements.1 Field-Programmable Gate Arrays FPGAs are modern programmable logic devices that can be configured to perform any logic operation. overall price. is the amended list of objectives. including this report. existence of Intellectual Property (IP) cores and educational material and so forth. 5 and 6 go into game-specific details. Design of an adaptor board. The decision which one to choose should not be based on the architectural differences of the two technologies. • • Learn about FPGAs. with objectives 9 . used in this project contain the following structures. LVTTL and LVCMOS logic standards are supported among others. CLBs contain Look-Up Tables (LUTs). available in Appendix B. The CD contains all the relevant material in digital format. Below.2 Project aims and plan • The aim of this project was to explore the capabilities of modern programmable logic devices while getting hands-on experience of FPGA development. The initial technical proposal can be found in Appendix A. scanned version of engineering logbook and more. For this purpose.filename. It may be helpful. Xilinx Spartan-3E development boards were readily available at the university and.FPGA BASED VGA DRIVER AND ARCADE GAME 1 INTRODUCTION 1. Organized as 18kb dual-port blocks. The above definition is rather abstract and can be hard to assess. Report is finished by discussing some of the issues experienced during the project. while Chapters 4. Throughout the report. Design some hardware. Xilinx technology was used for this project's implementation. used to create a game. Produce a simple application. development tools and VHDL. Digital clock manager block – provides management for clock signals. Configurable Logic Blocks (CLBs). also known as. were developed. if one needs to see the implementation details. development tools. is described in Chapter 7. start programming. connecting game pads to the development board. The configuration data is stored in the memory. such as device availability. and Conclusion. An FPGA typically contains a matrix of programmable elements. VHDL code. There are many more important aspects. Input/Output Block (IOB) – control the data flow between the I/O pins and internal logic of the device. Xilinx versus Altera There are two major manufacturers in the programmable logic business – Xilinx and Altera.

According to Wakerly [3]. enumerated lists. such as C++. It arose out of the United States government's Very High Speed Integrated Circuit (VHSIC) program. there are two predominant hardware description languages – VHDL and Verilog. A maximum of 232 I/O pins. run in parallel). 20 RAM blocks totalling 360kb of memory. it became clear that there was a need for a standard language for describing the structure and function of Integrated Circuits (ICs). In the course of this program. Internal signals are declared in the architecture body and cannot be connected to the outside world. only if necessary. Capabilities are pretty much equal. Every VHDL design must have an entity and an architecture. combinational logic and finite state machines have been used throughout the project. as it resembles the way hardware works. 10 . The board has a 15-pin D-subminiature connector to plug in a VGA monitor. it is best to “learn one well and. HDL usage is more a matter of preference.1.FPGA BASED VGA DRIVER AND ARCADE GAME 2.1: SPARTAN-3E BOARD The development board used in this project is shown in Figure 2. The Entity contains a declaration of I/O ports while the actual design code resides in the architecture part. 1996) [2]. whereas VHDL is based on Ada. VHDL supports many built-in and user-defined data types.3 Development board numerical types such as integer arrays. It uses a Spartan-3E series FPGA (model XC3S500E) with the following characteristics [1]: • • • • 500. an on-board 100-pin expansion port is used to connect an adaptor board. making over ten thousand equivalent logic cells. And just like with FPGAs. Concurrency is very useful in HDLs. The difference lies in how the hardware is described. FIGURE 2. etc. Some of most often used are • • • • std_logic (single bit) std_logic_vector (bit vector) Hardware description languages Other HDLs As with the FPGAs.2 VHDL “VHDL is a language for describing digital electronic systems. Signals declared in the entity are referred to as external and are usually tied to I/O pins on the FPGA. 2. Hence the VHSIC Hardware Description Language (VHDL) was developed” (Ashenden. Many of the basic concepts. Also. Unlike imperative programming languages. Full list of features can be found in the user guide [4].e. such as gate and register-transfer level design. Sequential statements can be implemented using a special construct called process. VHDL can be used not only to describe digital hardware but also to create test benches for testing the designs.000 system gates. VHDL became an IEEE standard in 1987. VHDL statements are concurrent (i. 20 dedicated multipliers. tackle the other later”. Digital systems theory VHDL is a good example of practical application of digital circuit theory. Several revisions have been done since then. Verilog is somewhat similar to C programming language. The mapping of signals to pins is done in the User Constraints File (UCF).

7V [4]. This part is also known as the retrace period. This divider scales the 3. In case of HSYNC. Visible part of the screen is shown as the white area. Below is the short description of each part of the screen. 11 .2: PARTS OF A SCREEN • Figure 2. and the total height is 524 pixels. Xilinx Spartan-3E board is only capable of producing eight colours (3-bits) as a digital-toanalogue converter (DAC) is not used. return paths and I2C clock/data or are reserved [5]. which form a potential divider with internal 75Ω termination. Sync pulse. VSYNC rate can also be referred to as a refresh rate (i. RED. Front porch. the trace goes back to row zero.2. This is the part that goes before the active video starts.2. video output is enabled. The maximum voltage that can be used is 0.2 shows parts that are required for an operation of a standard monitor. number of times per second the screen is redrawn) RED – red colour channel GREEN – green colour channel BLUE – blue colour channel FIGURE 2.3V signal from FPGA to required 0. HSYNC and VSYNC are TTL signals. and columns go from left to right. Other modes are described in the source [6]. Sequence and duration of these signals are discussed below. Rows are arranged top to bottom. This signal controls vertical position of the active pixel.4. but required for synchronization. followed by a table of dimensions. one by one. the video output is disabled. so logic one is represented by 5V and logic zero is represented by 0V [5].e. that is mostly used in personal computers. If pulse is VSYNC. These numbers are only valid for resolution of 640 x 480 and refresh rate of 60Hz. Back porch. When the trace reaches the end of the visible part of the screen. VGA connector uses a total of 15 pins. The board uses 270Ω resistors. This is the visible part of the screen. These areas are denoted as VBF (Vertical Back Porch) and HBF (Horizontal Back Porch) in Figure 2. This signal controls the horizontal position of the active pixel VSYNC – vertical synchronization signal. With these parts. Active video. The black and grey borders denote parts of the screen that are not visible.1 lists the dimensions for each part of the screen. but only 5 signals are needed for operation: • HSYNC – horizontal synchronization signal. that uses 640 x 480 pixels resolution. Synchronisation signals are used to tell the monitor to return the pixel back to the first row (VSYNC) or the first column (HSYNC).FPGA BASED VGA DRIVER AND ARCADE GAME 2. the total width of the screen is 800 pixels. the trace goes back to column zero. It has a resolution of 640 by 480 pixels. Table 2.4 VGA Hardware VGA is an analogue video standard. GREEN and BLUE signals are analogue. These areas are denoted as VPF (Vertical Front Porch) and HPF (Horizontal Front Porch) in Figure 2.7V and will result in full intensity of that colour [5]. The row and column addresses are constantly incremented thus changing the position of currently drawn pixel. • • • Other pins include ground. VGA can also refer to a piece of display hardware developed by IBM (Video Graphics Array) or a display mode. Timing Pixels on the screen are drawn in sequence.

we have the graphic objects.4. The FPGA can only go up to 3.1 below.FPGA BASED VGA DRIVER AND ARCADE GAME TABLE 2. The controllers use an 8-bit static shift register (4021B) to transmit user input as an 8-bit serial data. Signals shared between VGA. It is worth mentioning that the controllers and the development board cannot communicate directly with each other due to different voltage levels used. It passes pixel coordinates received from the VGA circuit.5 Nintendo controllers Logic blocks The classic Nintendo Entertainment System (NES) controller became a cultural icon among arcade game lovers and geeks. VGA synchronization logic provides information about the pixel which is currently being drawn on the screen. At the bottom of the hierarchy. TABLE 2. it is a good idea to separate the source into logic blocks. in the middle of the diagram. Finally. based on that information. When two buttons are pressed at the same time. Sound circuit provides acoustic feedback to the user. 2. is the Main block. routes the data. There are eight buttons on the gamepad. It therefore. generate RGB pixel values.3: GAME LOGIC HIERARCHY To make the code more manageable. It also outputs synchronization signals to the VGA port. graphics generation circuit. Buttons and their corresponding values are listed in Table 2.1: GAMEPAD OUTPUTS Button None A B SELECT START UP DOWN LEFT RIGHT Value 11111111 01111111 10111111 11011111 11101111 11110111 11111011 11111101 11111110 FIGURE 2. two bits will be set to zero.3V (LowVoltage TTL or CMOS).5. seemed like a good idea to use these controllers as an input device. An equivalent schematic diagram of the controller is shown in Appendix D. while the controllers need 5V . an adaptor board was designed and built.5.1: VGA TIMINGS 25MHz pixel Active Front clock video porch Horizontal Vertical 640 480 16 11 Sync pulse 96 2 Back porch 48 31 detail in Chapter 7. Sound. User Input and Graphics circuits all go through the main logic block. This logic depends on signals provided by the graphics generation circuit. can be thought of as a hub connecting all the objects. sends control signals and enables or Note that the signal is active-low. For this purpose. They take pixel coordinates and control signals and. so each button has its own bit. At the very top of the hierarchy.6 Principles of game implementation 2. This is discussed in greater 12 . Figure 2. Major logic parts are instantiated in this circuit. User input logic is responsible for logging input events and providing the graphics logic with appropriate control signals.3 shows one possible configuration of a game project.

logic and so forth.vhd. the values in the two counters VGA FIGURE 3. Comments in the code provide more detailed explanation. During operation.1. The object has a source of pixel values. Note that separate sync signals are used for vertical and horizontal synchronisation.3. there is not much to gain from writing a custom implementation. the outputs were measured with an oscilloscope. lines 95 to 100. This section will briefly explain the operation of the VGA controller logic.1 Code vga_sync. between the front porch and back porch). respectively. The value of the pixel is deduced from screen pixel coordinate.FPGA BASED VGA DRIVER AND ARCADE GAME disables the objects. is an example of an object. Results To get a visual representation of the generated synchronization signals.e. in this case.4. 13 . A ball in the game of Pong. position on the screen.1 shows the HSYNC trace. These coordinates are provided as 10-bit vectors. can be described in pseudo-code like this: sync_pulse = 1 when counter >= (display_area + front_porch) and counter < (display_area + front_porch + sync_pulse) Objects In the game. Channel 1 (top) in Figure 3. The HSYNC signal is left out. since no detail can be seen due to much higher frequency. counters (for the vertical and horizontal pixel coordinates) and constants representing the timing values listed in Table 2. the object knows its current location. which is used by graphics generation circuit to display the object on the screen. The idea here is to provide another layer of logic separation. dimensions. movement etc. by Pong P . The frequency needed to traverse 524 lines in 1/60th of a second is about 31kHz. and can update its coordinates to move or bounce of the wall. The corresponding VHDL code can be found in the vga_sync. The circuit also outputs x and y coordinates. The statement. Each object is responsible for its graphical appearance. each graphic element is treated as an object. It is one of the simplest parts in the project and.2 shows a zoomed-out version of the VSYNC trace. Three major components are needed for the driver: a 25MHz clock. named px_x and px_y. These counters are updated at the speed of the pixel clock – 25MHz in this case. Note the frequency of around 60Hz.1: VGA SIGNALS Figure 3. 3 IMPLEMENTATION 3. are checked against the predefined constants. therefore. The graphical representation of the ball is stored in the ROM. More on this in Chapter 3. position coordinates. The horizontal and vertical counters count to 799 and 523 respectively. SYNC signals are produced during the sync stage (i. The VSYNC signal is shown as channel 2. Chu [7]. Object generates a pixel value.vhd The VHDL code for driving a VGA monitor is taken from FPGA prototyping by VHDL examples.

4 shows the waveforms captured by an oscilloscope.5MHz [8].2: VSYNC SIGNAL The latch (ps_counter in the image) value is also used to assign the received value to the right bit in the data byte. This type of application does not require a very fast sample rate. so 100 samples per second seemed reasonable. Latch signal frequency was chosen to be 100Hz. The clock frequency should not.3: CONTROLLER INTERFACE TIMING DIAGRAM FIGURE 3.4: CLK AND P/S SIGNALS Note the frequencies of 800Hz and 100Hz. The latch signal must be eight times slower than the CLK in order to get all eight bits shifted out.2 Code NES controller interface Results Figure 3. This is done so that the sampling point can be chosen with greater accuracy. parallel data is loaded into the registers. This chapter takes a deeper look into objects and graphics generation.vhd The purpose of the driver is to provide control signals for game pads. the voltages are stable. . When all bits have been received. Controllers need external clock and latch signals. as it is in the middle of high state of CLK signal (shown as clk_out in the image) and. the data is made available as an 8-bit logic vector. 3. Figure 3. 14 FIGURE 3.3 Graphics Section Principles of game implementation in Chapter 2. The output signals are inverted to match the operation of the adaptor board (described in Chapter 7).3 shows a part of simulated operation of the interface. gave a brief introduction into the structure of a game. This is much lower than the maximum given in the datasheet.2kHz). as well as read the data from them. Clock signal. exceed 1. The CLK and latch signals are derived from the master counter. therefore.FPGA BASED VGA DRIVER AND ARCADE GAME FIGURE 3. This point was chosen. Channel 1 shows CLK and channel 2 shows latch signal. under normal conditions. controller. 3. When this signal is high. therefore. Three vertical lines show the points at which data is sampled (master counter value is changing from zero to one). bits are shifted out. which is running at four times the CLK speed (3. needed to be 800Hz. when it is low.

image data is sent to RGB output. The first pixel with coordinate (0. pixel <= pixel_data(col_addr). We want this image to appear in the top-left corner of the screen. we need to derive the row and column addresses. Otherwise. Because the screen pixel coordinates correspond directly to the image pixel coordinates. an image for example. Likewise. white colour is used as a background. To begin with. ROM instantiation and data type conversions are not 15 . we only need a single bit to describe monochrome images (same bit is used for Red. a 3-bit RGB scheme is used. Green and Blue channels). this array can be described as follows: type rom_type is array(0 to 1) of std_logic_vector(0 to 3). For simple cases. In VHDL. therefore. constant SQUARES: rom_type := ( "1010". the last pixel is located at the bottom-right corner. One simple way of doing this. a two-dimensional array is sufficient. Lastly. The active pixel is then retrieved from this vector. we need to define the boundaries of the image. Lets do a simple task of displaying an image on the screen. pixel values have to be stored in memory. Even though. 0) is located at the top-left corner. In our case. For storage of a simple monochrome image. the synthesizer will infer a correct type of RAM based on the structure of the code. single bit is converted to three bits for output at the RGB port. col_addr <= px_x(3 downto 0). This array defines a four-by-two pixel image like one denotes the foreground this: ▚▚. Array rows represent image rows. it is sufficient to just take four least significant bits (LSBs) of the pixel coordinates provided by the VGA driver. For more complex graphics. So when the pixel coordinates are less than 16. To keep the example as simple as possible.FPGA BASED VGA DRIVER AND ARCADE GAME Storing images The graphics generation circuit gets a pixel coordinate from the VGA driver. The ROM instance (not shown here) automatically takes the row address and outputs the appropriate row as a pixel_data vector. and array indices represent individual pixels. row_addr <= px_y(3 downto 0).5: BALL IMAGE The size of the example image is 16 x 16 pixels. FIGURE 3. To do this.5 below shows ball graphics used in the Pong game. Note that (black) and zero denotes the background (white). it is 16x16 square: rgb <= img_data when px_x < 16 and px_y < 16 else "111". img_data <= "000" when pixel = '1' else "111". Based on that coordinate. Figure 3. is to use the internal block RAM. we need the address to be 4-bits wide in order to be able to access each row and column. Now we need to set the image data. it generates a colour value for that pixel and outputs it to the RGB port. No special code to define RAM options was used in this project. "0101" ). Getting the pixels Row and pixel addresses are derived from pixel coordinates.

the image will change its position on the screen. and call it rgb_array: type rgb_array is array(0 to 3) of std_logic_vector(2 downto 0). These addresses add up to a 3-bit The code that enables the ball has to be updated as well. "001". Structure definition is quite similar. FPGalaxy . for example. but we use the type defined above instead of std_logic_vector: FIGURE 3. two bits will cover all four columns.vhd. "010". some updates to addressing are needed. If the 16 . There will be 4 pixels per row. "011"). In the colour mode. In the monochrome image example. two addresses (row and column) have to be provided to the ROM. with experience in lower-level programming. ("100". col_addr <= px_x(3 downto 0) ball_top_x(3 downto 0). and each pixel will be defined by 3-bit vector. array structure used before is not suitable. corresponding image pixel is (0. the row type is an array. Reader should refer to code listing for full details. may know the answer already – an array of arrays! To begin with. we need to have vectors defining the position of an object. This image will show all eight colours that can be generated using 3-bit colour space. "110". Now whenever we change the top coordinate. The first challenge is: how to define a 3D array in VHDL? Readers. "101". Likewise. See the next section for a pointer. Colour image storage Moving images In order to be able to move images around the screen. Plong – graphics. 3). a whole row was made available at the output of the ROM. so that externally the ROM looks the same. we define a two-dimensional array type as before. line 360 row_addr <= px_y(3 downto 0) ball_top_y(3 downto 0).FPGA BASED VGA DRIVER AND ARCADE GAME shown here.alien_1_1_rom. we need a way to relate screen pixel coordinate to image pixel position. These addresses are joined together. "111") ). when screen pixel is at (3. a constant with the pixel data is defined: constant SQUARES_2: rom_type := ( ("000". a single bit is sufficient. Next. so it is better to return a value of a single pixel instead. This type will be used to describe rows of an image. In Figure 3. The correct image pixel address is produced by simply subtracting the top coordinate of the ball from the current position of the screen pixel.6: IMAGE ADDRESSING type rom_type is array(0 to 1) of rgb_array.6. rgb <= img_data when (px_x >= ball_top_x and px_x < ball_top_x + BALL_SIZE and px_y >= ball_top_y and px_y < ball_top_y + BALL_SIZE) else "111". 0). Since there are now three bits per pixel. To access each row of the example image. coordinates are updated in a continuous manner. When the object is offset. we can see that. These will usually store x and y coordinates of the top-left corner of that image. we want to combine these row arrays to make an image. In the next step. For this purpose. Lastly.vhd A different approach is needed to implement the storage of colour images. a motion will be created.

"11111110". Go to 1 until all bits have been shifted. Our tiles are 8x8 pixels each. "00111000". a typeface has to be chosen. 3. The source image is shown in Figure 3. The address of the second symbol. all BCD registers are checked. Addressing is very simple. games need to convey some textual information to the user. an additional logic may be required to select the character address if ROM structure is used to store the text. After each shift. "11000110".vhd . 17 Grid Arcade . was borrowed from Uzebox Project [9] as it resembles the typeface used by many old arcade games. we can now talk about placing the text on to the screen. A simple Python script was written for this purpose and is provided in Appendix E. These addresses are used to define text. "01101100". "00000000". and there are 64 symbols in total.FPGA BASED VGA DRIVER AND ARCADE GAME wide vector. the column address). a binary-to-BCD (Binary Coded Decimal) converter is needed. For large amounts of text. This results in 512 rows and 8 columns. 3. as described in Chapter 3. 1. described in page 147 of source [7]. used by the two games. an exclamation mark.vhd To begin with. which means that 80 x 60 letter matrix can fit on a 640 x 480 resolution screen. a space. "11000110". Font codepage. "11000110". This section will go through the theory and implementation of such converter. This is how letter A looks after conversion. is 1. a ROM. provided the characters are placed strictly on the grid: • To get a row address. data <= rgb_row(addr(1 downto 0)). The address of the first symbol. it has to be converted to a code page or. "11000110". This chapter will describe the process of text generation in VGA applications. Also. we take the character address and add three lower bits of px_y (the screen pixel coordinate) to it. Bits are shifted to the left. The size of each symbol is 8 x 8 pixels. Three lower bits of px_x will select the right pixel in the row (i. Each character has its own address within the ROM.7. if value in the register is greater than four.4 Text generation Often-times. 2. to say simply. • FIGURE 3. The easy way is to treat each letter as a tile. so that the most significant bit (MSB) of a binary number becomes the least significant bit (LSB) of BCD0 digit. or 4k bits of data in a ROM. Entering this information by hand would be tedious and time-consuming. is 8 and so on. a proper subtraction is needed. 3. As the font has been chosen and the code page generated. three is added to that register. The ROM is no different from that described in Chapter 3.3. a ROM storage is appropriate. then the MSB of BCD0 digit becomes the LSB of BCD1 digit and so on. but a simple multiplexer is sufficient when only a few letters are needed.7: ARCADE TYPEFACE When a suitable font is chosen. which can be used like this: rgb_row <= SQUARES_2(addr(2)).5 Binary to BCD conversion In order to display multi-digit numbers as a text.3.menu. The font.e. --------### ## ## ## ## ## ## ####### ## ## ## ## If text is moving or otherwise offset. Theory Binary numbers can be converted to BCD using a “Shift and add 3” algorithm.

Start state clears all the registers and the shift counter and preloads a new binary number. Addition is done using concurrent statements outside of the FSMD. the counter will reset. It. The ROM contains a number of 9-bit vectors. 18 .6 Sound To make the games more complete. The sound is produced by a piezoelectric transducer which is driven directly by the FPGA. shift and done.8. that creates a square wave. resulting in 7 different values (zeros are used for termination). When start signal is set.bin2bcd. When the value of the counter matches the value of the period input. volume input. It has three states: start. The pulse width can be set as a fraction of the period by setting the FIGURE 3. a representation of data is stored. think of FSM as a flowchart. Done state does not do anything explicitly. the FSMD state changes to Playing. This FSMD has two states – Off and Playing. amplitudes and durations is needed. which are later mapped to actual values.8 for an example. The Playing state serves two purposes: it checks for the end of the tune and also sets the address of the next note (datapath). which takes data from sound ROM. An internal counter is running at 50MHz. gives the output logic a signal that the conversion has been completed and the BCD digits can be made available at the output. The FSMD. transforms it and feeds the result to the frequency generator. en <= '1' when state = playing else '0'. shown in Figure 3. To keep things simple. It can produce different frequencies and duty cycles depending on the parameter values provided. a variety of frequencies. otherwise. an audio feedback function was added. is the main control structure of the player logic. 3. volume and duration are each allocated 3 bits.vhd The conversion is controlled by a Finite State Machine with Datapath (FSMD). Pitch.FPGA BASED VGA DRIVER AND ARCADE GAME VHDL implementation FPGalaxy .vhd A high-level logic. the state is changed to done. is called a player. The generation logic is divided in to three parts: • • • Frequency generator Sound ROM Player Frequency generator sounds. and can be said to use the Moore model. See Figure 3. Player player.vhd The frequency generator is a low-level logic.8: SOUND CONTROL FSMD Output (enable signal) only depends on the state. however. The output can be switched on or off by setting the enable signal. A ROM is used to store all this data. Shift state checks the number of bits shifted. Sound ROM In order to create more complex sounds. The duty cycle determines how long the output stays high during the period. if all the bits have been shifted. If you are unfamiliar with digital circuit theory. rather than the actual data. shift operation is performed again.

The structure follows the pattern described in Chapter 2. enabling or disabling motion of the ball and announcing the winner. There was not much planning involved and the main goal was to get it working and to grasp the basics game development. 4.2: PONG ASMD CHART Start state is used to reset the scores before the game begins. The set of values is far from comprehensive. but will go under a paddle in case of the player missing the ball. It is responsible for keeping the scores.2 Graphics Main logic Plong . if one of the players has reached the seven-point limit.25 % 3.6.2. other columns show the corresponding output from the multiplexer. Background has the lowest priority.1 summarises operation of multiplexers used to transform the data from the sound ROM to appropriate values. but is sufficient for purposes of this project.1 Bits 000 001 010 011 100 101 110 111 110 Hz 220 Hz 440 Hz 880 Hz 1760 Hz 3520 Hz 7040 Hz Frequency Duration N/A 1/64 s 1/32 s 1/16 s 1/8 s 1/4 s 1/2 s 1s 50 % 25 % 12. TABLE 3.1 Structure Development of the Pong game was a learning exercise in its way.6. but the objects (ball and paddles) are not separated from the main graphics logic.vhd The main graphics generation logic consists of two noteworthy parts: a game control FSMD and a pixel routing logic. It basically defines object priorities. changes state to game over. The control FSMD is shown in Figure 4. This resulted in a large all-in-one file. When the ball is missed.56 % 0.graphics. The pixel routing is done with a conditional sentence. 4 PONG 4.78 % Duty cycle Figure 4.12 % 1.5 % 6. The Bits column represents the data in the ROM.FPGA BASED VGA DRIVER AND ARCADE GAME Table 3. when two or more objects are at the same location. FIGURE 4. or waits for user input otherwise. FIGURE 4.1: PONG GAME FILE STRUCTURE Playing state enables the ball.6. score count is updated and the state 19 . For example: the ball will go over the middle line and the score text. Waiting state disables movement of the ball.1 shows the file structure of the Pong game.

the ball position will be updated.3 shows the ball going down and to the right. The counter counts to some value. Ball logic Ball logic is probably the most complex part of the game. end if. but they have separate position coordinates. Dimensions and graphics are the same for both bars. if ball_v_dir = '1' then ball_y_next <= ball_y + 1. it starts going up and to the right. Likewise.FPGA BASED VGA DRIVER AND ARCADE GAME changes to waiting. A separate process is dedicated to controlling the direction of the ball. One of the most important features of the game is increasing the velocity of the ball. The counter limit is updated after a certain number of bounces from a paddle. Paddle logic This Pong implementation is a two-player game. Using this principle. and when it resets. it is easy to implement a vertical direction control: if ball_y = 0 then ball_v_dir_next <= '1'. There are only four levels of velocity. The bold arrow denotes the direction that does not change after the bounce.3 illustrates the principles of ball movement. The acceleration of the ball is controlled by a counter. When a paddle is at the top or bottom. Paddle control logic is fairly simple – it responds to user input by increasing or decreasing the top coordinate of each bar. Scores The pong game uses a text generation logic. Figure 4. but is hardly noticeable during the game. 20 . increase the velocity. but the principle stays the same. no further movement is allowed in that direction. By reducing the value of the counter limit.1. When the ball bounces. elsif ball_y = SCREEN_HEIGHT BALL_SIZE then ball_v_dir_next <= '0'. This results in small distortion of the ball (see Chapter 8). One has to keep track of ball position.1. data and pixel signals. This allows a player to get used to controlling paddles and ensures that the game will come to an end at some point. it was possible to use shared enable. and the horizontal direction changes from right to left. A horizontal direction control requires checking whether a paddle is in a right position. so two paddles are needed. ROM address. the x and y coordinates are updated independently. else ball_x_next <= ball_x . The position is updated according to the direction of the ball and is done like this: if ball_h_dir = '1' then ball_x_next <= ball_x + 1. but it proved to be sufficient to make players concentrate more at greater speeds. Since the two paddles cannot appear in the same location. end if. in the part b) the constant direction is downward. end if. enable or disable the motion and so forth. FIGURE 4. ball velocity can be increased. else ball_y_next <= ball_y . As you can see.3: CHANGES IN TRAJECTORY The part a) of Figure 4. Winner is announced when the FSMD state changes to Game over. One issue with this acceleration approach is that sometimes the ball coordinate is updated more often than the screen itself.

When the missile hits the target or leaves the screen. only the square wave generator was used to make these sounds. but not up or down. low pitch sound is played when the ball is missed. and need two shots to get killed. Since the functionality is very basic.g. ROM files) are not shown in the figure. Full file tree can be found in the source code listing. 5. it can more sideways. it would be possible to take the code that generates a spaceship. Multiplication by 8 is used to get the right digit (characters are 8 x 8 pixels in size). The spaceship is able to shoot one missile at a time. proper game pads used to control the game. At the end of the project development.4. they are stronger than Level 1. At the end. they can turn invisible and avoid being hit by a missile.1: FPGALAXY FILE STRUCTURE Sounds Two types of sounds are used in this Pong game. Simple implementation. enhanced sound logic is able to play simple tunes. The score font address is acquired using this formula: addr = 128 + (score_value * 8) Offset of 128 is needed because numbers start at this address in the memory. Space shooter is more complex than Pong – visual appeal improved by use of colour and animated graphics. The score value was deliberately limited to 7 for two reasons: 1. was developed as a complement to the Pong game. to render points and a game-over message. The purpose of these buttons should be obvious.FPGA BASED VGA DRIVER AND ARCADE GAME described in Chapter 3. It takes three hits to destroy a Level 3 alien. When all the aliens are destroyed. As can be seen. To conserve the space. graphics generation circuit now has many child files (objects). Initially. User input Initially. There are three rows. a space shooter. there is no need for switch debouncing logic. In fact. More work has been done on the design side – the file structure was improved. The aliens are located at the top of the screen.3 Sounds & User input FIGURE 5. 4. the player can shoot another one. While being more more complex. and put it into the Pong game with a minimum effort. and a longer. . Figure 5. each object is logically separated from all other objects. A player controls a spaceship located at the bottom of the screen. another fleet 21 5 SPACE SHOOTER The second game. there are Level 3 aliens. the game is less complicated.1 shows the improved file structure. A short. four on-board tactile switches were used to control the movement of paddles. with eight aliens in a row. 2. There are three buttons.1 Gameplay The point of the game is to destroy the alien invaders. Moreover. high pitch sound is played when a ball bounces. no need for a binary-to-BCD converter. The tones remained after the sound logic was updated. they are weak and need only one hit to be destroyed. Level 1 aliens hover in front (bottom row). files belonging to objects (e. that the game uses: UP . Duration of a match is well balanced. DOWN and START. Level 2 aliens reside in the middle. so only single frequency was used. the game was updated to make use of the Nintendo controllers.

When the missile is within the alien area. appropriate signals are generated for use by other logic parts (such as explosion and score counter) and the alien is disabled.alien_generator.3: COLOUR MASKING A more interesting design solution is implemented in the explosion generation logic. 22 . Apart from pixel generation. The duration of each frame is controlled by a counter. FIGURE 5.spaceship. The alien position coordinates are generated in the main file.2: ALIEN GRAPHICS The frame size was chosen to be 32 x 32 pixels.2 Graphics The two major improvements over the first game are use of colour (although limited to only 3 bits) and object animation. There is only a single frame in the ROM file and yet the explosion is animated in the game. Word “animation” here means that the aliens are not only moving around the screen.2 shows the levels and states of the aliens.vhd Alien generation logic constantly checks the missile coordinates. it only has to react to user input to move sideways and output its centre coordinate for use by the missile generation circuit. which depends on the internal counter. 5. in order to make it impossible to destroy higher level aliens first. There is enough room for a missile to fly between two aliens.graphics. If alien was already destroyed. Spaceship and missile FPGalaxy . The logic takes master coordinate and generates pixel values based on that and some other signals. Figure 5. nothing happens and missile continues its journey. Vertical coordinate is then updated at a certain frequency. The logic is responsible for object control signals and interfacing with the VGA port.vhd FPGalaxy . Main logic FPGalaxy . The score and level information is also updated here. the logic checks which alien is being attacked and whether that alien is still alive.missile.FPGA BASED VGA DRIVER AND ARCADE GAME shows up and the game continues. Aliens All the graphics were originally designed for the purpose of this project. In case of destruction. but also change their shape. Explosion logic FIGURE 5.vhd As most of the logic has been moved to other files. The missile generation logic also contains missile graphics (since the frame size is only 4 x 4 pixels). the logic records the position of the spaceship and uses that value as its horizontal coordinate. The width of all aliens had to be the same. graphics generation circuit has somewhat less work to do than in the case of the Pong game. An animation is created by changing the source of the alien graphics. The individual alien generators use signals generated by a simple FSMD.vhd The spaceship logic is very simple. FPGalaxy . Corresponding logic files are dedicated to displaying that information on the screen. These images were converted to ROM files for use by an alien generator logic. The missile is disabled when it leaves the visible part of the screen or destruction signal is generated. When a launch button is pressed.

as shown in the bottom row.vhd FPGalaxy . RGB output has to be fed from a game stream. 7. it seemed to be a good idea to combine the two games into a single application and provide a nice menu to select a game.vhd Score and level display FPGalaxy .5) converter for the numbers. it would effectively reduce the resolution by 50%. Extra functionality. The animation is controlled by a counter and a finite state machine. definition of signals etc.explosion.vhd When both games were finished. Remember that pixel coordinates are stored in 10bit vectors px_x and px_y.vhd The score and level display generation circuits are also rather simple. There are four pieces of text to be generated on the screen: • • • • title (text: 2 IN 1) game 1 (text: PLONG) game 2 (text: FPGALAXY) credits (author and date) 7 ADAPTOR BOARD After the decision to use NES controllers was made. the effect of animation is created. but is definitely simple and highlights the benefits of modular design. respond to the user input by changing the selection and provide an output signal. The pixel output depends on the state of that FSM.vhd The explosion image uses three colours: red at the centre.main. The list of parts can be found in Appendix B. Menu is the default one. This sort of combination may not be the most effective. and its RGB stream is selected after reset.e. three LSBs are discarded. but is generated from the same source.FPGA BASED VGA DRIVER AND ARCADE GAME FPGalaxy .1 Reverse engineering the controllers Some research into the internal construction of 23 . using different voltage levels. communicate with each other? The obvious solution was to design another piece of hardware that will have proper connectors to fit the development board and controllers and also host level conversion circuitry.menu. When there is no input from controllers. 6. Since the games run in parallel. yellow and white pixels. or in other words.2 Combining the applications Arcade . Font scaling is very easy to implement and does not require any additional code. The menu has to display some text. This was done by enabling/disabling user input for each game. 6 COMPLETING THE PROJECT 6. three frames can be created. Then follows a standard procedure of component instantiation. yellow in the middle and white on the outside.level_info.1 Game selection menu Arcade . Top row in Figure 5. game is chosen). They generate some text and use binary-to-BCD (see Chapter 3.3 shows location of red. double the pixel size! When generating the title text. By masking certain colours. a game will effectively be paused. When these frames are shown one after another. a way to disable on of them is needed.score_info. The title text is about eight times larger than normal letters. When SELECT button is pressed (i. The next step is to combine all three applications together. that indicates the current choice. was added to make better use of available board space. making the pixel eight times as large. a couple of issues had to be resolved: • • how to connect Nintendo controllers to Xilinx development board and how to make two devices. If we ignored the least significant bit. such as reset button and speaker.

While 3. In order to stay on the safe side. Design files for FX-2 connector were kindly provided by Philip Watson. After the game pads were acquired a proper schematic diagram of the internal construction had to be done. A 74HCT4600 analogue switch is used to pull the line down: input is connected to GND and the enable signal is controlled by the FPGA. 5V from the controller could possibly damage the FPGA. The FPGA I/O pins were chosen to make PCB design easier by reducing the length of tracks. latch and serial data lines.3V . uses low-voltage TTL/CMOS thresholds (0V to 3. This part is specifically made to interface 5V systems to 3V systems. The FPGA has to drive two lines – CLK and latch. Shift register to FPGA A 74LCX125 low-voltage buffer with 5V tolerant inputs was chosen to transform 5V output from a controller to 3.3V). which plugs into the expansion port on Xilinx development board. Both Nintendo and Hirose connector design files were custom made. so a 10k pull-up resistor was used on the board. so the signals are activelow. Manufacture The board was milled using a Computer 24 . Inside the controller. FPGA to Shift register PCB layout design The circuit is rather simple. these lines are pulled high with pull-up resistors. FPGA pins chosen to achieve minimum track length. At the heart of the device is a 4021B 8-bit static shift register used for parallel-to-serial data conversion.3V and 5V) lines. The resulting schematic diagram is shown in Appendix F. 7. 7. The FPGA. On the left there is a 100-pin Hirose FX-2 connector. Each of eight parallel inputs has a button assigned to it. The state of the signal is controlled by enabling and disabling the switch. There are also power. The data lines are not pulled high inside the game pads. A piezoelectric transducer and a RESET switch are located at the top. so there is not much to say about PCB design itself. On the right side there are level conversion chips and on the left – NES controller ports. Thicker tracks and “teardrops” used for power (3. vias done using special pins. in order to confirm the fitness for the purpose.3 Board design Schematic capture Schematic capture was done using Easy-PC EDA software. • • The top and bottom layer masks are shown in Appendix G.3V from FPGA could be interpreted as a logic high by TTL circuitry. Approach used in this project is described below. The connections were found using a multimeter in a continuity test mode.1: SWITCH CONFIGURATION Two-layer design. some sort of level conversion had to be implemented. though: • • FIGURE 7.FPGA BASED VGA DRIVER AND ARCADE GAME Nintendo controllers was done beforehand. clock. near the FX-2 connector.2 TTL / CMOS level conversion The shift register inside the controller operates at TTL logic levels – 0V to 5V . however. Some practices and design considerations may be worth mentioning. Top and bottom ground planes connected in multiple points by “stitching” vias. Equivalent schematic diagram can be found in Appendix D. There are many ways to combine TTL and CMOS circuits.

A simple way to make the ball go faster is to increase the update rate. a ball acceleration feature was being implemented. When ball position update rate is increased. This approach means that the ball position has to be calculated upfront or the ball may jump out of the visible portion of the screen. As the switch is located on the board. the image must not change while the pixels are being drawn on the screen. Some problems were minor. In order for graphics to be displayed properly. introduces a slight graphical distortion of the ball. From time to time. it is not constant and so does not affect the game in any significant way. The case was machined from a sheet of clear plastic with holes for controller ports and reset switch. 4. Initial suspect was the enable signal. pixels. others required a bit more effort to solve. FIGURE 8.1 Issues While the distortion can be spotted. so the controller interface problems were not considered. a bizarre behaviour was noted. The screen is updated sixty times per second. Figure 8. Other functions. Two ways were considered to do it: increase step size or increase position update rate.1 shows a an example distortion that could be perceived when the ball moves too fast towards the bottom-left corner of the screen. During the course of the project. the spaceship would stop responding to any user input for a few seconds. signals were made available at the output for 25 . this rule is violated and a slight distortion occurs. 3. the refresh rate has to be faster than the image update rate. After some “quick fixes” failed to solve the problem.FPGA BASED VGA DRIVER AND ARCADE GAME Numerically Controlled (CNC) machine at university. etc. The step size increase means that instead of moving 1 pixel every time the position is updated.1: BALL DISTORTION 8 DISCUSSION 8. such as missile launch worked fine.2: WAVEFORMS GO OUT OF SYNC While implementing control of a spaceship. that was supposed to limit speed of the spaceship. Soldering was done by hand. Synchronisation problems Pong ball acceleration In one of the final stages of development of the Pong game. This approach does not require any extra logic. but due to limitations of VGA mode. using a hot air pencil for SMD components and soldering iron for through-hole parts. In other words. extension rod was glued to improve accessibility. Note how the ball is divided into four parts. there has been a number of issues with various things. the ball would move 2. FIGURE 8. This chapter discusses issues that are most noteworthy.

were active-low. a '0' was appended in the place of the old LSB.1 was tied to 5V instead of GND. It would be possible to use a VHDL based VGA driver while implementing game logic on a softcore processor. Figure 8. that the line was active-high and the switch in Figure 7. that the the two signals drift in and out of sync. An adaptor board. A counter was added to track the number of bits shifted and the problem was gone. that it became clear. Step-by-step inspection made it trivial to notice the early termination of the conversion. behaviour was undefined when a gamepad was not plugged in. These include sound and text generation logic. It is clear. Note that the width of the enable signal was increased in order to be viewed on the oscilloscope. that the problem is really within the controller interface.5. a data converter and an interface for game pads. therefore. before moving on to work with the VGA graphics and game development.FPGA BASED VGA DRIVER AND ARCADE GAME inspection with an oscilloscope. Binary-to-BCD conversion While implementing the “Shift and add 3” algorithm. described in Chapter 3. The project was started by learning the basics of FPGA development. After the initial circuit was designed. there is still room for further improvement and experimentation. One possible approach to systems development on an FPGA is to use a soft-core microprocessor along with VHDL logic. While the absence of these resistors did not affect the operation of a controller. since all bits would be zero after just one shift. Top trace shows the data from the controller. connecting the game pads to the development board. a number of different goals could be considered. Temporary fix was to cut the track and solder some wire between the pad and the ground plane. The project provided valuable experience in FPGA based system design and was really enjoyable.2 Further work While most of the set objectives have been achieved. going on to produce simple applications.2 shows two screen shots taken at different times. 9 CONCLUSION The project was completed successfully – both aims and set objectives have been achieved. It was falsely assumed. a simple counter could be used to divide the sample rate to appropriate value. or even develop an emulator able to run more than a couple of games. The second mistake. to give extra functionality to the games. This could potentially give more flexibility and reduce the development time. was to omit the pull-up resistors on the data lines. this task gave an opportunity to work on circuit and PCB design. 8. a wrong condition was chosen for stopping the conversion. It was then. As well as providing a nice integration between two very different devices. User input was not supposed to be retained between samples. The second revision of the board was made to fix the remaining problems. This implied. The problem could not be identified by just inspecting the code. converted properly. so the Modelsim simulation software was used to track the bug down. Bottom trace is the enable signal. and. Such a condition meant that numbers like 1000002 would not be 26 . was designed and built. there was no need to have the enable signal any more and spaceship control started to work properly. If more time was given to work on this project. Another possibility is to focus more on improving the game features. time was not taken to double-check that the functionality of the adaptor matches the functionality of Nintendo game pads. Adaptor board This one can be written-off to silly mistakes. When the bits were shifted to the left. A number of modules have been developed. that the conversion should be finished when all bits were zero. If there was still an need to limit the speed of the spaceship. When the problem was fixed. Xilinx offers an 8-bit RISC microcontroller – PicoBlaze. This caused malfunction and was the reason why the enable signal had to be added in the first place. The clock and latch signals were internally pulled up.

com/p/uzebox/ [Accessed 26 March 2010] Bibliography 10.pdf [Accessed 26 February 2010] 5. The Designers Guide to VHDL. Chichester: John Wiley and Sons 6.com/PowerSolutions/product. Digital Logic Design. Inc. 2002. Display interfaces: fundamentals and standards. Available at: http://www. Available at: http://www. Xilinx. Ashenden. ON Semiconductor. 2008.References 1.com/support/documentation/boards_and_kits/ug230.onsemi. FPGA prototyping by VHDL examples. New Jersey: John Wiley & Sons 8.hinner. Peter J. 2006. Prentice Hall . 2008.do?id=MC14021BCP [Accessed 9 March 2010] 9... Short. VHDL for Engineers.html [Accessed 27 February 2010] 7. John F. 2008... Myers. Inc. New Jersey: Pearson Education. 2008. 4. http://code..info/vga/timing. Inc. 2005. Newnes 11. Digital Design: principles and practices.. http://martin. San Francisco: Morgan Kaufmann Publishers. Xilinx Spartan-3E FPGA Family Datasheet. Holdsworth. Inc.. 3. Xilinx Spartan-3E FPGA Starter Kit User Guide. Robert L. Xilinx.com/support/documentation/data_sheets/ds312.xilinx. Woods.pdf [Accessed 1 March 2010] 2. 2002.. Pong P. Available at: http://www. Chu. Brian.xilinx. Kenneth L. Wakerly. MC14021B: 8-Bit Static Shift Register. 1996.google. Clive..

etc. and FPGAs in general. If time allows. The following objectives would form the bulk of the project • • • • To complete and fully understand the capabilities of the development board To implement a VGA interface module capable of displaying visual information on a computer screen To implement control i/o functionality capable of interfacing to a controller To design and implement a custom arcade game. the following objectives will be completed • • • . including a non volatile high score table. using an FPGA development board. before moving on to develop a custom made arcade game. etc. The project will involve the use of a Xilinx Spartan-3E development board and will be based around the use of VHDL as a tool to describe and implement digital hardware designs onto the development board. The project will involve exploring the capabilities of the board. two player mode. using a VGA monitor and custom made controller To design and build a simple controller To design and implement sound effect functionality To implement more complex game functions.APPENDIX A Initial technical proposal Project brief Project Title: An FPGA Based VGA Driver and Arcade Game Armandas Jarusauskas Superisor: Dr Ahmet Aydin AASP1 Build a simple arcade game.

44 £0.APPENDIX B Project parts list Part NES controller x 2 NES 2 to 4 adaptor (Connectors) Hirose FX-2 100-pin connector 74LCX125 74HCT4066 TDK PS1720P02 Piezoelectronic Buzzer Total Unit price £3.45 £0.40 £22.99 £12.70 .00 £5.42 £0.

APPENDIX C Project plan .

APPENDIX D NES Controller: equivalent schematic diagram .

%s' % (tmp. '#')) output += t.split('_') if n1[0] == n2[0]: return cmp(int(n1[1]).open(sys.endswith('.stdout.listdir(sys. file in enumerate(files): if file.strip() + '\n' temp = '' sys. ' ').argv[1]) files. b): """ compare function for sorting """ n1 = a[:-4].write(output) .sort(cmp = compare_names) output = '' for i. pixels in enumerate(list(img.split('_') n2 = b[:-4]. -.png'): img = Image.%d\n' % i for j. int(n2[0])) files = os.replace('1'. int(n2[1])) else: return cmp(int(n1[0]).replace('0'. tmp.argv[1] + file) else: break # temporary storage for bits tmp = '' # rom contents output += '-.getdata())): tmp += '1' if pixels[0] == 255 else '0' # we have 8 pixels in a row if (j + 1) % 8 == 0: # generate bit vector and comment t = '"%s".APPENDIX E Python script for generating VHDL ROM from images #! /usr/bin/env python import os import sys from PIL import Image def compare_names(a.

APPENDIX F Adaptor board schematic diagram .

APPENDIX G Adaptor board PCB: top and bottom layer masks .

APPENDIX H Photographs .