TDA8594

I2C-bus controlled 4 × 50 W power amplifier
Rev. 02 — 11 December 2007 Product data sheet

1. General description
The TDA8594 is a complementary quad Bridge Tied Load (BTL) audio power amplifier made in BCDMOS technology. It contains four independent amplifiers in BTL configuration. Through the I2C-bus, diagnosis of temperature warning and clipping level is fully programmable and the information available via two diagnostic pins is selectable. The status of each amplifier (output offset, load or no load, short-circuit or speaker incorrectly connected) can be read separately.

2. Features
2.1 General
I I I I I I I I I I I I Operates in legacy mode (non I2C-bus) and I2C-bus mode (3.3 V and 5 V compliant) Three hardware-programmable I2C-bus addresses Drives 4 Ω or 2 Ω loads Speaker fault detection Independent short-circuit protection per channel Loss of ground and open VP safe (with 200 mΩ series impedance and a supply decoupling capacitor of 2200 µF maximum) All outputs short-circuit proof to ground, supply voltage and across the load All pins short-circuit proof to ground Temperature-controlled gain reduction to prevent audio holes at high junction temperatures Low battery voltage detection Offset detection This part has been qualified in accordance with AEC-Q100

2.2 I2C-bus mode
I DC load detection: open-circuit, short-circuit and load present I AC load (tweeter) detection I During start-up, can detect which load is connected so the appropriate gain can be selected without audio pop I Independently selectable soft mute of front channels (channel 1 and channel 3) and rear channels (channel 2 and channel 4) I Programmable gain (26 dB and 16 dB) of front channels (channel 1 and channel 3) and rear channels (channel 2 and channel 4)

NXP Semiconductors

TDA8594
I2C-bus controlled 4 × 50 W power amplifier

I Fully programmable diagnostic levels can be set: N Programmable clip detection: 2 %, 5 % or 10 % N Programmable thermal pre-warning I Selectable information on the DIAG and STB pins: N The STB pin can be programmed/multiplexed with second clip detection N Clip information of each channel can be directed separately to the DIAG pin or the STB pin N Independent enabling of thermal, clip or load fault detection (short across or to VP or to ground) on DIAG pin

3. Quick reference data
Table 1. Symbol VP Iq Po Quick reference data Parameter supply voltage quiescent current output power Conditions RL = 4 Ω no load VP = 14.4 V RL = 4 Ω; THD = 0.5 % RL = 4 Ω; THD = 10 % RL = 4 Ω; maximum power; Vi = 2 V (RMS) square wave RL = 2 Ω; maximum power; Vi = 2 V (RMS) square wave THD Vn(o) total harmonic distortion output noise voltage RL = 4 Ω; f = 1 kHz; Po = 1 W to 12 W filter 20 Hz to 22 kHz; RS = 1 kΩ normal mode line driver mode 45 22 65 29 µV µV 19 26 42 22 28 44 W W W Min 8 Typ 14.4 270 Max 18 400 Unit V mA

70

75

-

W

-

0.01

0.1

%

4. Ordering information
Table 2. Ordering information Package Name TDA8594J TDA8594SD DBS27P RDBS27P Description plastic DIL-bent-SIL (special bent) power package; 27 leads (lead length 6.8 mm) plastic rectangular-DIL-bent-SIL (reverse bent) power package; 27 leads (row spacing 2.54 mm) Version SOT827-1 SOT878-1 Type number

TDA8594_2

© NXP B.V. 2007. All rights reserved.

Product data sheet

Rev. 02 — 11 December 2007

2 of 48

NXP Semiconductors

TDA8594
I2C-bus controlled 4 × 50 W power amplifier

5. Block diagram
ADSEL SDA 1 SCL 23 VP1 21 VP2 7

26

STB

2

STANDBY/ FAST MUTE

I2C-BUS INTERFACE

5 CLIP DETECT/DIAGNOSTIC

DIAG

IN1

12

MUTE

26 dB/ 16 dB
PROTECTION/ DIAGNOSTIC

10 8

OUT1+ OUT1−

IN3

16

MUTE

26 dB/ 16 dB
PROTECTION/ DIAGNOSTIC

18 20

OUT3+ OUT3−

IN2

13

MUTE

26 dB/ 16 dB
PROTECTION/ DIAGNOSTIC

6 4

OUT2+ OUT2−

IN4

15 VP

MUTE

26 dB/ 16 dB
PROTECTION/ DIAGNOSTIC

22 24

OUT4+ OUT4−

27

TAB

TDA8594

11 SVR

14 SGND

17 ACGND

9 PGND1

3 PGND2

19 PGND3

25 PGND4

001aad119

Fig 1. Block diagram

TDA8594_2

© NXP B.V. 2007. All rights reserved.

Product data sheet

Rev. 02 — 11 December 2007

3 of 48

NXP Semiconductors

TDA8594
I2C-bus controlled 4 × 50 W power amplifier

6. Pinning information
6.1 Pinning

ADSEL STB PGND2 OUT2− DIAG OUT2+ VP2 OUT1− PGND1

1 2 3 4 5 6 7 8 9

OUT1+ 10 SVR 11 IN1 12 IN2 13 SGND 14 IN4 15 IN3 16 ACGND 17 OUT3+ 18 PGND3 19 OUT3− 20 VP1 21 OUT4+ 22 SCL 23 OUT4− 24 PGND4 25 SDA 26 TAB 27
001aad120

TDA8594

Fig 2. Pin configuration

6.2 Pin description
Table 3. Symbol ADSEL STB PGND2 OUT2− DIAG OUT2+ VP2
TDA8594_2

Pin description Pin 1 2 3 4 5 6 7 Description I2C-bus address select input standby (I2C-bus mode) or mode pin (legacy mode); programmable second clip indicator power ground channel 2 negative channel 2 output diagnostic/clip detection output positive channel 2 output supply voltage 2
© NXP B.V. 2007. All rights reserved.

Product data sheet

Rev. 02 — 11 December 2007

4 of 48

the capacitor connected to the ACGND pin must be four times the value of the input capacitor (or as close to the value as possible). In this mode. no I2C-bus is needed and the function of the STB pin will change from two-level (Standby mode and On mode) to a three-level pin (Standby mode. The TDA8594 is protected against overvoltage. must be connected to ground Table 3. the diagnostic functions of temperature level and clip level are fully programmable and the information to be shown on the two diagnostic pins can be selected. It contains four independent amplifiers in BTL configuration (see Figure 1). On mode and mute). over-temperature. 02 — 11 December 2007 5 of 48 . The status of each amplifier (output offset.1 Input stage The input stage is a high-impedance pseudo-differential input stage. TDA8594_2 © NXP B. load or no load. 7. For the best performance on supply voltage ripple rejection and pop noise. Functional description The TDA8594 is a complementary quad BTL audio power amplifier made in BCDMOS technology. short-circuit or speaker incorrectly connected) can be read separately. All rights reserved. Three different I2C-bus addresses are selected with an external resistor connected to the ADSEL pin. special reverse bending is applied. short-circuit. Symbol OUT1− PGND1 OUT1+ SVR IN1 IN2 SGND IN4 IN3 ACGND OUT3+ PGND3 OUT3− VP1 OUT4+ SCL OUT4− PGND4 SDA TAB To keep the output pins on the front side.V. 2007.NXP Semiconductors TDA8594 I2C-bus controlled 4 × 50 W power amplifier Pin description …continued Pin 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 Description negative channel 1 output power ground channel 1 positive channel 1 output half supply filter capacitor channel 1 input channel 2 input signal ground channel 4 input channel 3 input AC ground input positive channel 3 output power ground channel 3 negative channel 3 output supply voltage 1 positive channel 4 output I2C-bus clock input negative channel 4 output power ground channel 4 I2C-bus data input/output heatsink connection. Product data sheet Rev. If the ADSEL pin is short-circuit to ground. 7. open ground and open VP connections. the TDA8594 operates in legacy mode. The negative inputs of the four channels are combined on the ACGND pin. Through the I2C-bus.

and the current through the load is more than 8 A.2 Output stage The output stage of each amplifier channel consists of two PMOS power transistors and two NMOS transistors in a BTL configuration. After 16 ms the amplifier will be switched on again and. The speaker protection will be activated under the following conditions: • Vo < 1.6 Speaker protection To prevent damage of the speaker when one side of the speaker is connected to ground. 2007.NXP Semiconductors TDA8594 I2C-bus controlled 4 × 50 W power amplifier 7.75 V and Imissing(det) > 1 A for 80 µs • Vo > 1. When in one channel the current in the high side power is not equal to the current in the low side power.75 V and Imissing(det) > 3 A for 80 µs TDA8594_2 © NXP B. 02 — 11 December 2007 6 of 48 . 5 % or 10 %). All rights reserved. To prevent incorrect switch-off with an inductive load or very high input signals. the amplifier channel with the short-circuit can be disabled via the I2C-bus. If the DIAG pin is enabled for load fault information (IB2[D4] = 0) the DIAG pin will be pulled LOW. The channel that has a short-circuit and the type of short-circuit can be read-back via the I2C-bus.5 SOAR protection The output transistors are protected by Safe Operating ARea (SOAR) protection. Product data sheet Rev. the amplifier channel will be switched off for 16 ms. one of the two diagnostic pins (DIAG pin or STB pin) will be activated. only the amplifier with the short-circuit is switched off. the output will become distorted. To be able to detect if. which has almost no parasitic components and therefore prevents latch-up. 7. the front channels (channel 1 and channel 3) or rear channels (channel 2 and channel 4) are clipping. the amplifier channel will be switched off for 16 ms. Silicon On Insulator (SOI) process. the condition (Vo < 1 V and IL > 4 A) must exist for more than 300 µs. 7. a missing current protection is implemented. for instance. 7. The 16 ms cycle will reduce the dissipation. and the current through the load is more than 4 A.4 Output protection and short-circuit operation When a short-circuit to ground. • If the differential output voltage across the load is more than 1 V. a fault condition is assumed and the channel will be switched off. In this mode the temperature and load protection are still functional but can only be read via the I2C-bus. VP or across the load occurs on one or more outputs of an amplifier.V. 7.3 Distortion (clip) detection If the output of the amplifier starts clipping to the supply voltage or to ground. To prevent audible distortion. The process used is the BCDMOS process with an isolated substrate. The TDA8594 has a two-stage SOAR protection: • If the differential output voltage across the load is less than 1 V. the clip information can be directed per channel to the DIAG pin or the STB pin. It is possible to have only the clip information on the diagnostic pins by disabling the temperature and load information on the DIAG pin. the amplifier will be switched off. If the distortion per channel exceeds a selectable threshold (2 %. if the short-circuit conditions still occur.

1 Legacy mode (pin ADSEL connected to ground) The function of the STB pin will change from standby/operating to standby/mute/operating and the amplifier will start directly when the STB is put into mute or operating mode. The amplifier output voltage is charged to half the supply voltage minus 1. When the STB pin is switched HIGH. When the STB pin is switched directly from operating to standby. The start-up and shut-down pop can be further decreased by activating the low pop mode. The TDA8594 will start up when instruction bit IB1[D0] is set.V.7. All rights reserved. independent of the I2C-bus mute settings in I2C-bus mode or STB voltage in legacy mode.2 I2C-bus mode When the STB pin is LOW. Mute operating is controlled via an internal timer (20 ms) to minimize mute-on pops. 7. When the STB pin is switched to Standby mode and the amplifier has started.5 V in legacy mode).6 V < VSTB < 4. the amplifier is first muted (fast mute) and then the capacitor on the SVR pin is discharged.5 V in legacy mode).7. Product data sheet Rev. Releasing the mute after a fast mute will be by a soft un-mute of approximately 20 ms. it is possible to fully mute the amplifiers within 100 µs by switching the STB pin to zero.8 Start-up and shut-down sequence To prevent the amplifier producing switch-on or switch-off pop noise. the total quiescent current is low. The fast mute activates the mute for all channels at the same time and mutes the audio in 0. the capacitor on the SVR pin is used for smooth start-up and shut-down. When the low pop mode is enabled (IB2[D3] = 0). and the I2C-bus lines will not be loaded. first the fast mute will be activated and then the amplifier will shut-down. Increasing the value of the SVR capacitor will mean a longer start-up and shut-down time. is used to release the mute if the I2C-bus bits were set to mute off (IB2[D2:D0] = 000. TDA8594_2 © NXP B. 2007. and mutes the audio in 20 ms.NXP Semiconductors TDA8594 I2C-bus controlled 4 × 50 W power amplifier 7. Figure 4. during an engine start. the standby current has reached 1 second after the STB pin is switched to zero (see Figure 3. 7.1 ms. This will decrease the pop even more but will increase the start-up time. the TDA8594 is put in operating condition and will perform a Power-On Reset (POR). Bit D0 will also reset the ‘power-on reset occurred’ bit (DB2[D7]) and releases the DIAG pin. The last 1. When the amplifier is switched off by pulling the STB pin LOW. first the fast mute will be activated (switching to mute within 100 µs) and then the amplifier will shut-down. where the output will reach half the supply voltage. With an SVR capacitor of 22 µF. the output voltage rise from ground level during start-up will be slower (see Figure 5). Figure 5 and Figure 6). which results in a LOW level DIAG pin.4 V. 7.4 V in mute condition. The soft mute can be activated independently for the front channels (channel 1 and channel 3) and rear channels (channel 2 and channel 4). 02 — 11 December 2007 7 of 48 . VSTB > 6. The soft mute and fast mute can be activated via the I2C-bus. or will stay in mute when the bits were set to mute (2. For instance.7 Standby and mute operation The function of the STB pin is different in legacy mode and I2C-bus mode.

Start-up and shut-down timing in I2C-bus mode TDA8594_2 © NXP B.NXP Semiconductors TDA8594 I2C-bus controlled 4 × 50 W power amplifier VP DIAG DB2 bit D7 POR IB1 bit D0 start enable twake STB SVR tamp_on toff fast mute amplifier output td(mute_off) td(soft_mute) td(fast_mute) 001aad168 Fig 3. 2007. Product data sheet Rev. All rights reserved. 02 — 11 December 2007 8 of 48 .V.

Start-up and shut-down timing with DC load active in I2C-bus mode TDA8594_2 © NXP B.NXP Semiconductors TDA8594 I2C-bus controlled 4 × 50 W power amplifier VP DIAG DB2 bit D7 POR IB1 bit D0 start enable twake STB SVR tload tamp_on toff fast mute amplifier output td(mute_off) td(soft_mute) td(fast_mute) 001aad169 Fig 4. All rights reserved.V. Product data sheet Rev. 2007. 02 — 11 December 2007 9 of 48 .

All rights reserved.NXP Semiconductors TDA8594 I2C-bus controlled 4 × 50 W power amplifier VP DIAG DB2 bit D7 POR IB1 bit D0 start enable twake STB SVR tload tamp_on toff fast mute amplifier output td(mute_off) td(soft_mute) td(fast_mute) 001aad170 Fig 5. Product data sheet Rev. 02 — 11 December 2007 10 of 48 . 2007.V. Start-up and shut-down timing with low audible pop and DC load activated TDA8594_2 © NXP B.

If the supply voltage drops. 02 — 11 December 2007 11 of 48 . Start-up and shut-down timing in legacy mode 7. Product data sheet Rev. 2007.4 V).10 Engine start and low voltage operation The DC output voltage of the amplifier (VO) is set to half of the supply voltage and is related to the voltage on the SVR pin (see Figure 7.V. the output follows slowly due to the SVR capacitor. the DIAG pin will be released and the amplifier will start up.6 V. This protection first activates the fast mute and then discharges the capacitors on the SVR and ACGND pins to generate more headroom for the amplifier (see Figure 8).9 Power-on reset and supply voltage spikes If in I2C-bus mode the supply voltage drops below 5 V (see Figure 9). All latches are reset. the content of the I2C-bus latches cannot be guaranteed and the power-on reset will be activated. In legacy mode a supply voltage drop below 5 V will switch off the amplifier and the DIAG pin will not be pulled LOW. If the headroom voltage becomes lower than the headroom protection threshold of 1. The headroom voltage is the voltage needed for good operation of the amplifier and is defined as Vhr = VP − VO (see Figure 7). When IB1[D0] is set. the headroom protection is activated to prevent pop noise at the output.NXP Semiconductors TDA8594 I2C-bus controlled 4 × 50 W power amplifier VP DIAG on STB mute standby SVR tamp_on soft mute amplifier output toff fast mute td(mute_off) td(soft_mute) td(mute_on) td(fast_mute) 001aad171 Fig 6. the amplifier is switched off and the DIAG pin is pulled LOW to indicate that a power-on reset has occurred (bit DB2[D7]). during an engine start. 7. the power-on flag is reset. All rights reserved. A capacitor is connected on the SVR pin to suppress the ripple on the power supply. for instance. TDA8594_2 © NXP B. VO = VSVR − 1.

02 — 11 December 2007 12 of 48 . V (V) 14 VP VSVR 8.6 V. typically 7.4 V. Fig 7. a supply voltage drop below VP(reset).5 V. (2) Steady state output voltage VO = VSVR − 1.4 7 VO (2) headroom protection threshold (3) Vhr (1) 1. In I2C-bus mode.V. Low headroom protection TDA8594_2 © NXP B. (3) Headroom protection threshold = VO + 1. the amplifier starts up again if the VP voltage is above the low VP mute threshold. typically 5 V.6 V t (s) 001aad172 (1) Headroom voltage Vhr = VP − VO. results in setting bit DB2[D7] and not starting of the amplifiers but waiting for an I2C-bus command to start. To prevent pops on the output caused by the application during an engine start (for instance tuner regulator out of regulation). 2007. All rights reserved. The amplifier prevents audio pops during engine start. the STB pin can be made zero when an engine start is detected. the outputs of the amplifier remain low. Product data sheet Rev. The STB pin activates the fast mute and disturbances at the amplifier inputs are suppressed. Below the low VP mute threshold.NXP Semiconductors TDA8594 I2C-bus controlled 4 × 50 W power amplifier When the SVR capacitor has discharged.

legacy and I2C-bus modes TDA8594_2 © NXP B.4 legacy and I2C-bus mode VP output voltage 8.2 (1) Vhr (2) (3) VSVR 3. 02 — 11 December 2007 13 of 48 . Low VP behavior.6 7. (3) Low VP mute released. 2007. All rights reserved.V. (2) Low VP mute activated. Product data sheet Rev.5 output voltage (3) t(start-Vo(off)) t(start-SVRoff) t (s) 001aad173 (1) Headroom protection activated: a) Fast mute b) Discharge of SVR.8 8.NXP Semiconductors TDA8594 I2C-bus controlled 4 × 50 W power amplifier VO (V) 14. Fig 8.

2 (2) 5.6 (1) 7. (2) VPOR: VP level at which Power-On Reset (POR) is activated. Fig 9. Product data sheet Rev. All rights reserved. If the temperature increases further. 2007. If this does not reduce the average junction temperature. The default setting for the thermal pre-warning is IB3[D4] = 0 setting the warning level at 145 °C. typical 175 °C. 7. the amplifier stage will be switched to high-impedance. the pre-warning will be activated resulting in a LOW level on pin DIAG (if selected) and can be read out via the I2C-bus. I2C-bus mode only 7. The TDA8594 is protected against load dump voltage with supply voltage up to 50 V.NXP Semiconductors TDA8594 I2C-bus controlled 4 × 50 W power amplifier VO (V) 14.8 8. 02 — 11 December 2007 14 of 48 .4 I2C-bus mode only VP 8.5 VSVR output voltage 0 POR IB1 bit D0 DIAG t (s) 001aad185 (1) Low VP mute activated. TDA8594_2 © NXP B. all four channels will be switched off at the absolute maximum temperature Toff.11 Overvoltage and load dump protection When the battery voltage VP is higher than 22 V. selected with IB3[D4]. In legacy mode the thermal pre-warning is set at 145 °C.V. Low VP behavior. the temperature controlled gain reduction will be activated for all four channels to reduce the output power (see Figure 10).12 Thermal pre-warning and thermal protection If the average junction temperature reaches a level that is adjustable via the I2C-bus.0 3.

The DIAG pin has both fixed information (power-on reset occurred. To have full control over the clipping information.13 Diagnostics Diagnostic information can be read via the I2C-bus. Diagnostic information availability Legacy mode STB pin no DIAG pin no DIAG pin POR after power-on reset. the DIAG pin remains LOW and the failure information can be read from the microprocessor via the I2C-bus (the DIAG pin can be used as a microprocessor interrupt to minimize I2C-bus traffic). This information will be seen at the DIAG pin as a logic OR. Product data sheet Rev. Diagnostic information selection possibilities are shown in Table 4. the DIAG pin will be released. It is. 02 — 11 December 2007 15 of 48 . pre-warning level is 145 °C yes yes © NXP B. Temperature controlled amplifier gain 7. low battery and high battery) and. for instance. selectable information (temperature. via the I2C-bus. and can also be available on the DIAG pin or on the STB pin.V. DIAG pin will remain LOW until amplifier has been started yes can be enabled per channel can be enabled can be enabled can be enabled Diagnostic information I2C-bus mode Low battery Clip detection Temperature pre-warning Short Speaker protection (missing current) TDA8594_2 no can be enabled per channel no no no yes yes. the STB pin can be programmed as a second clip detection pin. In case of a failure. 2007. It is possible to select whether the clip information is available on the DIAG pin or on the STB pin for each channel separately. The clip detection level can be selected for all channels at once. Table 4.NXP Semiconductors TDA8594 I2C-bus controlled 4 × 50 W power amplifier 30 Gv (dB) 20 001aad174 10 0 145 155 165 Tj (°C) 175 Fig 10. All rights reserved. When the failure is removed. fixed level for all channels on 2 % yes. possible to distinguish between clipping of the front and the rear channels. load fault and clip).

a DC offset is slowly applied at the output of the amplifiers during the start-up cycle and the load currents are measured.14 Offset detection The offset detection can be performed with no input signal (for instance when the digital signal processor is in mute after a start-up) or with an input signal. In I2C-bus mode. the output has not crossed the offset threshold during the last 1 second (see Figure 11). 2007. This can mean the applied frequency is below 1 Hz (I2C-bus read interval = 1 s) or an output offset of more than 1.NXP Semiconductors TDA8594 I2C-bus controlled 4 × 50 W power amplifier Diagnostic information availability …continued Legacy mode STB pin no no no DIAG pin no no yes DIAG pin Table 4.75 V typical. if an I2C-bus read of the output offset is performed. Diagnostic information I2C-bus mode Offset detection Load detection Overvoltage no no yes 7. Offset detection 7.75 V is present. When the amplifier BTL output voltage is within a window with a threshold of 1. the I2C-bus latches DBx[D2] will be set. Different load levels will be detected to differentiate between normal load. 02 — 11 December 2007 16 of 48 . after 1 second an I2C-bus read is performed again and the offset bits are still set. All rights reserved.V. the latches DBx[D2] are reset and setting is disabled.15 DC load detection When the DC load detection is enabled with IB1[D1]. I2C-bus mode only VO = VOUT+ − VOUT− offset threshold reset: setting disabled t t = 1 s: read = no offset DB1 bit D2 reset VO = VOUT+ − VOUT− offset threshold read = set bit t = 1 s: read = offset DB1 bit D2 set t 001aad175 Fig 11. If. TDA8594_2 © NXP B. line driver load or open load. Product data sheet Rev. for instance.

at an output voltage of 2 V (peak) the total impedance must be less than 4 Ω to detect the AC-coupled load. The DC load bits are combined with the AC load bits and are only valid when the AC load detection is disabled. the DC load bits will contain DBx[D5:D4] = 10. The presence of an AC-coupled speaker can be determined using 460 mA (peak) and 230 mA (peak) threshold current detection. independent of the gain setting (see Table 5). the AC load detection bit will be set. 26 dB for normal mode or 16 dB for line driver mode. enabled with IB1[D2] = 1. DBx[D5] 0 1 1 0 DC load detection Meaning (when IB1[D2] = 0) DBx[D4] 0 0 1 1 normal load line driver load open load not valid DC load bits By reading the I2C-bus bits the microprocessor can determine.16 AC load detection The AC load detection.NXP Semiconductors TDA8594 I2C-bus controlled 4 × 50 W power amplifier LOAD DETECTION LEVEL NORMAL 20 Ω LINE DRIVER MODE 100 Ω 800 Ω OPEN-CIRCUIT 5 kΩ 001aad176 Fig 12. the bits DBx[D4] will show the content of the AC load detection.V. 2007. the gain select will be pop free. whether a speaker or an external booster is connected. 02 — 11 December 2007 17 of 48 . which was stored during the AC load measurement. the amplifier gain can be selected. All rights reserved. Depending on these bits. or more than 8 Ω to guarantee only a DC connection is detected. A three ‘threshold cross’ counter is used to prevent false AC load detection when switching the input signal on or off. The detection is audible because a sine wave of a certain frequency (e. If the amplifier peak current triggers a 460 mA (peak) threshold detector three times. is used to detect if AC-coupled speakers. When the AC load detection is disabled again. Product data sheet Rev. after the start-up of the amplifier. 19 kHz) needs to be applied to the inputs of the amplifier. The AC load detection can only be performed after the amplifier has completed its start-up cycle and will not conflict with the DC load detection. Table 5. An AC-coupled speaker will reduce the impedance at the output of the amplifier in a certain frequency band. are connected correctly during assembly.g. If the gain select is performed when the amplifier is muted. bit DBx[D4] will show the content of the DC load measurement. for example tweeters. When the AC load detection is enabled (IB1[D2] = 1). 7. For instance. TDA8594_2 © NXP B. The output voltage over the load impedance will generate an amplifier current. DC load detection levels If the amplifier is used as line driver and the external booster has an input impedance of more than 100 Ω and less than 800 Ω (DC-coupled).

the DIAG pin will be released instantly. Even when the failure is removed. AC load impedance as a function of peak output voltage 7. Table 6. The I2C-bus bits are set on a failure and will be reset with the I2C-bus read command. Product data sheet Rev. TDA8594_2 © NXP B. the microprocessor will know what was wrong by reading the I2C-bus. All rights reserved. the AC load detection is enabled. independently of the I2C-bus latches. 02 — 11 December 2007 18 of 48 . When a failure is removed. The AC load detection can only be performed after the amplifier has completed its start-up cycle and will not conflict with the DC load detection. DBx[D4] 0 1 AC load detection Meaning (when IB1[D2] = 1) no AC load detected AC load detected When bit IB1[D2] = 1. Most actual information will be gathered after two successive read commands. The consequence of this procedure is that old information is read during the I2C-bus readout.17 I2C-bus diagnostic readout The diagnostic information of the amplifier can be read via the I2C-bus. The DIAG pin will give actual diagnostic information (when selected). 2007.V. 20 |Zth(load)| (Ω) 16 001aad177 (1) 12 8 (2) 4 0 0 1 2 3 4 VoM (V) 5 (1) Ith(o)det(load)AC < 230 mA (no load detection level) (2) Ith(o)det(load)AC > 460 mA (load detection level) Fig 13.NXP Semiconductors TDA8594 I2C-bus controlled 4 × 50 W power amplifier The interpretation of line driver and normal mode DC load bit settings for AC load detection is shown in Table 6.

Product data sheet Rev. I2C-bus specification Table 7. Definition of START and STOP conditions SDA SCL data line stable. 02 — 11 December 2007 19 of 48 . data valid change of data allowed mba607 Fig 15. A4 0 0 0 A3 1 1 1 A2 1 1 1 A1 0 0 1 A0 0 1 1 R/W 0 = write to TDA8594 1 = read from TDA8594 0 = write to TDA8594 1 = read from TDA8594 0 = write to TDA8594 1 = read from TDA8594 legacy mode Pin ADSEL SDA SDA SCL S START condition P STOP condition SCL mba608 Fig 14. Open 51 kΩ to ground 10 kΩ to ground Ground TDA8594 hardware address select A6 1 1 1 no A5 1 1 1 I2C-bus. All rights reserved. 2007.V.NXP Semiconductors TDA8594 I2C-bus controlled 4 × 50 W power amplifier 8. Bit transfer TDA8594_2 © NXP B.

Table 8. 2007. Product data sheet Rev. IB1. Bit D7 D6 Instruction byte IB1 Description don’t care channel 3 clip information on DIAG or STB pin 0 = clip information on DIAG pin 1 = clip information on STB pin D5 channel 1 clip information on DIAG or STB pin 0 = clip information on DIAG pin 1 = clip information on STB pin TDA8594_2 © NXP B. Legacy mode: • All bits equal to zero define the setting.NXP Semiconductors TDA8594 I2C-bus controlled 4 × 50 W power amplifier I2C-BUS WRITE SCL 1 2 7 8 9 1 2 7 8 9 SDA MSB MSB − 1 LSB + 1 ACK MSB MSB − 1 LSB + 1 LSB ACK S ADDRESS W A WRITE DATA A P To stop the transfer.V. I2C-bus read and write modes 8.1 Instruction bytes I2C-bus mode: • If bit R/W = 0. with the exception of bit IB1[D0] which is ignored. 02 — 11 December 2007 20 of 48 . IB2 and IB3 • After a power-on reset. All rights reserved. after the last acknowledge (A) a STOP condition (P) must be generated I2C-BUS READ SCL 1 2 7 8 9 1 2 7 8 9 SDA MSB MSB − 1 LSB + 1 ACK MSB MSB − 1 LSB + 1 LSB ACK S ADDRESS R A READ DATA NA P : generated by master (microcontroller) : generated by slave S P A NA R/W : START : STOP : acknowledge : not acknowledge : read / write To stop the transfer. the last byte must not be acknowledged and a STOP condition (P) must be generated 001aac649 Fig 16. see Table 8. the TDA8594 expects three instruction bytes. all instruction bits are set to zero.

DBx[D4] bits not available for DC load detection D1 DC load detection enable 0 = DC load detection disabled 1 = DC load detection enabled D0 amplifier start enable 0 = amplifier not enabled. All rights reserved.V. Bit D7 and D6 Instruction byte IB2 Description clip detection level 00 = clip detection level 2 % 01 = clip detection level 5 % 10 = clip detection level 10 % 11 = clip detection level disabled D5 temperature information on DIAG pin 0 = temperature information on DIAG pin 1 = no temperature information on DIAG pin D4 load fault information (shorts. Bit D4 D3 channel 2 clip information on DIAG or STB pin 0 = clip information on DIAG pin 1 = clip information on STB pin D2 AC load detection enable 0 = AC load detection disabled 1 = AC load detection enabled. DIAG pin will remain LOW 1 = amplifier will start up. 2007. 02 — 11 December 2007 21 of 48 . power-on occurred (DB2[D7] will be reset) and DIAG pin will be released Table 9. Product data sheet Rev.NXP Semiconductors TDA8594 I2C-bus controlled 4 × 50 W power amplifier Instruction byte IB1 …continued Description channel 4 clip information on DIAG or STB pin 0 = clip information on DIAG pin 1 = clip information on STB pin Table 8. missing current) on DIAG pin 0 = fault information on DIAG pin 1 = no fault information on DIAG pin D3 low pop (slow start) enable 0 = low pop enabled 1 = low pop disabled D2 soft mute channel 1 and channel 3 (mute delay 20 ms) 0 = no mute 1 = mute D1 soft mute channel 2 and channel 4 (mute delay 20 ms) 0 = no mute 1 = mute TDA8594_2 © NXP B.

DB2. see Section 7.15 and Section 7.14 • For explanation of AC and DC load detection bits. 02 — 11 December 2007 22 of 48 . Bit D0 Table 10.16. • All bits except DBx[D4] and DBx[D5] are reset after a read operation.V.2 Data bytes I2C-bus mode: • If bit R/W = 1. DB3. the TDA8594 sends four data bytes to the microprocessor: DB1. Bit D7 D6 Instruction byte IB3 Description don’t care amplifier channel 1 and channel 3 gain select 0 = 26 dB 1 = 16 dB D5 amplifier channel 2 and channel 4 gain select 0 = 26 dB 1 = 16 dB D4 temperature pre-warning level 0 = warning level on 145 °C 1 = warning level on 122 °C D3 disable channel 3 0 = channel 3 enabled 1 = channel 3 disabled D2 disable channel 1 0 = channel 1 enabled 1 = channel 1 disabled D1 disable channel 4 0 = channel 4 enabled 1 = channel 4 disabled D0 disable channel 2 0 = channel 2 enabled 1 = channel 2 disabled 8. TDA8594_2 © NXP B. Product data sheet Rev. Bit DBx[D2] is set after a read operation. see Section 7.NXP Semiconductors TDA8594 I2C-bus controlled 4 × 50 W power amplifier Instruction byte IB2 …continued Description fast mute all amplifier channels (mute delay 100 µs) 0 = no mute 1 = mute Table 9. All rights reserved. and DB4 • All bits except DB1[D7] and DB3[D7] are latched. 2007.

bits D5 and D4 are available for DC load detection 00 = normal load 01 = not valid 10 = line driver load 11 = open load D3 channel 2 shorted load 0 = not shorted load 1 = shorted load D2 channel 2 output offset 0 = no output offset 1 = output offset D1 channel 2 short to VP 0 = no short to VP 1 = short to VP D0 channel 2 short to ground 0 = no short to ground 1 = short to ground Table 12.V.NXP Semiconductors TDA8594 I2C-bus controlled 4 × 50 W power amplifier Data byte DB1 Description temperature pre-warning 0 = no warning 1 = junction temperature too high Table 11. 02 — 11 December 2007 23 of 48 . AC load detection is disabled. Bit D7 D6 speaker fault channel 2 (missing current) 0 = no missing current 1 = missing current D5 and D4 channel 2 DC load or AC load detection if bit IB1[D2] = 1. bit D4 has the following meaning 0 = no AC load 1 = AC load detected if bit IB1[D2] = 0. Bit D7 Data byte DB2 Description power-on reset and amplifier status 0 = amplifier on 1 = power-on reset has occurred. bit D5 is don’t care. Product data sheet Rev. amplifier off D6 speaker fault channel 4 (missing current) 0 = no missing current 1 = missing current TDA8594_2 © NXP B. AC load detection is enabled. All rights reserved. 2007.

NXP Semiconductors TDA8594 I2C-bus controlled 4 × 50 W power amplifier Data byte DB2 …continued Description channel 4 DC load or AC load detection if bit IB1[D2] = 1. bit D4 has the following meaning 0 = no AC load 1 = AC load detected if bit IB1[D2] = 0. bit D5 is don’t care.V. All rights reserved. AC load detection is disabled. Product data sheet Rev. 2007. Bit D7 Data byte DB3 Description maximum temperature protection 0 = no protection 1 = maximum temperature protection D6 speaker fault channel 1 (missing current) 0 = no missing current 1 = missing current TDA8594_2 © NXP B. Bit D5 and D4 D3 channel 4 shorted load 0 = not shorted load 1 = shorted load D2 channel 4 output offset 0 = no output offset 1 = output offset D1 channel 4 short to VP 0 = no short to VP 1 = short to VP D0 channel 4 short to ground 0 = no short to ground 1 = short to ground Table 13. bits D5 and D4 are available for DC load detection 00 = normal load 01 = not valid 10 = line driver load 11 = open load Table 12. 02 — 11 December 2007 24 of 48 . AC load detection is enabled.

Bit D5 and D4 D3 channel 1 shorted load 0 = not shorted load 1 = shorted load D2 channel 1 output offset 0 = no output offset 1 = output offset D1 channel 1 short to VP 0 = no short to VP 1 = short to VP D0 channel 1 short to ground 0 = no short to ground 1 = short to ground Table 14. Product data sheet Rev. All rights reserved.V. bit D4 has the following meaning 0 = no AC load 1 = AC load detected if bit IB1[D2] = 0. Bit D7 D6 Data byte DB4 Description reserved speaker fault channel 3 (missing current) 0 = no missing current 1 = missing current D5 and D4 channel 3 DC load or AC load detection if bit IB1[D2] = 1. bit D5 is don’t care. 2007. bits D5 and D4 are available for DC load detection 00 = normal load 01 = not valid 10 = line driver load 11 = open load Table 13. AC load detection is enabled. AC load detection is disabled. bit D5 is don’t care.NXP Semiconductors TDA8594 I2C-bus controlled 4 × 50 W power amplifier Data byte DB3 …continued Description channel 1 DC load or AC load detection if bit IB1[D2] = 1. AC load detection is disabled. bit D4 has the following meaning 0 = no AC load 1 = AC load detected if bit IB1[D2] = 0. AC load detection is enabled. bits D5 and D4 are available for DC load detection 00 = normal load 01 = not valid 10 = line driver load 11 = open load TDA8594_2 © NXP B. 02 — 11 December 2007 25 of 48 .

ACGND and DIAG pin STB tmax = 10 minutes Min 8 −1 Max 18 +50 50 Unit V V V −55 −40 - −2 13 8 150 +150 +105 VP V A A °C °C °C V Vx voltage on pin x 0 0 6.V. All rights reserved. rise time > 2. IN2. duration 50 ms. 2007.5 13 V V 0 24 V TDA8594_2 © NXP B. 02 — 11 December 2007 26 of 48 . SVR. Limiting values Table 15. Symbol VP Parameter supply voltage Conditions operating non operating load dump protection. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134).NXP Semiconductors TDA8594 I2C-bus controlled 4 × 50 W power amplifier Data byte DB4 …continued Description channel 3 shorted load 0 = not shorted load 1 = shorted load Table 14.5 ms VP(r) IOSM IORM Tj(max) Tstg Tamb V(prot) reverse supply voltage non-repetitive peak output current repetitive peak output current maximum junction temperature storage temperature ambient temperature protection voltage AC and DC short-circuit of output pins and across the load pins SCL and SDA pins IN1. IN4. IN3. Bit D3 D2 channel 3 output offset 0 = no output offset 1 = output offset D1 channel 3 short to VP 0 = no short to VP 1 = short to VP D0 channel 3 short to ground 0 = no short to ground 1 = short to ground 9. Product data sheet Rev.

Tested at Tamb = 25 °C. Symbol Rth(j-c) Rth(j-a) Thermal characteristics Parameter thermal resistance from junction to case thermal resistance from junction to ambient in free air Conditions Typ 1 40 Unit K/W K/W 11. Ls = 0.1 4.8 +95 +25 +40 - Unit V V mA µA V V V V V V V mV mV mV Ω Ω Supply voltage behavior © NXP B.4 V with rising supply voltage with falling supply voltage [1] Min 8 8 6. guaranteed for Tamb = −40 °C to +105 °C.4 14. 2007. Rs = 10 Ω.75 µH Min Max 80 2000 Unit W V - 200 V 10. Symbol Ptot Vesd Parameter total power dissipation electrostatic discharge voltage Conditions Tcase = 70 °C human body model. C = 100 pF.1 −95 −25 −40 3. normal mode. Characteristics Refer to Figure 29 at VP = VP1 = VP2 = 14. Product data sheet Rev.5 kΩ machine model. Symbol VP Iq Istb VO VP(low)(mute) ∆VP(low)(mute) Vth(ovp) Vhr VPOR VO(offset) Parameter supply voltage quiescent current standby current output voltage low supply voltage mute low supply voltage mute hysteresis overvoltage protection threshold voltage headroom voltage power-on reset voltage output offset voltage when headroom protection is activated. f = 1 kHz.4 1 22 2. see Figure 7 see Figure 9 amplifier on amplifier mute line driver mode RL(tol) load resistance tolerance VP ≤ 18 V VP ≤ 16 V TDA8594_2 Conditions RL = 4 Ω RL = 2 Ω no load VSTB = 0.0 0 0 0 4 2 Max 18 16 400 15 7. Thermal characteristics Table 16.2 8 7. 02 — 11 December 2007 27 of 48 .6 Typ 14.5 6. All rights reserved.4 270 4 7 7. Rs = 1. Characteristics Table 17.8 0.9 6. Limiting values …continued In accordance with the Absolute Maximum Rating System (IEC 60134). RS = 0 Ω.2 1.4 V.6 5.NXP Semiconductors TDA8594 I2C-bus controlled 4 × 50 W power amplifier Table 15. unless otherwise specified. C = 200 pF.1 18 1.3 0.0 5.V. RL = 4 Ω.7 20 1.7 6.

RL = 4 Ω. guaranteed for Tamb = −40 °C to +105 °C. All rights reserved. RS = 0 Ω.2 30 70 500 V V µA µA µs ILO(SVR) td(mute_off) output leakage current on pin SVR mute off delay time 10 % of output signal. Product data sheet Rev.V.5 6.1 - 4 10 300 6. low pop disabled (IB2[D3] = 1). see Figure 4 I2C-bus mode. DC load active (IB1[D1] = 1). no DC load (IB1[D1] = 0). normal mode. 2007. see Figure 5 legacy mode.5 1 1 4. shut-down and mute timing twake wake-up time time after wake-up via STB pin before first I2C-bus transmission is recognized. VSTB = 7 V. DC load active (IB1[D1] = 1). see Figure 3 5. f = 1 kHz. 02 — 11 December 2007 28 of 48 . with ILO = 10 µA → +20 ms. low pop disabled (IB2[D3] = 1). Characteristics …continued Refer to Figure 29 at VP = VP1 = VP2 = 14.1 7. unless otherwise specified.5 VP VP V V V V V (I2C-bus low voltage on pin STB when pulled down during clipping ISTB = 150 µA ISTB = 500 µA ISTB current on pin STB VSTB = 0 V to 8. with ILO = 10 µA → +20 ms.5 2. see Figure 6 [3] - - 10 µA 295 465 795 ms 500 640 940 ms 640 830 1190 ms 430 650 1030 ms TDA8594_2 © NXP B.5 V clip detection not active. Tested at Tamb = 25 °C. ILO = 0 µA I2C-bus mode. see Figure 3 I2C-bus mode.4 V. Symbol VSTB Parameter voltage on pin STB Conditions Standby mode selected I2C-bus mode legacy mode mute selected legacy mode (I2C-bus off) Operating mode selected I2C-bus mode legacy mode (I2C-bus off) [2] Min Typ Max Unit Mode select and second clip detection: pin STB off) 2. RADSEL = 0 Ω. low pop enabled (IB2[D3] = 0). I2C-bus mode legacy mode Start-up. with ILO = 10 µA → +20 ms. with ILO = 10 µA → +15 ms.NXP Semiconductors TDA8594 I2C-bus controlled 4 × 50 W power amplifier Table 17.6 6.

V.4 V to 7 V. see Figure 4 I2C-bus mode.5 V. Vo < 0. VSTB from 8 V to 1. low pop disabled (IB2[D3] = 1).4 V V V 29 of 48 © NXP B. see Figure 6 from 90 % to 10 % of output signal. 90 % of output signal. DC load active (IB1[D1] = 1). 2007. Product data sheet . ILO = 0 µA with ILO = 10 µA → +0 ms.4 V to 7 V. with ILO = 10 µA → +30 ms. IL = 5 mA Rev. Vi = 50 mV. DC load active (IB1[D1] = 1).1 V. see Figure 6 [3] [3] Min Typ Max Unit 360 520 870 ms 565 695 1015 ms 710 890 1270 ms 510 720 1120 ms 120 245 530 ms 140 280 620 ms - 20 40 ms td(soft_mute) soft mute delay time - 20 40 ms td(fast_mute) fast mute delay time - 0. low pop disabled (IB2[D3] = 1). All rights reserved. RL = 4 Ω.4 V. low pop enabled (IB2[D3] = 0). RS = 0 Ω. see Figure 8 pins SCL and SDA pins SCL and SDA pin SDA. with ILO = 10 µA → +30 ms. see Figure 8 engine start to SVR off time VP from 14. see Figure 6 from 90 % to 10 % of output signal. low pop enabled (IB2[D3] = 0). with ILO = 10 µA → +35 ms. Characteristics …continued Refer to Figure 29 at VP = VP1 = VP2 = 14.NXP Semiconductors TDA8594 I2C-bus controlled 4 × 50 W power amplifier Table 17. unless otherwise specified. 02 — 11 December 2007 - 0.3 V (fast mute).3 - - 1.1 40 1 75 ms ms I2C-bus interface[4] VIL VIH VOL TDA8594_2 LOW-level input voltage HIGH-level input voltage LOW-level output voltage 2. see Figure 3 I2C-bus mode. Symbol tamp_on Parameter amplifier on time Conditions time from amplifier mute to amplifier on. IB2[D1] and IB2[D2] = 0 to 1 (soft mute). low pop disabled (IB2[D3] = 1). Vi = 50 mV.5 5. VSVR < 2 V. VSTB = 7 V. guaranteed for Tamb = −40 °C to +105 °C.5 0. see Figure 4 with ILO = 10 µA → +0 ms. ILO = 0 µA I2C-bus mode. with ILO = 10 µA → +20 ms.1 1 ms t(start-Vo(off)) t(start-SVRoff) engine start to output off time VP from 14. RADSEL = 0 Ω. IB2[D1] and IB2[D2] = 1 to 0. no DC load (IB1[D1] = 0). see Figure 5 legacy mode. see Figure 5 td(mute-on) mute to on delay time from 10 % to 90 % of output signal. f = 1 kHz. I2C-bus mode. Tested at Tamb = 25 °C. see Figure 6 toff amplifier switch-off time time to DC output voltage < 0. normal mode.

5dB)-of) 10 15 20 °C ∆G(th_fold) Zth(load) - 20 - dB 100 5000 - 20 800 - Ω Ω Ω Zth(open) Ith(o)det(load)AC open load detection threshold impedance AC load detection output threshold current I2C-bus mode AC load bit is set AC load bit is not set 460 230 mA mA TDA8594_2 © NXP B. 2007.5dB)) pre-warning average junction temperature IB3[D4] = 0 IB3[D4] = 1 fault condition. Symbol fSCL RADSEL Parameter SCL clock frequency resistance on pin ADSEL address A[6:0] = 110 1100 I2C-bus address A[6:0] = 110 1101 I2C-bus address A[6:0] = 110 1111 legacy mode Diagnostic VOL(DIAG) VO(offset_det) THDclip LOW-level output voltage on pin DIAG output voltage at offset detection total harmonic distortion clip detection level IB2[D7:D6] = 10 IB2[D7:D6] = 01 IB2[D7:D6] = 00 ∆THDclip total harmonic distortion clip detection level variation no overlap between IB2[D7:D6] = 10 and IB2[D7:D6] = 01 no overlap between IB2[D7:D6] = 01 and IB2[D7:D6] = 00 Tj(AV)(pwarn) Tj(AV)(G(−0. guaranteed for Tamb = −40 °C to +105 °C.NXP Semiconductors TDA8594 I2C-bus controlled 4 × 50 W power amplifier Table 17. normal mode.5dB)) ∆Tj(pw-G(−0.5 dB gain reduction junction temperature difference junction temperature difference between 0. RS = 0 Ω.5 Unit kHz kΩ kΩ kΩ kΩ average junction temperature Vi = 0. All rights reserved. 02 — 11 December 2007 30 of 48 .V. Product data sheet Rev. Tested at Tamb = 25 °C.5 5 3 1 1 1 135 112 150 7 ±1.05 V for 0. IDIAG = 1 mA ±1.4 V.5 145 122 155 10 0. Characteristics …continued Refer to Figure 29 at VP = VP1 = VP2 = 14.75 10 5 2 4 3.2 18 9 3 9 6 155 132 160 13 V V % % % % % °C °C °C °C I2C-bus Conditions Min 155 42 7 Typ 400 51 10 Max 57 15 0.5 dB gain reduction and off gain reduction of thermal foldback load detection threshold impedance from thermal foldback to when all outputs are switched off all channels switched off I2C-bus mode normal load detection line driver load detection I2C-bus mode ∆Tj(G(−0.5 dB gain reduction prewarning to 0. unless otherwise specified. f = 1 kHz. RL = 4 Ω.3 ±2.

Vi = 2 V (RMS) square wave RL = 2 Ω. f = 20 Hz to 20 kHz. RL = 4 Ω Po = 1 W to 12 W.5 16. unless otherwise specified. 2007. maximum power. RS = 1 kΩ. differential out normal mode line driver mode 25. RACGND = 250 Ω f = 10 kHz.4 V. RS = 1 kΩ. RACGND = 250 Ω f = 1 kHz filter 20 Hz to 22 kHz. VP = 14. normal mode. VP = 14. RS = 0 Ω. Vo = 1 V (RMS) and 5 V (RMS). THD = 0. Symbol Amplifier Po output power RL = 4 Ω. RL = 4 Ω.4 V.5 dB dB 19 22 45 26 29 65 µV µV µV [5] Parameter Conditions Min 19 26 42 Typ 22 28 44 Max - Unit W W W 47 50 - W 34 45 70 37 48 75 - W W W - 0. complex load.14 0. THD = 10 % RL = 4 Ω. THD = 10 % RL = 2 Ω. VP = 14.V. Tested at Tamb = 25 °C. VP = 14. f = 1 kHz. RACGND = 250 Ω common mode rejection ratio normal mode. Characteristics …continued Refer to Figure 29 at VP = VP1 = VP2 = 14.5 26 16 26. RS = 1 kΩ.5 % RL = 2 Ω. Vcm = 0.4 V.09 0.4 V.05 % % % % 65 60 55 45 80 65 70 65 - dB dB dB dB [5] [5] [5] Vcm(max)(rms) Vn(o) maximum common mode voltage (RMS value) output noise voltage - - 0.4 V. f = 1 kHz to 3 kHz.01 0. Vi = 2 V (RMS) square wave RL = 4 Ω. All rights reserved. VP = 15.NXP Semiconductors TDA8594 I2C-bus controlled 4 × 50 W power amplifier Table 17. guaranteed for Tamb = −40 °C to +105 °C.5 % RL = 4 Ω.3 V (p-p).5 15. Product data sheet Rev.4 V. THD = 0.3 0.4 V. f = 10 kHz Po = 1 W to 12 W. Vi = 2 V (RMS) square wave THD total harmonic distortion Po = 1 W to 12 W.1 0. RS = 1 kΩ. maximum power. RACGND = 250 Ω SVRR CMRR supply voltage ripple rejection 100 Hz to 10 kHz. 02 — 11 December 2007 31 of 48 . f = 1 kHz. VP = 14. VP = 14.02 0. maximum power.4 0. RS = 1 kΩ mute mode line driver mode normal mode Gv voltage gain single-ended in. see Figure 31 αcs channel separation f = 1 kHz.6 V TDA8594_2 © NXP B. f = 20 kHz line driver mode.2 V.

normal mode.6 V. guaranteed for Tamb = −40 °C to +105 °C.Ω should 4 be in series with the ACGND capacitor. maximum = (3143 × ISTB) + 5. Total harmonic distortion as a function of output power TDA8594_2 © NXP B. minimum HIGH level = 0. a resistor R ACGND = ----. The amplifier switches off and will restart after 16 ms resulting in an ‘audio hole’. To comply with 5 V and 3.7 × VDD. 02 — 11 December 2007 32 of 48 . Product data sheet Rev.NXP Semiconductors TDA8594 I2C-bus controlled 4 × 50 W power amplifier Table 17. Vi = 50 mV Vi = 1 V (RMS). The times are specified without leakage current. If the capacitor value on the SVR pin changes with ±30 %. Performance diagrams 102 THD (%) 10 001aad121 1 10−1 (1) 10−2 (2) (3) 10−3 10−2 10−1 1 10 Po (W) 102 VP = 14. unless otherwise specified. The specified times include an Equivalent Series Resistance (ESR) of 15 Ω for the capacitor on the SVR pin. Standard I2C-bus specification: maximum LOW level = 0.3 V. For optimum channel separation. RL = 4 Ω.3 V logic.4 V. (3) f = 100 Hz. supply voltage ripple rejection and common mode rejection ratio.4 V. VSTB depends on the current into the STB pin: minimum = (1429 × ISTB) + 5. Tested at Tamb = 25 °C. the maximal LOW level is defined by VDD = 5 V and the minimum HIGH level by VDD = 3.3 × VDD. Fig 17. (2) f = 1 kHz. Symbol Zi αmute Vo(mute)(RMS) Bp Parameter input impedance mute attenuation RMS mute output voltage power bandwidth Conditions Tamb = −40 °C to +105 °C Tamb = 0 °C to 105 °C Vo / Vo(mute). filter 20 Hz to 22 kHz −1 dB Min 50 60 80 Typ 70 70 92 25 20 to 20000 Max 95 95 Unit kΩ kΩ dB µV Hz [1] [2] [3] Operation above 16 V in a 2 Ω mode with reactive load can trigger the amplifier protection. Characteristics …continued Refer to Figure 29 at VP = VP1 = VP2 = 14. RS = 0 Ω. For a leakage current of 10 µA on the SVR pin. f = 1 kHz. the delta time is specified.4 V. the specified time will also change with ±30 %. All rights reserved.V. 2007. (1) f = 10 kHz. RL = 4 Ω. [4] [5] RS 12.

(3) f = 100 Hz. (2) THD = 0. (2) f = 1 kHz.NXP Semiconductors TDA8594 I2C-bus controlled 4 × 50 W power amplifier 102 THD (%) 10 001aad122 1 10−1 (1) 10−2 (2) (3) 10−3 10−2 10−1 1 10 Po (W) 102 VP = 14. Fig 19. (1) THD = 10 %. 02 — 11 December 2007 33 of 48 . Output power as a function of frequency TDA8594_2 © NXP B. 2007.V. RL = 4 Ω. Product data sheet Rev.4 V. Total harmonic distortion as a function of output power 30 Po (W) 28 (1) 001aad123 26 24 (2) 22 20 10−2 10−1 1 10 f (kHz) 102 VP = 14. All rights reserved.4 V. (1) f = 10 kHz. Fig 18.5 %. RL = 2 Ω.

Fig 20. 2007.4 V. Output power as a function of frequency 80 Po (W) 60 (1) 001aad125 40 (2) (3) 20 0 5 10 15 VP (V) 20 VP = 14. Product data sheet Rev.5 %.V. (2) THD = 10 %. RL = 2 Ω.5 %. 02 — 11 December 2007 34 of 48 . All rights reserved. Fig 21. Output power as a function of supply voltage TDA8594_2 © NXP B. (2) THD = 0. (1) Po(max).4 V. (3) THD = 0.NXP Semiconductors TDA8594 I2C-bus controlled 4 × 50 W power amplifier 60 Po (W) 50 (1) 001aad124 40 (2) 30 10−2 10−1 1 10 f (kHz) 102 VP = 14. RL = 4 Ω. (1) THD = 10 %.

(2) Po = 10 W.4 V. (1) Po = 1 W. (1) Po(max). (3) THD = 0. Total harmonic distortion as a function of frequency.V. in normal mode TDA8594_2 © NXP B.NXP Semiconductors TDA8594 I2C-bus controlled 4 × 50 W power amplifier 120 Po (W) 80 (2) 001aad126 (1) (3) 40 0 5 10 15 VP (V) 20 VP = 14. RL = 4 Ω. Fig 22.4 V. Product data sheet Rev. Output power as a function of supply voltage 1 THD (%) 10−1 001aad127 10−2 (1) (2) 10−3 10−2 10−1 1 10 f (kHz) 102 VP = 14. 2007. Fig 23. 02 — 11 December 2007 35 of 48 . RL = 2 Ω. All rights reserved.5 %. (2) THD = 10 %.

front channels. RL = 4 Ω.4 V. Fig 25. Vripple = 2 V (p-p). Fig 24.V.4 V. (2) Vo = 5 V. All rights reserved. Total harmonic distortion as a function of frequency in line driver mode −40 SVRR (dB) −50 001aad129 −60 −70 −80 −90 10−2 10−1 1 10 f (kHz) 102 VP = 14. 02 — 11 December 2007 36 of 48 .NXP Semiconductors TDA8594 I2C-bus controlled 4 × 50 W power amplifier 10−1 001aad128 THD (%) (1) 10−2 (2) 10−3 10−2 10−1 1 10 f (kHz) 102 VP = 14. (1) Vo = 1 V. Supply voltage ripple rejection as a function of frequency TDA8594_2 © NXP B. RS = 1 kΩ. Product data sheet Rev. 2007. RL = 600 Ω.

NXP Semiconductors TDA8594 I2C-bus controlled 4 × 50 W power amplifier 90 αcs (dB) 80 001aad130 70 60 50 10−2 10−1 1 10 f (kHz) 102 VP = 14. Power dissipation as a function of output power TDA8594_2 © NXP B. Product data sheet Rev. RL = 4 Ω. f = 1 kHz. All rights reserved. 2007.4 V. RS = 1 kΩ.4 V. RL = 4 Ω. Fig 26. 02 — 11 December 2007 37 of 48 . Channel separation as a function of frequency 50 P (W) 40 001aad730 30 20 10 0 0 10 20 30 Po (W) 40 VP = 14.V. Po = 1 W. Fig 27.

Fig 28.V. RL = 2 Ω. f = 1 kHz. All rights reserved.NXP Semiconductors TDA8594 I2C-bus controlled 4 × 50 W power amplifier 100 P (W) 80 001aad731 60 40 20 0 0 20 40 60 Po (W) 80 VP = 14. 2007. 02 — 11 December 2007 38 of 48 . Power dissipation as a function of output power TDA8594_2 © NXP B. Product data sheet Rev.4 V.

Product data sheet Rev. (1) For EMC reasons a capacitor of 1. (3) ACGND capacitor value must be close to 4 × input capacitor value. 4 × 470 nF capacitors can be used as an alternative to the 2.8 nF MUTE 6 OUT2+ 26 dB/ 16 dB PROTECTION/ DIAGNOSTIC 4 OUT2− RS 470 nF IN4 15 (1) 1. 2007. Application information 8.8 nF MUTE VP 22 OUT4+ 26 dB/ 16 dB PROTECTION/ DIAGNOSTIC 24 OUT4− 27 TAB TDA8594 11 SVR (2) 22 µF 14 SGND 17 ACGND (3) 2. 02 — 11 December 2007 39 of 48 .2 µF 9 PGND1 3 PGND2 19 PGND3 25 PGND4 001aad132 For EMC reasons.2 µF capacitor shown.8 nF MUTE 18 OUT3+ 26 dB/ 16 dB PROTECTION/ DIAGNOSTIC 20 OUT3− RS 470 nF IN2 13 (1) 1. Fig 29.NXP Semiconductors TDA8594 I2C-bus controlled 4 × 50 W power amplifier 13.8 nF from the input pin to SGND is advised (optional).5 V RADSEL (2) 5V SDA 1 SCL 23 VP1 21 VP2 7 ADSEL 26 10 kΩ 10 kΩ STB 2 STANDBY/ FAST MUTE I2C-BUS INTERFACE 5 DIAG CLIP DETECT/DIAGNOSTIC RS 470 nF IN1 12 (1) 1. a 10 nF capacitor (not shown) can be added from each amplifier output to ground. Test and application diagram TDA8594_2 © NXP B. All rights reserved.V. (2) The SVR and ACGND capacitors and the RADSEL resistor should first be connected to SGND before connecting to PGNDn pins.8 nF MUTE 10 OUT1+ 26 dB/ 16 dB PROTECTION/ DIAGNOSTIC 8 OUT1− RS 470 nF IN3 16 (1) 1.

7 kΩ 0.9 nF 180 pF 200 Ω 001aad134 Fig 31.9 nF 3. Circuit for combined mode selection and clip detection functions on pin STB TDA8594_2 © NXP B.9 nF 47 kΩ 180 pF 47 kΩ positive output b) negative output 3.V.3 V MICROPROCESSOR 001aad131 Fig 32. 2007. 02 — 11 December 2007 40 of 48 .7 kΩ 18 kΩ TDA8594 2 STB switch 10 kΩ 3.9 nF 3.NXP Semiconductors TDA8594 I2C-bus controlled 4 × 50 W power amplifier ACGND 1 µF 17 TDA8594 MICROPROCESSOR 1. Beep input circuit (gain = 0 dB) to apply a microprocessor beep signal to all four amplifiers positive output a) negative output 3. Product data sheet Rev. Complex loads for measuring THD in line driver mode 8.6 kΩ 4.22 µF 100 Ω 47 pF 001aad133 Fig 30.5 V 5. All rights reserved.

copper layer top tob 001aad163 Fig 34.1 PCB layout top 001aad162 Fig 33. All rights reserved. 2007.V. PCB layout of test and application circuit.NXP Semiconductors TDA8594 I2C-bus controlled 4 × 50 W power amplifier 13. copper layer bottom (top view) TDA8594_2 © NXP B. PCB layout of test and application circuit. Product data sheet Rev. 02 — 11 December 2007 41 of 48 .

2 µF + 470 nF + 2. 2007. TDA8594_2 © NXP B. by 12C on Mute off Legacy DZ 8.2 µF + clip 2 DE (11) + 10 µF mode on D1 470 nF diag s.2 V 10 kΩ 3 4 GND VP −4+ OUT SGND IN 2 1 −3+ +1− OUT +2− SCL GND + 5V SDA 001aad164 Fig 35. All rights reserved. components top tob 220 nF 10 kΩ BC859 2 kΩ 10 kΩ 12 kΩ 51 kΩ 250 Ω 4. Test information 14. components bottom (top view) 14.Stress test qualification for integrated circuits. PCB layout of test and application circuit. PCB layout of test and application circuit.7 kΩ 18 kΩ 22 kΩ 470 nF 470 nF 4 × 470 nF TDA3664 220 nF 001aad165 Fig 36. and is suitable for use in automotive applications.V.1 Quality information This product has been qualified in accordance with the Automotive Electronics Council (AEC) standard Q100 . Product data sheet Rev.NXP Semiconductors TDA8594 I2C-bus controlled 4 × 50 W power amplifier Sense address select GND VP 2200 µF TDA8594/TDA8595 1 µF top D8 (00) DA (01) 12C supply Philips Semiconductors + 2. 02 — 11 December 2007 42 of 48 .

65 0.9 15.5 e 2 e1 1 e2 4 Eh 8 j 3.3 D(1) d Dh 12 E(1) 15.8 v 0.25 0.9 3.9 0. Package outline DBS27P: plastic DIL-bent-SIL (special bent) power package.03 Note 1.2 25.8 1.45 29.8 L2 3. Package outline SOT827-1 (DBS27P) TDA8594_2 © NXP B.4 1.6 w x Z(1) 1.60 4.2 4. OUTLINE VERSION SOT827-1 REFERENCES IEC --JEDEC --JEITA --EUROPEAN PROJECTION ISSUE DATE 03-07-29 Fig 37.NXP Semiconductors TDA8594 I2C-bus controlled 4 × 50 W power amplifier 15.8 28.1 L 6.35 0.4 3.15 22.85 22.1 L3 L4 m 4 Q 2. All rights reserved.1 0.1 1. 2007.8 25.5 0. Product data sheet Rev.8 mm) SOT827-1 non-concave x Dh D Eh view B: mounting base side d A2 B j E A L3 L4 L 1 Z e1 e bp 27 w M Q m c e2 L2 v M 0 10 scale 20 mm DIMENSIONS (mm are the original dimensions) UNIT mm A 19 A2 bp c 0.V. Plastic or metal protrusions of 0. 02 — 11 December 2007 43 of 48 .25 mm maximum per side are not included. 27 leads (lead length 6.

03 Z (1) 1.2 Note 1.1 1.15 L1 3.3 D (1) 29.65 4.4 Dh 12 E (1) 15.60 0. 27 leads (row spacing 2.8 1.6 w 0. Package outline SOT878-1 (RDBS27P) TDA8594_2 © NXP B. Product data sheet Rev.5 e 2 e1 1 e2 2.54 mm) SOT878-1 non-concave x D Dh Eh view B: mounting base side d A2 B j E A L 1 27 c Z e e1 bp w M e2 Q L1 v M 0 10 scale 20 mm DIMENSIONS (mm are the original dimensions) UNIT mm A 13.1 L 3.5 0.54 Eh 8 j 3.2 28.V.8 25.4 3.5 A2 4.25 x 0. 2007.15 Q 2.75 3. 02 — 11 December 2007 44 of 48 .8 d 25.9 15.35 bp 0. Plastic or metal protrusions of 0.25 mm maximum per side are not included OUTLINE VERSION SOT878-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 05-01-11 05-01-26 Fig 38.45 c 0.8 v 0.NXP Semiconductors TDA8594 I2C-bus controlled 4 × 50 W power amplifier RDBS27P: plastic rectangular-DIL-bent-SIL (reverse bent) power package.75 3. All rights reserved.

SOT878-1 reflow soldering footprint 17. Product data sheet Rev. 02 — 11 December 2007 45 of 48 . Dimension ‘1’ relates to dimension ‘e1’ in Figure 38.92 ∅ 0. Mounting 2 27 1 1 2. Acronym ACK BCDMOS BTL CMOS DMOS DSP EMC ESR LSB MSB NMOS PMOS PCB POR SOAR SOI Abbreviations Description ACKnowledge not Bipolar CMOS/DMOS Bridge Tied Load Complementary Metal-Oxide Semiconductor Double-diffused Metal-Oxide Semiconductor Digital Signal Processor ElectroMagnetic Compatibility Equivalent Series Resistance Least Significant Bit Most Significant Bit Negative-channel Metal-Oxide Semiconductor Positive-channel Metal-Oxide Semiconductor Printed-Circuit Board Power-On Reset Safe Operating ARea Silicon On Insulator TDA8594_2 © NXP B.NXP Semiconductors TDA8594 I2C-bus controlled 4 × 50 W power amplifier 16. dimension ‘2’ relates to dimension ‘e2’ in Figure 38. Abbreviations Table 18. 0. All rights reserved.08 M Dimensions in mm sot878-1_fr Dimensions in mm. Reflow soldering is the recommended soldering method. 2007.54 26 2 hole diameter min. Fig 39.V.

Revision history Release date 20071211 Data sheet status Product data sheet Change notice Supersedes TDA8594_1 Document ID TDA8594_2 Modifications: • • • • • • The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Table 17. Revision history Table 19. Diagnostic: – Symbols and parameters of “junction temperature” characteristics updated (4×). 2007. Figure 1 and Figure 29: Changed internal circuit on pin SVR. Section 2. Product data sheet Rev. – (Old) symbol and parameter “IoM = peak current output” changed to “Ith(o)det(load)AC = AC load detection output threshold current”. All rights reserved.NXP Semiconductors TDA8594 I2C-bus controlled 4 × 50 W power amplifier 18. Legal texts have been adapted to the new company name where appropriate. TDA8594_1 (9397 750 15066) 20060302 Product data sheet - - TDA8594_2 © NXP B. Figure 32: Value of base-emitter resistor changed to 5. 02 — 11 December 2007 46 of 48 .V.1 and Section 14: Added device qualification “AEC-Q100 qualification”.6 kΩ.

nxp.nxp. patents or other industrial or intellectual property rights. NXP Semiconductors does not give any representations or warranties. Product data sheet Rev. Contact information For additional information. nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected 19. Suitability for use — NXP Semiconductors products are not designed. Please consult the most recently issued document before initiating or completing a design. product names. the latter will prevail. which may result in modifications or additions. the full data sheet shall prevail. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. to result in personal injury. This document contains data from the preliminary specification.NXP Semiconductors TDA8594 I2C-bus controlled 4 × 50 W power amplifier 19. space or life support equipment. conveyance or implication of any license under any copyrights. military. which is available on request via the local NXP Semiconductors sales office. Legal information 19. The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www. I2C-bus — logo is a trademark of NXP B.3 Disclaimers General — Information in this document is believed to be accurate and reliable. The content is still under internal review and subject to formal approval.V. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information.2 Definitions Draft — The document is a draft version only. expressed or implied. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. 02 — 11 December 2007 47 of 48 . The term ‘short data sheet’ is explained in section “Definitions”.com/profile/terms.4 Trademarks Notice: All referenced brands. Applications — Applications that are described herein for any of these products are for illustrative purposes only. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale. including those pertaining to warranty. unless explicitly otherwise agreed to in writing by NXP Semiconductors. authorized or warranted to be suitable for use in medical. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. This document contains the product specification. In case of any inconsistency or conflict with the short data sheet. aircraft. Exposure to limiting values for extended periods may affect device reliability. In case of any inconsistency or conflict between information in this document and such terms and conditions. 19. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document. 20.com. death or severe property or environmental damage. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. 19. at any time and without notice. 2007. However. as published at http://www. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. including without limitation specifications and product descriptions. intellectual property rights infringement and limitation of liability.1 Data sheet status Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet [1] [2] [3] Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. All rights reserved. For detailed and full information see the relevant full data sheet.V. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title.nxp. send an email to: salesaddresses@nxp.com TDA8594_2 © NXP B. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant. please visit: http://www. service names and trademarks are the property of their respective owners.com For sales office addresses. This document supersedes and replaces all information supplied prior to the publication hereof.

. . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . © NXP B. 2 Ordering information . . . 11 Overvoltage and load dump protection. . . . . . . . Contact information . . .2 19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 7. . . . . . . . . . . . . . . . . . . . . . .16 7. . . . All rights reserved. . . . . .2 7. . . . For more information. . . . . . . . . . . . . . . . . . . . please send an email to: salesaddresses@nxp. .com For sales office addresses.V. . . . . . . . 6 Distortion (clip) detection .12 7. . . . . . . . . . . . . . . . . . 42 Quality information . . . . . . . . . .2 7 7. . . . . . . . . . . . . . 7 Start-up and shut-down sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks . . . . . . . . .7. . . . . . . . . . . . . .11 7. . . . . . . . . . . . . . . . . . . . . . . 42 Package outline . . . . . please visit: http://www.2 7. . . 2007. . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . .1 7. . . . . . . 1 Quick reference data . . . . . . . . . . . . . . . . . . Definitions . . . . . . .2 9 10 11 12 13 13. . . . . .1 7. . . . . . 6 Output protection and short-circuit operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 I2C-bus mode .13 7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Legacy mode (pin ADSEL connected to ground) . . . . . . . . . 6 SOAR protection.4 7. . . . 46 47 47 47 47 47 47 48 Please be aware that important notices concerning this document and the product(s) described herein. Data sheet status . . . . . . . . . . . . . . . . . . . . 6 Speaker protection . . 11 Engine start and low voltage operation. . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 I2C-bus mode .7 7. 6 Standby and mute operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Diagnostics . . . . . .1 8. . . . . . . . .10 7. . . . . . . 27 Performance diagrams .nxp. . . . . . 7 Power-on reset and supply voltage spikes . . . . . . . . . . . . . . . . . . 22 Limiting values. . . . . . . . . . . . . . . . . . . 39 PCB layout . . . . . . . . .6 7. . . . . . . . . . . 41 Test information . . . . . . . . . . . . . . . . . . 16 AC load detection .1 14 14. . . .5 7.1 15 16 17 General description . . . . . . . . . . . . . . 27 Characteristics . . . . . . . 15 Offset detection. . . . . . . . . . . . . . . . . . . 20 Data bytes. . . . . . . . 18 2 I C-bus specification . . .3 19. .17 8 8. . . . . . . . . . .9 7. . . . . . . . . . . . . . . . . . . . . . 43 Mounting. . . . . . . . . . . . . 26 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 6. . 1 General . . . . . . . . . . 16 DC load detection . . . . . . . . . . .7. . . . . . . . . . . 32 Application information. . . . . . . 5 Input stage . . . . . . . . 45 Abbreviations . . . 45 18 19 19. . . . . . . . . . . . . . . . . . . .1 19. . . . . . . . .NXP Semiconductors TDA8594 I2C-bus controlled 4 × 50 W power amplifier 21.3 7. . . . . . . . . . . .com Date of release: 11 December 2007 Document identifier: TDA8594_2 . . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . 19 Instruction bytes . . . . . . . have been included in section ‘Legal information’. . . . . . . . . 3 Pinning information . . .4 20 21 Revision history . . . . . . . . . . . . . . . . Legal information . . 17 I2C-bus diagnostic readout . . Disclaimers. . .1 2. . . . .14 7. . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Contents. . . Contents 1 2 2. . . . . . . .2 3 4 5 6 6. . . . . 14 Thermal pre-warning and thermal protection . . . . . . . . .15 7. . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Output stage . . . .