Features

• 80C52 Compatible
– 8051 Pin and Instruction Compatible – Four 8-bit I/O Ports – Three 16-bit Timer/Counters – 256 Bytes Scratchpad RAM High-speed Architecture 40 MHz at 5V, 30 MHz at 3V X2 Speed Improvement Capability (6 Clocks/Machine Cycle) – 30 MHz at 5V, 20 MHz at 3V (Equivalent to 60 MHz at 5V, 40 MHz at 3V) Dual Data Pointer On-chip ROM/EPROM (8Kbytes) Programmable Clock Out and Up/Down Timer/Counter 2 Asynchronous Port Reset Interrupt Structure with – 6 Interrupt Sources – 4 Level Priority Interrupt System Full Duplex Enhanced UART – Framing Error Detection – Automatic Address Recognition Low EMI (Inhibit ALE) Power Control Modes – Idle Mode – Power-down Mode – Power-off Flag Once Mode (On-chip Emulation) Power Supply: 4.5 - 5.5V, 2.7 - 5.5V Temperature Ranges: Commercial (0 to 70 oC) and Industrial (-40 to 85 oC) Packages: PDIL40, PLCC44, VQFP44 1.4, PQFP44 (13.9 footprint)

• • • • • • • • • • •

8-bit Microcontroller 8 Kbytes ROM/OTP, ROMless TS80C32X2 TS87C52X2 TS80C52X2

• • • •

Description
TS80C52X2 is high performance CMOS ROM, OTP, EPROM and ROMless versions of the 80C51 CMOS single chip 8-bit microcontroller. The TS80C52X2 retains all features of the 80C51 with extended ROM/EPROM capacity (8 Kbytes), 256 bytes of internal RAM, a 6-source, 4-level interrupt system, an on-chip oscilator and three timer/counters. In addition, the TS80C52X2 has a dual data pointer, a more versatile serial channel that facilitates multiprocessor communication (EUART) and an X2 speed improvement mechanism. The fully static design of the TS80C52X2 allows to reduce system power consumption by bringing the clock frequency down to any value, even DC, without loss of data. The TS80C52X2 has 2 software-selectable modes of reduced activity for further reduction in power consumption. In the idle mode the CPU is frozen while the timers, the serial port and the interrupt system are still operating. In the power-down mode the RAM is saved and all other functions are inoperative.

Rev. 4184E–8051–09/02

Table 1. Memory Size
ROM (bytes) TS80C32X2 TS80C52X2 TS87C52X2 0 8k 0 EPROM (bytes) 0 0 8k TOTAL RAM (bytes) 256 256 256

Block Diagram
T2EX (1) P1 P2 P3 RxD TxD Vcc Vss T2 (1)

(3) (3) XTAL1 XTAL2 ALE/ PROG PSEN CPU EA/VPP RD WR (2) (2) Timer 0 Timer 1 INT Ctrl EUART RAM 256x8

ROM /EPROM 8Kx8

Timer2

C51 CORE

IB-bus

Parallel I/O Ports & Ext. Bus Port 0 Port 1 Port 2 Port 3

(2) (2) T0 RESET T1

(2) (2) INT0 INT1 P0

Notes:

1. Alternate function of Port 1 2. Alternate function of Port 3

2

TS8xCx2X2
4184E–8051–09/02

TS8xCx2X2
SFR Mapping
The Special Function Registers (SFRs) of the TS80C52X2 fall into the following categories: • • • • • • • C51 core registers: ACC, B, DPH, DPL, PSW, SP, AUXR1 I/O port registers: P0, P1, P2, P3 Timer registers: T2CON, T2MOD, TCON, TH0, TH1, TH2, TMOD, TL0, TL1, TL2, RCAP2L, RCAP2H Serial I/O port registers: SADDR, SADEN, SBUF, SCON Power and clock control registers: PCON Interrupt system registers: IE, IP, IPH Others: AUXR, CKCON

3
4184E–8051–09/02

Table 2. All SFRs with their address and their reset value
Bit Addressable 0/8 F8h F0h E8h E0h D8 h D0 h C8 h C0 h B8h IP XX00 0000 P3 1111 1111 IE 0X00 0000 P2 1111 1111 SCON 0000 0000 P1 1111 1111 TCON 0000 0000 P0 1111 1111 0/8 TMOD 0000 0000 SP 0000 0111 1/9 TL0 0000 0000 DPL 0000 0000 2/A TL1 0000 0000 DPH 0000 0000 3/B 4/C 5/D 6/E TH0 0000 0000 TH1 0000 0000 AUXR XXXXXXX0 CKCON XXXX XXX0 PCON 00X1 0000 7/F SBUF XXXX XXXX SADDR 0000 0000 AUXR1 XXXX XXX0 SADEN 0000 0000 IPH XX00 0000 PSW 0000 0000 T2CON 0000 0000 T2MOD XXXX XX00 RCAP2L 0000 0000 RCAP2H 0000 0000 TL2 0000 0000 TH2 0000 0000 ACC 0000 0000 B 0000 0000 1/9 2/A 3/B Non Bit Addressable 4/C 5/D 6/E 7/F FFh F7h EFh E7h

DFh

D7h

CFh

C7h

BFh

B0h

B7h

A8h

AFh

A0h

A7h

98h

9Fh

90h

97h

88h

8Fh

80h

87h

Reserved

4

TS8xCx2X2
4184E–8051–09/02

TS8xCx2X2
Pin Configuration
P1.0 / T2 P1.1 / T2EX P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 RST P3.0/RxD P3.1/TxD P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 P3.6/WR P3.7/RD XTAL2 XTAL1 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 VCC VSS1/NIC* P1.1/T2EX P0.0 / A0 P1.4 P1.3 P1.2 P0.1 / A1 P0.2 / A2 P0.3 / A3 P0.4 / A4 P0.5 / A5 P0.6 / A6 P0.7 / A7 EA/VPP ALE/PROG PSEN P2.7 / A15 P2.6 / A14 P2.5 / A13 P2.4 / A12 P2.3 / A11 P2.2 / A10 P2.1 / A9 P2.0 / A8 P1.5 P1.6 P1.7 RST P3.0/RxD NIC* P3.1/TxD P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 7 8 9 10 11 12 13 14 15 16 17 P0.2/AD2 P0.3/AD3 39 38 37 36 35 34 33 32 31 30 29 P0.0/AD0 P0.1/AD1

P1.0/T2

6 5 4 3 2 1 44 43 42 41 40 P0.4/AD4 P0.5/AD5 P0.6/AD6 P0.7/AD7 EA/VPP NIC* ALE/PROG PSEN P2.7/A15 P2.6/A14 P2.5/A13

PDIL/ CDIL40

PLCC/CQPJ 44

18 19 20 21 22 23 24 25 26 27 28
P2.2/A10 P2.3/A11 P2.4/A12 P3.6/WR P3.7/RD NIC* P2.0/A8 P2.1/A9 XTAL2 XTAL1 VSS

VSS1/NIC*

P1.1/T2EX

P0.0/AD0

P0.1/AD1

P0.2/AD2

44 43 42 41 40 39 38 37 36 35 34 P1.5 P1.6 P1.7 RST P3.0/RxD NIC* P3.1/TxD P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 1 2 3 4 5 6 7 8 9 10 11 33 32 31 30 29 28 27 26 25 24 23 P0.4/AD4 P0.5/AD5 P0.6/AD6 P0.7/AD7 EA/VPP NIC* ALE/PROG PSEN P2.7/A15 P2.6/A14 P2.5/A13

PQFP44 VQFP44

12 13 14 15 16 17 18 19 20 21 22
P2.3/A11 P2.4/A12 XTAL1 P3.7/RD NIC* P2.0/A8 XTAL2 P2.1/A9 P2.2/A10 P3.6/WR VSS

*NIC: No Internal Connection

P0.3/AD3

P1.0/T2

VCC

P1.4

P1.3

P1.2

VCC

5
4184E–8051–09/02

Port 2 pins that are externally pulled low will source current because of the internal pull-ups.4 Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. as listed below.2): External interrupt 0 P2.0-P1. Power Supply: This is the power supply voltage for normal. As inputs. Alternate functions for Port 1 include: VCC P0. Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups.1): Serial output port INT0 (P3. Port 3 pins that are externally pulled low will source current because of the internal pull-ups. As inputs. During accesses to external data memory that use 8-bit addresses (MOVX atRi). bidirectional I/O port.0-P3.7 18-25 I/O P3. Port 2 emits the highorder address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX atDPTR). it uses strong internal pull-ups emitting 1s.Mnemonic Pin Number VQFP 1.4 16 39 Type Name and Function DIL VSS Vss1 20 LCC 22 1 I I Ground: 0V reference Optional Ground: Contact the Sales Office for ground connection.0): Timer/Counter 2 external count input/Clockout T2EX (P1.7 40 3932 44 4336 38 I 37-30 I/O P1. Port 1 also receives the low-order address byte during memory programming and verification.7 1-8 2-9 40-44 1-3 I/O 1 2 2128 2 3 2431 40 41 I/O I T2 (P1. Port 0 also inputs the code bytes during EPROM programming. External pull-ups are required during program verification during which P0 outputs the code bytes.1): Timer/Counter 2 Reload/Capture/Direction Control Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Some Port 2 pins receive the high order address bits during EPROM programming and verification: P2. 1319 5.0-P0.0-P2.In this application. Port 3 also serves the special features of the 80C51 family. Port 2 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs.0): Serial input port TXD (P3. it uses strong internal pull-up when emitting 1s.0 to P2. idle and power-down operation Port 0: Port 0 is an open-drain. As inputs. In this application. Port 1 pins that are externally pulled low will source current because of the internal pull-ups. port 2 emits the contents of the P2 SFR. Port 0 pins that have 1s written to them float and can be used as high impedance inputs. RXD (P3.7 1017 11.Port 0 pins must be polarized to Vcc or Vss in order to prevent any parasitic current consumption. Port 0 is also the multiplexed low-order address and data bus during access to external program and data memory. Port 3 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. 7-13 I/O 10 11 12 11 13 14 5 7 8 I O I 6 TS8xCx2X2 4184E–8051–09/02 . Port 1 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs.

6): External data memory write strobe RD (P3. EA will be internally latched on Reset. and can be used for external timing or clocking. PSEN is not activated during fetches from internal program memory. Crystal 2: Output from the inverting oscillator amplifier Type Name and Function DIL 13 14 15 16 17 Reset 9 LCC 15 16 17 18 19 10 ALE/PROG 30 33 27 O (I) PSEN 29 32 26 O EA/VPP 31 35 29 I XTAL1 19 21 15 I XTAL2 18 20 14 O 7 4184E–8051–09/02 . This pin is also the program pulse input (PROG) during EPROM programming.4 9 10 11 12 13 4 I I I O O I INT1 (P3. This pin also receives the 12. or FFFFH (RD). except that two PSEN activations are skipped during each access to external data memory. In normal operation.4): Timer 0 external input T1 (P3.TS8xCx2X2 Mnemonic Pin Number VQFP 1.5): Timer 1 external input WR (P3. ALE is emitted at a constant rate of 1/6 (1/3 in X2 mode) the oscillator frequency. When executing code from the external program memory. PSEN is activated twice each machine cycle. ALE can be disabled by setting SFR’s AUXR. the device executes from internal program memory unless the program counter contains an address greater than 3FFFH (RB) or 7FFFH (RC) EA must be held low for ROMless devices.75V programming supply voltage (VPP) during EPROM programming.3): External interrupt 1 T0 (P3. Program Store ENable: The read strobe to external program memory. If security level 1 is programmed. ALE will be inactive during internal fetches.0 bit. resets the device. Address Latch Enable/Program Pulse: Output pulse for latching the low byte of the address during an access to external memory.7): External data memory read strobe Reset: A high on this pin for two machine cycles while the oscillator is running. With this bit set. Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock generator circuits. Note that one ALE pulse is skipped during each access to external data memory. An internal diffused resistor to VSS permits a power-on reset using only an external capacitor to VCC. If EA is held high. External Access Enable/Programming Supply Voltage: EA must be externally held low to enable the device to fetch code from external program memory locations 0000H and 3FFFH (RB) or 7FFFH (RC).

Description The clock for the whole circuit and peripheral is first divided by two before being used by the CPU core and peripherals.TS80C52X2 Enhanced Features In comparison to the original 80C52. shows the clock generation block diagram. This feature called ”X2” provides the following advantages: • • • • Divide frequency crystals by 2 (cheaper crystals) while keeping same CPU power Save power consumption while keeping same CPU power (oscillator power saving) Save power consumption by dividing dynamically operating frequency by 2 in operating and idle modes Increase CPU power by 2 while keeping same crystal frequency In order to keep the original C51 compatibility. a divider by 2 is inserted between the XTAL1 signal and the main clock input of the core (phase generator). Figure 1. the TS80C52X2 implements some new features. which are: • • • • • • • The X2 option The Dual Data Pointer The 4 level interrupt priority system The power-off flag The ONCE mode The ALE disabling Some enhanced features are also located in the UART and the Timer 2 X2 Feature The TS80C52X2 core needs only 6 clock periods per machine cycle. In X2 mode. Figure 1. X2 bit is validated on XTAL1÷2 rising edge to avoid glitches when switching from X2 to STD mode. as this divider is bypassed. CPU control 8 TS8xCx2X2 4184E–8051–09/02 . This allows any cyclic ratio to be accepted on XTAL1 input. This divider may be disabled by software. Clock Generation Diagram XTAL1 FXTAL 2 XTAL1:2 0 1 FOSC X2 CKCON reg state machine: 6 clock cycles. Figure 2 shows the mode switching waveforms. the signals on XTAL1 must have a cyclic ratio between 40 to 60%.

Do not set this bit. the standard speed is activated (STD mode). 5 4 3 2 1 0 X2 6 - 5 - 4 - 3 - 2 - 1 - 0 X2 Reset Value = XXXX XXX0b Not bit addressable For further details on the X2 feature. Set to select 6 clock periods per machine cycle (X2 mode. Setting this bit activates the X2 feature (X2 mode). At reset. Mode Switching Waveforms XTAL1 XTAL1:2 X2 bit CPU clock STD Mode X2 Mode STD Mode The X2 bit in the CKCON register (See Table 3.Clock Control Register (8Fh) 7 Bit Number 7 6 Bit Mnemonic Description Reserved The value read from this bit is indeterminate.atmel. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. CKCON Register CKCON . CPU and peripheral clock bit Clear to select 12 clock periods per machine cycle (STD mode. Note: In order to prevent any incorrect operation while operating in X2 mode. FOSC=FXTAL /2). For example a free running timer generating an interrupt every 20 ms will then generate an interrupt every 10 ms. FOSC=FXTAL ). Reserved The value read from this bit is indeterminate.) allows to switch from 12 clock cycles per instruction to 6 clock cycles and vice versa. Do not set this bit.TS8xCx2X2 Figure 2.com) 9 4184E–8051–09/02 . user must be aware that all peripherals using clock frequency as time reference (UART. timers) will have their time reference divided by two. Do not set this bit. UART with 4800 baud rate will have 9600 baud rate. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Table 3. Do not set this bit. Reserved The value read from this bit is indeterminate. Reserved The value read from this bit is indeterminate. please refer to ANM072 available on the web (http://www.

Reserved The value read from this bit is indeterminate. Set to select DPTR1.) that allows the program code to switch between them (Refer to Figure 3). Do not set this bit. This bit is a general purpose user flag Reserved Always stuck at 0 Reserved The value read from this bit is indeterminate. Reserved The value read from this bit is indeterminate. Do not set this bit.Dual Data Pointer Register (Ddptr) The additional data pointer can be used to speed up code execution and reduce code size in a number of ways. AUXR1: Auxiliary Register 1 7 Bit Number 7 6 Bit Mnemonic Description Reserved The value read from this bit is indeterminate. Figure 3. 5 4 3 GF3 2 0 1 0 DPS 6 - 5 - 4 3 2 GF3 0 1 - 0 DPS Reset Value = XXXX XXX0 Not bit addressable 10 TS8xCx2X2 4184E–8051–09/02 . Data Pointer Selection Clear to select DPTR0. There are two 16-bit DPTR registers that address the external memory. Do not set this bit. Do not set this bit. The dual DPTR structure is a way by which the chip will specify the address of an external data memory location. Reserved The value read from this bit is indeterminate. Do not set this bit. and a single bit called DPS = AUXR1/bit0 (See Table 5. Use of Dual Pointer External Data Memory 7 0 DPS DPTR1 DPTR0 AUXR1(A2H) DPH(83H) DPL(82H) Table 4.

However. check for 0 terminator 0012 05A2 INC AUXR1 . for example. In simple routines. such as the block move example. Destroys DPTR0. (optional) restore DPS INC is a short (2 bytes) and fast (12 clocks) way to manipulate the DPS bit in the AUXR1 SFR. In other words.. block operations (copy. search . DPTR1.) are well served by using one data pointer as a ’source’ pointer and the other one as a "destination" pointer.#DEST . write the byte to DEST 000F A3 INC DPTR . note: DPS exits opposite of entry state . increment SOURCE address 000C 05A2 INC AUXR1 . address of SOURCE 0003 05A2 INC AUXR1 . switch data pointers 000E F0 MOVX atDPTR. 11 4184E–8051–09/02 . ASSEMBLY LANGUAGE .#SOURCE . increment DEST address 0010 70F6JNZ LOOP . 0000 909000MOV DPTR. but simply toggles it. unless an extra INC AUXR1 is added . only the fact that DPS is toggled in the proper sequence matters. Observe that without the last instruction (INC AUXR1). address of DEST 0008 LOOP: 0008 05A2 INC AUXR1 .atDPTR . Block move using dual data pointers . the routine will exit with DPS in the opposite state.TS8xCx2X2 Application Software can take advantage of the additional data pointers to both increase speed and reduce code size.A . A and PSW . get a byte from SOURCE 000B A3 INC DPTR . switch data pointers 0005 90A000 MOV DPTR. not its actual value. switch data pointers 000A E0 MOVX A. the block move routine works the same whether DPS is '0' or '1' on entry. 00A2 AUXR1 EQU 0A2H . compare. note that the INC instruction does not directly force the DPS bit to a particular state..

Timer underflow occurs when the count in the timer registers TH2 and TL2 equals the value stored in RCAP2H and RCAP2L registers. timer 2 counts down. If DCEN bit in T2MOD is cleared. The overflow also causes the 16-bit value in RCAP2H and RCAP2L registers to be loaded into the timer registers TH2 and TL2. TCLK and CP/RL2 (T2CON). EXF2 does not generate any interrupt. timer 2 acts as an Up/down timer/counter as shown in Figure 4. If DCEN bit is set. 12 TS8xCx2X2 4184E–8051–09/02 . connected in cascade. It is controlled by T2CON register (See Table 5) and T2MOD register (See Table 6). C/T2 selects FOSC/12 (timer operation) or external pin T2 (counter operation) as the timer clock input. as described in the Atmel 8-bit Microcontroller Hardware description. In this mode the T2EX pin controls the direction of count. Timer 2 operation is similar to Timer 0 and Timer 1. Timer 2 has 3 operating modes: capture. Setting TR2 allows TL2 to be incremented by the selected input. It is a 16-bit timer/counter: the count is maintained by two eight-bit timer registers. The underflow sets TF2 flag and reloads FFFFh into the timer registers. timer 2 behaves as in 80C52 (refer to the Atmel 8-bit Microcontroller Hardware description). When T2EX is low. autoreload and Baud Rate Generator. timer 2 counts up. In TS80C52X2 Timer 2 includes the following enhancements: • • Auto-reload mode with up or down counter Programmable clock-output Auto-reload Mode The Auto-reload mode configures timer 2 as a 16-bit timer or event counter with automatic reload.Timer 2 The timer 2 in the TS80C52X2 is compatible with the timer 2 in the 80C52. Timer overflow occurs at FFFFh which sets the TF2 flag and generates an interrupt request. This bit can be used to provide 17-bit resolution. TH2 and TL2. These modes are selected by the combination of RCLK. The EXF2 bit toggles when timer 2 overflows or underflows according to the the direction of the count. When T2EX is high. Refer to the Atmel 8-bit Microcontroller Hardware description for the description of Capture and Baud Rate Generator Modes.

Timer 2 is programmed for the clock-out mode as follows: • • • • • Set T2OE bit in T2MOD register. set TR2 run control bit in T2CON register. At overflow.0). the baud rates and clock frequencies are not independent since both functions use the values in the RCAP2H and RCAP2L registers.TS8xCx2X2 Figure 4. The timer repeatedly counts to overflow from a loaded value. the contents of RCAP2H and RCAP2L registers are loaded into TH2 and TL2. The input clock increments TL2 at frequency FOSC/2. It is possible to use timer 2 as a baud rate generator and a clock generator simultaneously. Auto-reload Mode Up/Down Counter (DCEN = 1) XTAL1 FXTAL FOSC T2 C/T2 T2CONreg TR2 T2CONreg (:6 in X2 mode) :12 0 1 T2EX: (DOWN COUNTING RELOAD FFh FFh (8-bit) (8-bit) if DCEN=1. In this mode. For this configuration. To start the timer. It can be the same as the reload value or a different one depending on the application. timer 2 has a programmable frequency range of 61 Hz (FOSC/216) to 4 MHz (FOSC/4). Clear C/T2 bit in T2CON register. timer 2 operates as a 50%-duty-cycle. The formula gives the clock-out frequency as a function of the system oscillator frequency and the value in the RCAP2H and RCAP2L registers : F osc Clock – OutFrequency = ------------------------------------------------------------------------------------------4 × ( 65536 – RCAP 2 H ⁄ RCAP 2 L ) For a 16 MHz system clock. Determine the 16-bit reload value from the formula and enter it in RCAP2H/RCAP2L registers. Enter a 16-bit initial value in timer registers TH2/TL2. 0=DOWN if DCEN = 0. up counting TOGGL T2CONreg EXF2 TL2 (8-bit) TH2 (8-bit) TF2 T2CONreg TIMER 2 INTERRUPT RCAP2L RCAP2H (8-bit) (8-bit) (UP COUNTING RELOAD VALUE) Programmable Clock-output In the clock-out mode. 1=UP if DCEN=1. The generated clock signal is brought out to T2 pin (P1. 13 4184E–8051–09/02 . timer 2 overflows do not generate interrupts. programmable clock generator (See Figure 5) .

Figure 5. Clock-Out Mode C/T2 = 0 XTAL1 :2 (:1 in X2 mode) TR2 T2CON reg TL2 (8-bit) TH2 (8-bit) OVERFLOW RCAP2L (8-bit) Toggle T2 Q D RCAP2H (8-bit) T2OE T2MOD reg T2EX EXEN2 T2CON reg EXF2 T2CON reg TIMER 2 INTERRUPT 14 TS8xCx2X2 4184E–8051–09/02 .

Must be 0 for clock out mode. 6 EXF2 5 RCLK 4 TCLK 3 EXEN2 2 TR2 1 C/T2# 0 CP/RL2# Reset Value = 0000 0000b Bit addressable 15 4184E–8051–09/02 . Transmit Clock bit Clear to use timer 1 overflow as transmit clock for serial port in mode 1 or 3. Set to capture on negative transitions on T2EX pin if EXEN2=1. Set to use timer 2 overflow as transmit clock for serial port in mode 1 or 3. Set to turn on timer 2. if timer 2 is not used to clock the serial port. CP/RL2# is ignored and timer is forced to Auto-reload on timer 2 overflow. Set by hardware on timer 2 overflow. Timer 2 External Flag Set when a capture or a reload is caused by a negative transition on T2EX pin if EXEN2=1. When set. Must be cleared by software.Timer 2 Control Register (C8h) 7 TF2 Bit Number 7 6 EXF2 5 RCLK 4 TCLK 3 EXEN2 2 TR2 1 C/T2# 0 CP/RL2# Bit Mnemonic Description TF2 Timer 2 overflow Flag Must be cleared by software. falling edge trigger). Set to cause a capture or reload when a negative transition on T2EX pin is detected. Set to use timer 2 overflow as receive clock for serial port in mode 1 or 3. Timer 2 Capture/Reload bit If RCLK=1 or TCLK=1. Clear to Auto-reload on timer 2 overflows or negative transitions on T2EX pin if EXEN2=1. Timer/Counter 2 select bit Clear for timer operation (input from internal clock system: FOSC). if RCLK = 0 and TCLK = 0. EXF2 doesn’t cause an interrupt in Up/down counter mode (DCEN = 1) Receive Clock bit Clear to use timer 1 overflow as receive clock for serial port in mode 1 or 3. Timer 2 External Enable bit Clear to ignore events on T2EX pin for timer 2 operation. T2CON Register T2CON . causes the CPU to vector to timer 2 interrupt routine when timer 2 interrupt is enabled. Timer 2 Run control bit Clear to turn off timer 2.TS8xCx2X2 Table 5. Set for counter operation (input from T2 input pin.

0/T2 as clock input or I/O port. Set to program P1.Timer 2 Mode Control Register (C9h) 7 Bit Number 7 6 Bit Mnemonic Description Reserved The value read from this bit is indeterminate. 5 4 3 2 1 T2OE 0 DCEN 6 - 5 - 4 - 3 - 2 - 1 T2OE 0 DCEN Reset Value = XXXX XX00b Not bit addressable 16 TS8xCx2X2 4184E–8051–09/02 . Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. T2MOD Register T2MOD .0/T2 as clock output. Do not set this bit. Do not set this bit. Set to enable timer 2 as up/down counter. Down Counter Enable bit Clear to disable timer 2 as up/down counter. Timer 2 Output Enable bit Clear to program P1. Reserved The value read from this bit is indeterminate.Table 6. Do not set this bit. Do not set this bit. Reserved The value read from this bit is indeterminate. Reserved The value read from this bit is indeterminate. Do not set this bit.

It provides both synchronous and asynchronous communication modes. UART Timings in Mode 1 RXD Start bit RI SMOD0=X FE SMOD0=1 D0 D1 D2 D3 D4 D5 D6 D7 Stop bit Data byte 17 4184E–8051–09/02 . Framing Error Block Diagram SM0/FE SM1 SM2 REN TB8 RB8 TI RI SCON (98h) Set FE bit if stop bit is 0 (framing error) (SMOD0 = 1) SM0 to UART mode control (SMOD = 0) SMOD1SMOD0 POF GF1 GF0 PD IDL PCON (87h) To UART framing error control When this feature is enabled. 2 and 3). Asynchronous transmission and reception can occur simultaneously and at different baud rates Serial I/O port includes the following enhancements: • • Framing Error Detection Framing error detection Automatic address recognition Framing bit error detection is provided for the three asynchronous modes (modes 1. set SMOD0 bit in PCON register (See Figure 6). If a valid stop bit is not found.TS8xCx2X2 TS80C52X2 Serial I/O Port The serial I/O port in the TS80C52X2 is compatible with the serial I/O port in the 80C52. Subsequently received frames with valid stop bits cannot clear FE bit. RI rises on stop bit instead of the last data bit (See Figure 7. Software may examine FE bit after each reception to check for data errors. Figure 7.). Once set.) bit is set. and Figure 8. To enable the framing bit error detection feature. It operates as an Universal Asynchronous Receiver and Transmitter (UART) in three full-duplex modes (Modes 1. When FE feature is enabled. An invalid stop bit may result from noise on the serial lines or from simultaneous transmission by two CPUs. 2 and 3). only software or a reset can clear FE bit. Figure 6. the receiver checks each incoming data frame for a valid stop bit. the Framing Error bit (FE) in SCON register (See Table 9.

you may enable the automatic address recognition feature in mode 1. a device is identified by a given address and a broadcast address. automatic address recognition enhances the multiprocessor communication feature by allowing the serial port to examine the address of each incoming command frame. bit 0 is a 1. For example: SADDR0101 0110b SADEN1111 1100b Given0101 01XXb The following is an example of how to use given addresses to address different slaves: Slave A:SADDR1111 0001b SADEN1111 1010b Given1111 0X0Xb Slave B:SADDR1111 0011b SADEN1111 1001b Given1111 0XX1b Slave C:SADDR1111 0010b SADEN1111 1101b Given1111 00X1b The SADEN byte is selected so that each slave may be addressed separately. If desired. To support automatic address recognition. The following example illustrates how a given address is formed. 18 TS8xCx2X2 4184E–8051–09/02 . the master must send an address where bit 0 is clear (e. for slaves B and C. Given Address Each device has an individual address that is specified in SADDR register. the receiver sets RI bit in SCON register to generate an interrupt. UART Timings in Modes 2 and 3 RXD Start bit RI SMOD0=0 RI SMOD0=1 FE SMOD0=1 D0 D1 D2 D3 D4 D5 D6 D7 D8 Ninth Stop bit bit Data byte Automatic Address Recognition The automatic address recognition feature is enabled when the multiprocessor communication feature is enabled (SM2 bit in SCON register is set). the SADEN mask byte must be 1111 1111b. Note: The multiprocessor communication and automatic address recognition features cannot be enabled in mode 0 (i. the stop bit takes the place of the ninth data bit.e. Implemented in hardware. For slave A. the SADEN register is a mask byte that contains don’t-care bits (defined by zeros) to form the device’s given address. In this configuration. To communicate with slave A only. To address a device by its individual address.g. This ensures that the CPU is not interrupted by command frames addressed to other devices. Only when the serial port recognizes its own address. The don’t-care bits provide the flexibility to address one or more slaves at a time. Bit RI is set only when the received command frame address matches the device’s address and is terminated by a valid stop bit.Figure 8. bit 0 (the LSB) is a don’t-care bit. setting SM2 bit in SCON register in mode 0 has no effect).

To communicate with slaves A.e. and bit 2 clear (e. Table 7. SADDR Register SADDR .g. and so. e. To communicate with slaves A and B.g. for slaves B and C. a broadcast address is FFh. the SADDR and SADEN registers are initialized to 00h. bit 2 is a don’t care bit. the master must send an address with bit 0 set. SADEN Register SADEN . To communicate with slaves B and C. Reset Addresses On reset. but not slave A. bit 1 clear. 1111 0001b).TS8xCx2X2 1111 0000b). the master can send and address FBh. bit 2 is set. the master must send an address with bits 0 and 1 both set (e. B and C. bit 1 is a 1. the given and broadcast addresses are XXXX XXXXb (all don’t-care bits). Broadcast Address A broadcast address is formed from the logical OR of the SADDR and SADEN registers with zeros defined as don’t-care bits. Slave B:SADDR1111 0011b SADEN1111 1001b Broadcast1111 1X11B.Slave Address Register (A9h) 7 6 5 4 3 2 1 0 Reset Value = 0000 0000b Not bit addressable 19 4184E–8051–09/02 . however in most applications.g.: SADDR 0101 0110b SADEN 1111 1100b Broadcast =SADDR OR SADEN1111 111Xb The use of don’t-care bits provides flexibility in defining the broadcast address. 1111 0011b). that it is backwards compatible with the 80C51 microcontrollers that do not support automatic address recognition. i. Slave C:SADDR=1111 0010b SADEN1111 1101b Broadcast1111 1111b For slaves A and B.Slave Address Mask Register (B9h) 7 6 5 4 3 2 1 0 Reset Value = 0000 0000b Not bit addressable Table 8. For slave A. The following is an example of using broadcast addresses: Slave A:SADDR1111 0001b SADEN1111 1010b Broadcast1111 1X11b. To communicate with all of the slaves. the master must send an address FFh. for slave C. but not slave C. This ensures that the serial port will reply to any address. bit 1 is a don’t care bit.

Receiver Bit 8 / Ninth bit received in modes 2 and 3 Cleared by hardware if 9th bit received is a logic 0. if SM2 = 0. In mode 1. Transmitter Bit 8 / Ninth bit to transmit in modes 2 and 3. /16 in X2 mode) Variable 5 SM2 Serial port Mode 2 bit / Multiprocessor Communication Enable bit Clear to disable multiprocessor communication feature.Serial Control Register (98h) 7 FE/SM0 Bit Number 6 SM1 Bit Mnemonic Description Framing Error bit (SMOD0=1) Clear to reset the error state. This bit should be cleared in mode 0. not cleared by a valid stop bit. In mode 0 RB8 is not used. Set to transmit a logic 1 in the 9th bit. Set by hardware if 9th bit received is a logic 1.Table 9. Set by hardware at the end of the 8th bit time in mode 0 or at the beginning of the stop bit in the other modes. SCON Register SCON . SMOD0 must be cleared to enable access to the SM0 bit Serial port Mode bit 1 Mode Description SM0 SM1 0 0 0 Shift Register 0 1 1 8-bit UART 1 0 2 9-bit UART 1 1 3 9-bit UART 5 SM2 4 REN 3 TB8 2 RB8 1 TI 0 RI 7 FE SM0 6 SM1 Baud Rate FXTAL /12 (/6 in X2 mode) Variable FXTAL /64 or FXTAL/32 (/32. Set by hardware at the end of the 8th bit time in mode 0. Transmit Interrupt flag Clear to acknowledge interrupt. 2 RB8 1 TI 0 RI Reset Value = 0000 0000b Bit addressable 20 TS8xCx2X2 4184E–8051–09/02 . see Figure 7. 4 REN 3 TB8 Clear to transmit a logic 0 in the 9th bit. Set to enable multiprocessor communication feature in mode 2 and 3. SMOD0 must be set to enable access to the FE bit Serial port Mode bit 0 Refer to SM1 for serial port mode selection. in the other modes. and eventually mode 1. and Figure 8. Set by hardware when an invalid stop bit is detected. Set to enable serial reception. Receive Interrupt flag Clear to acknowledge interrupt. RB8 is the received stop bit. Reception Enable bit Clear to disable serial reception.

21 4184E–8051–09/02 .Power Control Register (87h) 7 SMOD1 Bit Number 7 6 SMOD0 Bit Mnemonic SMOD1 Description Serial port Mode bit 1 Set to select double baud rate in mode 1. Do not set this bit. Set by user for general purpose usage. Reserved The value read from this bit is indeterminate. General purpose Flag Cleared by user for general purpose usage. Can also be set by software. Power-down mode bit Cleared by hardware when reset occurs. A warm reset doesn’t affect the value of this bit. Set to enter idle mode.TS8xCx2X2 Table 10. Set to enter power-down mode. General purpose Flag Cleared by user for general purpose usage. PCON Register PCON . Power-off Flag Clear to recognize next reset type. Set by user for general purpose usage. 5 4 POF 3 GF1 2 GF0 1 PD 0 IDL 6 SMOD0 5 - 4 POF 3 GF1 2 GF0 1 PD 0 IDL Reset Value = 00X1 0000b Not bit addressable Power-off flag reset value will be 1 only after a power on (cold reset). Set to to select FE bit in SCON register. Serial port Mode bit 0 Clear to select SM0 bit in SCON register. 2 or 3. Set by hardware when VCC rises from 0 to its nominal voltage. Idle mode bit Clear by hardware when interrupt or reset occurs.

Figure 9. If interrupt requests of the same priority level 22 TS8xCx2X2 4184E–8051–09/02 .x 0 0 1 1 IP.Interrupt System The TS80C52X2 has a total of 6 interrupt vectors: two external interrupts (INT0 and INT1). Each interrupt source can also be individually programmed to one out of four priority levels by setting or clearing a bit in the Interrupt Priority register (See Table 13. These interrupts are shown in Figure 9. shows the bit values and priority levels associated with each combination.). decreasing from high to low priority High priority interrupt TF2 EXF2 Individual Enable Global Disable Low priority interrupt Each of the interrupt sources can be individually enabled or disabled by setting or clearing a bit in the Interrupt Enable register (See Table 12. Priority Level Bit Values IPH. This register also contains a global disable bit. IP 3 INT0 IE0 0 3 TF0 0 3 INT1 IE1 0 3 TF1 0 RI TI 3 0 3 0 Interrupt polling sequence. which must be cleared to disable all interrupts at once.x 0 1 0 1 Interrupt Level Priority 0 (Lowest) 1 2 3 (Highest) A low-priority interrupt can be interrupted by a high priority interrupt.). three timer interrupts (timers 0. 1 and 2) and the serial port interrupt. Interrupt Control System IPH. Table 11. A high-priority interrupt can’t be interrupted by any other interrupt source. If two interrupt requests of different priority levels are received simultaneously. the request of higher priority level is serviced. but not by another low-priority interrupt.) and in the Interrupt Priority High register (See Table 14.

IE Register IE . an internal polling sequence determines which request is serviced. Set to enable external interrupt 0. If EA=1. Set to enable serial port interrupt. Timer 2 overflow interrupt Enable bit Clear to disable timer 2 overflow interrupt. Set to enable external interrupt 1. External interrupt 1 Enable bit Clear to disable external interrupt 1. 5 ET2 4 ES 3 ET1 2 EX1 1 ET0 0 EX0 7 EA 6 - 5 ET2 4 ES 3 ET1 2 EX1 1 ET0 0 EX0 Reset Value = 0X00 0000b Bit addressable 23 4184E–8051–09/02 . Timer 0 overflow interrupt Enable bit Clear to disable timer 0 overflow interrupt.TS8xCx2X2 are received simultaneously. Set to enable timer 2 overflow interrupt. Set to enable timer 1 overflow interrupt. External interrupt 0 Enable bit Clear to disable external interrupt 0. Thus within each priority level there is a second priority structure determined by the polling sequence. Table 12. Reserved The value read from this bit is indeterminate. Set to enable timer 0 overflow interrupt.Interrupt Enable Register (A8h) 7 EA Bit Number 6 Bit Mnemonic Description Enable All interrupt bit Clear to disable all interrupts. Do not set this bit. Timer 1 overflow interrupt Enable bit Clear to disable timer 1 overflow interrupt. Set to enable all interrupts. Serial port Enable bit Clear to disable serial port interrupt. each interrupt source is individually enabled or disabled by setting or clearing its own interrupt enable bit.

Timer 0 overflow interrupt Priority bit Refer to PT0H for priority level. Timer 2 overflow interrupt Priority bit Refer to PT2H for priority level.Interrupt Priority Register (B8h) 7 Bit Number 7 6 Bit Mnemonic Description Reserved The value read from this bit is indeterminate. External interrupt 1 Priority bit Refer to PX1H for priority level. Do not set this bit. Timer 1 overflow interrupt Priority bit Refer to PT1H for priority level. 5 PT2 4 PS 3 PT1 2 PX1 1 PT0 0 PX0 6 - 5 PT2 4 PS 3 PT1 2 PX1 1 PT0 0 PX0 Reset Value = XX00 0000b Bit addressable 24 TS8xCx2X2 4184E–8051–09/02 . Reserved The value read from this bit is indeterminate. Do not set this bit. IP Register IP .Table 13. Serial port Priority bit Refer to PSH for priority level. External interrupt 0 Priority bit Refer to PX0H for priority level.

Timer 2 overflow interrupt Priority High bit PT2H PT2 Priority Level 0 0 Lowest 0 1 1 0 1 1 Highest Serial port Priority High bit PSH PS Priority Level 0 0 Lowest 0 1 1 0 1 1 Highest Timer 1 overflow interrupt Priority High bit PT1H PT1 Priority Level 0 0 Lowest 0 1 1 0 1 1 Highest External interrupt 1 Priority High bit PX1H PX1 Priority Level 0 0 Lowest 0 1 1 0 1 1 Highest Timer 0 overflow interrupt Priority High bit PT0H PT0 Priority Level 0 0 Lowest 0 1 1 0 1 1 Highest External interrupt 0 Priority High bit PX0H PX0 Priority Level 0 0 Lowest 0 1 1 0 1 1 Highest 5 PT2H 4 PSH 3 PT1H 2 PX1H 1 PT0H 0 PX0H 6 - 5 PT2H 4 PSH 3 PT1H 2 PX1H 1 PT0H 0 PX0H Reset Value = XX00 0000b Not bit addressable 25 4184E–8051–09/02 . Reserved The value read from this bit is indeterminate. IPH Register IPH .TS8xCx2X2 Table 14. Do not set this bit.Interrupt Priority High Register (B7h) 7 Bit Number 7 6 Bit Mnemonic Description Reserved The value read from this bit is indeterminate. Do not set this bit.

When Idle is terminated by an interrupt. Accumulator and all other registers maintain their data during Idle. the reset or external interrupt should not be executed before VCC is restored to its normal operating level and must be held active long enough for the oscillator to restart and stabilize. The interrupt will be serviced. the next instruction to be executed after RETI will be the one following the instruction that put TS80C52X2 into power-down mode.0 to be cleared by hardware. The CPU status is preserved in its entirely : the Stack Pointer. In this case the higher priority interrupt service routine is executed. For example. Either a hardware reset or an external interrupt can cause an exit from powerdown.0 causes that to be the last instruction executed before going into the Idle mode. a power-down mode can be invoked by software (Refer to Table 10. Program Status Word. Since the clock oscillator is still running.. Activation of any enabled interrupt will cause PCON. Only external interrupts INT0 and INT1 are useful to exit from power-down. Power-down Exit Waveform INT0 INT1 XTAL1 Active phase Power-down phase Oscillator restart phase Active phase 26 TS8xCx2X2 4184E–8051–09/02 . interrupt must be enabled and configured as level or edge sensitive interrupt input. Figure 10. The port pins hold the logical states they had at the time Idle was activated. The other way of terminating the Idle mode is with a hardware reset. and Serial Port functions. the hardware reset needs to be held active for only two machine cycles (24 oscillator periods) to complete the reset. The flag bits GF0 and GF1 can be used to give an indication if an interrupt occured during normal operation or during an Idle. Timer. Power-down Mode To save maximum power. To properly terminate power-down. VCC can be lowered to save further power. but not to the interrupt. and following RETI the next instruction to be executed will be the one following the instruction that put the device into idle. ALE and PSEN hold at logic high levels. The internal RAM and SFRs retain their value until the power-down mode is terminated. There are two ways to terminate the Idle. When both interrupts are enabled. the oscillator is stopped and the instruction that invoked powerdown mode is the last instruction executed. In power-down mode. Program Counter. an instruction that activates Idle can also set one or both flag bits. the internal clock signal is gated off to the CPU.Idle mode An instruction that sets PCON. Once the interrupt is serviced. the interrupt service routine can examine the flag bits. PCON register). terminating the Idle mode. the oscillator restarts as soon as one of the two inputs is held low and power down exit will be completed when the first input will be released. Holding the pin low restarts the oscillator but bringing the pin high completes the exit as detailed in Figure 10. For that. In the Idle mode.

Exit from power-down by either reset or external interrupt does not affect the internal RAM content. the exit sequence is unchanged. A "one" will leave port floating. The State of Ports During Idle and Power-down Modes Mode Idle Idle Power Down Power Down Program Memory Internal External Internal ALE 1 1 0 PSEN 1 1 0 PORT0 Port Data(1) Floating Port Data(1) Floating PORT1 Port Data Port Data Port Data PORT2 Port Data Address Port Data PORT3 Port Data Port Data Port Data External 0 0 Port Data Port Data Port Data Note: 1. exit from power-down by external interrupt does no affect the SFRs. when execution is vectored to interrupt. PD and IDL bits are cleared and idle mode is not entered. Table 15.TS8xCx2X2 Exit from power-down by reset redefines all the SFRs. Note: If idle mode is activated with power-down mode (IDL and PD bits set). 27 4184E–8051–09/02 . Port 0 can force a "zero" level.

an emulator or test CPU can be used to drive the circuit Table 26. The ONCE mode is invoked by driving certain pins of the TS80C52X2. While the TS80C52X2 is in ONCE mode. the following sequence must be exercised: • • Pull ALE low while the device is in reset (RST high) and PSEN is high. External Pin Status during ONCE Mode ALE Weak pullup PSEN Weak pullup Port 0 Float Port 1 Weak pullup Port 2 Weak pullup Port 3 Weak pullup XTAL1/2 Active 28 TS8xCx2X2 4184E–8051–09/02 . shows the status of the port pins during ONCE mode. Table 16. Normal operation is restored when normal reset is applied.ONCETM Mode (ON Chip Emulation) The ONCE mode facilitates testing and debugging of systems using TS80C52X2 without removing the circuit from the board. Hold ALE low as RST is deactivated.

Set by user for general purpose usage. Set by hardware when VCC rises from 0 to its nominal voltage. reading POF bit will return indeterminate value. Set to enter power-down mode. Idle mode bit Clear by hardware when interrupt or reset occurs. Do not set this bit. Set to to select FE bit in SCON register. 5 4 POF 3 GF1 2 GF0 1 PD 0 IDL 6 SMOD0 5 - 4 POF 3 GF1 2 GF0 1 PD 0 IDL Reset Value = 00X1 0000b Not bit addressable 29 4184E–8051–09/02 .). The power-off flag (POF) is located in PCON register (See Table 17. PCON Register PCON . Set to enter idle mode.Power Control Register (87h) 7 SMOD1 Bit Number 7 6 SMOD0 Bit Mnemonic SMOD1 Description Serial port Mode bit 1 Set to select double baud rate in mode 1. Power-off Flag Clear to recognize next reset type.5V. A cold start reset is the one induced by VCC switch-on. A warm start reset occurs while VCC is still applied to the device and could be generated for example by an exit from power-down. Serial port Mode bit 0 Clear to select SM0 bit in SCON register.5V to 5. POF is set by hardware when VCC rises from 0 to its nominal voltage. Set by user for general purpose usage. General purpose Flag Cleared by user for general purpose usage. General purpose Flag Cleared by user for general purpose usage. The POF value is only relevant with a Vcc range from 4.TS8xCx2X2 Power-off Flag The power-off flag allows the user to distinguish between a “cold start” reset and a “warm start” reset. 2 or 3. Reserved The value read from this bit is indeterminate. Power-down mode bit Cleared by hardware when reset occurs. Table 17. The POF can be set or cleared by software allowing the user to determine the type of reset. For lower Vcc value. Can also be set by software.

Do not set this bit.Auxiliary Register (8Eh) 7 Bit Number 7 6 Bit Mnemonic Description Reserved The value read from this bit is indeterminate. Reserved The value read from this bit is indeterminate. Do not set this bit. ALE is no longer output but remains active during MOVX and MOVC instructions and external fetches. Do not set this bit. Table 18.Reduced EMI Mode The ALE signal is used to demultiplex address and data buses on port 0 when used with external program or data memory. ALE signal can be disabled by setting AO bit. Reserved The value read from this bit is indeterminate. ALE pin is weakly pulled high. During ALE disabling. ALE signal is still generated. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. AUXR Register AUXR . Reserved The value read from this bit is indeterminate. Do not set this bit. In order to reduce EMI. The AO bit is located in AUXR register at bit location 0. Do not set this bit. As soon as AO is set. Nevertheless. 5 4 3 2 1 0 AO 6 - 5 - 4 - 3 - 2 - 1 - 0 AO Reset Value = XXXX XXX0b Not bit addressable 30 TS8xCx2X2 4184E–8051–09/02 . Set to disable ALE operation during internal fetches. Do not set this bit. Reserved The value read from this bit is indeterminate. during internal code execution. ALE Output bit Clear to restore ALE operation during internal fetches.

This will ensure program protection. will return the code in its original.TS8xCx2X2 TS80C52X2 ROM Structure The TS80C52X2 ROM memory is divided in three different arrays: • • • the code array:8 Kbytes. MOVC instruction executed from external program memory returns non encrypted data. protects the on-chip program against software piracy. 1 U U U 2 P U U U: unprogrammed P: programmed Signature bytes The TS80C52X2 contains 4 factory programmed signatures bytes. Table 19. perform the process described in section 9. the signature array:4 bytes. Code verify will still be encrypted by the encryption array if programmed. For this reason all the unused code bytes should be programmed with random values. Every time a byte is addressed during program verify. The algorithm. Refer to Section “Verify Algorithm”. a verification routine will display the content of the encryption array. 6 address lines are used to select a byte of the encryption array. with the encryption array in the unprogrammed state. one important factor needs to be considered. Within the ROM array are 64 bytes of encryption array that are initially unprogrammed (all FF’s). To read these bytes. This byte is then exclusive-NOR’ed (XNOR) with the code byte. Program Lock Bits The lock bits when programmed according to Table 19. If a large block (>64 bytes) of code is left unprogrammed. EA is sampled and latched on reset. If a byte has the value FFh. Verify Algorithm 31 4184E–8051–09/02 . Program Lock bits Program Lock Bits Security level LB1 LB2 LB3 Protection Description No program lock features enabled. the encryption array:64 bytes. when programmed. verifying the byte will produce the encryption byte value. ROM Lock System Encryption Array The program Lock system. will provide different level of protection for the on-chip code and data. MOVC instruction executed from external program memory are disabled from fetching code bytes from internal memory. creating an encrypted verify byte. unmodified form. When using the encryption array.

EA is sampled and latched on reset. This will ensure program protection. with the encryption array in the unprogrammed state. when programmed according to Table 1. and further programming of the EPROM is disabled. If a large block (>64 bytes) of code is left unprogrammed. The algorithm. unmodified form. also verify is disabled. Code verify will still be encrypted by the encryption array if programmed. also external execution is disabled. For this reason all the unused code bytes should be programmed with random values. MOVC instruction executed from external program memory are disabled from fetching code bytes from internal memory. Same as 2. This byte is then exclusiveNOR’ed (XNOR) with the code byte.TS87C52X2 EPROM Structure The TS87C52X2 is divided in two different arrays: • • • the code array: 8 Kbytes the encryption array: 64 bytes the signature array: 4 bytes In addition a third non programmable array is implemented: EPROM Lock System Encryption Array The program Lock system. If a byte has the value FFh. will return the code in its original. when programmed. MOVC instruction executed from external program memory returns non encrypted data. will provide different level of protection for the on-chip code and data. creating an encrypted verify byte. 6 address lines are used to select a byte of the encryption array. When using the encryption array. Within the EPROM array are 64 bytes of encryption array that are initially unprogrammed (all FF’s). Same as 3. one important factor needs to be considered. Program Lock Bits The three lock bits. To read these bytes. 1 U U U 2 P U U 3 4 U U P U U P U: unprogrammed P: programmed WARNING: Security level 2 and 3 should only be programmed after EPROM and Core verification. 32 TS8xCx2X2 4184E–8051–09/02 . perform the process described in section 9. Signature Bytes The TS80/87C52X2 contains 4 factory programmed signatures bytes. Program Lock Bits Security level LB1 LB2 LB3 Protection Description No program lock features enabled.. a verification routine will display the content of the encryption array. verifying the byte will produce the encryption byte value. protects the on-chip program against software piracy. Every time a byte is addressed during program verify.

75V 1 0 1 1 0 33 4184E–8051–09/02 . Table 20. Program Signals: ALE/PROG.0-P1.75V 1 1 1 1 1 Program Lock bit 2 1 0 12.0-P2. the TS87C52X2 is placed in specific set-up modes (See Figure 11.75V 1 1 1 0 0 Program Lock bit 3 1 0 12. EA/VPP.6. PSEN.6 1 P3.0-P0.3. P3.7 1 Verify Code data 1 0 1 1 0 0 1 1 Program Encryption Array Address 0-3Fh 1 0 12.75V 0 1 1 0 1 Read Signature Bytes 1 0 1 1 0 0 0 0 Program Lock bit 1 1 0 12. P2. P3.TS8xCx2X2 EPROM Programming Set-up modes In order to program and verify the EPROM or to read the signature bytes.7 for D0-D7 Control Signals: RST.7. P3.7.6.3 1 P3. Control and program signals must be held at the levels indicated in Table 35. P2. EPROM Set-up Modes Mode Program Code data RST 1 PSEN 0 ALE/ PROG EA/ VPP 12.6 0 P2. Definition of terms Address Lines: P1. P2.7 1 P3.).7.4 respectively for A0-A12 Data Lines: P0.75V P2.

7 RST PSEN P2.7 is used to enable data output.7 P3. Step 2: Input the valid address on the address lines. To verify the TS87C52X2 code the following sequence must be exercised: • • • Step 1: Activate the combination of program and control signals. 34 TS8xCx2X2 4184E–8051–09/02 .). Verify Algorithm Code array verify must be done after each byte or block of bytes is programmed.0-P2. Step 3: Read data on the data lines.0-P0. Step 3: Input the appropriate data on the data lines. In either case. P 2. To program the TS87C52X2 the following sequence must be exercised: • • • • • • Step 1: Activate the combination of control signals. Set-Up Modes Configuration +5V PROGRAM SIGNALS* EA/VPP ALE/PROG P0.6 P3.4 A0-A7 A8-A12 CONTROL SIGNALS* 4 to 6 MHz VSS GND * See Table 31. Repeat step 2 through 3 changing the address for the entire array verification (See Figure 12.0-P1. a complete verify of the programmed array will ensure reliable programming of the TS87C52X2. Verification of the encryption array is done by observing that the code array is well encrypted.Figure 11.7 P2.7 XTAL1 D0-D7 VCC P1.) The encryption array cannot be directly verified. Step 2: Input the valid address on the address lines. Step 4: Raise EA/VPP from VCC to VPP (typical 12. for proper value on these inputs Programming Algorithm The Improved Quick Pulse algorithm is based on the Quick Pulse algorithm and decreases the number of pulses applied during byte programming from 25 to 1. Step 5: Pulse ALE/PROG once.3 P3.6 P2. Step 6: Lower EA/VPP from VPP to VCC Repeat step 2 through 6 changing the address and data for the entire array or until the end of the object file is reached (See Figure 12.75V).

Programming and Verification Signal’s Waveform Programming Cycle A0-A12 D0-D7 Data In Data Out Read/Verify Cycle 100 µs ALE/PROG 12. An exposure of 1 hour is recommended with most of standard erasers. 60h and 61h. Table 35.TS8xCx2X2 Figure 12. or 3 years in room-level fluorescent lighting) could cause inadvertent erasure. should be sufficient.000 Å. Table 21. at a distance of about 25 mm. the encryption array and the lock bits returning the parts to full functionality. Erasure of the EPROM begins to occur when the chip is exposed to light with wavelength shorter than approximately 4. 31h. exposure to these light sources over an extended time (about 1 week in sunlight.000 µW/cm2 rating for 30 minutes. Signature Bytes The TS80/87C52X2 has four signature bytes in location 30h. To read these bytes follow the procedure for EPROM verify but activate the control lines provided in Table 31. If an application subjects the device to this type of exposure. Since sunlight and fluorescent lighting have wavelengths in this range. for Read Signature Bytes. Erasure leaves all the EPROM cells in a 1’s state (FF). it is suggested that an opaque label be placed over the window. shows the content of the signature byte for the TS80/87C52X2.75V 5V 0V EA/VPP Control signals EPROM Erasure (Windowed Packages Only) Erasure Characteristics Erasing the EPROM erases the code array. Signature Bytes Content Location 30h 31h 60h 60h 60h 61h Contents 58h 57h 2Dh ADh 20h FFh Comment Manufacturer Code: Atmel Family Code: C51 X2 Product name: TS80C52X2 Product name: TS87C52X2 Product name: TS80C32X2 Product revision number 35 4184E–8051–09/02 . The recommended erasure procedure is exposure to ultraviolet light (at 2537 Å) to an integrated dose at least 15 W-sec/cm2. Exposing the EPROM to an ultraviolet lamp of 12.

5 mA(4) VOL Output Low Voltage...........5V to + 7 V Voltage on VPP to VSS ... Atmel presents a new way to measure the operating Icc: Using an internal test ROM..-0.. TA = -40°C to +85°C....... port 0 (6) 0. the following code is executed: Label: SJMP Label (80 FE) Ports 1.. 2..5V to VCC + 0....... 1 W(2) 1.......0°C to 70 °C I = industrial .3 VOL2 Output Low Voltage. ports 1...0 mA(4) IOL = 100 µA(4) IOL = 1. F = 0 to 40 MHz...............1 VCC + 0.. Port 0 is tied to FFh........ Exposure to absolute maximum rating conditions may affect device reliability. 2........... In Atmel new devices............ so the power consumption is very low but is not really representative of what will happen in the customer system........... RST Min -0....... VSS = 0 V...... while keeping measurements under Reset.......-40°C to 85 °C Storage Temperature .........5V Power Dissipation ....................... PSEN 0...... -65°C to + 150°C Voltage on VCC to VSS .-0..0 36 TS8xCx2X2 4184E–8051–09/02 .......0... DC Parameters for Standard Voltage TA = 0°C to +70°C... every manufacturer made operating Icc measurements under reset.......7 VCC (6) Typ Max 0.2 VCC + 0. 3 are disconnected. EA = Vcc...... This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied... This value is based on the maximum allowable die temperature and the thermal resistance of the package. VCC = 5V ± 10%........ VSS = 0 V..........45 1............6 mA(4) IOL = 3.. DC Parameters in Standard Voltage Symbol VIL VIH VIH1 Parameter Input Low Voltage Input High Voltage except XTAL1.....5 0..0 0. That’s why.2 mA(4) IOL = 7.... which made sense for the designs were the CPU was running under reset... This is much more representative of the real operating Icc.. RST Input High Voltage....3 Unit V V V V V V V V V V V V Test Conditions IOL = 100 µA(4) IOL = 1...... Table 22..Electrical Characteristics Absolute Maximum Ratings(1) Notes: Ambiant Temperature Under Bias: C = commercial.6 mA(4) IOL = 3..5 mA(4) IOL = 200 µA(4) IOL = 3..2 VCC ....3 VOL1 Output Low Voltage........ Stresses at or above those listed under “ Absolute Maximum Ratings” may cause permanent damage to the device...... F = 0 to 40 MHz. ALE...45 1.. 3 0.5V to + 13 V Voltage on Any Pin to VSS .. 2. XTAL2 is not connected and XTAL1 is driven by the clock..... Power Consumption Measurement Since the introduction of the first C51 devices....-0............ the CPU is no more active during reset..... VCC = 5V ± 10%..... XTAL1....0 0..... RST = Vss..........5 VCC + 0.5 0.................9 0............45 1..

0. X1 mode: (7) mA VCC = 5.3 VOH Output High Voltage.45V < Vin < VCC Vin = 2. ports 1.6 mA IOH = -3.7 VCC .TS8xCx2X2 Table 22. 2.0 mA VCC = 5V ± 10% IOH = -100 µA IOH = -1.5 V V V VCC .0. ports 1.5V(8) ICC idle Power Supply Current Maximum values. 3 VCC . port 0 VCC . DC Parameters in Standard Voltage (Continued) Symbol Parameter Min VCC .7 VCC .9 at16MHz 5.5 Typ Max Unit V V V Test Conditions IOH = -10 µA IOH = -30 µA IOH = -60 µA VCC = 5V ± 10% IOH = -200 µA IOH = -3.0 V Fc = 1 MHz TA = 25°C 2. X1 mode: (7) RST Pulldown Resistor Logical 0 Input Current ports 1.0.5 RRST IIL ILI ITL CIO IPD ICC under RESET Power Supply Current Maximum values.2 mA IOH = -7.3 VOH2 Output High Voltage.1.6 0.2 at16MHz 12. PSEN VCC .0 V < VCC < 5.1 V V V kΩ µA µA µA pF µA Vin = 0.3 Freq (MHz) at12MHz 3. X1 mode: (7) mA VCC = 5.1.0.3 VOH1 Output High Voltage.1.4 3 + 0. 2 and 3 Input Leakage Current Logical 1 to 0 Transition Current.6 Freq (MHz) at12MHz 10.8 at16MHz 7.7 VCC .0.0. 2.ALE.4 Freq (MHz) at12MHz 5.5V(1) ICC operating Power Supply Current Maximum values.5V(3) mA VCC = 5. 3 Capacitance of I/O Buffer Power Down Current 20 (5) 50 90 (5) 200 -50 ±10 -650 10 50 1 + 0.5 mA VCC = 5V ± 10% VCC .25+0.5V(2) 37 4184E–8051–09/02 .45V 0.

5.5V.5V .. PSEN (6) Output High Voltage. 2. Idle ICC is measured with all output pins disconnected. the noise pulse on the ALE line may exceed 0. XTAL1.9 0. 2 and 3 Input Leakage Current Logical 1 to 0 Transition Current. VCC = 2. TCHCL = 5 ns (see Figure 17.2 VCC .6V. VIL = VSS + 0. DC Parameters for Low Voltage Unit V V V V V V V µA µA µA kΩ pF Fc = 1 MHz TA = 25 °C VCC = 2. TA = -40°C to +85°C.5V. A Schmitt Trigger use is not necessary. 3. ICC would be slightly higher if a crystal oscillator used.45 0. XTAL2 N. ICC under reset is measured with all output pins disconnected. ALE.0 V to 5.7 V to 5. ports 1.5V(3) VCC = 2. X1 mode: (7) mA VCC = 3. VIH = VCC 0.2 at12MHz 2 at16MHz 2.5 0.8 mA(4) IOL = 1.C. EA = RST = V SS (see Figure 15. PSEN Logical 0 Input Current ports 1. VCC = 2. VSS = 0 V.4 at16MHz 4. ALE.7 V to 5. X1 mode: (7) mA VCC = 3. EA = RST = Port 0 = VCC. 2.).). 3 (6) Output Low Voltage.). F = 0 to 30 MHz. Typicals are based on a limited number of samples and are not guaranteed.5 0.15 Freq (MHz) + 0. Min -0. 2.DC Parameters for Low Voltage Symbol VIL VIH VIH1 VOL VOL1 VOH VOH1 IIL ILI ITL RRST CIO Parameter Input Low Voltage TA = 0°C to +70°C. Power Down ICC is measured with all output pins disconnected. 3 Output High Voltage.45 0. port 0.0.0 V Test Conditions Input High Voltage except XTAL1. RST = V SS (see Figure 16.2 Freq (MHz) at12MHz 3. ports 1.45V with maxi VOL peak 0.5V .3 Freq (MHz) at12MHz 4. Capacitance loading on Ports 0 and 2 may cause spurious noise pulses to be superimposed on the VOLs of ALE and Ports 1 and 3. TCHCL = 5 ns. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins make 1 to 0 transitions during bus operation.3 V(2) Notes: 1. V IL = VSS + 0.45V < Vin < VCC Vin = 2. 3 RST Pulldown Resistor Capacitance of I/O Buffer 200 10 IPD ICC under RESET Power Down Current 20 10 (5) (5) 50 30 1 + 0.5V.0.0 V to 3. RST Input High Voltage. XTAL2 NC.3 V(3) IOL = 0.C. XTAL1 driven with T CLCH. RST Output Low Voltage. XTAL2 N.1 VCC + 0. In the worst cases (capacitive loading 100pF).7 VCC Typ Max 0.. ports 1.6 at16MHz 5. 6.3 V(8) ICC idle Power Supply Current Maximum values. 2. F = 0 to 30 MHz.8 0. 4.45V 0. port 0.2 1 + 0. Under steady state (non-transient) conditions. VSS = 0 V.2 VCC + 0. EA = VSS. The values listed are at room temperature and 5V.5 VCC + 0.3 V(1) ICC operating Power Supply Current Maximum values. VIH = V CC . Port 0 = VCC.. XTAL1 driven with TCLCH . IOL must be externally limited as follows: Maximum IOL per port pin: 10 mA Maximum IOL per 8-bit port: 38 TS8xCx2X2 4184E–8051–09/02 . X1 mode: (7) mA VCC = 3.6 µA Power Supply Current Maximum values.6 mA(4) IOH = -10 µA IOH = -40 µA Vin = 0.5V. PORT 0 = V CC.9 VCC -50 ±10 -650 50 90 (5) Table 23.9 VCC 0.

The internal ROM runs the code 80 FE (label: SJMP label). 7. Figure 13.C. RST = VSS. P0 EA VCC Figure 15. under reset VCC ICC VCC VCC RST (NC) CLOCK SIGNAL XTAL2 XTAL1 VSS All other pins are disconnected. which is the worst case. 39 4184E–8051–09/02 . ICC would be slightly higher if a crystal oscillator is used. XTAL2 N.0. XTAL1 driven with T CLCH.5V. Operating ICC is measured with all output pins disconnected. ICC Test Condition. Idle Mode VCC ICC VCC Reset = Vss after a high pulse during at least 24 clock cycles RST (NC) CLOCK SIGNAL XTAL2 XTAL1 VSS P0 EA VCC All other pins are disconnected. EA = Port 0 = VCC. For other values.. Measurements are made with OTP products when possible. 2 and 3: 15 mA Maximum total IOL for all output pins: 71 mA If IOL exceeds the test condition. P0 EA VCC Figure 14.TS8xCx2X2 Port 0: 26 mA Ports 1. Pins are not guaranteed to sink current greater than the listed test conditions. 8. Operating ICC Test Condition VCC ICC VCC Reset = Vss after a high pulse during at least 24 clock cycles RST (NC) CLOCK SIGNAL XTAL2 XTAL1 VSS All other pins are disconnected. VIH = V CC . ICC Test Condition. V OL may exceed the related specification. TCHCL = 5 ns (see Figure 17.). please contact your sales office. VIL = VSS + 0.5V.

2. -M and -V ranges. Higher capacitance values can be used. TA = 0 to +70°C (commercial temperature range). ICC Test Condition.. and Table 32.1 AC Parameters Explanation of the AC Symbols Each timing symbol has 5 characters. Table 29. 2.2VCC-0. in pF -M Port 0 Port 1.5V. V SS = 0 V. TA = -40° C to +85°C (industrial temperature range). The first character is always a “T” (stands for time).7 V < V CC < 5. and Table 33.7 V < V CC < 5. 0.5V. gives the maximum applicable load capacitance for Port 0.5V 0. Clock Signal Waveform for ICC Tests in Active and Idle Modes VCC-0. -L range. Table 30. 2. depending on their positions. Table 24. and ALE and PSEN signals. TA = -40°C to +85°C (industrial temperature range). The following is a list of all the characters and what they stand for. Timings will be guaranteed if these capacitances are respected.. Port 1. TLLPL = Time for ALE Low to PSEN Low. 3 ALE / PSEN 100 80 100 -V 50 50 30 -L 100 80 100 Table 5. -L range. VCC = 5V ± 10%.45V TCLCH TCHCL TCLCH = TCHCL = 5ns. stand for the name of a signal or the logical status of that signal. give for each range the AC parameter. Load Capacitance versus speed range. Table 24. 40 TS8xCx2X2 4184E–8051–09/02 . -M and -V ranges. VSS = 0 V. The other characters. 2 and 3. Table 27. VSS = 0 V. Power-down Mode VCC ICC VCC Reset = Vss after a high pulse during at least 24 clock cycles RST (NC) XTAL2 XTAL1 VSS All other pins are disconnected. but timings will then be degraded. VSS = 0 V. P0 EA VCC Figure 17.Figure 16. Example:TAVLL = Time for Address Valid to ALE Low. give the description of each AC symbols. TA = 0 to +70°C (commercial temperature range).7VCC 0. VCC = 5V ± 10%.

) T= 50ns TLLIV= 2T . give the frequency derating formula of the AC parameter. To calculate each AC symbols. take the x value corresponding to the speed grade you need (-M.x = 2 x 50 . and Table 34. Symbol Description Symbol T TLHLL TAVLL TLLAX TLLIV TLLPL TPLPH TPLIV TPXIX TPXIZ TPXAV TAVIV TPLAZ Parameter Oscillator clock period ALE pulse width Address Valid to ALE Address Hold After ALE ALE to Valid Instruction In ALE to PSEN PSEN Pulse Width PSEN to Valid Instruction In Input Instruction Hold After PSEN Input Instruction FloatAfter PSEN PSEN to Address Valid Address to Valid Instruction In PSEN Low to Address Float 41 4184E–8051–09/02 . Max frequency for derating formula regarding the speed grade -M X1 mode Freq (MHz) T (ns) 40 25 -M X2 mode 20 50 -V X1 mode 40 25 -V X2 mode 30 33.3 -L X1 mode 30 33.22 = 78ns External Program Memory Characteristics Table 26.TS8xCx2X2 Table 28. Values of the frequency must be limited to the corresponding speed grade: Table 25. -V or -L) and replace this value in the formula. Table 31..3 -L X2 mode 20 50 Example: TLLIV in X2 mode for a -V part at 20 MHz (T = 1/20E6 = 50 ns): x= 22 (Table 28.

x x 0.x 2T-x 0.x 0. Min 50 35 5 5 78 10 50 30 0 18 122 10 65 18 75 55 Max -L standard mode 30 MHz Units Min 33 52 13 13 98 Max ns ns ns ns ns ns ns ns ns ns ns ns Min 25 42 12 12 Max Table 28. AC Parameters for a Variable Clock: derating formula Symbol TLHLL TAVLL TLLAX TLLIV TLLPL TPLPH TPLIV TPXIX TPXIZ TAVIV TPLAZ Type Min Min Min Max Min Min Max Min Max Max Max Standard Clock 2T-x T-x T-x 4T-x T-x 3T-x 3T-x x T-x 5T-x x X2 Clock T-x 0.5 T .5 T .x 1.Table 27.5 T . AC Parameters for Fix Clock -V X2 mode 30 MHz -M Speed Symbol T TLHLL TAVLL TLLAX TLLIV TLLPL TPLPH TPLIV TPXIX TPXIZ TAVIV TPLAZ 0 18 85 10 15 55 35 0 12 53 10 40 MHz Min 25 40 10 10 70 9 35 25 0 20 95 10 Max 60 MHz equiv. Min 33 25 4 4 45 17 60 50 0 10 80 10 Max -V standard mode 40 MHz -L X2 mode 20 MHz 40 MHz equiv.5 T .5 T .x 1.5 T .5 T .x 2.x x -M 10 15 15 30 10 20 40 0 7 40 10 -V 8 13 13 22 8 15 25 0 5 30 10 -L 15 20 20 35 15 25 45 0 15 45 10 Units ns ns ns ns ns ns ns ns ns ns ns 42 TS8xCx2X2 4184E–8051–09/02 .

Symbol Description Symbol TRLRH TWLWH TRLDV TRHDX TRHDZ TLLDV TAVDV TLLWL TAVWL TQVWX TQVWH TWHQX TRLAZ TWHLH Parameter RD Pulse Width WR Pulse Width RD to Valid Data In Data Hold After RD Data Float After RD ALE to Valid Data In Address to Valid Data In ALE to WR or RD Address to WR or RD Data Valid to WR Transition Data set-up to WR High Data Hold After WR RD Low to Address Float RD or WR High to ALE high 43 4184E–8051–09/02 .TS8xCx2X2 External Program Memory Read Cycle Figure 18. External Program Memory Read Cycle 12 TCLCL TLHLL ALE TLLIV TLLPL TPLPH PSEN TLLAX TAVLL PORT 0 INSTR IN A0-A7 TAVIV PORT 2 ADDRESS OR SFR-P2 ADDRESS A8-A15 ADDRESS A8-A15 TPLIV TPLAZ TPXIX INSTR IN A0-A7 INSTR IN TPXAV TPXIZ External Data Memory Characteristics Table 29.

Table 30. AC Parameters for a Fix Clock -V X2 mode 30 MHz Speed -M 40 MHz Symbol TRLRH TWLWH TRLDV TRHDX TRHDZ TLLDV TAVDV TLLWL TAVWL TQVWX TQVWH TWHQX TRLAZ TWHLH 10 50 75 10 160 15 0 40 7 0 30 160 165 100 30 47 7 107 9 0 27 15 Min 130 130 100 0 18 98 100 70 55 80 15 165 17 0 35 5 Max 60 MHz equiv. Min 125 125 102 0 25 155 160 105 70 103 13 213 18 0 53 95 0 42 222 235 130 Max -L standard mode 30 MHz Units Min 175 175 137 Max ns ns ns ns ns ns ns ns ns ns ns ns ns ns Min 135 135 Max 44 TS8xCx2X2 4184E–8051–09/02 . Min 85 85 60 0 35 165 175 95 45 70 5 155 10 0 45 13 Max -V standard mode 40 MHz -L X2 mode 20 MHz 40 MHz equiv.

x 1.x x 0.x 0.5 T .x 0.5 T .5 T + x 2T-x 0.TS8xCx2X2 Table 31.5 T . AC Parameters for a Variable Clock: Derating Formula Symbol TRLRH TWLWH TRLDV TRHDX TRHDZ TLLDV TAVDV TLLWL TLLWL TAVWL TQVWX TQVWH TWHQX TRLAZ TWHLH TWHLH Type Min Min Max Min Max Max Max Min Max Min Min Min Min Max Min Max Standard Clock 6T-x 6T-x 5T-x x 2T-x 8T-x 9T-x 3T-x 3T+x 4T-x T-x 7T-x T-x x T-x T+x X2 Clock 3T-x 3T-x 2.5 T .x x T-x 4T -x 4.5 T . External Data Memory Write Cycle ALE TWHLH PSEN TLLWL TWLWH WR TLLAX PORT 0 A0-A7 TAVWL PORT 2 ADDRESS OR SFR-P2 ADDRESS A8-A15 OR SFR P2 TQVWX TQVWH DATA OUT TWHQX 45 4184E–8051–09/02 .5 T + x -M 20 20 25 0 20 40 60 25 25 25 15 15 10 0 15 15 -V 15 15 23 0 15 35 50 20 20 20 10 10 8 0 10 10 -L 25 25 30 0 25 45 65 30 30 30 20 20 15 0 20 20 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns External Data Memory Write Cycle Figure 19.x 1.5 T .5 T .x 3.

AC Parameters for a Fix Clock -V X2 mode 30 MHz -M Speed Symbol TXLXL TQVHX TXHQX TXHDX TXHDV 40 MHz Min 300 200 30 0 117 Max 60 MHz equiv. External Data Memory Read Cycle ALE TLLDV TWHLH PSEN TLLWL TRLDV TRLRH RD TLLAX PORT 0 A0-A7 TAVWL PORT 2 ADDRESS OR SFR-P2 TRLAZ ADDRESS A8-A15 OR SFR P2 TAVDV TRHDX DATA IN TRHDZ Serial Port Timing . Symbol Description Symbol TXLXL TQVHX TXHQX TXHDX TXHDV Parameter Serial port clock cycle time Output data set-up to clock rising edge Output data hold after clock rising edge Input data hold after clock rising edge Clock rising edge to input data valid Table 33.External Data Memory Read Cycle Figure 20.Shift Register Mode Table 32. Min 300 200 30 0 117 117 Max -L standard mode 30 MHz Min 400 283 47 0 200 Max ns ns ns ns ns Units Min 300 200 30 0 Max 46 TS8xCx2X2 4184E–8051–09/02 . Min 200 117 13 0 34 Max -V standard mode 40 MHz -L X2 mode 20 MHz 40 MHz equiv.

x X2 Clock 6T 5T-x T-x x 5 T.x 2T-x x 10 T . AC Parameters for a Variable Clock: Derating Formula Symbol TXLXL TQVHX TXHQX TXHDX TXHDV Type Min Min Min Min Max Standard Clock 12 T 10 T .TS8xCx2X2 Table 34.x 50 20 0 133 50 20 0 133 50 20 0 133 -M -V -L Units ns ns ns ns ns Shift Register Timing Waveforms Figure 21. Shift Register Timing Waveforms INSTRUCTION ALE TXLXL CLOCK TQVXH OUTPUT DATA WRITE to SBUF INPUT DATA CLEAR RI 0 TXHDV VALID VALID TXHQX 1 2 TXHDX VALID VALID VALID VALID VALID 3 4 5 6 7 SET TI VALID SET RI 0 1 2 3 4 5 6 7 8 47 4184E–8051–09/02 .

4. VCC = operating range while verifying.EPROM Programming and Verification Characteristics TA = 21°C to 27° C. Table 35. 64KB: up to P3.4-P3.5 48 TS8xCx2X2 4184E–8051–09/02 .5 Max 13 75 6 Units V mA MHz Data Hold after PROG (Enable) High to VPP VPP Setup to PROG Low VPP Hold after PROG PROG Width Address to Valid Data ENABLE Low to Data Valid Data Float after ENABLE EPROM Programming and Verification Waveforms Figure 22. VCC = 5V ± 10% while programming.5.0-P1. 32KB: up to P3. 16KB: up to P2. V SS = 0V. EPROM Programming Parameters Symbol VPP IPP 1/TCLCL TAVGL TGHAX TDVGL TGHDX TEHSH TSHGL TGHSL TGLGH TAVQV TELQV TEHQZ Parameter Programming Supply Voltage Programming Supply Current Oscillator Frquency Address Setup to PROG Low Adress Hold after PROG Data Setup to PROG Low 4 48 TCLCL 48 TCLCL 48 TCLCL 48 TCLCL 48 TCLCL 10 10 90 110 48 TCLCL 48 TCLCL 0 48 TCLCL µs µs µs Min 12.5* P P0 TDVGL TAVGL ALE/PROG TSHGL TGLGH EA/VPP CONTROL SIGNALS (ENABLE) VCC TEHSH VPP TGHSL VCC TELQV DATA IN TGHDX TGHAX ADDRESS VERIFICATION ADDRESS TAVQV DATA OUT TEHQZ * 8KB: up to P2.0-P2. EPROM Programming and Verification Waveforms PROGRAMMING P1.4.5 P3.7 P2.

45V for a logic “0”.2VCC-0.1 AC inputs during testing are driven at VCC .1 V VLOAD-0.45V 0. Timing measurement are made at VIH min for a logic “1” and VIL max for a logic “0”. AC Testing Input/Output Waveforms VCC-0. IOL/IOH ≥ ± 20mA.2VCC+0.5V INPUT/OUTPUT 0. Float Waveforms Figure 25.TS8xCx2X2 External Clock Drive Characteristics (XTAL1) Table 36.2VCC-0.1 V For timing purposes a port pin is no longer floating when a 100 mV change from load voltage occurs and begins to float when a 100 mV change from the loaded VOH/V OL level occurs.0.5V 0. AC Parameters Symbol TCLCL TCHCX TCLCX TCLCH TCHCL TCHCX/TCLCX Parameter Oscillator Period High Time Low Time Rise Time Fall Time Cyclic ratio in X2 mode 40 Min 25 5 5 5 5 60 Max Units ns ns ns ns ns % External Clock Drive Waveforms Figure 23.9 0. 49 4184E–8051–09/02 .7VCC 0. Float Waveforms FLOAT VOH-0. External Clock Drive Waveforms VCC-0.1 V VLOAD+0.1 V TCHCL TCLCX TCHCX TCLCH TCLCL AC Testing Input/Output Waveforms Figure 24.45V 0.5 for a logic “1” and 0.1 V VLOAD VOL+0.

Typically though (TA = 25°C fully loaded) RD and WR propagation delays are approximately 50ns. INT1. P2. Propagation also varies from output to output and component. ranges from 25 to 125 ns. 50 TS8xCx2X2 4184E–8051–09/02 . The other signals are typically 85 ns. P2. Figure 26.Clock Waveforms Valid in normal clock mode. P2. P3) (INCLUDES INT0. P3 PINS SAMPLED NEW DATA P0 PINS SAMPLED INDICATES DPH OR P2 SFR TO PCH TRANSITION PCL OUT (IF PROGRAM MEMORY IS EXTERNAL) PCL OUT (EVEN IF PROGRAM MEMORY IS INTERNAL) INDICATES DPH OR P2 SFR TO PCH TRANSITION RXD SAMPLED RXD SAMPLED This diagram indicates when signals are clocked internally. The time it takes the signals to propagate to the pins. Propagation delays are incorporated in the AC specifications. however. T1) SERIAL PORT SHIFT CLOCK TXD (MODE 0) P1. In X2 mode XTAL2 signal must be changed to XTAL2 divided by two. Clock Waveforms INTERNAL CLOCK XTAL2 ALE EXTERNAL PROGRAM MEMORY FETCH PSEN P0 DATA SAMPLED FLOAT PCL OUT DATA SAMPLED FLOAT PCL OUT DATA SAMPLED FLOAT PCL OUT THESE SIGNALS ARE NOT ACTIVATED DURING THE EXECUTION OF A MOVX INSTRUCTION STATE4 P1P2 STATE5 P1P2 STATE6 P1P2 STATE1 P1P2 STATE2 P1P2 STATE3 P1P2 STATE4 P1P2 STATE5 P1P2 P2 (EXT) READ CYCLE RD INDICATES ADDRESS TRANSITIONS PCL OUT (IF PROGRAM MEMORY IS EXTERNAL) P0 DPL OR Rt FLOAT P2 WRITE CYCLE WR P0 DPL OR Rt DATA OUT P2 PORT OPERATION OLD DATA P0 PINS SAMPLED MOV DEST P0 MOV DEST PORT (P1. TO. P3 PINS SAMPLED P1. This propagation delay is dependent on variables such as temperature and pin loading.

7 to 5.TS8xCx2X2 Ordering Information Table 37.5V 2.5V 2.5V 5V ±10% 5V ±10% 5V ±10% 5V ±10% 5V ±10% 5V ±10% 5V ±10% 2.7 to 5.5V 2.7 to 5.7 to 5.7 to 5.5V 2.7 to 5.5V 2.5V 2.7 to 5.7 to 5. Possible Ordering Entries Part Number TS80C32X2 -MCA TS80C32X2 -MCB TS80C32X2-MCC TS80C32X2-VCA TS80C32X2-VCB TS80C32X2-VCC TS80C32X2-LCA TS80C32X2-LCB TS80C32X2-LCC TS80C32X2-LCED TS80C32X2-MIA TS80C32X2-MIB TS80C32X2-MIC TS80C32X2-VIA TS80C32X2-VIB TS80C32X2-VIC TS80C32X2-VIED TS80C32X2 -LIA TS80C32X2 -LIB TS80C32X2-LIC TS80C32X2-LIED TS80C32X2-EDA TS80C32X2-EDB TS80C32X2-EDC TS80C32X2-EDED TS80C52zzz-MCA TS80C52zzz-MCB TS80C52zzz-MCC TS80C52zzz-VCA Memory Size ROMLess ROMLess ROMLess ROMLess ROMLess ROMLess ROMLess ROMLess ROMLess ROMLess ROMLess ROMLess ROMLess ROMLess ROMLess ROMLess ROMLess ROMLess ROMLess ROMLess ROMLess ROMLess ROMLess ROMLess ROMLess 8K ROM 8K ROM 8K ROM 8K ROM Supply Voltage 5V ±10% 5V ±10% 5V ±10% 5V ±10% 5V ±10% 5V ±10% 2.5V Samples Samples Samples Samples 5V ±10% 5V ±10% 5V ±10% 5V ±10% Temperature Range 0 to 70°C 0 to 70°C 0 to 70°C 0 to 70°C 0 to 70°C 0 to 70°C 0 to 70°C 0 to 70°C 0 to 70°C 0 to 70°C -40 to 85°C -40 to 85°C -40 to 85°C -40 to 85°C -40 to 85°C -40 to 85°C -40 to 85°C -40 to 85°C -40 to 85°C -40 to 85°C -40 to 85°C Samples Samples Samples Samples Samples Samples Samples 0 to 70°C Max Frequency 40 MHz(1) 40 MHz(1) 40 MHz(1) 40 MHz(1) 40 MHz(1) 40 MHz(1) 30 MHz(1) 30 MHz(1) 30 MHz(1) 30 MHz(1) 40 MHz (1) Package PDIL40 PLCC44 PQFP44 PDIL40 PLCC44 PQFP44 PDIL40 PLCC44 PQFP44 VQFP44 PDIL40 PLCC44 PQFP44 PDIL40 PLCC44 PQFP44 VQFP44 PDIL40 PLCC44 PQFP44 VQFP44 PDIL40 PLCC44 PQFP44 VQFP44 PDIL40 PLCC44 PQFP44 PDIL40 Packing Tape & Reel Tape & Reel and Dry Pack Tape & Reel Tape & Reel Tape & Reel and Dry Pack Tape & Reel Tape & Reel Tape & Reel and Dry Pack Tape & Reel Dry Pack Tape & Reel Tape & Reel and Dry Pack Tape & Reel Tape & Reel Tape & Reel Tape & Reel Dry Pack Tape & Reel Tape & Reel Tape & Reel Dry Pack Samples Tape & Reel Tape & Reel Dry Pack Samples Tape & Reel Tape & Reel Tape & Reel 40 MHz(1) 40 MHz(1) 40 MHz (1) 40 MHz(1) 40 MHz (1) 40 MHz(1) 30 MHz (1) 30 MHz(1) 30 MHz (1) 30 MHz(1) Samples Samples Samples Samples 40 MHz (1) 40 MHz(1) 40 MHz (1) 40 MHz(1) 52 4184E–8051–09/02 .

7 to 5.5V Temperature Range 0 to 70°C 0 to 70°C 0 to 70°C 0 to 70°C 0 to 70°C 0 to 70°C 0 to 70°C -40 to 85°C -40 to 85°C -40 to 85°C -40 to 85°C -40 to 85°C -40 to 85°C -40 to 85°C -40 to 85°C -40 to 85°C -40 to 85°C -40 to 85°C Samples Samples 0 to 70°C Samples Samples Samples Samples 0 to 70°C 0 to 70°C 0 to 70°C 0 to 70°C 0 to 70°C 0 to 70°C 0 to 70°C 0 to 70°C Max Frequency 40 MHz(1) 40 MHz(1) 40 MHz(1) 30 MHz(1) 30 MHz(1) 30 MHz(1) 30 MHz(1) 40 MHz(1) 40 MHz(1) 40 MHz(1) 40 MHz(1) 40 MHz(1) 40 MHz(1) 40 MHz(1) 30 MHz(1) 30 MHz(1) 30 MHz(1) 30 MHz(1) Samples Samples Samples Samples 40 MHz(1) 40 MHz (1) Package PLCC44 PQFP44 VQFP44 PDIL40 PLCC44 PQFP44 VQFP44 PDIL40 PLCC44 PQFP44 PDIL40 PLCC44 PQFP44 VQFP44 PDIL40 PLCC44 PQFP44 VQFP44 PDIL40 PLCC44 PQFP44 VQFP44 PDIL40 PLCC44 PQFP44 PDIL40 PLCC44 PQFP44 VQFP44 PDIL40 PLC44 PQFP44 VQFP44 Packing Tape & Reel Tape & Reel Dry Pack Tape & Reel Tape & Reel Tape & Reel Dry Pack Tape & Reel Tape & Reel Tape & Reel Tape & Reel Tape & Reel Tape & Reel Dry Pack Tape & Reel Tape & Reel Tape & Reel Dry Pack Tape & Reel Tape & Reel Tape & Reel Dry Pack Tape & Reel Tape & Reel Tape & Reel Tape & Reel Tape & Reel Tape & Reel Dry Pack Tape & Reel Tape & Reel Tape & Reel Dry Pack 40 MHz(1) 40 MHz(1) 40 MHz(1) 40 MHz(1) 40 MHz(1) 30 MHz(1) 30 MHz(1) 30 MHz(1) 30 MHz(1) 53 TS8xCx2X2 4184E–8051–09/02 .7 to 5.5V 2.7 to 5. Possible Ordering Entries (Continued) Part Number TS80C52zzz-VCB TS80C52zzz-VCC TS80C52zzz-VCED TS80C52zzz-LCA TS80C52zzz-LCB TS80C52zzz-LCC TS80C52zzz-LCED TS80C52zzz-MIA TS80C52zzz-MIB TS80C52zzz-MIC TS80C52zzz-VIA TS80C52zzz-VIB TS80C52zzz-VIC TS80C52zzz-VIED TS80C52zzz-LIA TS80C52zzz-LIB TS80C52zzz-LIC TS80C52zzz-LIED TS80C52zzz-EDA TS80C52zzz-EDB TS80C52zzz-EDC TS80C52zzz-EDED TS87C52-MCA TS87C52-MCB TS87C52-MCC TS87C52-VCA TS87C52-VCB TS87C52-VCC TS87C52-VCED TS87C52-LCA TS87C52-LCB TS87C52-LCC TS87C52-LCED Memory Size 8K ROM 8K ROM 8K ROM 8K ROM 8K ROM 8K ROM 8K ROM 8K ROM 8K ROM 8K ROM 8K ROM 8K ROM 8K ROM 8K ROM 8K ROM 8K ROM 8K ROM 8K ROM 8K ROM 8K ROM 8K ROM 8K ROM 8K OTP 8K OTP 8K OTP 8K OTP 8K OTP 8K OTP 8K OTP 8K OTP 8K OTP 8K OTP 8K OTP Supply Voltage 5V ±10% 5V ±10% 5V ±10% 2.5V 2.5V 2.5V 2.5V 2.7 to 5.5V 2.5V 5V ±10% 5V ±10% 5V ±10% 5V ±10% 5V ±10% 5V ±10% 5V ±10% 2.5V Samples Samples Samples Samples 5V ±10% 5V ±10% 5V ±10% 5V ±10% 5V ±10% 5V ±10% 5V ±10% 2.7 to 5.7 to 5.5V 2.7 to 5.7 to 5.7 to 5.Table 37.7 to 5.7 to 5.5V 2.7 to 5.5V 2.

7 to 5.5V Samples Samples Samples Samples Temperature Range -40 to 85°C -40 to 85°C -40 to 85°C -40 to 85°C -40 to 85°C -40 to 85°C -40 to 85°C -40 to 85°C -40 to 85°C -40 to 85°C -40 to 85°C Samples Samples Samples Samples Max Frequency 40 MHz(1) 40 MHz(1) 40 MHz(1) 40 MHz(1) 40 MHz(1) 40 MHz(1) 40 MHz(1) 30 MHz(1) 30 MHz(1) 30 MHz(1) 30 MHz(1) Samples Samples Samples Samples Package PDIL40 PLCC44 PQFP44 PDIL40 PLCC44 PQFP44 VQFP44 PDIL40 PLCC44 PQFP44 VQFP44 PDIL40 PLCC44 PQFP44 VQFP44 Packing Tape & Reel Tape & Reel Tape & Reel Tape & Reel Tape & Reel Tape & Reel Dry Pack Tape & Reel Tape & Reel Dry Pack Tape & Reel Tape & Reel Tape & Reel Tape & Reel Dry Pack Notes: 1. Tape and Reel available for B. 2. Possible Ordering Entries (Continued) Part Number TS87C52-MIA TS87C52-MIB TS87C52-MIC TS87C52-VIA TS87C52-VIB TS87C52-VIC TS87C52-VIED TS87C52-LIA TS87C52-LIB TS87C52-LIC TS87C52-LIED TS87C52-EA TS87C52-EB TS87C52-EC TS87C52-EE Memory Size 8K OTP 8K OTP 8K OTP 8K OTP 8K OTP 8K OTP 8K OTP 8K OTP 8K OTP 8K OTP 8K OTP 8K OTP 8K OTP 8K OTP 8K OTP Supply Voltage 5V ±10% 5V ±10% 5V ±10% 5V ±10% 5V ±10% 5V ±10% 5V ±10% 2. C and E packages 3.TS8xCx2X2 Table 37.7 to 5.5V 2. Dry pack mandatory for E packages 54 4184E–8051–09/02 .7 to 5. 20 MHz in X2 Mode.7 to 5.5V 2.5V 2.

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