- Wireless Equipment Control Using AT89C51
- fifo code
- power line communication-2
- MAX127-MAX128
- Intelligent Blind Stick
- C.A cptr 4
- HC157
- Second Draft
- Design of various Logic gates and Multiplexer in QCA
- Zero to Five.pptx
- DIG_02 new
- EC1258- Digital Electronics Laboratory Manual [REC]
- CodeExample.txt
- The Juggler Effects Reverser
- unit_6
- LC72723
- L04-Pipelining
- Logic Design Lec3
- 8051 Address Decoding
- AN1602_ADSD_syllabus
- 5.Design.and.Implementation.of.Test.of.Audiometric.based.on.Microcontroller
- New Microsoft Office PowerPoint Presentation
- Virtex-6 FPGA Configurable Logic Block User Guide
- rolling display project - charter 2015 r1
- Fault Tolerant Processor Using Hybrid Hardware Redundancy
- um0150
- Reference Information.pdf
- 00329965 - Quasi-Parallel Resonant DC Link Inverter With Improved PWM Capability
- 6430
- Elec204-lecture08
- Boolean Testing Using Fault Models
- Java Tutorial
- Tut Timing Verilog
- ESO13-2 Founding Fathers1
- tsu_and_th
- Fundamentals of Logic Design with examples
- UART
- Introduction State Machine

)

Text: Charles H. Roth, Jr.

**Fundamentals of Logic Design
**

5th Edition 2004 THOMSON BROOKS/COLE

Review units 1-9

1

**Digital Systems and Switching Circuits
**

Digital system The physical quantities or signals can assume only discrete values Greater accuracy Analog system The physical quantities or signals may vary continuously over a specified range

Review units 1-9

2

Review units 1-9

3

arithmetic unit : binary addition: logic gates.g. digital computer : memory units. arithmetic unit. and transistors to form a gate.Digital Systems and Switching Circuits Design of digital systems System design Breaking the overall system into subsystems Specifying the characteristics of each subsystem E. interconnections Circuit design Specifying the interconnection of specific components such as resistors. diodes.g.g. Flip-Flop: resistors. control unit Logic design Determining how to interconnect basic logic building blocks to perform a specific function E. Flip-Flops. flip-flop or other logic building block E. transistors Review units 1-9 4 . I/O devices. diodes.

Digital Systems and Switching Circuits Many of subsystems of a digital system take the form of a switching network Switching Networks Combinational Networks • No memory Sequential Networks • Combinational Circuits + Memory Review units 1-9 5 .

NOT (Complement) 0′ = 1 1′ = 0 X ′ = 1 if X = 0 and X ′ = 0 if X = 1 Inverter Review units 1-9 6 . and NOT (complement. or inverse).Basic Operations The basic operations of Boolean algebra are AND. OR.

”. A . B=AB AND Gate Review units 1-9 7 .Basic Operations AND Operation Omit the symbol “.

Basic Operations OR operation OR Gate Review units 1-9 8 .

Exclusive-OR and Equivalence Operations Exclusive-OR: 0 ⊕ 0 = 0 0 ⊕1 = 1 1⊕ 0 = 1 1⊕1 = 0 Truth table and gate for X ⊕ Y X ⊕Y =1 if and only if X=1 or Y=1 and X and Y are not both 1. Review units 1-9 9 .

Review units 1-9 10 .Exclusive-OR and Equivalence Operations The equivalence operation( ≡) is defined by The truth table for X ≡ Y is (X ≡Y) =1 if and only if X = Y .

Review units 1-9 11 .Exclusive-OR and Equivalence Operations ( X ≡ Y ) = XY + X ′Y ′ Equivalence is the complement of exclusive-OR: ( X ⊕ Y )′ = ( X ′Y + XY ′)′ = ( X + Y ′)( X ′ + Y ) = XY + X ′Y ′ = ( X ≡ Y ) Alternate symbol for the equivalence gate The equivalence gate is also called an exclusive-NOR gate.

. X n )′ = X 1′ + X 2 Review units 1-9 12 .NAND and NOR Gates NAND gate: An AND gate followed by an NOT gate n-input NAND gates: n=2 F = ( AB )′ = A′ + B′ n=3 F = ( ABC )′ = A′ + B′ + C ′ ′ + .... + X n ′ F = ( X 1 X 2 .

.. + X n )′ = X 1′X 2 Review units 1-9 13 . X n ′ F = ( X 1 + X 2 .NAND and NOR Gates NOR gate: An OR gate followed by an NOT gate n-input NOR gates: n=2 F = ( A + B )′ = A′B′ n=3 F = ( A + B + C )′ = A′B′C ′ ′ ...

Boolean Expressions and Truth Tables Order in which the operations are perform ParenthesesComplentationANDOR Circuits for expressions AB′ + C [ A(C + D )]′ + BE Review units 1-9 14 .

the number of different combinations of values of the variables is 2n. Therefore. a truth table for n-variable expression will have 2n rows. Review units 1-9 15 . ( 2n ) There are 2 functions of n variables.Truth Table If an expression has n variables.

Review units 1-9 16 . (A + B)(C + D) + EF is not in POS form. ( A + B′)(C + D′ + E )( A + C ′ + E ′) . Sum-of-products (SOP) An expression is said to be in sum-of-products form when all products are the products of only single variables. Product-of-sums (POS) An expression is said to be in product-of-sums form when all sums are the sums of only single variables. AB′ + CD′E + AC ′E . AB′C ( D′ + E ) are in POS form. A + B′ + C + D′E are in SOP form. ( A + B)CD + EF is not in SOP form.

The input A. B.Combinational Logic Design Using a Truth Table Example: Design a switching circuit with three inputs A. Sol-1: Review units 1-9 17 . and C and one output f.B. f=1 if N ≥ 0112 and f=0 if N < 0112 . and third bits. and C represent the first. second. for a binary number N. respectively.

B. and C for which f=1.Combinational Logic Design Using a Truth Table Sol-1 (cont. f = A′BC + AB′C ′ + AB′C + ABC ′ + ABC = A′BC + AB′ + AB = A′BC + A = A + BC The circuit is Review units 1-9 18 .): Derive an algebraic expression for f from the truth table by using the combinations of values of A.

and then complement the result.input OR gates and one 3 .input AND gate) = ( A + B )( A + B′ + C ) [Two OR gates and one AND gate] = A + BC Review units 1-9 19 . so f ′ = A′B′C ′ + A′B′C + A′BC ′ f = ( f ′)′ = ( A′B′C ′ + A′B′C + A′BC ′)′ = ( A + B + C )( A + B + C ′)( A + B′ + C ) ( Three 3 . f’ is 1 for input combinations ABC=000. 001. 010.Combinational Logic Design Using a Truth Table Sol-2: First write f’ as a sum of products.

Review units 1-9 20 . but not both.Minterm and Maxterm Expansions Minterm A minterm of n variables is a product of n literals in which each variable appears exactly once in either true or complement form. Maxterm A maxterm of n variables is a sum of n literals in which each variable appears exactly once in either true or complement form. but not both.

Minterm and Maxterm Expansions Minterm and Maxterm for three variables Review units 1-9 21 .

C ) = A′BC + AB′C ′ + AB′C + ABC ′ + ABC f ( A. this is referred to as a minterm expansion or standard sum of products.6. B. C ) = ∑ m(3. C ) = m3 + m4 + m5 + m6 + m7 f ( A. Examples: f ( A. B.7) Review units 1-9 22 . B.5.4.Minterm and Maxterm Expansions Minterm expansion or Standard sum of products When a function is written as a sum of minterms.

B. B.1.2) Review units 1-9 23 . Example: f ( A. C ) = ( A + B + C )( A + B + C ′)( A + B′ + C ) f ( A. B. C ) = M 0 M 1M 2 f ( A. C ) = ∏ M (0.Minterm and Maxterm Expansions Maxterm expansion or Standard product of sums When a function is written as a product of maxterms . this is referred to as a maxterm expansion or standard product of sums.

C ) = m3 + m4 + m5 + m6 + m7 f ′ = (m3 + m4 + m5 + m6 + m7 )′ ′ m4 ′ m5 ′ m6 ′ m7 ′ = M 3M 4 M 5M 6 M 7 = m3 f ( A. C ) = M 0 M 1M 2 ′ + M 1′ + M 2 ′ = m0 + m1 + m2 f ′ = ( M 0 M 1M 2 )′ = M 0 Review units 1-9 24 . Example: f ( A. B. B.Minterm and Maxterm Expansions Complement of a function f .

Review units 1-9 25 . Assume that there are no combinations of values for w.B.Incompletely Specified Functions Incompletely Specified Function A function contains don’t care terms. and z which cause A. Example 1: The output of subcircuit N1 drives the input of the subcircuit N2. The function F is incompletely specified.x..y. and C to assume values of 001 or 110.

Assign 0 to both X’s F = A ′ B ′C ′ + A ′ BC + ABC = A ′ B ′C ′ + BC 2.Incompletely Specified Functions Example 1(cont.6) F = ∏ M (2.6) 1.3.simplest solution F = A′B′C ′ + A′B′C + A′BC + ABC = A′B′ + BC 3.4. Assign 1 to the first X and 0 to the second --.5) ⋅ ∏ D (1. Assign 0 to the first X and 1 to the second F = A′B′C ′ + A′BC + ABC ′ + ABC = A′B′C ′ + A′BC + AB 4.7) + ∑ d (1. Assign 1 to both X’s F = A′B′C′ + A′B′C + A′BC+ ABC′ + ABC= A′B′ + BC+ AB Review units 1-9 26 .): F = ∑ m(0.

The circuit has 4 inputs and 3 outputs : Review units 1-9 27 .Examples of Truth Table Construction Example 2: Design an adder which adds two 2-bit binary numbers to give a 3-bit binary sum.

C . D ) = ∑ m(1.8.6.11.10.15) Y ( A. D ) = ∑ m(2.14.Examples of Truth Table Construction Example 2(cont.3.12. b.3. B.5.14) Review units 1-9 28 .11. B.9. C .): The output functions are : X ( A. C .9.6. D) = ∑ m(7.15) Z ( A.13.4.12.

Design of Binary Adders and Subtracters Half Adder: Review units 1-9 29 .

Design of Binary Adders and Subtracters Full Adder: Review units 1-9 30 .

Design of Binary Adders and Subtracters The logic equation for the full adder: Review units 1-9 31 .

Design of Binary Adders and Subtracters The logic circuit of full adder: Review units 1-9 32 .

Design of Binary Adders and Subtracters 4-Bit Parallel Adder Adds two 4-bit unsigned binary numbers Review units 1-9 33 .

Design of Binary Adders and Subtracters 4-Bit Parallel Adder Review units 1-9 34 .

Unit 5 Karnaugh Maps .

Variable Karnaugh Maps 2.Two.and Three.variable Karnaugh Maps Example: Review units 1-9 36 .

and Three.variable Karnaugh Maps Example: Review units 1-9 37 .Two.Variable Karnaugh Maps 2.

and Three.Two.Variable Karnaugh Maps 3-variable Karnaugh Maps Review units 1-9 38 .

and Three. Review units 1-9 39 . 2k adjacent calls can be combined.Two.Variable Karnaugh Maps Adjacent Cells Two cell which differ in just one variable are said to be adjacent.

Two.Variable Karnaugh Maps If F is given as a minterm (maxterm) expansion. c) = m1 + m3 + m5 = M0M2M4M6M7 Review units 1-9 40 . the map by placing 1’s(0’s) in the squares which correspond to the minterm ( maxterm) and then by filling in the remaining squares with 0’s(1’s).b. Example: F(a.and Three.

and Three. b. c) = abc′ + b′c + a′ Review units 1-9 41 . plot it’s Karnaugh Map.Variable Karnaugh Maps If a function is given in algebraic form.Two. Example: f (a.

5) Review units 1-9 42 .3.Two.and Three.Variable Karnaugh Maps Simplify a function using Karnaugh Map Example: F = ∑ m(1.

Variable Karnaugh Maps Simplify a function using Karnaugh Map Example: Simplify the complement of F = ∑ m(1.3.and Three.Two.5) Review units 1-9 43 .

and Three.Two.Variable Karnaugh Maps Illustrate the Consensus Theorem Example: xy + x′z + yz = xy + x′z Review units 1-9 44 .

2.7) Example: Review units 1-9 45 .and Three.1. f = ∑ m(0.6.5.Variable Karnaugh Maps Minimum sum-of-products is not unique.Two.

Variable Karnaugh Maps 4-Variable Karnaugh Maps Review units 1-9 46 .Four.

b. d ) = acd + a′b + d ′ Review units 1-9 47 .Four.Variable Karnaugh Maps Example: f (a. c.

5.13) f 2 = ∑ m(0.5.10.3.7.14.10.Four.8.4.11.12.3.2.15) Review units 1-9 48 .6.Variable Karnaugh Maps Example: Simplify f1 = ∑ m(1.

13) All the 1’s must be covered.Variable Karnaugh Maps Simplify a function with don’t care Example: f = ∑ m(1.5. Review units 1-9 49 .7. but the X’s are only used if they will simplify the resulting expression.3.9) + ∑ d (6.Four.12.

Variable Karnaugh Maps Find a minimum product-of-sums 1. Complement F’ using DeMorgan’s Theorem Example: Find a minimum product-of-sums for f = x′z′ + wyz + w′y′z′ + x′y f ′ = y′z + wxz′ + w′xy f = ( f ′)′ = ( y + z′)(w′ + x′ + z)(w+ x′ + y′) Review units 1-9 50 . Find a minimum sum-of-products for F’ 2.Four.

Implicant : Given a function F of n variables. if f assumes the value 1 whenever g does.x2. Essential Prime Implicant: If a minterm is covered by only one prime implicant.….Determination of Minimum Expansions Using Essential Prime Implicants Cover: A switching function f(x1.x2. F is also equal 1. then that prime implicant is called an essential prime implicant.…. P=1 implies F=1. Review units 1-9 51 . a product term P is an implicant of F iff for every combination of values of the n variables for which P=1 .xn).That is. Prime Implicant: A prime implicant of a function F is a product term implicart which is no longer an implicant if any literal is deleted from it.xn) is said to cover another function g(x1.

Implicant :函數f在卡諾圖中任何單一個1或 任何一組1可以被合併在一起而形成一個積 項，則被稱為F的含項。 Prime Implicant:若一個積項不能再和其他 項合併消去變數則稱為質含項。 Essential Prime Implicant:某些最小項 (minterm、全及項)只被單一個質含項包 含，如果一個最小項只被一個質含項包 含，則包含此最小項的質含項稱為基本質 含項。 Review units 1-9 52 .

2. then that prime implicant is called an essential prime implicant.Determination of Minimum Expansions Using Essential Prime Implicants On a Karnaugh Map Any single 1 or any group of 1’s (2k 1’s. Review units 1-9 53 . A product term implicant is called a prime implicant if it cannot be combined with another term to eliminate a variable. If a minterm is covered by only one prime implicant.1. k=0.…) which can be combined together on a map of the function F represents a product term which is called an implicant of F.

z=1. g is an implicant of f. g=wxy’ g=1 (w=1.Determination of Minimum Expansions Using Essential Prime Implicants Examples f=wx+yz.x=0. [w=1 does not imply f=1 (w=1.y=0. h=wx is a prime implicant.1+0. g is not a prime implicant. g is a product term.z=0 imply f=0)] Review units 1-9 54 .y=0) implies f=1. The deletion of any literal (w or x) results a new product (x or w) which is not covered by f. f covers g. the resulting term wx is also an implicant of f.x=1. The literal y’ is deleted from wxy’.

5-Variable Karnaugh Maps 5-variable Karnaugh Map Review units 1-9 55 .

31) Review units 1-9 56 . C.30.21.26.4.15.5. B.1.13. D.5-Variable Karnaugh Maps Example : Simplify the function F( A. E) = ∑ m(0.23.22.24.20.28.

Unit 7 Multi-Level Gate Circuits NAND and NOR Gates .

speed up the operation of the digital system Review units 1-9 58 .Multi-Level Gate Circuits Increasing/reducing the number of levels Increasing the number of levels Reduce the required number of gates Reduce the number of gate inputs Increase gate delays Reducing the number of levels Reduce gate delays.

Multi-Level Gate Circuits Example: 4 levels 6 gates 13 gate inputs Review units 1-9 59 .

{NAND} is functionally complete.NOT} is functionally complete. Review units 1-9 60 .OR. and NOT is also functionally complete. {NOR} is functionally complete. Any set of logic gates which can realize AND.Functionally Complete A set of logic operations is said to be functionally complete if any Boolean function can be expressed in terms of this set of operations. {AND.OR.OR} is not functionally complete. {AND.

NOT} is functionally complete. Review units 1-9 61 .NOT} is functionally complete.Functionally Complete {AND. {OR.

Any switching function can be realized using only NAND gates.Functionally Complete {NAND} is functionally complete. Review units 1-9 62 .

Review units 1-9 63 .Functionally Complete {NOR} is functionally complete. Any switching function can be realized using only NOR gates.

Design of Two-level Circuits Using NAND and NOR Gates Example (cont.): Review units 1-9 64 .

): Review units 1-9 65 .Design of Two-level Circuits Using NAND and NOR Gates Example (cont.

11. C .13. D) = ∑ m(11.15) F2 ( A.13. The cost of the resulting circuit is 9 gates and 21 gate inputs. B. D) = ∑ m(3.14. C .Design of Two-Level.15) Sol: Each function is realized individually.7. Review units 1-9 66 .15) F3 ( A. B.13.12. MultipleOutput Circuits Example: Design a circuit with four inputs and three outputs which realizes the functions F1 ( A. B. C .12. D ) = ∑ m(3.7.14.12.

D) = ∑ m( 3.12 . D) = ∑ m(11.7 .12.13.7 .13.15 ) = ABC ′ + CD F3(A.15 ) = A′CD + AB Review units 1-9 67 .12 .C. C .B.B. B.15) = AB + ACD F2(A.14 .C.11.D) = ∑ m( 3.Design of Two-Level.14.): F1 ( A.13. MultipleOutput Circuits Sol (cont.

Design of Two-Level. MultipleOutput Circuits Sol (cont.): Review units 1-9 68 .

MultipleOutput Circuits Sol (cont. F1=AB+ACD F2=ABC’+CD=ABC’+A’CD+ACD F3=A’CD+AB Review units 1-9 69 .): Use the common terms to save gates.Design of Two-Level.

): 4 AND gates 3 OR gates In realizing multiple-output circuits. the use of a minimum sum-of-product implicants for each function does not necessarily lead to a minimum cost solution for the circuit as a whole. MultipleOutput Circuits Sol (cont.Design of Two-Level. Review units 1-9 70 .

Unit 08 Combinational Circuit Design and Simulation Using Gates .

Propagation delay in an inverter Review units 1-9 72 . we say that this gate has a propagation delay of ε .Gate Delays and Timing Diagrams Propagation delay : If the change in output is delayed by time .ε . with respect to the input.

Review units 1-9 73 .Gate Delays and Timing Diagrams Timing Diagram Example: Assume that each gate has a propagation delay of 20 ns (nanoseconds).

Gate Delays and Timing Diagrams Example: Circuit with and delay element Review units 1-9 74 .

Review units 1-9 75 . Static 1. in response to any single input change and for some combination of propagation delays. we say that the circuit has a static 1-hazard.hazard: If . we say that the circuit has a static 0-hazard. Static 0.Hazards in Combinational Logic The unwanted switching transients may appear in the output when different paths from input to output have different propagation delays. a circuit output may momentarily go to 1 when it should remain a constant 0. a circuit output may momentarily go to 0 when it should remain a constant 1.hazard: If . in response to any single input change and for some combination of propagation delays.

Hazards in Combinational Logic Dynamic hazard: If. the output may change three or more times. when output is supposed to change from 0 to 1 (or 1 to 0). Review units 1-9 76 . we say that the circuit has a dynamic hazard.

then F=B+B’=1. F should remain a constant 1 when B changes from 1 to 0. Review units 1-9 77 . If A=C=1.Hazards in Combinational Logic Example: Circuit with a static 1-hazard Assume that each gate has a propagation delay of 10 ns.

Hazards in Combinational Logic Procedure for detecting hazards in a two-level AND-OR circuit 1. 3. 2. Review units 1-9 78 . a 1-hazard exists for the transition between the two 1’s.Write down the SOP expression for the circuit.Plot each term on the map and loop it.If any two adjacent 1’s are not covered by the same loop. this transition occurs when one variable changes and the other n-1 variables are held constant. For an nvariable map.

Hazards in Combinational Logic Eliminating hazards Add a loop to cover two adjacent 1’s. Review units 1-9 79 .

D=0. C changes from 0 to 1 Gate delay : 3 ns for NOT.Hazards in Combinational Logic Example: A circuit with several 0-hazards F=(A+C)(A’+D’)(B’+C’+D) A=0. B=1. 5 ns for AND/OR Review units 1-9 80 .

Hazards in Combinational Logic Example (cont.): Review units 1-9 81 .

): Review units 1-9 82 .Hazards in Combinational Logic Example (cont.

): Eliminating the 0-hazards by looping additional prime implicants that cover the adjacent 0’s that are not covered by a common loop. F = ( A + C)(A′ + D′)(B′ + C′ + D)(C + D′)(A + B′ + D)(A′ + B′ + C′) Review units 1-9 83 .Hazards in Combinational Logic Example (cont.

Decoders.Unit 9 Multiplexers. and Programmable Logic Devices .

or data selector) A MUX has a group of data inputs and a group of control inputs. 2-to 1 MUX A=0. Z=I0 A=1.Multiplexers Multiplexers (MUX. Z=I1 Z=A’I0+AI1 Review units 1-9 85 . The control inputs are used to select one of the data inputs and connect it to the output terminal.

Multiplexers 4-to-1. 2n-to-1 MUX Logic equation for 8-to-1 MUX Z = A′B′C ′I 0 + A′B′CI1 + A′BC ′I 2 + A′BCI 3 + AB′C ′I 4 + AB′CI 5 + ABC ′I 6 + ABCI 7 Review units 1-9 86 . 8-to-1.

Multiplexers Logic Diagram for 8-to-1 MUX Review units 1-9 87 .

Multiplexers

Logic equation for 2n-to-1 MUX

2 n −1 k =0

Z=

∑

mk I k

**where mk is a minterm of the n control variables and I k is the corresponding data input
**

Review units 1-9 88

Multiplexers

Quad Multiplexer Used to Select Data

**A=0, (z0z1z2z3)=(x0x1x2x3) A=1, (z0z1z2z3)=(y0y1y2y3)
**

Review units 1-9 89

Multiplexers

Quad Multiplexer with Bus Input and Output

A=0, Z=X

A=1, Z=Y

Review units 1-9

90

A buffer may be used to increase the driving capability of a gate output. F =C Review units 1-9 91 .Three-State Buffers A gate output can only be connected to a limited number of other device inputs without degrading the performance of a digital system.

Three-State Buffers A logic circuit will not operate correctly if the outputs of two or more gates or other logic devices are directly connected to each other. Review units 1-9 92 . Use of three-state logic permits the outputs of two or more gates or other logic devices to be connected together.

output C=A. This is referred to a Hi-Z (high-impedance) state of the output because the circuit offers a very high resistance or impedance to the flow of current. when B=0. Review units 1-9 93 . C is effectively disconnected from the buffer output so that no current can flow.Three-State Buffers Three-state buffer (Tri-state buffer) Enable input B=1. C acts like an open circuit.

Three-State Buffers Data Selection Using Three-State Buffers D=B’A+BC Review units 1-9 94 .

Three-State Buffers Circuit with Two Three-State Buffers Review units 1-9 95 .

Three-State Buffers Three-state Bus A bus is driven by three-state buffers 4-Bit Adder with four sources for one operand Use a 4-to-1 MUX to select one of several sources Set up a three-state bus Review units 1-9 96 .

Three-State Buffers Bi-directional I/O Pin Buffer is enabled. Input Review units 1-9 97 . Output Buffer is disabled.

3-to-8 Decoder Review units 1-9 98 .Decoders and Encoders Decoder Generates all of minterms Exactly one of the outputs lines will be 1 for each combination of the values of the input variables.

Decoders and Encoders 4-to-10 Line Decoder with Inverted Output Review units 1-9 99 .

Decoders and Encoders 4-to-10 Line Decoder Review units 1-9 100 .

….2n-1 yi=mi .Decoders and Encoders n-to-2n line decoder Generate all 2n minterms (or maxterms) of the n input variables Outputs Noninverted i=0.1.….1. i=0.2n-1 Review units 1-9 101 .2.2. Inverted yi=mi’=Mi .

Decoders and Encoders Use decoder and gates to realize a function Example: Realize the following functions using a decoder. f1 (a. d ) = m4 + m7 + m9 Sol: ′m2 ′ m4 ′ )′ f1 = (m1 ′ m7 ′ m9 ′ )′ f 2 = (m4 Review units 1-9 102 . c. b. c. b. d ) = m1 + m2 + m4 f 2 (a.

Decoders and Encoders Sol: ′m2 ′ m4 ′ )′ f1 = (m1 ′ m7 ′ m9 ′ )′ f 2 = (m4 Review units 1-9 103 .

Decoders and Encoders Encoder The inverse function of a decoder 8-to-3 Priority Encoder Review units 1-9 104 .

Read-Only Memories Read-Only Memory (ROM) Consists of semiconductor devices that interconnected to store binary data Review units 1-9 105 .

F2. Review units 1-9 106 .…Fn) of n variables. A ROM consists of a decoder and a memory array.Read-Only Memories n m 2 A × m ROM can realize m functions (F1.

Review units 1-9 107 . Example: Realize the following functions using ROM.Read-Only Memories Multiple-output combinational circuits can be realized using ROMs.

Read-Only Memories Sol: Review units 1-9 108 .

Read-Only Memories Example: Design a code converter that converts a 4-bit binary number to a hexadecimal digit and outputs the 7-bit ASCII code. Review units 1-9 109 .

The decoder is a 4-to-16 decoder. The ROM size is 16 words by 5 bits.Read-Only Memories ′ . the ROM needs Sol: Because A5 = A4 . Review units 1-9 110 . A6 = A4 only five outputs.

Review units 1-9 111 .Read-Only Memories Types of ROMs Mask-programmable ROMs Programmable ROMs (PROMs) Electrically Erasable Programmable ROMs (EEPROMs. E2PROMs) Flash memories Flash memory has built-in programming and erase capability so that data can be written to it while it is in place in a circuit without the need for a separate programmer.

- Wireless Equipment Control Using AT89C51Uploaded bychi005
- fifo codeUploaded byImran Hayder
- power line communication-2Uploaded bydogudogu
- MAX127-MAX128Uploaded byCarlos Posada
- Intelligent Blind StickUploaded byBanish Gupta
- C.A cptr 4Uploaded bySadaf Rasheed
- HC157Uploaded byaxf9dtjhd
- Second DraftUploaded byVirendra Kumar Pareek
- Design of various Logic gates and Multiplexer in QCAUploaded byijaert
- Zero to Five.pptxUploaded byJacquilyn Ramilo
- DIG_02 newUploaded byboymatter
- EC1258- Digital Electronics Laboratory Manual [REC]Uploaded byjeyaganesh
- CodeExample.txtUploaded byAdan Dube
- The Juggler Effects ReverserUploaded byRui Oliveira
- unit_6Uploaded byravibabukancharla
- LC72723Uploaded byMUHAMMAD SISWANTORO
- L04-PipeliningUploaded byMitali Dixit
- Logic Design Lec3Uploaded bySainath Reddy Duke
- 8051 Address DecodingUploaded byDangthieuhoi Vu
- AN1602_ADSD_syllabusUploaded byJagan Rajendiran
- 5.Design.and.Implementation.of.Test.of.Audiometric.based.on.MicrocontrollerUploaded byجعفرالشموسي
- New Microsoft Office PowerPoint PresentationUploaded byProsenjit Chatterjee
- Virtex-6 FPGA Configurable Logic Block User GuideUploaded byNam Nguyen
- rolling display project - charter 2015 r1Uploaded byapi-281497934
- Fault Tolerant Processor Using Hybrid Hardware RedundancyUploaded byProject Symphony Collection
- um0150Uploaded byJames Earl Cubillas
- Reference Information.pdfUploaded byble310
- 00329965 - Quasi-Parallel Resonant DC Link Inverter With Improved PWM CapabilityUploaded byfatyfrois
- 6430Uploaded bytb77
- Elec204-lecture08Uploaded byMohamed Nabil

- Boolean Testing Using Fault ModelsUploaded byAnkit Singh
- Java TutorialUploaded byAnkit Singh
- Tut Timing VerilogUploaded byAnkit Singh
- ESO13-2 Founding Fathers1Uploaded byAnkit Singh
- tsu_and_thUploaded byAnkit Singh
- Fundamentals of Logic Design with examplesUploaded byAnkit Singh
- UARTUploaded byAnkit Singh
- Introduction State MachineUploaded byAnkit Singh