ONLINE PLATFORM FOR PROGRAMMING AND RESEARCH (OP2R

)

T_TO_D FLIP FLOP CONVERSION VHDL CODE

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;
--------------------------------------------------------entity T_to_D is
Port ( D,clock,reset : in STD_LOGIC;
Q,Q1 : inout STD_LOGIC);
end T_to_D;



Library ieee declaration.
In “ieee” library std_logic_1164 package is
declared for std_logic data types (predefined data
types).

Entity describes circuit external ports.
D, clock, reset: - input port to T flip-flop.
Q, Q1: - output port to T flip-flop.

--------------------------------------------------------architecture structural_con of T_to_D is
--------------------------------------------------------signal s1:std_logic;
---------------------------------- Signal s1 is declared to hold a particular
component t_ff is
value. These are acting as inout ports.
 Components (t_ff and xor_1) declaration.
port (t,clk,rst:in std_logic;
 Declarative part of D flip-flop’s
y,z:out std_logic);
architecture.
end component;
 Components represent the structure of
----------------------------------converted flip-flop circuit.
component xor_1 is
 Xor_1 component represents XOR
port (o,p:in std_logic;
operation in digital circuit.
q:out std_logic);
end component;
-----------------------------------begin
Architecture begins.
------------------------------------------------------------------------

a1:xor_1 port map (D,Q,s1);

ff: t_ff port map (s1,clock,reset,Q,Q1);
-------------------------------------------------------------------------end structural_con;

INFOOP2R.WIX.COM/OP2R

Statements part of the
architecture.
Components are port mapped to
perform D flip flop operation.