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A 32 kb 10T sub-threshold sram array with bitinterleaving and differential read scheme in 90 nm CMOS
Ik Joon Chang Jae-Joon Kim Sang Phill Park Kaushik Roy

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Chang, Ik Joon; Kim, Jae-Joon; Park, Sang Phill; and Roy, Kaushik, "A 32 kb 10T sub-threshold sram array with bit-interleaving and differential read scheme in 90 nm CMOS" (2009). ECE Faculty Publications. Paper 8.

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In this bit-interleaved structure. In conventional SRAMs. robust subthreshold operation of SRAM. we propose a fully differential 10T subthreshold SRAM [6]. To verify the proposed techniques. 44. Kim is with the IBM T. The proposed bit-cell also provides efficient bit-interleaving structure to achieve soft-error tolerance with conventional Error Correcting Codes (ECC). In this work. J. and K. Chang. For example.-J. incurring functional failures during read access. The low voltage operation (below 400 mV) of such designs has been successfully demonstrated in real silicon measurements [2]. FEBRUARY 2009 A 32 kb 10T Sub-Threshold SRAM Array With Bit-Interleaving and Differential Read Scheme in 90 nm CMOS Ik Joon Chang. P. However. the single-end 8T and 10T SRAMs suffer from small bitline swing in subthreshold operation. researchers have considered different configuration SRAMs for subthreshold operations having single-ended 8T or 10T bit-cells for improved stability. a peripheral circuit called buffer-foot has been proposed [4]. Since the read stability and the writability have conflicting design requirements. In the subthreshold region. It has been shown that conventional 6T SRAMs fail to achieve reliable subthreshold operation. In this paper.22x of 6T). However. I.00 © 2009 IEEE . Roy was supported in part by Semiconductor Research Corporation and by a grant from Boeing Corporation. J. S. SER can be much larger than that in the superthreshold region. The contributions of this work can be summarized as follows: • Our bit-cell provides isolation of read and write operations leading to improved noise margin.g. it is extremely difficult to operate the 6T SRAM in the subthreshold region. In addition. However. It ensures read SNM to be almost the same as hold SNM. The subthreshold operation of the designs with these techniques has been verified through hardware measurement data as well [3]. Current version published January 27. conventional 6T SRAM experiences poor read stability or weak writability [3]. For read access. The work of I. and we employ dynamic DCVSL scheme to compensate bitline leakage noise. the single-end 8T or 10T SRAMs cannot efficiently deal with multiple bit soft-errors.650 IEEE JOURNAL OF SOLID-STATE CIRCUITS. enhancing read stability and writability simultaneously. voltage scaling in SRAM. in [8] is also reduced the subthreshold region. stable operation of SRAMs is critical for the success of low-voltage SRAMs. due to parameter variations in scaled technologies.. operating memory circuits at such a low voltage is more challenging since SRAM yield degrades Manuscript received April 06. NY 10598 USA (e-mail: jjkim2@us. revised November 11. soft-error rate (SER) increases [7]. Hence. IEEE. Chang. 0018-9200/$25. The hardware measurement results demonstrate that this bit-cell array successfully operates down to 160 mV. Yorktown Heights. the multiple-bit soft errors can be a real issue. Measurement results show that the leakage power of the proposed bit-cell is close to that of the 6T (between 0. [10] employed Schmitt-trigger based SRAM cell. 2008. Sang Phill Park. Color versions of one or more of the figures in this paper are available online at http://ieeexplore. Jae-Joon Kim. the single-ended sensing methods suffer from reduced bit-line swing due to bit-line leakage noise. While these bit-cells improve SRAM stability in subthreshold region significantly. and Kaushik Roy. we propose a differential 10T bit-cell that effectively separates read and write operations. [5]. kaushik@purdue. NO. In these schemes. due to pseudo-read problem [5]. [5] SRAMs have been explored. Index Terms—Low voltage SRAM design. Watson Research Center. A virtual ground scheme has been proposed to utilize the small bitline swing more efficiently [5]. junction leakage) still degrade the bitline swing significantly. In addition. P. improving read stability significantly.2011972 considerably at these low voltages. Roy are with the School of Electrical and Computer Engineering. [4]. For leakage power comparison. we also fabricated 49 kb arrays of the 6T and the proposed 10T bit-cells. data nodes are fully decoupled from read access. we may not obtain efficient bit-interleaving structure in the 8T and 10T subthreshold SRAMs [3]. single-end 8T [4] or 10T [3]. the raised virtual ground also reduces the sense margin of the following inverter buffer and hence. 2008. adjacent bits are implemented as different logic words. INTRODUCTION P ORTABLE applications such as implantable medical devices and wireless sensor networks require ultra-low power dissipation. park143@purdue. West Lafayette. On the other hand.96x and 1. efficient bit-interleaving in column may not be possible and hence. 2009. To further increase read SNM. This technique can mitigate the subthreshold leakage noise current from bitline. Purdue University. IN 47907 USA (e-mail: ichang@purdue. Many researchers have explored digital subthreshold logic [1]. this scheme may not improve the sense margin effectively. researchers have considered different configuration for SRAM cells. critical charge due to low gate capacitance and hence. However.2008. other leakage components (e. conventional Error Correction Code (ECC) can address multiple bit soft-errors easily [9]. Park.1109/JSSC. Moreover. VOL. S. which can have large impact on SRAM operation in the subthreshold region. Student Member. IEEE Abstract—Ultra-low voltage operation of memory cells has become a topic of much interest due to its applications in very low energy computing and communications. 2. a 32 kb array of the proposed 10T bit-cell is fabricated in 90 nm CMOS technology. As supply power scales down. To overcome this problem. In addition. thereby improving bitline thereby achieving high cell stability. several design techniques such as supply power gating [3] and long-channel access transistors [5] also have been proposed for writability improvement. Digital Object Identifier 10. [2] as a possible option to deliver this requirement. Nonetheless. To improve the bitline swing.

But. four columns have a common VGND node. Therefore. In our 10T cell. 3. Fig. as shown in Fig. the read value is developed as an inverted signal of cell data and hence. In this scheme.CHANG et al. In this scheme. writability. VGND node can be shared by several SRAM cells. as shown in Fig. 1. It threatens the hold stability of other rows sharing the supply power line. the read SNM of our 10T cell is almost same as the hold SNM of conventional 6T cell. providing large bitline swing. PROPOSED 10T SUBTHRESHOLD SRAM A. To verify the proposed technique. The operating principle of our 10T SRAM can be summarized as follows using the timing diagram in Fig. resulting in large area penalty individual (more than 50% in thin-cell layout assuming poly pitch cannot Fig. Depending on the cell data value. both WL and transfer the write data to cell node from bitlines. 2. soft-error tolerance can be achieved with conventional ECC. degrading read current significantly. 5. 2. writability is a critical issue. 4 shows that such boosting provides good writability even in the worst-case process corner (Slow NMOS and Fast PMOS). In this work. be altered [11]). 1(a)). The and VGND is forced to 0 V while makes data nodes (‘Q’ and ‘QB’) decoupled disabled from bitline during the read access. 100 mV (at 300 mV Since the gate input boosting overwhelms sizing effect in the subthreshold region. 1(b)). stability of the SRAM cells in other row sharing the To operate this technique successfully. This timing diagram explains the operating principle of our 10T SRAM. we made the pull-down transistor of the VGND driver four times larger than the evaluation transistors of an SRAM cell (NL and NR in Fig. 300 mV II. weak writability is another major challenge for subthreshold SRAMs. one of the bitlines starts discharging after WL is enabled. each row should have line (Fig. In read mode. The measurement results show that our SRAM successfully operates below . we fabricated the proposed bit-cell in 32 kb SRAM array in 90 nm CMOS. Since hold SNM is much larger than read SNM in the 6T cell. The Proposed 10T SRAM and Operating Principle Fig. 3(a). Fig. However. (a) Our proposed 10T SRAM cell (b) SNM comparison of conventional 6T and our 10T cells.: A 32 KB 10T SUB-THRESHOLD SRAM ARRAY WITH BIT-INTERLEAVING AND DIFFERENTIAL READ SCHEME IN 90 NM CMOS 651 Fig. • Dynamic Differential Cascade Voltage Switch Logic (DCVSL) scheme is employed for read access. 1(a) shows our proposed 10T SRAM cell [6]. As discussed in the introduction. Hence. In this work. we employed dynamic-threshold MOS (DTMOS) technique for the VGND driver (Fig. as shown in Fig. In some previous is collapsed to enhance subthreshold SRAMs [3]. subthreshold component of bitline leakage current is significantly reduced due to stacked bitline leakage path. • During hold mode. the . To mitigate this effect. 1(a). it also degrades hold line. Due to this isolation. 5). In order to reduce the area overhead of a VGND driver. Note that the pull-down strength of the VGND driver can be weakened due to process variations. we boost and by ) to compensate weak writability. (b) For the successful operation of the supply power collapsing. WL is enabled remains disabled. • A column-by-column write control enables implementation of bit-interleaving structure efficiently. (a) In the previous works [3]. individual supply power line is required. bitline leakage noise is compensated by the drive current of a keeper. [4]. this scheme incurs large area penalty. we exchange the position of BL and BLB. Since our 10T cell has series access transistors. read stability is remarkably improved in our 10T cell (Fig. we can obtain strong writability without incurring large area penalty in spite of having series access transistors. 3(b)). [4]. are enabled to During write mode. supply power is collapsed for the write.

5. pull-down of NMOS is much stronger than pull-up of PMOS in short-channel length region (a) Minimum width NMOS drive current in 90 nm CMOS (b) Drive current ratio between minimum width NMOS and PMOS. VOL. 6. . For Fig. (a) Voltage transfer characteristic curves of write mode at V and V are boosted by 100 mV. Since NMOS shows extreme Vt-roll off [13] in 90 nm CMOS. Fig. NO. For example. subthreshold SRAM compared to superthreshold SRAM. Read (Hold) SNM simulation results (V = 300 mV. pull-down device is forward-biased during read. threshold voltage varies significantly in small geometry transistors. Gate Length Modulation In sub-100 nm technologies. Since transistor current is extremely sensitive to variation in the subthreshold region and the small size transistors are employed in an SRAM variation may have larger impact on the stability of cell. entire simulations.652 IEEE JOURNAL OF SOLID-STATE CIRCUITS. T = 25 C). The gate length modulation from 80 nm to 120 nm improves overall read (hold) SNM significantly. enhancing the drive current. 44. the forward biasing current is not critical. V = 300 mV. 7. 2. NMOS transistors experience large roll-off [13] in Fig. B. the DTMOS technique may incur faulty operations due to forward biasing current of PN junction. Since our SRAM is designed for subthreshold operation (below 300 mV). 4. In superthreshold operation. FEBRUARY 2009 Fig. SRAM Array architecture and a VGND driver. (b) Monte Carlo simulation results for the write margin (write SNM).

multiple bit errors are regarded as single bit errors of several logic words. 9 ( . overall write delay increases since additional read operation is needed before write. Bit-interleaving structure may not be efficiently applicable in the previous subthreshold SRAMs [3]–[5]. III. The Fig. For the cell sharing 6T cell. adjacent bits need to be implemented as the same logic word. Hence. multiple bit soft-errors can be corrected by bit-interleaving and ECC [9].: A 32 KB 10T SUB-THRESHOLD SRAM ARRAY WITH BIT-INTERLEAVING AND DIFFERENTIAL READ SCHEME IN 90 NM CMOS 653 Fig. extra read operation is required for a write. in this scheme. bit-interleaving enables us to handle multiple bit soft-errors efficiently. Fig. Compared to the cell with the minimum channel length transistors. The worst-case data pattern of the single-end 8T SRAM [4]. writing a cell hardly affects the hold stability of other cells in the proposed 10T SRAM [6]. SER in 0. For these SRAMs. In this situation. Monte Carlo simulation shows that the hold stability is almost comparable to that of the conventional short-channel length region of the technology which we use for this paper. degrading their hold stability significantly. Bitline swing simulation results of Fig. it is clear that soft-error is more critical in subthreshold SRAMs compared to its superthreshold counterpart. To avoid this problem. 6(b)). EFFICIENT BIT-INTERLEAVING FOR SOFT-ERROR IMMUNITY According to [7].6% improvement in the mean value of read (hold) SNM. Since the variation of drive current ratio between NMOS and PMOS starts to stabilize around 120 nm gate length (Fig. The effectiveness of this gate length modulation can be verified through Monte Carlo (MC) simulation. this scheme increases total write power dissipation. These effects degrade read and hold stability of SRAM considerably. Since conventional ECC techniques can detect and correct single bit errors.CHANG et al. Low gate capacitance of weak inverthan that in 1. 10. the entire cells sharing a word line Fig. To mitigate this problem. 9. 8. as shown in Fig.2 V sion makes the problem worse due to the reduction of critical charge (Qc) [8]. the short-channel roll-off makes transistor current more sensitive to other parameter variations such as line-edge roughness [14]. [5] employs a write after read scheme for bit-interleaving. In the bit-interleaving structure. V = 300 mV are written at the same time in [3].3 V can be 8. making the SRAMs exposed to multiple bit soft-errors. typical process corner) We measured the bitline swing at steady-state after RWL turns on. the read operation consumes comparable power to the write in one column. other cells sharing a word line suffer from pseudo-read problem [5] while writing into a cell.6X higher . As shown . [4]. It should also be noted that due to full-swing read. pull-down transistor becomes much stronger than pull-up transistor at short-channel lengths (Fig. On the other hand. the cell with 120 nm channel length transistors provides 114. we employ 120 nm length for the pull-up PMOS’s and pull-down NMOS’s in the proposed SRAM cell. In addition. If we consider the read power of unselected columns. 6(b)). which is the worst-case process corner for read and hold stability. In conventional SRAMs. In addition. In such a scenario. W WL with the written cell. 6(a). A soft-error may flip adjacent multiple bits simultaneously [9]. we need to modulate transistor gate length. SER increases by 18% for every 10% reduction and hence. However. 7 shows 4000 Monte-Carlo (MC) simulation results for the read (hold) SNM of two different gate length 10T SRAM cells at fast NMOS and slow PMOS corner.

(a) Column architecture of our SRAM (b) The figure of (a) is unfolded equivalently. bitline leakage noise reduces bitline swing considerably. is improved by 59%. To mitigate the bitline leakage noise. bitline swing degrades much larger than the ‘ at 32 cells per bitline). At the considerably (below 0. 44. which is more critical in SRAM design. is shared by the cells in a column. Since such a scheme relies on the trip voltage of an inverter or an absolute reference voltage. the rise of WL does not influence hold stability of unwritten cells sharing the WL. However. buffer-foot scheme is employed in [4] to increase bitline swing. Since the hold stability of adjacent cells is not affected during a write. Moreover. MC simulation results in Fig. which are measured at steady-state after RWL turns on. mean hold SNM of these cells has 2. It is because the drive current flowing through NMOS transistors (NL and NR) from VGND node compensates weak pull-up current at fast NMOS and slow PMOS corner. The data input pattern shows the worst-case leakage scenario of our SRAM. bit-interleaving can be implemented efficiently in our design. RBL should not be and discharged.4% improvement compared to that of conventional 6T cell. We simulated this scenario in a 90 nm CMOS technology. of other columns are still maintained at 0 V. For example. Fig. DIFFERENTIAL READ SCHEME A. VOL. The graph of Fig. Hence. is In low temperature region. 8 indicate that the hold stability of unwritten cells sharing does not degrade during write as well. NO. we believe that a differential read scheme is more appropriate for subthreshold operation. due to slow speed and small threshold operation.5 worse-case process corner.5 . Since ‘QB’ of the accessed cell is ‘0’. When the of a column is raised for writing a cell. These make it difficult to distinguish logic high and low from the developed bitline swing and hence. junction leakage noise ’ and hence. . 10 shows the simulation results of the bitline swing. junction leakage noise compenAlthough other subthreshold leakage current ’ decreases exponentially sates for the discharging. dynamic DCVSL read scheme is used for the read sensing. FEBRUARY 2009 Fig. effective sense margin can be much smaller. which is the worst-case process corner for hold stability. their sense margin is at most 0. 5. in Fig. ratio in subMoreover. subthreshold leakage noise discharge RBL significantly. 11. thereby achieving soft-error immunity with conventional ECC. 9 shows the worst-case data pattern for the bitline swing in this scheme. further deteriorating the sense margin. 2. single-ended read scheme has been used. Considering undefined region of inverter or offset voltage of sense amplifier. IV. the minimum hold SNM. Sense Margin Problem in Single-Ended Read Schemes In [3]–[5]. In our SRAM.654 IEEE JOURNAL OF SOLID-STATE CIRCUITS. the bitline swing is expected to be further deteriorated. the ‘ due to stacked leakage paths of this data input pattern. As shown in this figure. several approaches have been explored in [3]–[5].

We compare viding large differential bitline swing the bitline swing to that of the single-end 8T SRAM [4]. the area penalty is 61%. The write driver in the test-chip. the discharge of BLB turns on keeper M2 and hence. However.: A 32 KB 10T SUB-THRESHOLD SRAM ARRAY WITH BIT-INTERLEAVING AND DIFFERENTIAL READ SCHEME IN 90 NM CMOS 655 Fig. In this technique. 11(a)). which improves the bitline noise immunity during read. Without any keeper. During read. 15. we set up 32 cells per each bitline. Final bitline swing simulation results of our 10T SRAM. we employ the footer transistor M0 instead of the strobe-delay method (Fig. 10. 14. 12(b). we employ dynamic DCVSL technique. The unfolded circuit diagram of Fig. For the 8T SRAM. (a) Transient simulation results for Fig. For these simulations. 11) and the worst-case process corner (Fast NMOS and Slow PMOS). 11(a). incurring large area and performance penalty. pro. 11(b). Thin-cell layout of our 10T bit-cell. as shown in Fig. Transient simulation results of Fig. 13. 11(b). Fig. For two designs. Drive current flowing through . Hence. shows the worst-case data pattern for bitline leakage noise. We compare the results with the simulation results of other design. To obtain the leakage tolerance. one of the precharged bitlines (BL or BLB) starts discharging. Dynamic DCVSL Read Scheme The proposed SRAM has a fully differential read scheme. In order to further improve the bitline leakage tolerance. 12. The column structure of Fig. Die micrograph and layout. In this work. Four columns share one write driver. the leakage current through unselected cells (storing complementary value in the accessed cell) impedes a successful read operation. 12(a) verify the effectiveness of the dynamic DCVSL read scheme. When read begins. we add sense amplifier using cross-coupled inverters. 16. Fig. the keeper drive current prevents discharging. In the subthreshold region. Fig. BL node is considerably discharged at Fast NMOS and Slow PMOS (FS) process corner. bitline leakage current in BL is compensated by the drive current of M2. the write data is inverted for the correct writing. which is equivalent to the column of Fig. extremely long delay buffer is required for strobe timing [12]. DCVSL read provides much bigger bitline swing than the single-ended read of 8T SRAM. intra-die variation results in large delay variation and increases the worst-case offset voltage of the sense amplifier. in the dynamic DCVSL scheme. Compared to the 8T bit-cell. we include a sense amplifier in the design. 11(a) explains our read mechanism. B.CHANG et al. we used the worst-case leakage scenario (Figs. the word lines (WL and ) of the accessed SRAM cells are raised and precharge signal is disabled. Depending on the data value of the access cell. which do not have the keeper M1 and M2. In spite of larger number of cells per bitline (256 cells/bitline). Since the position of BL and BLB is exchanged. Fig. (b) Comparison of the bitline swing simulation results between our 10T SRAM and the single-end 8T [4].

the position of BL and BLB is exchanged in our SRAM and hence.81 and 1. Measured read and write power dissipation. The environment temperature is set to 27 during measurement. B. we fabricated test-chips in 90 nm. M0 is almost negligible before there is significant discharging from a bitline. the node ‘ other adjacent cells. we down-converted the voltage for the input and clock signals using level-down converters. Fig. The word line drivers are boosted by 33% of V (b) Measured waveforms (V = 160 mV. 8-metal CMOS technology. To generate input and clock signals. The measured waveforms at this voltage are shown in Fig. more aggressive boosting is required. which successfully demonstrates 500 Hz read operation . 2 V input and clock signal is leveled down inside the test-chip. . 18. which are divided into 24 sub-blocks (8 columns per a sub-block). we separated power supply pad for row and column decoders from that of other parts. TEST-CHIP IMPLEMENTATION AND MEASUREMENT RESULT A. NO.07 300 mV power for read and write. To obtain boosting effect in the word line drivers. VOL. Due to this characteristic of thin-cell layout.68 worst-case process corner (Fast NMOS and Slow PMOS). Interestingly. 13 shows the simulation results of the bitline swing when the sense amplifier is included. the write data is also inverted for correct writing as shown in this figure. we wrote complementary data between adjacent cells and read them sequentially. For the write operation. 18. Each sub-block has two VGND and write drivers. As discussed earlier. 16. Moreover. respectively. The layout of our SRAM is shown in Fig. we used a Tetronix pattern generator. the overall area penalty Fig. However. 15. is less since we can include more cells on the bitline (explained in Section IV-B).656 IEEE JOURNAL OF SOLID-STATE CIRCUITS. 14 shows the die micrograph and layout of the test-chip. our design dissipates 1. 2. 80 mV word line boosting). 49 kb SRAM arrays are implemented for both conventional 6T cell and our 10T cell. . a 32 kb SRAM array is implemented using our cell as shown in Fig. which is shown in Fig. . we can further scale down the to 160 mV with more aggressive word line boosting (50% boosting ). preventing malfunction induced by the offset voltage of the sense amplifier. In spite of extreme temperature variations bitline swing develops for 512 cells per bitline at the 0. For leakage comparison. At . incurring more power dissipation. for We measured total read and write power dissipation for the maximum operation frequency. which is measured with the 33% boosting of word line drivers. The frequency decreases exponentially due to scales the subthreshold MOS device characteristic as the for successful read operation was down. (a) Measured maximum operating frequency. Fig. we assumed that of word line drivers is boosted by 33% of the SRAM array . FEBRUARY 2009 Fig. which is due to full-swing read method. VGND nodes are also switched for the read. Fig. As discussed in Section II-A. The minimum 160 mV. 14. our SRAM functions correctly at 581. However. For performance and power measurement. 1(a). degradation of writability resulting from IR-drop of the stacked NMOS structure in the write driver is almost negligible.4 kHz At 300 mV clock frequency. V. Since a boosted signal is used for . Only cell arrays and VGND driver are implemented in these arrays. Since this equipment has 2 V output swing. The output signal toggles per 2 clock cycles. 17(a) shows the maximum operation frequency. Performance and Power Measurement In the power and performance measurement. To verify the read operation. Test-Chip Implementation To verify the proposed SRAM. We employ direct probe pad for supply power of these arrays to exclude leakage current through ESD diode in the I/O pad. 17. The SRAM array has 256 rows and 192 columns. we need at least 3 poly pitches for the thin-cell layout [11] of our SRAM cell. 17(b). Leakage current through the write driver reduces bitline swing. our 10T SRAM adds 61% area overhead relative to 8T SRAM of [4]. the read power dissipation is larger than the write power. and hence stacked transistors are used to reduce this leakage as and shown in Fig. Below 180 mV. . Hence. the minimum at 160 mV was 180 mV. 44. In the schematic ’ and ‘ ’ cannot be shared by of Fig.

Dig. J. “A 256 kb 65 nm 8T sub-Vt SRAM employing sense-amplifier redundancy. 2. however. J. vol. the total leakage current of our SRAM is close to that of the 6T (between 0. Feb. Chang. Chandrakasan. no. “A 32 kb 10T subthreshold SRAM array with bit-interleaving and differential read scheme in 90 nm CMOS. Solid-State Circuits. 1. Roy. In our 10T bit-cell. H. “A high-density subthreshold SRAM with data-independent bitline leakage and virtual ground replica scheme.. 20. 20. At 6 and 300 mV . the subthreshold component of bitline leakage current decreases significantly.: A 32 KB 10T SUB-THRESHOLD SRAM ARRAY WITH BIT-INTERLEAVING AND DIFFERENTIAL READ SCHEME IN 90 NM CMOS 657 Fig. 25 . Symp... Solid-State Circuits. which is critical to cope with multiple bit soft-errors. the operating frequency is 500 Hz and the read power dissipation is 0. this leakage current increases exponentially as shown in Fig. Hazucha et al. Nonetheless. 518–529.1–21. Park. Mar. Papers. 1999.21 raised. 2008. 19. In our SRAM. pp. vol. 42.25- to 90-nm generation. VI. [4] N.” IEEE J. 19(a). H. Soeleman and K. the total leakage 50 and 100 . the previous schemes need improvements in the bit-interleaving structure. 19. In the low temperature region. S. Our proposed 10T SRAM cell allows the bit interleaving with the column-wise write access control while having differential read path. vol. Previous subthreshold SRAM cells [3]–[5] used single-ended read paths.” IEEE J. The graph of Fig.” in Symp. pp. In this situation. pp. Hence. 2008. . Due to extra cell transistors and VGND drivers. P. pp. The measurement results show that the leakage power consumption of our 10T SRAM is comparable to that of the 6T cell. the leakage paths from the bitlines to the cell node have the stacked devices as shown in Fig. 19(b) shows the leakage comparison results between conventional 6T and our 10T SRAM. reducing subthreshold leakage from the bitlines to cell node. 1993. [8] C. At this voltage. 154–155. reducing the subthreshold component of the bitline leakage drastically. no. 2008. Measurements of 32 kb 90 nm CMOS test-chip demonstrate successful opera.22x).5. VLSI Circuits Dig.. pp. “Soft error rate and stored charge requirement in advanced high-density SRAMs.CHANG et al.” in IEDM Tech. Kim. Dig..4.25 kHz with 180 mV supply and 33% boosted WL and . The design operates tion of our 10T cell below 300 mV at 31. With more aggressive word line boosting of 80 mV.1–33. junction and gate leakages have profound impact on the total leakage current and hence. Jan. [7] P. pp. CONCLUSION We propose a new differential 10T SRAM cell for the reliable subthreshold operation. Feb. Calhoun and A. Low Power Electronics and Design (ISLPED). no. Lage et al. the VGND node is forced to during the hold mode. Hwang et al. “Neutron soft error rate measurements in 90-nm CMOS process and scaling trends from 0. As the temperature is current of the 10T SRAM is 1.96x and 1. leakage reduction provides substantial total power saving. 21. pp.” IEEE J. Fig. Leakage Measurement Leakage measurement results of the 49 kb arrays are summarized in Fig.” in IEEE ISSCC Dig.” in Int.123 . “A 85 mV 40 nW process-tolerant sub-threshold 8 8 FIR filter in 130 nm technology. J. as shown in Fig. This is due to the reduction of the bitline leakage. Roy. The methods. the bitline leakage paths have stacked devices. Liu. Tech. 19(b).5. Kim. “Ultra-low power digital subthreshold logic circuits. [5] T. Dec. (a) Leakage measurement results of our 10T SRAM (b) Leakage measurement result comparison of our 10T and the 6T.4. 43. 94–96. Since the leakage power is substantial portion of total power in subthreshold logic. 680–688. 141–149.4. can be scaled down to 160 mV. 3. Dec. subthreshold leakage becomes dominant compared to other leakages at higher temperature. 33. 388–389. Solid-State Circuits. pp. our SRAM has more junction and gate leakage compared to the 6T. 43. Kim. we observe that the total leakage current is almost comparable to that of the 6T beyond 50 . J. REFERENCES [1] H. 2 m . Our main focus is enabling bit interleaving along the word line as well as designing reliable data read path.” in IEDM Tech. Jun. we swept the from 200 mV to 300 mV at different temperatures—6 . Proc. and K. This effort is more effective in high temperature region. For these measurements. It allows large bitline swing despite of extreme process and temperature variations. suffer from reduced bitline swing due to bitline noise. However. In addition. and C. [6] I. 2007. It is due to the fact that our 10T cell has stacked bitline leakage paths and hence. We also implemented 49 kb arrays of 6T and the 10T cell for leakage comparison.4. we employ dynamic DCVSL read scheme. 2003. “A 256 kb sub-threshold SRAM in 65 nm CMOS.. To improve the read margin even further. C. 2007. Verma and A. Chandrakasan. [2] M. Keane. [3] B. our SRAM still has the larger leakage current than the 6T cell.

“An autonomous SRAM with on-chip sensors in an 80 nm double stacked cell technology. His research interests include VLSI design/CAD for nanoscale silicon and non-silicon technologies. New York: Cambridge Univ.04 /spl mu/m/sup 2/ 8T-thin cell using dynamically-controlled column bias scheme. 2003 IEEE Nano. degree from the School of Electrical and Computer Engineering. 2.” in IEEE ISSCC Dig. Dallas. 44. Korea. Armstrong. West Lafayette. and 2005 IEEE Circuits and Systems Society Outstanding Young Author Award (Chris Kim).” IEEE J. May 2003. He was Guest Editor for the Special Issue on Low-Power VLSI in the IEEE Design and Test (1994) and IEEE TRANSACTIONS ON VLSI SYSTEMS (June 2000). in 2002 and 2005. [10] J. [13] Y. respectively. pp. and A. He was with the Semiconductor Process and Design Center of Texas Instruments. and the Ph. and 2004. degrees in electronics engineering from Seoul National University. NY. “Characterization of multi-bit soft error events in advanced SRAMs. where he worked on FPGA architecture development and low-power circuit design. 2004. IN.S. His current research interest includes technology/circuit codesign. NO. and is a coauthor of two books on low power CMOS VLSI design. and K. J. He is a Purdue University Faculty Scholar. IEE Proceedings—Computers and Digital Techniques (July 2002).. J.1–21. “A 90 nm dual-port SRAM with 2. K. Kulkarni. and Best Paper Awards at 1997 International Test Conference. Purdue College of Engineering Research Excellence Award. pp. 2002. degree in electronics and electrical communications engineering from the Indian Institute of Technology. Jae-Joon Kim received the B.. He has published more than 450 papers in refereed journals and conferences. in 2004. During summer and fall of 2007. TX. Nii et al. 10. vol. IN.S. He is currently working toward the Ph. degree in computer engineering from University of Arizona. Solid-State Circuits. . Electron Devices. He was a Research Visionary Board Member of Motorola Labs (2002). Brown. AZ. where he is currently a Professor and holds the Roscoe H. Papers. “Intrinsic parameter fluctuations in decananometer MOSFETs introduced by gate line edge roughness. 21. degree from the School of Electrical and Computer Engineering. West Lafayette. Ning. Roy received the National Science Foundation Career Development Award in 1995. 42. Yorktown Heights. S. West Lafayette. Purdue University. CA. VLSI testing and verification. His research interests include variation-tolerant circuit design and ultra-low power circuit design. pp. holds eight patents.” in IEDM Tech. IEEE 2000 International Symposium on Quality of IC Design. Feb. R. He joined the electrical and computer engineering faculty at Purdue University. He worked with LG Electronics as a software engineer in 2003. [14] A. During the summer of 2000.D. Dig. IBM Faculty Partnership Award. 50. degree in electrical engineering at Purdue University. and 2006 IEEE TRANSACTIONS ON VLSI SYSTEMS Best Paper Award. IN. respectively. 2004 IEEE International Conference on Computer Design. 2007. Kim.S. pp. 2003. [11] K. Zhang.Tech. degree in electrical and computer engineering from the University of Illinois at Urbana-Champaign in 1990. Press. Kaushik Roy (SM’95–F’01) received the B. Tech. Dr. degree in electrical engineering (summa cum laude) from Seoul National University. He also spent the summer of 2001 and 2002 at IBM T. OR. and IEEE TRANSACTIONS ON VLSI SYSTEMS. Ik Joon Chang received the B. low-power electronics for portable computing and wireless communications. in 1994. no. Dec. where he performed research related to low-power circuit techniques. Fundamentals of Modern VLSI Devices. Since 2005.D. Kharagpur. 508–543. vol. 1254–1260.S. Roy. 2005 SRC Technical Excellence Award.. 2006 IEEE/ACM International Symposium on Low Power Electronics & Design. and reconfigurable computing. FEBRUARY 2009 [9] J. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS. West Lafayette. Sohn et al. He has been on the editorial board of IEEE Design and Test. George Chair of Electrical and Computer Engineering. Hillsboro. In summer of 2008. Watson Research Center.S. and M. India. he was an intern at Intel Circuit Research Laboratory. 2303–2313. Maiz.4..658 IEEE JOURNAL OF SOLID-STATE CIRCUITS. for SOI circuit research. [12] K. he had an internship with Qualcomm.D. 2005. VOL. K. 2003 IEEE Latin American Test Workshop. Kaya.” IEEE Trans. degree at Purdue University. “A 160 mV robust Schmitt trigger based sub-threshold SRAM. ATT/Lucent Foundation Award.4. and P. 232–235. and the Ph. Korea. Jun. in 1993. Chang was awarded from the Samsung Scholarship Foundation in 2005. Hareland. Seoul. Taur and T. he has been pursuing the Ph.4. He was with TLI Inc. 1998. Tucson. he was with the Exploratory VLSI design group at IBM Austin Research Laboratory as an intern. Korea as a custom circuit designer from 1998 to 1999. S. Watson Research Center as a Research Staff Member since May 2004. and the M.D.” in Symp. pp. Seoul. Oct. SRC Inventors Award. He has been with IBM T. IN. His current research interest is robust and low power circuit design in nanoscaled CMOS technologies. Mr. Sang Phill Park (S’07) received the B. VLSI Circuits Dig. Asenov. Purdue University.