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A 10T Non-Precharge Two-Port SRAM for 74% Power Reduction in Video Processing

Hiroki Noguchi†, Yusuke Iguchi†, Hidehiro Fujiwara†, Yasuhiro Morita†, Koji Nii†,‡, Hiroshi Kawaguchi†, and Masahiko Yoshimoto†

Kobe University, 1-1 Rokkodai, Nada, Kobe, Hyogo 657-8501, Japan Renesas Technology Corporation, 4-1 Mizuhara, Itami 664-0005, Japan Email: h-nog@cs28.cs.kobe-u.ac.jp

Abstract
We propose a low-power non-precharge-type two-port SRAM for video processing. The proposed memory cell (MC) has ten transistors (10T), comprised of the conventional 6T MC, a readout inverter and a transmission gate for a read port. Since the readout inverter fully charges/discharges a read bitline, there is no precharge circuit on the read bitline. Thus, power is not consumed by precharging, but is consumed only when a readout datum is changed. This feature is suitable to video processing since image data have special correlation and similar data are read out in consecutive cycles. As well as the power reduction, the prechargeless structure shortens a cycle time by 38% compared with the conventional SRAM, because it does not require a precharge period. This, in turn, demonstrates that the proposed SRAM operates at a lower voltage, which achieves further power reduction. Compared to the conventional 8T SRAM, the proposed SRAM reduces a charge/discharge possibility to 19% (81% reduction) on the bitlines, and saves 74% of a readout power when considered as an H.264 reconstructed-image memory. The area overhead is 14.4% in a 90-nm process technology.

not selected as a readout bit. Even when a selected MC did not discharge the LRBL (“1” readout), the LRBL voltage would be decreased by the bitline leakage in such case if there was no bitline keeper. The bitline keeper compensates this bitline leakage, and maintains the voltage level on the LRBL during “1” readout [7]. Otherwise, we cannot distinguish a readout current from the bitline leakage, which turns out to readout malfunction.
Precharge signal MC MC RWL WWL P1 N3 N1 WBL P2 N4 N2 WBL_N N6 N5 Precharge circuit Bitline leakage Memory cell (MC) Readout current Bitline keeper Compensation

Keywords
Low-power SRAM, non-precharge SRAM, two-port SRAM, video processing, H.264.

LRBL

Fig. 1. A schematic of the conventional 8T precharge-type twoport memory cell. As a process technology is advanced, a supply voltage and a threshold voltage of transistors go down. Since the low threshold voltage increases the bitline leakage, we have to upsize the bitline keeper, and then have to pay area overhead. The large bitline keeper gives negative influence to a readout time as well. To make the matters worse, the delay overhead becomes larger as a supply voltage is decreased. Fig. 2 illustrates simplified operation waveforms in read cycles in the conventional 8T precharge-type SRAM. Since a precharge scheme is adopted and an LRBL needs to be precharged to a supply voltage by the start time of a clock cycle, a charge/discharge power is consumed on the LRBL when “0” is read out. In contrast, no power is consumed when “1” is read out because the LRBL keeps the supply-voltage level and we do not have to precharge the LRBL. In our prior study that saves the charge/discharge power on a read bitline, a majority logic circuit and data-bit reordering are accommodated to write “1”s in as many as possible [8] (hereafter, we call the prior SRAM “MJ SRAM” in this paper). The MC structure in the MJ SRAM is same as the conventional 8T SRAM although the read and write circuits are different. Input data comprised of eight pixels are reordered into digit groups (from the most-significant-bit group to the least-significant-bit group), and

1. Introduction
As the ITRS Roadmap predicts, a memory area is becoming larger, and will occupy 90% of an SoC’s area in 2013 [1]. Even on a real-time video SoC, this trend is going on. An H.264 encoder for a high-definition television requires, at least, a 500-kb memory as a search-window buffer, which consumes 40% of a total power [2]. As a process technology is scaled down, a large-capacity SRAM will be adopted as a frame buffer and/or a restructuredimage memory on a video chip, and may potentially dissipate a larger portion of power. To save the power in the real-time video application, we report a low-power two-port SRAM in this paper. A two-port SRAM is suitable for real-time video processing since it can make one read and one write at the same time in a clock cycle [2-5]. In the conventional eight-transistor (8T) twoport memory cell (MC) shown in Fig. 1, two nMOS transistors (N5 and N6) for a read wordline (RWL) and a local read bitline (LRBL) are added to a single-port 6T MC, which frees a static noise margin (SNM) in a read operation [6]. Meanwhile, a precharge circuit must be implemented on the LRBL so that the two nMOS transistors can sink a bitline charge to the ground. In addition to the precharge circuit, we have to prepare a bitline keeper on the LRBL in the conventional two-port SRAM. Many MCs connecting to the LRBL draw bitline leakage even if they are

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264 codec.2µm / 0. Thereby. the charge/discharge power consumed on the LRBLs is proportional to the number of times that a datum flips (the number of transitions: “0” to “1” and “1” to “0”) along the time axis. On the contrary. 2. 2. and then they are put back in the original order so that we can read out the original data. the number of charge/discharge times becomes one as an expected value. we will describe design and evaluation of a 64-kb SRAM test chip in a 90-nm process technology. Transistor sizes are also denoted. The rest of this paper is organized as follows. Please make sure that there is no precharge circuit either on 2. only luma data are considered. the proposed SRAM operates in a shorter cycle time since a precharge period is not required. since there is no precharge circuit on bitlines.1µm LRBL P1. The charge/discharge power is consumed only when a readout datum is changed. The LRBL power is thus reduced to about 50% in our proposed SRAM in the read operation. a stored node is connected to an LRBL through the inverter.1 Circuit Fig. we can maximize the number of “1”s in the input data. which improves an operation in a low-voltage region. no power is dissipated on the LRBL if an upcoming datum is same as the previous state. and controls the appended pMOS transistor at the transmission gate. RWL No power consumed RBL Power consumed on RBL Fig. In the MJ SRAM. “0” read “0” read “0” read “1” read CLK Precharge Fig. Two pMOS transistors are added to the conventional 8T two-port MC. which results in the combination of the conventional 6T single-port MC.00 © 2007 . In a read cycle. “0” read “0” read “0” read “1” read CLK differential write bitlines (WBL and WBL_N) since they are dedicated for a write port. The transient probability in a sequence of random data is 50% in the proposed non-precharge SRAM while in the MJ SRAM. 5. the YUV format is adopted as a pixel datum. 4 illustrates operation waveforms in the proposed 10T nonprecharge SRAM. The proposed SRAM theoretically reduces a power on the LRBL to a half of the MJ SRAM in a read operation. Thus. While the RWL and RWL_N are asserted and the transmission gate is on.13µm LRBL Power consumed on LRBL Fig. Section 4 summarizes this paper. In Section 3. our proposed SRAM eliminates the flag bit that causes a power overhead. In this paper. 10T Non-Precharge SRAM 2. and exhibits the reduction of the number of charge/discharge times in simulation. we can exploit the proposed SRAM for video processing as well as the MJ SRAM.2µm / 0. An example is in Fig. In comparison with the MJ SRAM. The proposed SRAM reduces bitline power in both cases that consecutive “0”s are read out and consecutive “1” are read out. 3. Besides. The additional signal (RWL_N) is an inversion signal of RWL. 3 shows a schematic of the proposed 10T non-precharge two-port MC. Waveforms in the conventional 8T precharge-type twoport SRAM in read cycles. The additional pMOS transistor (P4) increases an LRBL capacitance by 5. Therefore. In addition to the power reduction with the consecutive readout. we can get rid of the bitline keeper. P4 0. It is not necessary to prepare a precharge circuit since the inverter can fully charge/discharge the LRBL by itself. consecutive-“0” readout leads to a large bitline power. an inverter. Waveforms in the proposed 10T non-precharge-type two-port SRAM in read cycles. the “0” data are inverted to “1”s by the majority logic circuit. and a transmission gate.5%.then a flag bit is appended to each group. compared to the conventional 8T two-port SRAM. One pixel is comprised of an 8-bit luma (Y signal) and 4-bit chroma (U and V signals). This mechanism reduces the power of the read bitline because we can statistically increase the possibility that “1” is read where no power is dissipated. the charge/discharge power on the LRBL is consumed only when the LRBL is changed. P2 0. A schematic of the proposed 10T non-precharge-type two-port memory cell. In H. P3. the group data are inverted if a flag bit is true.2 Application to Video Image In the proposed SRAM. Section 2 introduces the proposed 10T non-precharge SRAM. we will propose a novel nonprecharge-type SRAM in this paper. a pair of a charge and a discharge takes place when “0” is readout. The most significant bits (MSBs) in IEEE Computer Society Annual Symposium on VLSI(ISVLSI'07) 0-7695-2896-1/07 $20. MC MC RWL WWL P1 N3 N1 RWL_N WBL Transistors Width / Length P2 N4 N2 N5 P4 P3 N6 Memory cell (MC) Inverter (P3 and N5) Transmission gate (P4 and N6) RWL No power consumed WBL_N N1 – N6. 4. if readout data are random and the bitline capacitance is same. Since the non-precharge scheme is employed. in the conventional SRAM. For further power reduction. If the number of “0”s in a group is more than that of “1”s. The inversion information (“1” means inversion) is stored in the additional flag bit. because adjacent pixels have strong correlation one another in a video image. Fig.

“Intersections”.3 Optimization of Block Size In this subsection.73% Q 20 Reconstructed images -75% 0 6 25 1x 8 12 2x .consecutive data tend to be lopsided to either “0” or “1” with high probability. and proposed 10T SRAMs when a block size is changed.264 encoder.52% Proposed 10T SRAM . “Building along the Canal”. in the simulation. Profile Frame rate Bit rate Search range Symbol mode JM version Original image Motion estimation Motion compasation Intra prediction Loop filter Reconstructed image 80 Main profile 30 fps 7. Hence. SRAM Conventional (8T) . It is important to determine the block size mapped onto an LRBL since a scan path affects effective use of the spatial correlation and power. 7 compares the transition possibilities (the normalized numbers of charge/discharge times) on an LRBL between the conventional 8T SRAM. because the search range is ±128 × ±128 in the H. Fig. which indicates that the statistical characteristic of the reconstructed image is well exploited. H. the correlations among local pixels are supposed to be different in the IEEE Computer Society Annual Symposium on VLSI(ISVLSI'07) 0-7695-2896-1/07 $20.00 © 2007 . Trasition posibility (Normarized # of charge/discharge) [%] 100 Conv.264 encoder. the block size of 256 × 1 pixels is optimum in terms of power reduction. Table 1. statistic analysis was carried out with the original images and reconstructed images. which was well exploited in the MJ SRAM. 6. In the simulation.8 + Integer DCT Entropy coding 60 Original images MJ SRAM .264 image data and its mapping onto eight LRBLs. The values are average ones in the ten sequences. We set the number of pixels in a block to 256. The maximum power saving is achieved when a reconstructed image that has a stronger correlation than the original image is considered. 5 illustrates an example of the block size and its scan path. It can Fig. 7. “Japanese Room”. The graph indicates that the proposed 10T SRAM saves 73% of a dynamic power on an LRBL compared to the conventional 8T SRAM when the original image is read out. The encoding process is depicted in Fig. and then its reconstructed image is generated in a local decoding loop. The scan path from the 1st pixel to the Wth pixel is mapped onto eight LRBLs. 5. Simulation conditions in H.264 encoder and a burst access over 256 pixels is possible if a full-search algorithm is considered. As discussed in the previous subsection. Transition possibilities (the normalized numbers of charge/discharge times) on an LRBL between the conventional 8T. we made a simulation under the condition shown in Table 1 to fix the block size. “Yachting”. the correlation becomes stronger in a more significant bit. the values of the bits are random. “Whale Show”. further power reduction is promising since image data are lopsided to “0”s or “1”s with higher possibility in a more significant digit. In a video image.81% . An example of H.68% Original images . “Street Car”. 2. “Church”. and proposed 10T SRAM when the block size is changed. Y (Luna Y) 1st row One pixel 8bits U (Chroma U) V (Chroma V) 1920pixels MSB LSB 1st pixel Wth pixel 1024pixels Mapping 2nd pixel 1st row 2nd row along LRBL 2nd row vertical and lateral directions. and “Yacht Harbor”. In other words.53% Reconstructed images 40 . and utilized for motion estimation and motion compensation. 6. Besides.5 Mbps ±128 × ±128 CABAC 9. while in the least significant bits (LSBs). Fig.43% Majority (MJ) Proposed (10T) 1st pixel H pixels Hth row W pixels Last pixel Hth row Wth pixel Last pixel Col mapping (=8LRBLs) Fig. We exploit these characteristics in the proposed SRAM to reduce the LRBL power as well as the MJ SRAM. In the both cases of the original image and reconstructed image.60% 64 x4 x8 32 4x 64 8x 32 Block size (W x H pixels) 2 8x 12 1 6x 25 + Integer + IDCT IQ Fig. a pixel block (W × H pixels) has 256 pixels.264 encoding process. MJ. Assuming an H. we discuss the optimum data mapping that utilizes the spatial correlation in an image. extracted from ten high-definition test sequences: “Bronze with Credit”. the power reduction on the LRBLs is theoretically expected thanks to the non-precharge scheme even if input data are random. “European Market”. MJ SRAM. The saving factor is extended to 81% compared to the conventional 8T SRAM. The original image is encoded.

9. MJ SRAM. we can get rid of flip-flops at data output since a GRBL voltage is not changed up by precharging and it is needless to latch the data output at the beginning of the precharge phase.96 × 0. We make an area comparison between the conventional SRAM.16 ns) operation since the proposed SRAM does not requires a precharge period.5 n Time [s] (b) 2n MCs x64 Fig.16 ns.93 ns Dataout 3.00 © 2007 . 10 (a) and (b) show operation waveforms of the proposed non-precharge SRAM when “0” and “1” are read out. respectively.5 n Time [s] (a) Dataout CLK 2n Read and write circuits 1.4% because there are two pMOS transistors added to the conventional 8T MC.0 LRBL CLK RWL Voltage [V] 0.76 µm2.16 ns. and proposed SRAM in Fig. the read and write circuits are smaller than the conventional SRAM by 1% because of the elimination of precharge and bitline keeper circuits. in which two 256-pixel blocks can be put. A GRBL driver drives a GRBL with a block selector signal from the X decoders. WBL_Ns GRBLs LRBLs WBLs MC block RWL0 RWL_N0 WWL0 X decoders GRBL Block selector signal 0 1n 1. The access times at the “0” and “1” readouts are 0. The figure demonstrates that the proposed SRAM shortens a cycle time IEEE Computer Society Annual Symposium on VLSI(ISVLSI'07) 0-7695-2896-1/07 $20. respectively. However. A hierarchical read-bitline structure (double-bitline structure: LRBLs and global read bitlines (GRBLs)) is applied to avoid a speed overhead of a single-bitline scheme [6]. 8 is a chip layout of the proposed non-precharge 64-kb SRAM in a 90-nm process technology. The area overhead in the proposed SRAM is 14. The schematic and the transistor sizes have been already shown in Fig. 8.1 Overview Fig. Fig. MC blocks (64 words x 64 bits) GRBL Block selector signal 0 448 µm X decoders 1n 1. MPEG4. A block diagram of an memory cell block in the proposed SRAM. a GRBL is discharged/charged as Dataout. Design in 90-nm Process Technology 3. The “0” readout is faster than the “1” readout because nMOS transistors in the GRBL driver and read circuit are stronger than pMOS ones. and H.be said that the proposed non-precharge SRAM is suitable for realtime video codec such as MPEG2. Fig. 1. Besides. 10.0 561 µm RWL Voltage [V] 1. 9 is a block diagram of the proposed SRAM. A layout of the proposed non-precharge 64-kb SRAM in 90-nm CMOS process technology. An MC block is 64 words by 64 bits.93 ns and 1. 11.16 ns LRBL Fig. The MC area comprised of ten transistors is 3. to 1. This access time corresponds to a 862-MHz (= 1 / 1. thanks to the precharge-less structure. RWL63 RWL_N63 WWL63 4 MCs GRBL drivers Block selector signal 64 10 Addresses 64 64 Read circuits 64 Dataout Write circuits 64 Datain Fig. Operation waveforms of the proposed non-precharge SRAM when (a) “0” and (b) “1” are read out. 3. After a block selector signal is asserted.264 that require a large-capacity reconstructed-image memory. The chip is currently under fabrication.

Fig. 12 shows frequency dependences on supply voltage in simulation. 900 Operating frequency [MHz] .85 V.0V 0.6 0.0V Proposed SRAM@1.0V 862MHz @1.0 V and a frequency of 300 MHz.58 . according to Fig. 0.4 0.0 V and 300 MHz (temperature: 25°C).98mW 1. please note that the number of charge/discharge times is a half of the conventional case. As a video memory.10 0. increases an LRBL capacitance by 5. in a read operation. MJ SRAM. 14 compares the readout power in the conventional SRAM.4% 1 1.09 +14. and proposed SRAM.0 0 Fig. On the other hand.39% . bitline keepers hinder low-voltage operation as mentioned in Section 1.85V 1. where we can save 65% of the readout power. The supply voltages are set to 0.4 0. The readout power on the LRBLs and GRBLs occupies 81% of the total power in the conventional SRAM.99 0.09 0. 3. we do not have to pay any power overhead in a write operation because the 6T structure at the write port is same as the conventional one.8 Supply voltage: Vdd [V] Fig.0V MJ SRAM @1. 12. and hence the proposed SRAM reduces this part. the proposed SRAM properly operates at 0.80V 300MHz @0.8 V.66 0. In contrast. 13.51 3.66 0. 11.85 V.83 0.39% (a) Conventional SRAM@1. (b) original image data.1. Its power 0.2 frequently than write-in.0V 0.12 0.58% 3. power reduction in a read operation is technically important since readout is made more IEEE Computer Society Annual Symposium on VLSI(ISVLSI'07) 0-7695-2896-1/07 $20.66 1. 12. (a) Random data.77 2. When random data are considered.42mW 3.10 0.28% Fig. respectively. Our proposed SRAM with a 64kb capacity saves 74% of a total power at the lower supply voltage when it is utilizes as a reconstructed image buffer.00 © 2007 . 13 makes power comparisons when we vary content stored in the SRAMs. At a supply voltage of 1 V.89 1.12 0. the proposed SRAM works at a lower voltage.98 mW at a supply voltage of 1.3 Power In the proposed SRAM.0V Proposed SRAM@1.3). the additional pMOS transistor.88 0.69V 0 1. In a reconstructed image. This means higher performance in operating frequency. the proposed SRAM can run at a lower supply voltage when an operating frequency is same as others.98mW 3.68 0. Leakage Conventional SRAM@1.07 0.69 V while the MJ SRAM does not below 0.0V Proposed SRAM@1. there is no precharge period in the proposed SRAM. which can shorten a cycle time compared with other precharge-type SRAMs.10 0. and 0.MCs Conventional SRAM MJ SRAM Proposed SRAM 0 0. we can maximize the power improvement.22 2. and proposed SRAM when a supply voltage is changed.68 0. the saving factor gets larger to 58% compared with the conventional SRAM.22 . 3.66 0.21 600 . An area comparison between 64-kb SRAMs in a 90nm process technology.66 0. If the memory content is an H.09 +7.11 0.0V 0 0.97mW Proposed 10T SRAM 300 300MHz @0. while the operating-frequency condition is still 300 MHz that is the same condition Fig. respectively. MJ SRAM.65% 3.62 1.67mW 2.8 Normarized area Others 0.5% as mentioned in Subsection 2.37mW 3.40mW 2. The supply voltage is the minimum one where an SRAM properly functions at the 300 MHz.0V MJ SRAM @1. At an operating frequency of 300 MHz. Readout power comparisons between 64-kb SRAMs in a 90-nm process technology at 1.2 Read and write circuits 0. In the conventional SRAM and MJ SRAM. 13.68 0.6 0.64 Peripheral Charge/discharge 81% 3.11 0. In other words.2 Operating Frequency and Supply Voltage As described above. Operating frequencies versus supply voltage in a 90nm process technology.08 0. However. Fig. the readout power is theoretically reduced in the proposed SRAM even if data are random.264 original image (average of ten video sequences mentioned in Subsection 2. P4 in Fig.1% 0. the proposed SRAM reduces the readout power by 39% and 28% compared with the conventional SRAM and our previous work.69 V in the conventional SRAM. 3. which achieves much lower power since a dynamic power is proportional to the square of a supply voltage. SRAM MJ SRAM 300MHz @0. the proposed non-precharge SRAM improves the operating frequency by 315 MHz (65% faster) compared with the conventional precharge SRAM. Fig. the readout power is estimated at 3. Thereby. In the conventional 64-kb SRAM.0V MJ SRAM @1.35% .66 0.0V Conventional SRAM@1.30mW (c) Conv.12 0. and (c) reconstructed image data.56mW (b) +315MHz @1. MJ SRAM.10 0.11 0.

” IEEE J. T. “A Read-Static-NoiseMargin-Free SRAM Cell for Low-Vdd and High-Speed Applications. Wang. Vol. Kobatake. Ma. Acknowledgments This study has been supported by Renesas Technology Corporation. Fig. Y. T. Electronics. K. T. Kamei. T. Mar. References [1] International Technology Roadmap for Semiconductors 2005. HC. B-Y. Hamano. Michinaka. Murachi.08 0. Summary We have proposed a two-port non-precharge SRAM comprised of ten transistors. Solid-State Circuits Conf. G. Yoshimoto.dissipation is 0.3TOPS H.3492-3499. S-Y. 2003. N.42 0.06 0. Matsushita Electric Industrial Company Limited. Fujitsu Limited. Miyakoshi. C-H. [4] S.itrs. 0. M. Miyama. and M. and M.30 SRAM@0.54mW [5] Y-W. K. Nomura.61-66. A. Fundamentals. Hsieh. Feb. Tsuboi.3. Kodama. Y. and S. M. Y. This SRAM is suitable for a real-time video image that has statistical similarity. The area overhead is 14.06 Proposed 0. Vol. Chen. Miyakoshi. No. the University of Tokyo. No. Kitazawa. T-C.79mW (b) Conventional SRAM@0. [6] K. Miyama. T.1. May 2002." IEEE J. 2005. 2006.” IEICE Trans. (a) Random data. Huang. The proposed SRAM saves 74% of a readout power when it is used as an H. Krishnamurthy.60% 1. T-C. G. and M.41.net/Common/2005ITRS/Home2005. Please note that supply voltages are different although the operating frequency is fixed to the 300 MHz. 2. http://www. Chen. The proposed SRAM can operate at a 65% higher frequency than the conventional 8T SRAM since it has no precharge period.12. Matsuno.67mW (c) .06 Proposed 0.80V MJ SRAM @0. Aimoto. Soumyanath. pp. 14. T. Renesas Technology Corporation. NEC Electronics Corporation. and H. Miyakoshi. Yamakage. Oue. Y. C-Y. Y.85V 0. Saito.86 . pp. Dec. M.08 0.08 0. S. Symp. Kawaguchi.09 2. T-W. “A 95 mW MPEG2 MP@HL Motion Estimation Processor Core for Portable HighResolution Video Application. Ishiwata. Y.49 1. Hamano. in collaboration with STARC.06 1.42 0.49 0.128-129. J. Murachi.28 . Vol.78 1.E88-C. T.80V MJ SRAM @0.” ACM/IEEE Int.559-569. Ootomo. M. Matsuno. 4.57% . IEEE Computer Society Annual Symposium on VLSI(ISVLSI'07) 0-7695-2896-1/07 $20.42 0.” IEEE J. 2006. Chen. N.53% .05 0. "A 130-nm 6GHz 256 × 32 bit leakage-tolerant register file.31 0.264 reconstructedimage memory. Apr.85V 0. H.530-540. Solid-State Circuits.38. Vol. Shimazawa. K. Leakage Conventional SRAM@0.113-121. K.85mW 2. Solid-State Circuits. J. “A 1. Shen. Shanbhag.49 1.69% 1.55mW Peripheral Charge/discharge 2. Oct. pp. No. Chen. K.5. Nii. T. No.69V 0 0.264/AVC SingleChip Encoder for HDTV Applications. C-F. and M. “A Single-Chip MPEG-2 Codec Based on Customizable Media Embedded Processor. pp.31 0.43mW 2. K.69V 0 6. Chen. T. Ishii. “A Two-Port SRAM for Real-Time Video Processor Saving 53% of Bitline Power with Majority Logic and Data-Bit Reordering. Y.67 mW.htm. 2005.31 SRAM@0.Tsai. [8] H. SolidState Circuits. pp. and L-G.69V 0 0. pp. Nakazawa.06 0. Fang.85V 0. [7] R.55% 2. Vol. Fujiwara. C-S. Yoshimoto. A. (b) original image data.66mW .06 0. R. Balamurugan. No. The VLSI chip in this study is being fabricated through the chip fabrication program of the VLSI Design and Education Center (VDEC). [2] J. Hagihara. Borkar. Yahagi. 2005. Y.4. 37..00 © 2007 . pp. Readout power comparisons between 64-kb SRAMs in a 90-nm process technology at 300 MHz (temperature: 25°C).42 SRAM@0. Murachi.06 Proposed 0. Jan.80V MJ SRAM @0. and Toshiba Corporation. Matsui.15mW (a) Conventional SRAM@0. [3] Y. on Low Power Electronics and Design.4% in a 90-nm process technology. “A Low-Power Systolic Array Architecture for Block-Matching Motion Estimation. Miyamori. Yoshimoto.55mW 5.624-632. and (c) reconstructed image data. Takeda.06 0. Matsumoto.74% 2.” IEEE Int.E88-A. Alvandpour. Morita.” IEICE Trans.