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IEEE TRANSACTIONS ON POWER DELIVERY, VOL. 18, NO. 4, OCTOBER 2003

Load Compensating DSTATCOM in Weak AC Systems
Arindam Ghosh and Gerard Ledwich
Abstract—The paper discusses load compensation using a distribution static compensator (DSTATCOM). It is assumed that the DSTATCOM is associated with a load that is remote from the supply. It is shown that the operation of a DSTATCOM assuming that it is connected to a stiff source in such situations will result in distortions in source current and voltage at the point of common coupling. To avoid this, the DSTATCOM is connected in parallel with a filter capacitor that allows the high frequency component of the current to pass. This however generates control issues in tracking, as standard controls such as a hysteresis control are not suitable in these circumstances. This paper proposes a new switching control scheme and demonstrates its suitability for this problem. It also proposes a scheme in which the fundamental sequence components of a three-phase signal can be computed from its samples. The overall performance of the proposed scheme is verified using digital computer simulation studies. Index Terms—DSTATCOM, load compensation, switching control, weak ac system.

I. INTRODUCTION OWER quality issues are rising in importance particularly for highly integrated plants that are sensitive to distortions or voltage dips. Almost all power quality problems originate in distribution networks. In most countries, there exist regulations which place limits on the distortion and unbalance that a customer can inject to a distribution system [1]. These regulations may require the installation of compensators (filters) on customer premises. This paper specifically examines the use of a power electronic shunt compensator to correct the current drawn from a utility to closely approximate balanced sinusoidal waveforms, without adversely affecting the voltage at the point of common coupling. A distribution static compensator (DSTATCOM) is a voltage source converter (VSC)-based power electronic device. Usually, this device is supported by short-term energy stored in a dc capacitor. The DSTATCOM filters load current such that it meets the specifications for utility connection. If properly utilized, this device can cancel • the effect of poor load power factor such that the current drawn from the source has a near unity power factor; • the effect of harmonic contents in loads such that current drawn from the source is sinusoidal;
Manuscript received March 24, 2000; revised August 31, 2001. A. Ghosh is with the School of Electrical and Electronic Systems Engineering, Queensland University of Technology, Brisbane 4001, Australia, on leave from the Indian Institute of Technology, Kanpur 208016, India. G. Ledwich is with the School of Electrical and Electronic Systems Engineering, Queensland University of Technology, Brisbane 4001, Australia (e-mail: g.ledwich@ qut.edu.au). Digital Object Identifier 10.1109/TPWRD.2003.817743

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• the effect of unbalanced loads such that the current drawn from the source is balanced; • the dc offset in loads such that the current drawn from the source has no offset. In this paper, the discussion concerns the structure and control of a DSTATCOM that is capable of the first three cancellations even when the ac supply system is weak. In this, a weak (or nonstiff) supply implies that the load is connected at the end of a long radial feeder. One of the major considerations in applying a DSTATCOM is the generation of the reference compensator currents. The compensator, when it tracks these reference currents, injects three-phase currents in the ac system to cancel out disturbances caused by the load. Therefore, the generation of reference currents from the measurements of local variables has attracted wide attention [2]–[5]. These methods carry an implicit assumption that the source is stiff (i.e., the voltage at the point of common coupling is tightly regulated and cannot be influenced by the currents injected by the shunt device). This however is not a valid assumption and the performance of the compensator will degrade considerably with high impedance ac supplies. This paper assumes that a balanced source supplies an unbalanced load through a long feeder. The load power factor may be poor and it can also contain harmonics. The compensator is designed such that it not only cleans the distortion created by the load, but also improves the voltage quality at the point of common coupling (PCC). Specifically, a compensator-passive filter structure is proposed for this. The other aspect of the proposal is for a linear quadratic regulator (LQR)-based switching controller scheme that tracks reference using the proposed compensator-filter structure.

II. DSTATCOM PERFORMANCE EVALUATION The system under study is a three-phase, four-wire distribution system, the single line diagram of which is shown in Fig. 1. In this system, a nonlinear load is supplied by a balanced voltage through a feeder. The feeder has a resistance and source an inductance . The load is compensated by a DSTATCOM , a resistance , that contains a VSC, a dc capacitor . Three phase quantities are denoted by and an inductance subscripts a, b, and c. For example, the source voltages are de, , and , and the load currents by , , and noted by , and so on. Further, the voltage at the point of common coupling is defined as the terminal voltage . It can be seen that this voltage is equal to the load voltage.

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3(b) depicts the source currents.e.GHOSH AND LEDWICH: LOAD COMPENSATING DSTATCOM IN WEAK AC SYSTEMS 1303 Fig. 3(a). 2) The combined load and compensator system draws unity power factor current (i. 1. Fig.e. B. Compensator structure used in which three separate VSCs are supplied from a common dc storage capacitor. These are then given by and . This prevents the use of the three leg bridge as a DSTATCOM power circuit. The iron losses of the transformer are neglected. average load power). A four leg converter can also be used and the control techniques described here would be readily translated. 2. each switch represents a power semiconductor device combined with an antiparallel diode. Each VSC is connected to the network through a transformer. the reference current generation method proposed in [4]. It is to be noted that due to the presence of transformers. In the above ages are balanced) and is obtained by a moving average filter algorithm. The requirement of DSTATCOM is a topology that will be able to force three independent currents through its limbs. DSTATCOM Structure The DSTATCOM structure considered in this paper is shown in Fig. The inductance leakage inductance of each transformer and additional external inductance. One alternate topology for loads containing dc current is given in [6]. In this figure. [5] is utilized. the voltage is switched high. if any. This prevents the dc storage capacitor from being shorted through switches in difin this figure represents the ferent inverters. Let us illustrate this with the following example. The switching losses of an inverter and the copper loss of the connecting transformer are represented by a . Example 1: Consider the system shown in Fig. The results of the Matlab simulation are shown in Fig. this topology is not suitable for canceling any dc component in the load current. the compensator supplies the zero-mean oscillating power required by the unbalanced nonlinear load. resistance For star connected load. A. . ). the converter voltage is switched low. The control is based on hysteretic control of compensator current. . The load currents are shown in Fig. Six output terminals of the transformer are connected in star. The topology shown in Fig. the neutral point of the three transformers is connected to the load neutral. 3. Single-line diagram of shunt compensation of a load supplied through a feeder. The problem of using an ordinary three-phase bridge inverter is that the sum of three currents must be equal to zero. It can be seen that the source currents become distorted as soon as the compensator is pressed into action. The DSTATCOM parameters in per unit are given by The compensator is connected at the end of first half cycle when the average power measurement becomes available. 3) The source supplies only the real power required by the where is the load (i. It is to be noted however that the source power factor may not be unity due to the presence of feeder impedance. when the current is correspondingly high. 2 allows three independent current injections as this contains three separate H-bridge inverters... it is assumed that the VSCs are lossless and connected to a fixed dc supply. a direct application of this method will suffer from the problem of harmonic contamination of the point of common coupling due the inverter switching of DSTATCOM. Under this condition. the phase angle difference between the terminal voltage and source current is zero). However. When the current is below the reference by more than the hysteresis band. the term that gives a continuous measurement of the average power by averaging it over the immediate previous half cycle.. 1 where the source voltage is balanced with a peak of 1. (1) ( when the terminal voltwhere .u. while Fig. The purpose of including the transformers is to provide isolation between the inverters. Let us denote the reference compensator currents by . It contains three H-bridge VSCs that are connected to a common dc storage capacitor [5].e. DSTATCOM Performance In this paper. This method ensures that 1) The sum of the three source currents is zero (i. It supplies an unbalanced RL load given in per unit by The feeder impedance in per unit is given by For simplicity.0 p. 2.

a hysteresis band of 0. the switch-frequency component in the terminal voltage still remains. As a result. 3(a). 4(b). As a result of this. 5. 3(c) depicts the phase-a voltage of the point of common coupling. OCTOBER 2003 Fig. 18. The magnitude of the dc voltage is the same as chosen in the previous two examples. the following filter-DSTATCOM parameters in per unit are chosen as The VSC is still assumed to be lossless and it is still supplied by a fixed dc voltage source rather than a storage capacitor. The hysteresis band in this case is also chosen as 0. The injected current contains high frequency harmonics. The results with this added computation are shown in Fig.5 kHz.u. III. the terminal voltage still contains a very large amount of harmonics. With respect to this figure. Since the source voltages are assumed to be balanced. has been chosen and this has resulted in a switching frequency of around 15. It can be seen that they are balanced and relatively free of low-frequency harmonics. the injected shunt current is defined as (2) This choice enables us to use the relations given in (1) since the ) remains undisturbed. An algorithm for extracting the fundamental frequency sequence components from the measurements of voltage signal is given in Appendix A. the instantaneous terminal voltages are synthesized with respect to the phase of the voltage waveform as measured over the previous half cycle. This algorithm assumes that voltage signals are sampled at discrete intervals of time. any distortion in the source current can be eliminated. 3. 4(d). The above example clearly demonstrates that the algorithm given in (1) cannot be utilized in a direct manner due to the presence of the VSC distortion of the terminal voltage. These harmonic currents. the magnitude of the load currents increases with it. 4(a). However.01 p. In addition to the feeder and load parameters mentioned. The source currents are shown in Fig. This Fourier average is taken to be the moving average such that any change in the voltage can be fully reflected on the extracted voltage. Tolerable compensation but undesirable terminal voltage of a system with a nonstiff source. This is evident from Fig. 4. Thus. the reference current generation scheme based on this voltage will not function properly. VOL. The load currents are unbalanced as seen in Fig.1304 IEEE TRANSACTIONS ON POWER DELIVERY. the injected compensator currents will be erroneous thereby injecting more harmonics in the feeder. when injected into the feeder. The phase-a of the injected shunt current is shown in Fig. The algorithm given in Appendix A is used to extract the fundamental positive sequence voltage. This. DSTATCOM Structure to Eliminate Terminal Voltage Harmonics The above example demonstrates that through the extraction of the fundamental component of the terminal voltage. 4.. The phase a voltage at the terminals is seen in Fig. This is shown in Fig. 4. Further KCL at the PCC (i. These samples are then transformed into instantaneous symmetrical component vectors.01 p. It is to be noted that for online application. the switching frequency is below 4.4 kHz. Single-line diagram of shunt compensation in the presence of a filter capacitor. Once the reference currents are generated . Therefore. Fig. Example 2: Let us consider the same system as given in example 1. note that the terminal voltage in this case is the voltage across the (i. Once the magnitude and phase of the positive sequence voltage are obtained. 1 is modified by placing a filter capacitor in parallel with the DSTATCOM at the point of common coupling. This voltage increases in magnitude and also gets distorted as soon as the compensator is connected. the circuit of Fig. which is excessively high. will cause distortion in any other load that may be connected in the terminal bus.e. To facilitate this.. Example 3: Let us consider the same system used in examples 1 and 2. since the computation now is based on fundamental extraction. the discrete Fourier transform of which produces the symmetrical components. NO. 4(c) and the current injected by the compensator is shown in Fig. Fig.u. an average over half a cycle replaces the integral associated with the determination of Fourier coefficients. of course.e. corrupt the terminal voltage. Furthermore. It is evident that even though the source currents are almost free of harmonics. Let us now demonstrate the efcapacitor ficacy of this algorithm with the help of the following example. the fundamental component of this voltage must be extracted online. a path for the switching harmonic current must provided to flow thorough a filter. exactly half a cycle after the change. Now since the terminal voltage is not sinusoidal. However. 3(d). ). The reason for the distortion in the source current is simple. DSTATCOM FOR NONSTIFF SOURCES A. the other two sequences theoretically remain zero.

6. it can be seen that the local variables for the DSTATCOM are terminal voltage. 5.01 s. Based on where is a diagonal matrix. In an LQR problem. Fig. The state-space equation of the circuit then can be written as (3) is the switch state.01. the LQR performance index is minimized with where is the transpose operator. the following state transformation can be made: (4) The state (3) then can be transformed into (5) 1) Proportional Control: Assuming full control over . This reduced state feedback restricted to results in a minimal shift in the closed-loop eigenvalues to the . 5. 5. The compensator is turned on at 0. they are tracked using a hysteresis band current control scheme with a band of 0. From Fig. this never makes the closed-loop system unstable. this can have a detrimental effort on an oscillatory system as shown in Fig. Also. 5. the control design is presented for the structure shown in Fig. 7. Effect of hysteresis control on the DSTATCOM of Fig. 5 are defined in terms of the currents of Fig. 7. The control is of the form (6) is the desired state vector. and the filter capacitor current. any feedback controller must rely only on the locally measured variables. To avoid the complexity to the left of the line of forming a reference for the load current. It can be seen that the source current diverges as soon as the compensator is pressed into action. B. the gain matrix is . Moreover. Equivalent circuit of the DSTATCOM. states. The weighting matrix reflects the importance of these . It is then minimized to obtain the optimal control law through the solution of steady state Riccati equation [7]. like the DSTATCOM of Fig. 6 shows the phase-a source current for this case. Fig. The two variables that are most and the terminal important to be controlled are the current voltage. A hysteresis controller can be viewed as a high gain proportional controller. 7 as follows: The state (3) contains the feeder and load impedances. the oscillatory closed-loop eigenvalues are . DSTATCOM Control In this subsection. However. the latter may change at any time. It is thus imperative that an alternative stabilizing controller be designed for this system. an infinite time linear quadratic regulator (LQR) can be designed for this problem. The gain matrix is given by Using this feedback. 5. Single-line diagram of shunt compensation in the presence of a filter capacitor. a where performance index of the form (7) is chosen. the hysteresis band adds a certain phase lag in the operation. For a first order system. of Fig. using (1). The currents In the above equation. 1. source current. left of . The equivalent circuit of the compensated system is shown in Fig. For the system described in Example 3. Let the state vector be defined as Fig. While the former is measurable. the above observation.GHOSH AND LEDWICH: LOAD COMPENSATING DSTATCOM IN WEAK AC SYSTEMS 1305 Fig. filter current.

For a set of decreasing values of . . Fig. The feeder resistance is forced to zero and its reactance is changed to 0. the switching decision is based on a linear combination of multiple states. there is a corresponding set of increasing values of . 8. This gives a better performance such that as than the exponential convergence of proportional control as discussed in [7] for regulator problems.9 p.u. therefore. Thus. Keeping the feeder resistance to zero. the system will converge to the switching surface. the control based only on the sign of LQR value will chatter at a rate limited by the switches. the stability properties imply that the system will converge. the algorithm can be claimed to be robust to the variations in the load parameters. the reference signals are computed based on the actual measurements and fundamental extraction. NO.u. Compensation of a load containing harmonics when the source is nonstiff and the compensator includes a filter capacitor. In this control law. Starting from an arbitrary initial state. Hence. Subsequently. From this. The switching control is 1 when the LQR value is positive. 9(d) shows the three instantaneous powers. If the above conditions are always satisfied. This use of projection of the LQR design gives good convergence to the tracking band as well as good stability of tracking. The response is shown in Fig. there will always exist a value of such that is bounded appropriately. the fundamental positive sequence component of the terminal voltage is also obtained. as mentioned in Example 2. It is to be noted however that unmodeled disturbances such as lightning strikes. or large load changes may saturate the control leading to imperfect tracking. the gains of must be small. it has a settling time of half a cycle—which implies that the compensator requires half a cycle to settle to zero power flow following any transient. and has the value 1 when it is negative. 9.08 s). as shown in Fig. LQR design is stable provided that the effective gain of the input nonlinearity is constrained in the sector between and 2 [7]. The consistency of the state references is an integral part of the proof of control convergence given in Appendix B. the feeder reactance is changed to 0. It is also important to investigate the robustness of the system with respect to the variations in the feeder parameters since the feeder configuration may change with time. As expected. the range of errors is known beforehand. perfect tracking of system states to within tracking band will result. VOL. 18. it can be seen that both load currents and the terminal voltages become balanced and free of harmonics once the compensator action settles. is also added.u. It can be seen that both source current and terminal voltage remain balanced and distortion free despite the changes in the feeder parameters. Finite time convergence of the regulator problem can be shown.12 s). One important property of the linear quadratic regulator is that it is tolerant of input nonlinearities. OCTOBER 2003 2) Switching Control: The control signal as defined by the LQR design is a continuous signal. In the process of forming (1). State feedback control with a nonlinear element in the forward path. this control is called a switching band tracking control. 8. To avoid this.1306 IEEE TRANSACTIONS ON POWER DELIVERY.0 p. In addition to the load given in Example 1. Since the load parameters are different for the different phases. such as tracking sine waves. . It is to be noted here that the measurements and the fundamental extraction are continuous. faults. and a reactance of 0. the control signal is the switching decision of the VSC of the DSTATCOM and is thus constrained to be either 1 or 1. Once this voltage is obtained. However. the feeder impedance is changed again to have a resistance of 2.05 p. 10 which shows that the desired current compensation is maintained. It is to be noted that the gain matrix is designed with the parameters of phase-a of the system and is subsequently used for the other two phases. both the references for terminal voltage as well as the current through the filter capacitor can be formed. Thus. Example 4: Let us consider the same system given in Example 3. at the end of the second cycle (0. at the end of sixth cycle (0. The system is started with the parameters and gain matrix given above where the DSTATCOM is switched at the end of first half cycle. 3) Computation of References: To implement the switching control of (8) using the reduced state feedback.1 p. Fig.u. 9. (9) The selection of lim determines the switching frequency while tracking the reference. The and LQR controller is used with a gain of . For a well-known environment. 4. The results are seen in Fig. The references for the terminal voltage and the current through the filter capacitor must be formed consistent with the compensator reference. a rectifier load that is drawing a peak current of 0. In practice. It can be seen that the power drawn by the load changes dramatically with the introduction of the compensator as it balances the terminal voltage as well. provided is chosen .u. the references for compensator current are computed using (1). the switching is based on (8) where the function is defined by Fig. the system aims to remain in close proximity to the reference. if the reference is suffi- ciently small. After the initial transient is over. When the errors are large and the control is bounded between 1 and 1.35 p. For the tracking problems. a gain matrix can be found that will keep the control value in the desired range (1/2 to 2).04 s). at the end of the fourth cycle (0. the source power becomes constant and the compensator power becomes zero-mean.

In the simplest form of feedback. In order to accommodate this. a proportional-plus-integral (PI) controller is used to correct for any discharge in the capacitor voltage. The capacitor is assumed to be precharged to 1. The results are shown in Fig. It can be seen that after the initial transient.3 s. In practice. The average value can value of be obtained at the end of each cycle or even running average can be can be used as a feedback signal.15 s. where the capacitor value is quoted at the system frequency of 50 Hz to maintain the per unit system (10) The PI controller parameters chosen are is the power lost due to . The system response is shown in Fig. Changes in instantaneous powers and capacitor voltage with load Example 5: Consider the same system as given in Example 4.u.5 p. This is again an ther that the compensator is lossless invalid assumption as there will always be switching losses and losses in the connecting transformer. . and this value is also chosen as the set point for this voltage.. 11.e. the instantaneous powers are shown. Fig. 10. To investigate the effect of load change on the compensator system. dc capacitor is used as shown in Fig. The following per unit quantities have been chosen. System response to changes in the feeder parameters. Control signal and dc capacitor voltage when the control system is started from zero initial condition. The system is started from rest (i. IV. Let us define the following error signal (11) is the average value of the dc capacitor voltage. the source power and the compensator power take longer to settle. modeled here as . it has been assumed that the VSCs of the DSTATCOM are supplied by a dc source. 12. 12(a).GHOSH AND LEDWICH: LOAD COMPENSATING DSTATCOM IN WEAK AC SYSTEMS 1307 Fig. The harmonic currents drawn by the load however remains unchanged. the compensator is connected at the end of first half cycle after the average load power is obtained). the capacitor voltage returns to its desired value. DC CAPACITOR CONTROL So far in the discussion. In Fig. The controller is started from a zero initial condition. 11 in which the capacitor voltage and the control signal are plotted. The controller is then given by (12) is then substituted in (10) and as a result of The value of which an additional amount of real power will be drawn from the source to maintain the dc capacitor voltage. change. These losses will tend to force the dc capacitor to discharge resulting in loss of tracking. The feedback aims to correct the deviation of the average from a reference value . the real power supplied by the source is not only the average load power but also the total of average load power and power lost in the DSTATCOM circuit. Equation (1) can be modified to accommodate this loss as Fig. It has been assumed fur. The DSTATCOM is not assumed to be lossless in this case. The capacitor voltage settles within 0. 12. where measured at the end of a cycle. This is only possible by drawing additional power to overcome the losses due the switching. Even if the load power settles within a couple of cycles. The correction where must be generated through a suitable feedback control such across the storage capacitor is that the dc voltage maintained. 2. the RL component of the load is sudden changed to when the system is operating in the steady state. in the It is therefore imperative that the dc voltage stored is maintained around a prespecified set storage capacitor value. The capacitor voltage settles in about 0.

6) Thus. is the zero-sequence. NO. apart from the half cycle delay in formulation of correct references.5) In a similar way it can show that (A. if is chosen equal to half a cycle (or any integer multiple of half a cycle).2) Defining an error vector as the above two equations that (B. PROOF OF TRACKING CONTROLLER CONVERGENCE The system state space description is given in (5) as (B. the above equation can be evaluated as (A. This has faster settling time for reference extraction compared with cycle by cycle averaging. the addition of the filter capacitor complicates the tracking problem.4) Then from (A.3) From the control law given in (5). the system quantities also settle faster. APPENDIX A VI. APPENDIX B (A. the Fourier coefficients of the instantaneous symmetrical components are able to yield the sequence components. It has been shown that for weak ac buses. The reference current generation scheme along with fundamental extraction of PCC voltage constitutes the reference of this controller. CONCLUSIONS This paper discusses the issues for correction of load unbalance and distortion at a weak ac bus using DSTATCOM. 18. To solve the tracking problem. Let us now define the nent operator is defined as following coefficients: VII. 4.1308 IEEE TRANSACTIONS ON POWER DELIVERY. We recommend the use moving average filter for this half cycle averaging such that the reference signals are continuously extracted as we move along in time. during this transient. the tracking is perfect. if the trajectory remains on the switching surface [7] The above are the complex Fourier coefficients for the fundamental components. OCTOBER 2003 However. . we utilize the method of instantaneous symmetrical component that is defined in [8] Their phasor symmetrical components are then (A. For this. The control scheme proposed in the paper is based on half cycle sliding (moving) averaging. and and are two vectors that are complex conjugate of each other. we propose a method for the extraction of phasor symmetrical components of currents (or voltages) from their samples.2).2) .3) The instantaneous components of these currents are then From (A. the zero-sequence is given by (A.1) where . The distortion in the line current may be eliminated using the fundamental voltage of the PCC in the governing equations. and are the instantaneous three-phase currents. it can be shown from (B. the DSTATCOM may introduce distortion in the line current or the voltage at the point of common coupling.2) Now. EXTRACTING SEQUENCE COMPONENTS FROM SAMPLES In this appendix. However. we have proposed a control scheme that depends on the extraction of the reference signals. Let us define a set of three unbalanced currents phasor terms as . The symmetrical compo.1) Let us form a reference that is defined by (A.[9]. but the voltage distortion cannot be eliminated without adding a filter capacitor in parallel with the DSTATCOM. for a system in steady state. VOL. Consequently. V.

posed as the output of the plant following some reference . “A new method for load balancing and power factor correction using instantaneous symmetrical components. (B. A. In practice. (B. then the condition (3) can be satisfied and perfect tracking can occur. pp. The system states that a bounded and the system states are not necessarily bounded.7) Thus. where he has been since 1998. New York: Macmillan.2). 18.). pp. that It is a property of switching law based on LQR design that condition (1) above is satisfied. Moore. then from (B. C. from (B. [6] M. and Queensland Electricity Commission. Akagi.” IEEE Trans. Jan. Since the source is always bounded. and controls. Brisbane. Ind. and H. A. NJ: Prentice-Hall. D. 1998. [3] H.” IEEE Power Eng. he is a Chair Professor in Electrical Asset Management at the Queensland University of Technology.. he is a Visiting Professor at the Queensland University of Technology. Joshi. Australia. 9. [9] J. 1971. “Control strategy of active power filters using multiple voltage-source PWM converters. Lyon. no. Ghosh and A. Currently. Currently. power electronics. F. Electrical Power Systems Quality. Ind. Lett. Anderson and J. Rev. Nabae. 4th ed. 460–465. “A new approach to load balancing and power factor correction [5] in power distribution system. “A new STATCOM topology to compensate loads containing ac and dc components. IA-22. degree in electrical engineering from the University of Calgary.4) Substituting (B. Newcastle. M. V. Australia. no. 15. Y. Applicat. AB. [8] W. Most tracking problems are . . University of Wisconsin at Madison. 1954. May/June 1986. The task is to define a state reference satisfying In frequency domain.3). This will satisfy condition (2).4) requires . Applicat. the control error can be found as (B.1) is single input. Basic Engineering Circuit Analysis. He has held visiting positions in Nanyang Technological University. Englewood Cliffs. D. New York: McGraw-Hill. Beaty. Power Delivery. vol. Akagi. ch. Singapore. particularly for sinusoidal tracking. 625–630. 2000. O. (Power Eng. and A. W. But if are sufficiently small. vol. and the University of Queensland. 1996. He is also a Professor of Electrical Engineering at the Indian Institute of Technology Kanpur since 1991. IA-20. [4] A. in electrical engineering from the University of Newcastle. Ghosh. 60–62.2). vol. and S.. Linear Optimal Control. K. Atoh. in 1976. He has also held visiting appointments with the University of Calgary. Dugan. 2000. and A. and controls. the output equation can be given as (B. power electronics. Kanazawa.” IEEE Trans. pp.D. Irwin. 2) the reference signal can be generated by an equation in the form of (B. Auckland University in New Zealand.” in IEEE Winter Power Meeting. circuit analysis would be the easiest method to form from . McGranaghan. the error equation becomes (B. 3) Since u is bounded between 1 and 1. Singapore. Mishra. “Instantaneous reactive power compensators comprising switching devices without energy storage components.6) Assuming that the system is tracking a single output and since the plant in (B. 417–422. Nabae. 2. May/June 1984.5) Hence. His interests are in the areas of power systems. Transient Analysis of Alternating-Current Machinery. He was also Head of Electrical Engineering at the University of Newcastle from 1997 to 1998. . 3.7) it can seen implies a bounded . B. [7] B. vol. Australia.4) in (B. any single output-tracking problem can be translated into a state tracking problem and expressed in the form of (B. New York: Wiley.6) Condition (3) cannot be true satisfied for arbitrary references. 1993.8) Thus. in 1983. pp. Gerard Ledwich (M’73–SM’92) received the Ph. Canada.” IEEE Trans. He was associated with the University of Queensland from 1976 to 1994. His research interests include power systems. the tracking error will converge to zero for any initial condition provided that have 1) all the eigenvalues of the matrix negative real parts.D. Arindam Ghosh (S’80–M’83–SM’93) received the Ph.GHOSH AND LEDWICH: LOAD COMPENSATING DSTATCOM IN WEAK AC SYSTEMS 1309 This yields From the above equation. Joshi. REFERENCES [1] R. the corresponding reference state can be formed from (B. [2] H.