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Design And Simulation of New Multilevel Inverter Topology

Design And Simulation of New Multilevel Inverter Topology
DHARAVATH KISHAN
M. Tech Student Scholar Department of Electrical and Electronics Engineering, CMR College Of Engineering & Technology; Medchal (M); RangaReddy (Dt); A.P, India. e-mail: dharavathkishan4@gmail.com PUSHPA DEEPTHI Assistant professor Department of Electrical and Electronics Engineering, CMR College Of Engineering & Technology Medchal (M); RangaReddy (Dt); A.P, India e-mail:deepthi.ponnuri@gmail.com

Abstract
Multilevel inverters have been widely accepted for high-power high-voltage applications. Their performance is highly superior to that of conventional two-level inverters due to reduced harmonic distortion, lower electromagnetic interference, and higher dc link voltages. However, it has some disadvantages such as increased number of components, complex pulse width modulation control method, and voltage-balancing problem. In this paper, a new topology with a reversing-voltage component is proposed to improve the multilevel performance by compensating the disadvantages mentioned. This topology requires fewer components compared to existing inverters (particularly in higher levels) and requires fewer carrier signals and gate drives. Therefore, the overall cost and complexity are greatly reduced particularly for higher output voltage levels. Finally, a prototype of the seven-level proposed topology is built and tested to show the performance of the inverter by experimental results. the disadvantages of traditional inverters. Multilevel inverters can be divided into three remarkable topologies: diode clamped, flying capacitors, and cascaded H-bridge cells with separate DC sources. In addition in recent years, many topologies have been suggested to multilevel converter with a low number of switches and gate driver circuits. Compared with the traditional two-level voltage inverter, the main advantages of the multilevel inverter are a smaller output voltage step, lower harmonic components, a better electromagnetic compatibility and lower switching losses. The main disadvantages of the multilevel inverter are the use of a larger number of semiconductors and a complex control circuitry and needing the equilibrating of the voltage at the boundaries of capacitors. The modulation methods used in multilevel inverters can be classified according to switching frequency. A very popular method in industrial applications is the classic carrier based sinusoidal pulse width modulation (SPWM) that uses the phase shifting technique to reduce the harmonics in the load voltage. Other methods that work with low switching frequencies generally perform one or two commutations of the power semiconductor switches during one cycle of the output voltages, generating a staircase waveform. Representatives of this family are multilevel selective harmonic elimination and space vector control. Modern industrial processes are based on a large amount of electronic devices such as programmable logic controllers and adjustable speed drives. Various power quality problems faced by these industrial and commercial customers. Custom power devices are introduced in the distribution system to deal with various power quality problems. Among various
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I. Introduction In recent years, power electronics engineers have paid great attention to multilevel inverters as a new kind of power converter. Most multilevel inverters have an arrangement of switches and capacitor voltage sources. By a proper control of the switching devices, these can generate stepped output voltages with low harmonic distortions. These multilevel inverters are widely used in manufacturing factories and acquired public recognition as one of the new power converter fields because they can overcome

International Journal of Electrical and Electronics Engineering (IJEEE), ISSN (PRINT): 2231 – 5184, Volume-3, Issue-2, 2013

The S number of sources or stages and the associated number of output level can be written as follows The output voltage of the multilevel inverter is given as. ISSN (PRINT): 2231 – 5184. Issue-2. The operation and performance of the proposed multilevel inverter has been verified on a single-phase nine-level multilevel inverter prototype. These topologies are known as symmetrical multilevel inverters. Vdc2. The drawback of this topology needs a separate DC source for each of H-bridge and involves high number of semiconductor switches. Volume-3. Multi Level Inverters The general structure of cascaded multilevel inverter for a single phase system is shown in Figure 1. the output wave form has seven levels (±3Vdc. Single-phase structure of a multilevel cascaded H-bridges inverter. II. It is fairly easy to generalize the number of distinct levels. Vdc3 is connected in cascade with other sources via a special H-bridge circuit associated with it. 2013 25 . Simulation results verify the theoretical consideration. voltage sags are more serious as they can cause customer equipment to malfunction or a production shutdown. An effective way of controlling the sags is to inject power into the system using DVR. This paper investigates the multilevel inverters and focuses on topologies where the input DC voltages are the same. ±1Vdc and 0). the proposed topology is used in DVR. ±2Vdc. the difference between output waveform and reference sinusoidal waveform would be reduced. Where A1. This enables the manufacturing process to be done more quickly and cheaply. 1. Each Hbridge circuit consists of four active switching elements that can make the output voltage either positive or negative polarity. Each separate voltage source Vdc1. In order to verify the capabilities of proposed inverters in injection of voltage. where it can inject a controllable voltage in series with the supply voltage to keep the voltage constant at the load terminals. The main purpose of this paper is reduction of the components of the multilevel inverters. When the number of levels increases. A2 and A3 are DC voltage sources. The voltage on each stage can be calculated by using the equation. or it can also be simply zero volts which depends on the switching condition of switches in the circuit. This multilevel inverter topology employs three voltage sources of unequal magnitudes. This paper proposes a novel topology for symmetrical multilevel inverter with reduced number of switches. The advantages of cascaded multilevel inverter are modularized layout and packaging. Fig. International Journal of Electrical and Electronics Engineering (IJEEE). The DVR is the best suited to protect sensitive loads against voltage disturbances. For example if S=3. too. The number of controlled switches used in this topology is expressed as.Design And Simulation of New Multilevel Inverter Topology power quality problems.

if S=3. Similarly +3Vdc levels can be achieved by turning on S1. Similarly turning on of switches S1. This inverter consists of a multi conversion cell and an H bridge. similarly for negative half cycle switches Q3 and Q4 must be in ON condition. The main advantage of proposed modified cascaded multilevel inverter is seven levels with only use of seven switches. Volume-3. ±2Vdc. which is outputted as a stepped or approximately sinusoidal AC waveform by the Hbridge inverter. each source connected in cascade with other sources via a circuit consists of one active switching element and one diode that can make the output voltage source only in positive polarity with several levels. 2013 26 . Issue-2. By turning on controlled switches S1 (S2 and S3 turn off) the output voltage +1Vdc (first level) is obtained. The switching table for modified cascaded multilevel inverter is shown in Table I. Figure 2: Topology for modified cascaded multilevel inverter For an example. Similarly voltage on each stage can be calculated by using the equation as given. ±1Vdc and 0). Figure 2 shows the Topology for modified cascaded multilevel inverter. The number switches used in this topology is given by the equation as follows. A multi conversion cell consists of three separate voltage sources (Vdc1. Multi conversion cell converts DC voltage into a stepped DC voltage. Vdc3). S3 switches as shown in Table I.Design And Simulation of New Multilevel Inverter Topology Modified Cascaded Multilevel Inverter The general structure of a proposed cascaded multilevel inverter is shown in Figure 3. The S number of DC sources or stages and the associated number output level can be calculated by using the equation as follows. ISSN (PRINT): 2231 – 5184. S2 (S3 turn off) +2Vdc (second level) output is produced across the load. In this H-bridge. only one of the switches is in ON condition among the paralleled switches. It depicts that for each voltage level. Vdc2. Only one Hbridge is connected with multi conversion cell to acquire both positive and negative polarity. for positive half cycle. S2. switches Q1 and Q2 will be turned on. the output wave form will have seven levels (±3Vdc. International Journal of Electrical and Electronics Engineering (IJEEE).

S10.S8 S10. which is the low-frequency part operating at line frequency. The RV topology in seven levels is shown in Fig. One part is named level generation part and is responsible for level generating in positive polarity.S6.S7.S10 S2.S6. NEW MULTILEVEL TOPOLOGY A. The topology combines the two parts (high frequency and low frequency) to generate the multilevel voltage output.S8.S8. This part. Volume-3.S4. ISSN (PRINT): 2231 – 5184.S2. this part is fed to a full-bridge inverter (polarity generation).S11. The principal idea of this topology as a multilevel inverter is that the left stage in Fig.Design And Simulation of New Multilevel Inverter Topology Seven level CHB Inverter III. which will generate the required polarity for the output.S12 Voltage Level Vdc/3 2Vdc/3 Vdc 0 -Vdc/3 -2Vdc/3 -Vdc International Journal of Electrical and Electronics Engineering (IJEEE). This part requires high-frequency switches to generate the required levels.S9.S6.S8.S12 S3. Figure Shows the seven level multilevel inverter and Table shows the switching states of the seven level inverter Table V Switching table for Full H-Bridge of seven level inverter Switches Turn ON S1. This topology is a hybrid multilevel topology which separates the output voltage into two parts. As can be seen.S12 S1. The other part is called polarity generation part and is responsible for generating the polarity of the output voltage. This idea has been put into practice by the new topology. 1 generates the required output levels (without polarity) and the right circuit (full-bridge converter) decides about the polarity of the output voltage. It reverses the voltage direction when the voltage polarity requires to be changed for negative polarity. In order to generate a complete multilevel output.S12 S3. Issue-2.S8. This will eliminate many of the semiconductor switches which were responsible to generate the output voltage levels in positive and negative polarities.S10. 1.S4. it requires ten switches and three isolated sources. transfers the required output level to the output with the same direction or opposite direction according to the required output polarity. However. The switches in this part should have high-switching-frequency capability. the power semiconductor switches are combined to produce a high-frequency waveform in positive and negative polarities. and then.S10.S6.S12 S3.S12 S1. PROPOSED CONCEPT II.S4. there is no need to utilize all the switches for generating bipolar levels. which is named polarity generation.S10.S2.S5. 2013 27 .S7.S6.S4. the positive levels are generated by the high-frequency part (level generation).S2. General Description In conventional multilevel inverters.S5.

as the dc sources are externally adjustable sources (dc power supplies). In Fig. 3. Number of Components As mentioned earlier. Volume-3. Instead. 4. 2013 . it does not face voltagebalancing problems due to fixed dc voltage values. 5) are chosen for levels 0 up to 3. there is no need for voltage balancing for this work. C. According to the table. In comparison with a cascade topology. the sequences of switches (2–3-4).Design And Simulation of New Multilevel Inverter Topology phase inverter for seven levels is shown with a threephase delta connected system. Fig. This will also help to decrease switching power dissipation. Issue-2. Three-phase RV multilevel topology. In Table I. This topology easily extends to higher voltage levels by duplicating the middle stage as shown in Fig. In order to produce seven levels by SPWM. Highfrequency switches and diodes are expensive and are more prone to be damaged than low-frequency switches. this topology is modular and can be easily increased to higher voltage levels by adding the middle stage in Fig. (2-6-5). 1. (2-3-5). and (1. and the required level is produced by the high-switching-frequency component of the inverter. respectively. there are six possible switching patterns to control the inverter. 1 which should be turned on to generate the required voltage level. 1. 1. 2. According to the aforementioned suggestions. one of the promising advantages of the topology is that it requires less high-switching-frequency components. there is no need for extra conditions for controlling the negative voltage. However. It can also be applied for three-phase applications with the same principle. 2. the switching modes should be selected so that the switching transitions become minimal during each mode transfer. These sequences are shown in Fig. This topology uses isolated dc supplies. this level is translated to negative or positive according to output voltage requirements. ISSN (PRINT): 2231 – 5184. it does not need to generate negative pulses for negative cycle control. the numbers show the switch according to Fig. Therefore. Thus. the complete three28 International Journal of Electrical and Electronics Engineering (IJEEE). As can be observed from Fig. 3. This topology is redundant and flexible in the switching sequence. Schematic of a seven-level inverter in single phase. three saw-tooth waveforms for carrier and a sinusoidal reference signal for modulator are required as shown in Fig. It shows the great redundancy of the topology. the output voltage levels are generated in this part by appropriate switching sequences. Fig. it requires just one-third of isolated power supplies used in a cascade-type inverter. Then. the reversing full-bridge converter performs this task. Different switching modes in generating the required levels for a seven-level RV inverter are shown in Table I. which are included in the current path that is marked in bold. Therefore. The ultimate output voltage level is the sum of voltage sources. B. Switching Sequences Switching sequences in this converter are easier than its counter parts. According to its inherent advantages. In order to avoid unwanted voltage levels during switching cycles.

Issue-2. In the proposed converter. Thus. MATLAB/SIMULINK RESULTS: Fig 1. the reliability of a system is indirectly proportional to the number of its components.1:The above figure shows the Simulation Circuit diagram Single phase Seven Level Inverter Fig 2. half of the switches in the full-bridge converter will not require to be switched on rapidly since they are only switched at zero crossings operating at line frequency (50 Hz). as can be seen.3: The above figure shows the Simulation Output Voltage Wave forms of Single Phase Seven Level Inverter Fig 1. in this case. 2013 29 . ISSN (PRINT): 2231 – 5184. The number of required three-phase components according to output voltage levels.2: The above figure shows the Simulation Circuit of RPhase Sub-System International Journal of Electrical and Electronics Engineering (IJEEE).Design And Simulation of New Multilevel Inverter Topology According to the MIL-HDBK-217F standard.2: The above figure shows the Simulation Control Circuit of Single Phase Seven Level Inverter Fig 2. as the number of high-frequency switches is increased. the reliability of the converter and also related expenses are highly improved. the reliability of the converter is decreased. Therefore.1: The above figure shows the Simulation Circuit of Three phase Seven Level Inverter Fig 1. Volume-3. IV.

5: The above figure shows the Simulation circuit B-Phase Sub-System Fig 2.6: The above figure shows the Simulation Control Circuit of B-Phase Sub-System Fig 2. 2013 30 . ISSN (PRINT): 2231 – 5184.4: The above figure shows the Simulation Control Circuit of Y-Phase Sub-System International Journal of Electrical and Electronics Engineering (IJEEE).4: The above figure shows the Simulation Circuit of YPhase Sub-System Fig 2.7: The above figure shows the Simulation Output Voltage Wave Form of three phase Seven Level Inverter Fig 2. Issue-2. Volume-3.3: The above figure shows the Simulation Control Circuit of R-Phase Sub-System Fig 2.Design And Simulation of New Multilevel Inverter Topology Fig 2.

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