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# VLSI Sytem Design Syllabus:

UNIT I INTRODUCTION Introduction to IC technology, The IC Era, MOS and related VLSI Technology, Basic MOS transistors, Enhanced and Depletion modes of transistor action, IC production process, MOS and CMOS a!rication process, BiCMOS technology, Comparison !et"een CMOS and Bipolar technologies UNIT II BASIC ELECTRICAL PROPERTIES o !OS an" BiC!OS Ci#\$uits Ids#Vds relationships, \$spects of MOS Threshold Voltage, MOS Transistor transconductance and output conductance, MOS transistor figure of merit, pass transistor, %MOS in&erter, Determination of pull up to pull do"n ratio for nMOS in&erter dri&en !y another nMOS in&erter, Determination of pull up to pull do"n ratio for nMOS in&erter Dri&en through one or more pass transistors, \$lternati&e forms of pull#ups, The CMOS in&erter, MOS Transistor circuit model and design, BiCMOS in&erters, Latch up in CMOS and BiCMOS latchup suscepti!ility UNIT III !OS an" BiC!OS CIRCUIT DESI%N PROCESSES MOS layers, Stic' diagrams, Design (ules and Layout, )eneral o!ser&ations on the design rules, * um CMOS design rules for "ires, * um Dou!le Metal, Dou!le +oly, CMOS,BiCMOS rules, -.* um Dou!le Metal, Dou!le +oly CMOS rules, Layout Diagrams of %\$%D and %O( gates and CMOS in&erter, Sym!olic Diagrams# Translation to Mas' orm UNIT IV BASIC CIRCUIT CONCEPTS: Sheet resistance, Sheet (esistance concept applied to MOS transistors and In&erters, \$rea Capacitance of layers, standard unit capacitance, Some area capacitance calculation, The delay /nit, In&erter Delays, Dri&ing Large Capaciti&e loads, +ropagation Delays, 0iring capacitances, an in an out characteristics, Choice of layers, transistor s"itches, reali1ation of gates using nMOS and CMOS technologies

UNIT V S\$aling O !OS Ci#\$uits: Scaling models and scaling factors, Scaling factors for de&ice parameters, Limitations of Scaling, Limits due to su! threshold currents, Limits on Logic le&els and supply &oltage due to noise, Limits due to current density, some architectural issues, Introduction to

s"itch logic and gate logic UNIT VI SE!ICONDUCTOR INTE%RATED CIRCUIT DESI%N Introduction to +rogramma!le logic De&ices 2+LDs3, +L\$s, +\$Ls, Implementation approach in VLSI Design, ull Custom Design, Semi Custom design, )ate arrays, standard cells, +)\$s, C+LDs

UNIT VII Digital Design Using &DL: Digital system Design +rocess, VLSI circuit Design +rocess, 4ard"are Simulation, 4ard "are synthesis, 4istory of V4DL, V4DL re5uirements, Le&els of \$!straction, Elements of V4DL, +ac'ages, Li!raries and Binding, O!6ects and Classes, Varia!le assignments, Se5uential statements, /sage of Su!programs, Comparison of V4DL and Verilog 4DL

UNIT VIII V4DL MODELLI%)7 Simulation, Logic Synthesis, Inside a logic Synthesi1er, Constraints, Technology Li!raries, V4DL and Logic Synthesis, unctional )ate Le&el Verification, +lace and (oute, +ost Layout Timing Simulation, Static Timing, Ma6or %etlist ormats for design representation, V4DL Synthesis# +rogramming \$pproach. I'( TE'T BOO)S: -. Essentials of VLSI circuits and systems 8 9amran Eshraghian, Eshraghian Dougles and \$. +uc'nell, +4I, *::; Edition. *. VLSI DESI)%#\$. Shanti and \$. 9a&itha, %e" age International +ri&ate Limited, *::< irst Edition. =. VLSI DESI)% # 9. Lal 9ishore, V.S.V +ra!ha'ar, I.9 International, *::>.
RE*ERENCES

-. VLSI DESI)% By De!aprasad Das, O?ford /ni&ersity +ress, *:-: *. VLSI DESI)% By \$l!ert (a6 @ T. Latha, +4I Learning +ri&ate Limited, *:-:. =. +rinciples of VLSI and CMOS Integrated Circuits By (icha Aain @ \$mrita (ai, S.Chand @ Company Limited, irst Edition, *:-*