Ordering number : ENN6928

CMOS IC

LC75411ES, 75411WS
Electronic Volume Controller for Car Audio Systems

Overview
The LC75411ES and 75411WS are electronic volume controllers that enable control of volume, balance, fader, bass/treble, loudness, input switching, and input gain using only a small number of external components.

Features
• On-chip buffer amplifier cuts down number of external components • Low switching noise generated by on-chip switch through use of silicon gate CMOS process, for low switching noise when there is no signal • Low switching noise when there is a signal due to use of on-chip zero-cross switching circuit • On-chip 1/2 VDD reference voltage circuit • Controls performed with serial input (CCB)

Functions
• Volume: 0 dB to –79.5 dB in 0.5-dB steps, and –∞ (161 positions) Balance function with separate L/R control • Fader: rear output or front output can be attenuated across 16 positions (in 1-dB steps from 0 dB to –2 dB, 2-dB steps from –2 dB to 20 dB, 10-dB steps from –20 dB to –30 dB, and –45 dB, –60 dB, –∞) • Bass/treble: Both bass and treble can be controlled in 1-dB steps from 0 dB to ±6 dB, and in 2-dB steps from ±8 dB to ±12 dB. • Input gain: 0 dB to +18.75 dB (1.25-dB steps) amplification is possible for the input signal. • Input switching: four input signals can be selected for Left and for Right • Loudness: A tap is output from the –32 dB position of a 2 dB step volume control resistor ladder. A loudness function can be implemented by connecting an external RC circuit.

• CCB is a trademark of SANYO ELECTRIC CO., LTD. • CCB is SANYO’s original bus format and all the bus addresses are controlled by SANYO.

Any and all SANYO products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft’s control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO representative nearest you before using any SANYO products described or contained herein in such applications. SANYO assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO products described or contained herein.

SANYO Electric Co.,Ltd. Semiconductor Company
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
62901RM (OT) No. 6928-1/34

LC75411ES, 75411WS

Package Dimensions
unit: mm 3148-QIP44MA
[LC75411ES]
13.2 10.0 1.0 0.8 0.35
33 34 23

unit: mm 3163A-SQFP48
[LC75411WS]
1.6 1.0
22

9.0 7.0

1.6

0.2

0.75
36 37

0.5

0.18
25

0.75

0.15

13.2 10.0 0.8 1.0

9.0 7.0

0.5

0.75

24

44

0.1 2.5

1

12

11.6

0.8

0.5

0.1 0.5

SANYO: QIP44MA

Pin Assignment [LC75411ES]
LVROUT LCOM LTOUT LF1C1 LF1C2 LF1C3 LF3C1 LVRIN

33

32

31

30

29

LTIN

LCT

28

27

26

25

24

23 22 LFOUT 21 LROUT 20 VSS 19 CL 18 DI

LSELO 34 L4 35 L3 36 L2 37 L1 38 VDD 39 Vref 40 R1 41 R2 42 R3 43 R4 44
1 2 3 4 5 6 7 8 9 10 11

LC75411ES

LFIN

17 CE 16 TEST 15 TIM 14 RROUT 13 RFOUT 12 RFIN

RSELO

RVRIN

RCT

RCOM

RVROUT

RTIN

RF1C1

RF1C2

RF1C3

RF3C1

RTOUT

1.7max

1

12 11

2.8max

1.0

48

13

0.75

SANYO: SQFP48

No. 6928-2/33

4.7kΩ 0.1µF 0.1µF 0.1µF 10µF 220pF 68kΩ 1µF 10µF 10µF LF1C1 LF1C2 LF1C3 LTIN LVRIN LCT LTOUT LCOM LVROUT LSELO
34 33 32 31 30 29 28 27 26 25 24 23

[LC75411ES]

[BASS fo=100Hz]

[TREBLE]

2700pF LF3C1 LFIN LFOUT LROUT
21
PA

1µF × 4 LVref
22

L4 LVref

10µF
PA

Equivalent Circuit Block Diagram

35

L3

36

L2 LVref

37

20

VSS CL
19

10µF

L1
Multiplexer
ZEROCROSS DET

38

CL
CCB INTERFACE
18

VDD LVref
CONTROL CIRCUIT LOGIC CIRCUIT Multiplexer
ZEROCROSS DET

39

DI CE
17

DI CE VDD
NO SIGNAL TIMER
16

Microcontroller

22µF RVref

Vref

40

LC75411ES, 75411WS

R1 RVref

41

TEST TIM
15

R2

42

R3 RVref

RROUT
14

0.033µF
PA

43

R4

RFOUT RVref
13

10µF
PA

44

12

RFIN

10µF

1

2

3

4

5

6

7

8

9

10

11

RTIN

RF1C1

RF1C2

RF1C3

RCT

RCOM

RVRIN 10µF 68kΩ 0.1µF 4.7kΩ

RTOUT

RVROUT

RF3C1 2700pF

220pF

RSELO 1µF

10µF 10µF 0.1µF [BASS fo=100Hz] 0.1µF

No. 6928-3/33

[TREBLE]

LC75411ES, 75411WS Sample Application Circuit [LC75411ES]

0.1µF 4.7kΩ 68kΩ 1µF 220pF LVROUT LVRIN LCOM 10µF 10µF 0.1µF LF1C1 LF1C2

2700pF

0.1µF LTOUT
24

10µF LF3C1

LTIN

LF1C3

33

32

31

30

29

28

27

26

25

LFIN
23 22 21 20 19 18

LCT

LSELO 1µF 1µF 1µF 1µF VDD 22µF 1µF 1µF 1µF 1µF L4 L3 L2 L1 VDD Vref R1 R2 R3 R4

34 35 36 37 38 39 40 41 42 43 44 1 2 3 4 5 6 7 8 9 10 11

LFOUT LROUT DVSS CL DI CE TEST TIM RROUT RFOUT RFIN

10µF
PA PA

10µF

Microcontroller

LC75411ES

17 16 15 14 13 12

0.033µF 10µF
PA PA

10µF

RSELO

RCT

RCOM

RVROUT

RF1C1

RF1C2

RF1C3

RF3C1

1µF 220pF 68kΩ 4.7kΩ 0.1µF 10µF

RTOUT 10µF

RVRIN

10µF

RTIN

0.1µF 0.1µF

2700pF

No. 6928-4/33

LC75411ES, 75411WS Pin Assignment [LC75411WS]

LVROUT

LCOM

LTIN

LCT

LTOUT
26

LSELO

LF1C1

LF1C2

LF1C3

LF3C1

LVRIN

36

35

34

33

32

31

30

29

28

27

25 24 LFIN 23 LFOUT 22 LROUT 21 VSS 20 CL 19 DI

L4 37 L3 38 L2 39 L1 40 NC 41 VDD 42 Vref 43 NC 44 R1 45 R2 46 R3 47 R4 48
1 2 3 4 5 6 7 8 9 10 11 12

LC75411WS

NC
18 CE 17 TEST 16 TIM 15 RROUT 14 RFOUT 13 RFIN

RSELO

RCT

RCOM

RVROUT

RF1C1

RF1C2

RF1C3

RF3C1

RTOUT

RVRIN

RTIN

NC

No. 6928-5/33

4.7kΩ 220pF 0.1µF 0.1µF 10µF 68k Ω 2700pF 10µF 10µF NC
25

[LC75411WS]

0.1µF

[BASS fo=100Hz]

[TREBLE]

1µF LF1C1 LF1C2 LF1C3 LF3C1 LTOUT LTIN LSELO LCOM LCT LVROUT LVRIN
36 35 34 33 32 31 30 29 28 27 26

1µF × 4
24

L4 LFOUT LROUT
22

37

LFIN 10µF
PA

Equivalent Circuit Block Diagram

LVref

L3
23

38

L2

LVref

39

PA

L1 LVref

40

21

VSS CL
20

10µF

NC 41
Multiplexer
ZEROCROSS DET

CL
CCB INTERFACE
19

VDD LVref
CONTROL CIRCUIT LOGIC CIRCUIT Multiplexer
ZEROCROSS DET

42

DI CE
18

DI CE VDD
NO SIGNAL TIMER
17

Microcontroller

22µF RVref RVref

Vref

43

NC 44

TEST TIM
16

LC75411ES, 75411WS

R1

45

R2 RVref

RROUT
15

0.033µF
PA

46

R3

RFOUT RVref
14

10µF
PA

47

R4

48

13

RFIN

10µF

1

2

3

4

5

6

7

8

9

10

11

12

NC

RTIN

RVROUT

RF1C1

RF1C2

RF1C3

RF3C1

RCT

RCOM

RVRIN 10µF

RTOUT

2700pF

1µF 68kΩ 220pF

RSELO 4.7kΩ

10µF 10µF 0.1µF 0.1µF

0.1µF

No. 6928-6/33

[BASS fo=100Hz]

[TREBLE]

LC75411ES, 75411WS Sample Application Circuit [LC75411WS]

0.1µF 4.7kΩ 68kΩ 220pF 1µF LVROUT LSELO LVRIN LCOM 10µF 10µF 0.1µF LF1C1 LF1C2

2700pF

0.1µF LTOUT
26

10µF LF3C1

LTIN

LF1C3

LCT

36

35

34

33

32

31

30

29

28

27

25 24 23 22 21 20 19

1µF 1µF 1µF 1µF

L4 L3 L2 L1

NC

37 38 39 40

LFIN LFOUT LROUT VSS CL DI CE TEST TIM RROUT RFOUT RFIN 10µF 10µF
PA PA

10µF
PA PA

10µF

NC 41 VDD 22µF VDD Vref
42 43

LC75411WS

Microcontroller

18 17 16 15 14 13

NC 44 1µF 1µF 1µF 1µF R1 R2 R3 R4
45 46 47 48 1 2 3 4 5 6 7 8 9 10 11 12

RSELO

RVRIN

RVROUT

RTIN

RTOUT

RCT

RCOM

RF1C1

RF1C2

RF1C3

RF3C1

1µF 220pF 68kΩ

10µF 10µF

0.1µF 0.1µF

10µF

4.7kΩ 0.1µF 2700pF

NC

No. 6928-7/33

LC75411ES, 75411WS

Specifications
Absolute Maximum Ratings at Ta = 25°C, VSS = 0 V
Parameter Maximum supply voltage Maximum input voltage Allowable power dissipation Operating temperature Storage temperature Symbol VDD max VIN max Pd max Topr Tstg VDD All input pins Ta ≤ 85°C, when mounted on board LC75411ES LC75411WS Conditions Ratings 11 VSS – 0.3 to VDD + 0.3 600 550 –40 to +85 –50 to +125 Unit V V mW °C °C

Allowable Operating Ranges at Ta = 25°C, VSS = 0 V
Parameter Supply voltage Input high-level voltage Input low-level voltage Input amplitude voltage Input pulse width Setup time Hold time Operating frequency Symbol VDD VIH VIL VIN TøW Tsetup Thold fopg CL CL, DI, CE CL, DI, CE CL VDD CL, DI, CE, TEST CL, DI, CE, TEST Conditions Ratings min 6.0 4.0 VSS VSS 1 1 1 500 typ max 10.5 10.5 1.0 VDD Unit V V V Vp-p µs µs µs kHz

Electrical Characteristics at Ta = 25°C, VDD = 9 V, VSS = 0 V
Parameter [Input block] Input resistance Minimum input gain Maximum input gain Step setting error L/R balance [Volume Block] Input resistance Step setting error L/R balance [Tone block] Step setting error Bass control range Treble control range L/R balance ATerr Gbass Gtre BAL max. boost/cut max. boost/cut ±9 ±9 ±12 ±12 ±1.0 ±15 ±15 ±0.5 dB dB dB dB Rvr ATerr BAL LVRIN, RVRIN, loudness off 113 226 452 ±0.5 ±0.5 kΩ dB dB Rin Ginmin Ginmax ATerr BAL L1 to L4, R1 to R4 L1 to L4, R1 to R4 25 –1 +16.5 50 0 +18.75 100 +1 +21 ±0.5 ±0.5 kΩ dB dB dB dB Symbol Pin Name Conditions Ratings min typ max Unit

Continued on next page.

No. 6928-8/33

LC75411ES, 75411WS
Continued from preceding page.
Parameter [Fader Block] Input resistance Rfed LFIN, RFIN 0dB to –2dB Step setting error ATerr –2dB to –20dB –20dB to –30dB –30dB to –60dB L/R balance [General] Total harmonic distortion Input crosstalk L/R crosstalk Maximum attenuated output THD (1) THD (2) CT CT VIN = –10dBV, f = 1 kHz VIN = –10dBV, f = 10 kHz VIN = 1Vrms, f = 1 kHz VIN = 1Vrms, f = 1 kHz 80 80 80 90 0.004 0.006 88 88 88 95 5 7 33 CL, DI, CE, VIN = 9 V CL, DI, CE, VIN = 0 V THD = 1%, RL = 10 kΩ flat overall, fIN = 1 kHz –10 2.5 2.9 10 15 40 10 0.01 0.01 % % dB dB dB dB µV µV mA µA µA Vrms BAL 25 50 100 ±0.5 ±1 ±2 ±3 ±0.5 kΩ dB dB dB dB dB Symbol Pin Name Conditions Ratings min typ max Unit

Vomin (1) VIN = 1Vrms, f = 1 kHz VIN = 1Vrms, f = 1 kHz Vomin (2) INMUTE, fader –∞ VN (1) VN (2) IDD IIH IIL VCL Flat overall, IHF-A filter Flat overall, 20 to 20 kHzBPF

Output noise voltage Current drain Input high-level current Input low-level current Maximum input voltage

Control Timing and Data Format To control the LC75411ES and LC75411WS input specified serial data to the CE, CL, and DI pins. The data configuration consists of a total of 52 bits broken down into 8 address bits and 44 data bits.
CE DI CL
B0 B1 B2 B3 A0 A1 A2 A3 D0 D1 D2 D3 D4 D5 D38 D39 D40 D41 D42 D43

CE
1µs min

1µs 1µs 1µs min min min

1µs min

CL

DI
1µs min ≤ TDEST

No. 6928-9/33

LC75411ES, 75411WS Address code (B0 to A3) The LC75411ES and 75411WS use 8-bit address code and can be used in common with ICs that support SANYO’s CCB serial bus. Address Code
(LSB) B0 1 B1 0 B2 0 B3 0 A0 0 A1 0 A2 0 A3 1 (81HEX)

Control code allocation Input Switching Control
D0 0 1 0 1 D1 0 0 1 1 D2 0 0 0 0 Setting L1 (R1) L2 (R2) L3 (R3) L4 (R4) Setting

0 1

1 1

1 1

For IC testing: Normally not used

D3

Bit for IC testing: Normally set to 0

Input Gain Control
D4 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 D5 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D6 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 D7 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0dB +1.25dB +2.50dB +3.75dB +5.00dB +6.25dB +7.50dB +8.75dB +10.0dB +11.25dB +12.5dB +13.75dB +15.0dB +16.25dB +17.5dB +18.75dB Operation

No. 6928-10/33

LC75411ES, 75411WS Volume Control (0 to –20.5dB)
D8 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 D9 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 D10 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 D11 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 D12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 D13 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D15 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0dB –0.5dB –1dB –1.5dB –2dB –2.5dB –3dB –3.5dB –4dB –4.5dB –5dB –5.5dB –6dB –6.5dB –7dB –7.5dB –8dB –8.5dB –9dB –9.5dB –10dB –10.5dB –11dB –11.5dB –12dB –12.5dB –13dB –13.5dB –14dB –14.5dB –15dB –15.5dB –16dB –16.5dB –17dB –17.5dB –18dB –18.5dB –19dB –19.5dB –20dB –20.5dB Operation

No. 6928-11/33

LC75411ES, 75411WS Volume Control (–21 to –40.5dB)
D8 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 D9 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 D10 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 D11 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 D12 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D13 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 D14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D15 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Operation –21dB –21.5dB –22dB –22.5dB –23dB –23.5dB –24dB –24.5dB –25dB –25.5dB –26dB –26.5dB –27dB –27.5dB –28dB –28.5dB –29dB –29.5dB –30dB –30.5dB –31dB –31.5dB –32dB –32.5dB –33dB –33.5dB –34dB –34.5dB –35dB –35.5dB –36dB –36.5dB –37dB –37.5dB –38dB –38.5dB –39dB –39.5dB –40dB –40.5dB

No. 6928-12/33

LC75411ES, 75411WS Volume Control (–41 to –59.5dB)
D8 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D9 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 D10 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 D11 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 D12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 D13 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 D14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D15 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Operation –41dB –41.5dB –42dB –42.5dB –43dB –43.5dB –44dB –44.5dB –45dB –45.5dB –46dB –46.5dB –47dB –47.5dB –48dB –48.5dB –49dB –49.5dB –50dB –50.5dB –51dB –51.5dB –52dB –52.5dB –53dB –53.5dB –54dB –54.5dB –55dB –55.5dB –56dB –56.5dB –57dB –57.5dB –58dB –58.5dB –59dB –59.5dB

No. 6928-13/33

LC75411ES, 75411WS Volume Control (–60 to –∞)
D8 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 D9 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 D10 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 D11 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 D12 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 D13 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 D14 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 D15 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Operation –60dB –60.5dB –61dB –61.5dB –62dB –62.5dB –63dB –63.5dB –64dB –64.5dB –65dB –65.5dB –66dB –66.5dB –67dB –67.5dB –68dB –68.5dB –69dB –69.5dB –70dB –70.5dB –71dB –71.5dB –72dB –72.5dB –73dB –73.5dB –74dB –74.5dB –75dB –75.5dB –76dB –76.5dB –77dB –77.5dB –78dB –78.5dB –79dB –79.5dB –∞

No. 6928-14/33

LC75411ES, 75411WS Tone Control
D16 D24 0 1 0 1 1 0 0 1 1 0 1 1 0 0 1 1 0 1 0 D17 D25 1 0 0 1 1 1 1 0 0 0 0 0 1 1 1 1 0 0 1 D18 D26 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 D19 D27 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 D40 D42 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 +12dB +10dB +8dB +6dB +5dB +4dB +3dB +2dB +1dB 0dB –1dB –2dB –3dB –4dB –5dB –6dB –8dB –10dB –12dB Bass Treble

D20 0

D21 0

D22 0

D23 0

D41 0 Set to 0

Setting

Fader Volume Control
D28 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 D29 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D30 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 D31 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0dB –1dB –2dB –4dB –6dB –8dB –10dB –12dB –14dB –16dB –18dB –20dB –30dB –45dB –60dB –∞ Operation

Channel Selection Control
D32 0 1 0 1 D33 0 0 1 1 Operation Initial setting mode: Rapid charging RCH LCH L/R simultaneously

No. 6928-15/33

LC75411ES, 75411WS Fader Rear/Front Control
D34 0 1 Setting Rear Front

Loudness Control
D35 0 1 Setting OFF ON

Zero-Cross Control
D36 0 1 D37 0 1 Setting Data write through zero-cross detection Zero-cross detection stopped (data write at falling edge of CE)

Zero-Cross Signal Detection Block Control
D38 0 1 0 1 D39 0 0 1 1 Selector Volume Tone Fader Setting

Test Mode Control
D43 0 Setting For IC testing. Always set to 0.

No. 6928-16/33

LC75411ES, 75411WS Pin Functions
Pin Name Pin No. LC75411ES LC75411WS 38 37 36 35 41 42 43 44 40 39 38 37 45 46 47 48 • Single-end input pin Function Equivalent circuit

L1 L2 L3 L4 R1 R2 R3 R4

VDD

LVref RVref VDD

LSEL0 RSEL0

34 1

36 1

• Input selector output pins

VDD

LVRIN RVRIN

33 2

35 2

• 2-dB step volume input pins • Perform input at low-impedance.

LVref RVref

VDD
LCT RCT 32 3 34 3 • Loudness pins. Connect high-pass compensation RC between LCT (RCT) and LVRIN (RVRIN), and connect low-pass compensation RC between LCT (RCT) and GND.

VDD
LCOM RCOM 31 4 33 4 • 2-dB stop volume output pins. • Connect these pins to GND through coupling capacitors to reduce switching noise.

VDD
LVROUT RVROUT 30 5 32 5 • 0.5-dB step volume output pin

VDD
LTIN RTIN 29 6 31 6

• Equalizer input pin

Lvref RVref Continued on next page.

No. 6928-17/33

LC75411ES, 75411WS
Continued from preceding page.
Pin Name Pin No. LC75411ES LC75411WS Function Equivalent circuit

VDD VDD TIN

LF1C1 LF1C2 LF1C3 RF1C1 RF1C2 RF1C3

28 27 26 7 8 9

30 29 28 7 8 9 • Equalizer F1 band filter configuration capacitor connection pins. Connect capacitor between LF1C1 (RF1C1) and LF1C2 (RF1C2) LF1C2 (RF1C2) and LF1C3 (RF1C3)

Vref

VDD FnC1 FnC3

VDD

FnC2

VDD

LF3C1 RF3C1

25 10

27 10

• Equalizer F3 band circuit filter configuration capacitor connection pins. Connect high-pass compensation capacitor between LF3C1 (RF3C1) and VSS.

VDD C1

VDD
LTOUT RTOUT 24 11 26 11 • Equalizer output pins

VDD
LFIN RFIN 23 12 24 13 • Fader block input pins • Drive at low impedance.

VDD
LFOUT LROUT RFOUT RROUT 22 21 13 14 23 22 14 15 • Fader output pins. Attenuation is possible separately for the front end and rear end. The attenuation amount is the same for L and R.

VDD

Vref

40

43

• Connect a capacitor of a few tens of µF between Vref and VSS as a 0.55 VDD voltage generator, current ripple countermeasure.

LVref RVref Continued on next page.

No. 6928-18/33

LC75411ES, 75411WS
Continued from preceding page.
Pin Name Pin No. LC75411ES LC75411WS Function Equivalent circuit

VDD

39

42

• Power supply pin

VSS

20

21

• Ground pin

VDD
TEST 16 17 • Dedicated IC test pin • Normally this pin is used connected to GND.

VDD
TIM 15 16 • Timer pin when there is no signal in the zero-cross circuit. Forcibly set data when there is no zero-cross signal, from the time the data is set until the timer ends.

CL DI

19 18

20 19

• Input pin for serial data and clock used for control

VDD

CE

17

18

• Chip enable pin. Data is written to the internal latch and the analog switches are operated when the level changes from High to Low. Data transfer is enabled when the level is High.

12 NC — 25 41 44 • No Connect pin. Leave this pin open or connect it to VSS.

No. 6928-19/33

LC75411ES, 75411WS Internal Equivalent Circuit Block Diagram Selector Block Equivalent Circuit Block Diagram

L4 50k LVref L3 50k LVref L2 50k LVref L1 50k LVref INMUTE SW 0dB 6.702k 1.25dB 5.804k 2.50dB 5.026k 3.75dB 4.352k 5.00dB 3.769k 6.25dB 3.264k 7.50dB 2.826k 8.75dB 2.447k 10.0dB LVref 11.25dB Total resistance: 50 kΩ Same for right channel Unit (Resistance: Ω) 1.835k 12.5dB 1.589k 13.75dB 1.376k 15.0dB 1.192k 16.25dB 1.032k 17.5dB 0.894k 18.75dB 5.774k LVref 2.119k

LSELO

No. 6928-20/33

LC75411ES, 75411WS 2-dB Volume Block Equivalent Circuit Block Diagram

LVRIN 0dB 41.139k 32.678k 25.957k 20.618k 16.378k 13.009k Total resistance of 195 kΩ over tap 10.334k 8.208k –16dB 6.520k –18dB 5.179k Initial setting switch 4.114k –22dB 3.268k 2.596k 2.062k 1.638k 1.301k LCT 6.344k 5.040k 5.750k 4.003k 3.180k 2.526k 2.006k 1.594k 1.266k Total resistance of 30.847 kΩ under tap 1.006k 0.799k –52dB 0.634k 0.504k 0.400k 0.318k –60dB 0.253k 0.201k –64dB 0.159k 0.127k –68dB 0.101k 0.080k –72dB 0.063k 0.050k –76dB 0.040k –78dB 0.154k –∞dB LVref –74dB –70dB –66dB –62dB –56dB –58dB –54dB –48dB –50dB –40dB –42dB –44dB –46dB –32dB –34dB –36dB –38dB –24dB –26dB –28dB –30dB Same for right channel Unit (Resistance: Ω) –20dB –2dB –4dB –6dB –8dB –10dB –12dB –14dB To left channel 0.5–dB block

No. 6928-21/33

LC75411ES, 75411WS 0.5-dB Volume Block Equivalent Circuit Block Diagram

From left channel 2-dB block 2.797k

LVROUT 0dB –0.5dB

Initial setting switch

2.640k –1dB 2.493k –1.5dB 42.070k –∞dB Vref Initial setting switch

Unit: Ω Total resistance: 50 kΩ Same for right channel

LCOM

No. 6928-22/33

LC75411ES, 75411WS Tone Block Equivalent Circuit Diagram

LTOUT

LTIN 50k LVref

SW2 SW1

SW3 SW1

SW2

SW3

0.027k 12dB 3.373k 10dB 4.246k 8dB 5.346k 6dB 3.172k 5dB 3.558k 4dB 3.993k 3dB 4.480k 2dB 5.027k 1dB 5.640k 0dB

SW4

12.840k 12dB 3.373k 10dB 4.246k 8dB 5.346k 6dB 3.172k 5dB 3.558k 4dB 3.993k 3dB 4.480k 2dB 5.027k 1dB 5.640k 0dB

SW4

6.50k

LF1C1

LF1C2

LF1C3

LF3C1

Unit: Ω Total resistance: 38.861 kΩ Same for right channel During boost, SW 1 and SW 3 are ON, during cut SW 2 and SW 4 are ON, and when 0 dB, 0 dB SW and SW 2 and SW 3 are ON.

No. 6928-23/33

LC75411ES, 75411WS Tone Circuit Constant Calculation Example Bass Band Circuit The equivalent circuit and the formula for calculating the external RC with a mean frequency of 100 Hz are shown below. • Bass band equivalent circuit block diagram

C1

R1

R2

C2

R3

• Calculation example Specification Mean frequency: f0 = 100 Hz Gain during maximum boost: G = 12 dB Let us use R1 = 0, R2 = 38.861 kΩ, R3 = 6.5 kΩ (assuming R1 = 0 during maximum boost) , and C1 = C2 = C. 1. We obtain C from mean frequency f0 = 100 Hz, as follows.

f0= C=

1 2π R3R2C1C2

1 1 = ≅ 0.1µF 2πf0 R3R2 2π × 100 38861×6500

2. We obtain Q as follows.

Q=

R3R2 1 × ≅ 1.223 2 R3 R3R2

No. 6928-24/33

LC75411ES, 75411WS Treble Band Circuit The shelving characteristics for the treble band can be obtained. The equivalent circuit and the calculation formula during boost are shown below.

C

R1

R2

• Calculation example Specification Setting frequency: f = 26000 Hz Gain during maximum boost: G = 12 dB Let us use R1 = 12.840 kΩ and R2 = 38.861 kΩ The above constants are inserted in the following formula.

G = 20 × LOG10 1 +

R2 R12 + (1 / ωC ) 2

C= 2πf ( 10

1 R2
G / 20

–1

) 2 – R12 1

= 2π × 26000

38861 3.981 – 1

2

≅ 2700(pF) – 12840 2

No. 6928-25/33

LC75411ES, 75411WS Fader Volume Block Equivalent Circuit Block Diagram
S1 LFIN 0dB 5.437k –1dB 4.846k –2dB 8.169k –4dB 6.489k –6dB 5.154k –8dB 4.094k –10dB 3.252k –12dB 2.583k –14dB 2.052k –16dB 1.630k –18dB 1.295k –20dB 3.419k –30dB 1.300k –45dB 0.231k –60dB 0.050k –∞dB Unit: Ω Total resistance: 50 kΩ When FADER = "1", S2 and S3 are ON. When FADER = "0", S1 and S4 are ON. S4 LROUT S3 S2 LFOUT

LVref When –∞ data is sent to the main volume 0.5dBSTEP, S1 and S2 become open, and S3 and S4 simultaneously become ON.

No. 6928-26/33

LC75411ES, 75411WS Usage Cautions (1) Data transmission at power ON • The status of internal analog switches is unstable at power ON. Therefore, perform muting or some other countermeasure until the data has been set. • At power ON, initial setting data must be sent once in order to stabilize the bias of each block in a short time.

(2) Description of zero-cross switching circuit operation The LC75411ES and 75411WS have a function to switch zero-cross comparator signal detection locations, enabling the selection of the optimum detection location for blocks whose data is to be updated. Basically, the switching noise can be minimized by inputting the signal immediately following the block whose data is to be updated to the zerocross comparator, so it is necessary to switch the detection location every time.

Selector

Volume

Tone

Fader

Switch Zero-cross comparator

LC75411ES, 75411WS Zero-Cross Detection Circuit

No. 6928-27/33

LC75411ES, 75411WS (3) Zero-cross switching control method The zero-cross switching control method consists of setting the zero-cross control bits to the zero-cross detection mode (D36, D37 = 0), and specifying the detection blocks (D38, D39) before transmitting the data. These control bits are latched immediately following data transfer, that is to say beforehand in sync with the falling edge of CE, so when updating data of volumes, etc., it is possible to perform mode setting and zero-cross switching with one data transfer. An example of control when updating the data of the volume block is shown below.
D36 0 D37 0 D38 1 Volume block setting D39 0

Zero-cross detection mode setting

(4) Zero-cross timer setting If the input signal becomes lower than the zero-cross comparator detection sensitivity, or if only low-frequency signals are input, zero-cross detection continues to be impossible, and data is not latched during this time. The zero-cross timer can set a time for forcible latch during such a status when zero-cross detection is not possible. For example, to set 25 ms, using T = 0.69CR and C = 0.033 µF, we obtain
R=

25 × 10 –3 0.69 × 0.033 × 10 –6

1.1 MΩ

Normally, a value between 10 ms and 50 ms is set.

(5) Cautions related to serial data transfer 1. To ensure that the high-frequency digital signals transferred to the CL, DI, and CE pins do not spill over to the analog signal block, either guard these signal lines with a ground pattern, or perform transmission using shielded wires. 2. The data format of the LC75411ES and 75411WS uses 8-bit addresses and 44-bit data. When sending data using multiples of 8 (when sending 48 bits), use the method described in Figure 1. Method for Receiving Data Using Multiple of 8 of LC75411ES and 75411WS

X

X

X

X

D0

D1

D2

D3

D36

D37

D38

D39

D40

D41

D42

D43

Dummy data

Input switching control

Test mode control X : don’t care

Figure 1

No. 6928-28/33

LC75411ES, 75411WS

Gain Step Characteristics
LC75411ES VDD=9V VIN=–30dBV Input L1 Output LFOUT f=1kHz

Gain Step Characteristics
LC75411WS VDD=9V VIN=–30dBV Input L1 Output LFOUT f=1kHz

Output level — dB

Step setting — dB

Output level — dB

Step setting — dB

Main volume block

Main volume block

Graphic equalizer block

Graphic equalizer block

Input gain block

Input gain block

Fader block

Main Volume Control Step Characteristics
LC75411ES VDD=9V VIN=0 f=1kHz Input L1 Output LFOUT

Main Volume Control Step Characteristics
LC75411WS VDD=9V VIN=0 f=1kHz Input L1 Output LFOUT

Attenuation — dB

Step setting — dB Main volume block

Attenuation — dB

Step setting — dB Main volume block

Graphic equalizer block

Graphic equalizer block

Input gain block

Input gain block

Fader block

Fader block No. 6928-29/33

Fader block

LC75411ES, 75411WS

Fader Volume Control Step Characteristics
LC75411ES VDD=9V VIN=0dBV Input L1 Output LFOUT f=1kHz

Fader Volume Control Step Characteristics
LC75411WS VDD=9V VIN=0dBV Input L1 Output LFOUT f=1kHz

Fader Volume Attenuation — dB

Step setting — dB

Fader Volume Attenuation — dB

Step setting — dB

Main volume block

Main volume block

Graphic equalizer block

Graphic equalizer block

Input gain block

Input gain block

Fader block

THD — Frequency Characteristics
LC75411ES VDD=9V Input L1 Output LFOUT 80kHz LPF

THD — Frequency Characteristics
LC75411WS VDD=9V Input L1 Output LFOUT 80kHz LPF

Total harmonic distortion — %

Frequency, f — dB

Total harmonic distortion — %

Frequency, f — dB

Main volume block

Main volume block

Graphic equalizer block

Graphic equalizer block

Input gain block

Input gain block

Fader block

THD METER

Fader block

Fader block THD METER No. 6928-30/33

Total harmonic distortion, THD — %

Total harmonic distortion, THD — %

Input gain gain block block Input Input gain gain block block Input

LC75411ES VDD=9V 80kHz LPF Input L1, Output LFOUT With MV=0dB

Main volume volume block block Main Main volume volume block block Main

Supply voltage — V

Graphicequalizer equalizerblock block Graphic Graphicequalizer equalizerblock block Graphic

THD — Input Level Characteristics

Input level, VIN — dBV

THD — Supply Voltage Characteristics

Fader block block Fader Fader block block Fader LC75411ES 80kHz LPF Input L1 Output LFOUT

Input gain gain block block Input

LC75411WS VDD=9V 80kHz LPF Input L1, Output LFOUT With MV=0dB

Main volume volume block block Main

Supply voltage — V

Graphicequalizer equalizerblock block Graphic

THD — Input Level Characteristics

Input level, VIN — dBV

THD — Supply Voltage Characteristics

Fader block block Fader

THD METER THD METER Input gain gain block block Input Main volume volume block block Main Graphicequalizer equalizerblock block Graphic Fader block block Fader THD METER LC75411WS 80kHz LPF Input L1 Output LFOUT

LC75411ES, 75411WS

Total harmonic distortion, THD — %

Total harmonic distortion, THD — %

THD METER

No. 6928-31/33

LC75411ES, 75411WS
Bass Control Characteristics
LC75411ES VDD=9V VIN=–20dBV Input L1 Output LFOUT Level — dB Level — dB

Bass Control Characteristics
LC75411WS VDD=9V VIN=–20dBV Input L1 Output LFOUT

Frequency, f — Hz

Frequency, f — Hz

Treble Control Characteristics
LC75411ES VDD=9V VIN=–20dBV Input L1 Output LFOUT Level — dB Level — dB

Treble Control Characteristics
LC75411WS VDD=9V VIN=–20dBV Input L1 Output LFOUT

Frequency, f — Hz

Frequency, f — Hz

Output Level Control Characteristics
VDD=9V, VIN=0 MV=0 to –54dB

Output Level Control Characteristics
VDD=9V, VIN=0 MV=0 to –54dB

Level — dB

Frequency, f — Hz

Level — dB

Frequency, f — Hz

Loudness Control Characteristics
VDD=9V, VIN=0, Input=L1, Output=LFOUT Loudness On, MV=0 to –54dB

Loudness Control Characteristics
VDD=9V, VIN=0, Input=L1, Output=LFOUT Loudness On, MV=0 to –54dB

Level — dB

Frequency, f — Hz

Level — dB

Frequency, f — Hz No. 6928-32/33

LC75411ES, 75411WS

Specifications of any and all SANYO products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer’s products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer’s products or equipment. SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all semiconductor products fail with some probability. It is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO products (including technical data, services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be exported without obtaining the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of SANYO Electric Co., Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the “Delivery Specification” for the SANYO product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties.
This catalog provides information as of June, 2001. Specifications and information herein are subject to change without notice. PS No. 6928-33/33

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