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The 8085 Microprocessor Architecture :
The 8085 Microprocessor Architecture www.yesnaraynan.blogspot.com

The 8085 and Its Busses :
The 8085 and Its Busses The 8085 is an 8-bit general purpose microprocessor that can address 6 ! Byte o" memory. It has 0 pins and uses #5$ "or power. It can run at a ma%imum "re&uency o" ' M(). The pins on the chip can be grouped into 6 groups* Address Bus. +ata Bus. ,ontrol and -tatus -ignals. .ower supply and "re&uency. /%ternally Initiated -ignals. -erial I01 ports. www.yesnarayanan.blogspot.com

The Address and Data Busses :
The Address and +ata Busses The address bus has 8 signal lines A8 2 A35 which are unidirectional. The other 8 address bits are multiple%ed 4time shared5 with the 8 data bits. -o6 the bits A+0 2 A+7 are bi-directional and ser8e as A0 2 A7 and +0 2 +7 at the same time. +uring the e%ecution o" the instruction6 these lines carry the address bits during the early part6 then during the late parts o" the e%ecution6 they carry the 8 data bits. In order to separate the address "rom the data6 we can use a latch to sa8e the 8alue be"ore the "unction o" the bits changes. www.yesnarayanan.blogspot.com

The Control and Status Signals :
The ,ontrol and -tatus -ignals There are main control and status signals. These are* A9/* Address 9atch /nable. This signal is a pulse that become 3 when the A+0 2 A+7 lines ha8e an address on them. It becomes 0 a"ter that. This signal can be used to enable a latch to sa8e the address bits "rom the A+ lines. :+* :ead. Acti8e low. ;:* ;rite. Acti8e low. I10M* This signal speci"ies whether the operation is a memory operation 4I10M<05 or an I01 operation 4I10M<35. -3 and -0 * -tatus signals to speci"y the =ind o" operation being per"ormed .>sually un-used in small systems. www.yesnarayanan.blogspot.com

Frequenc Control Signals :
?re&uency ,ontrol -ignals There are ' important pins in the "re&uency control group. @0 and @3 are the inputs "rom the crystal or cloc= generating circuit. The "re&uency is internally di8ided by A. -o6 to run the microprocessor at ' M()6 a cloc= running at 6 M() should be connected to the @0 and @3 pins. ,9! 41>T5* An output cloc= pin to dri8e the cloc= o" the rest o" the system.

yesnarayanan. This turns o"" the output Tri-state bu""ers in the memory. 9ets loo= at timing and the data "low o" an instruction "etch operation. www. +uring TA 6 memory places the data "rom the memory location on the lines A+72 A+0 .yesnarayanan. At e%actly the same time6 the I10M signal goes low to indicate a memory operation. The A9/ signal goes high to indicate that A+0 2 A+8 are carrying an address.com Steps For Fetching an Instruction : -teps ?or ?etching an Instruction 9ets assume that we are trying to "etch the instruction at memory location A005. (owe8er6 the low order bits remain "or only one cloc= period and they would be lost i" they are not sa8ed .com Ti!ing Signals For Fetching an Instruction : Timing -ignals ?or ?etching an Instruction Cow6 lets loo= at the e%act timing o" this se&uence o" e8ents as that is e%tremely important.blogspot. The "ollowing is the se&uence o" operations* The program counter places the address 8alue on the address bus and the controller issues a :+ signal. That ma=es the A+72 A+0 lines go to high impedence mode. The high order bits o" the address remain on the bus "or three cloc= periods. The 8alue on the data bus is read into the instruction decoder inside the microprocessor. The signal remains low 4acti8e5 "or two cloc= periods to allow "or slow de8ices.yesnarayanan.blogspot.com Microprocessor Co!!unication and Bus Ti!ing : Microprocessor . +uring T' the :+ signal is +isabled 4goes high5. www.'5 At T3 6 the high order 8 address bits 4A0(5 are placed on the address lines A8 2 A35 and the low order bits are placed on A+72A+0. The 8alue in the memory location is placed on the data bus.com De!ultiple"ing AD#$AD0 : +emultiple%ing A+7-A+0 ?rom the abo8e description6 it becomes ob8ious that the A+72 A+0 lines are ser8ing a dual purpose and that they need to be demultiple%ed to get all the in"ormation.35 www. That means that the program counter is now set to that 8alue. A"ter decoding the instruction6 the control unit issues the proper control signals to per"orm the operation. www.. 4/%ample '.blogspot. The memoryBs address decoder gets the 8alue and determines which memory location is being accessed. At the beginning o" the TA cycle6 the low order 8 address bits are remo8ed "rom A+72 A+0 and the controller sends the :ead 4:+5 signal to the memory.yesnarayanan.ommunication and Bus Timing To understand how the microprocessor operates and uses these di""erent signals6 we should study the process o" communication between the microprocessor and memory during a memory read or write operation. 4"igure '.e will discuss the rest o" the control signals as we get to them.blogspot.

A35-A8 9atch A+7-A+0 +7.e%ternally. Cow6 lets loo= at some o" its "eatures with more detail.ontrol -ignals The 8085 generates a single :+ signal. -o6 it must be combined with the I10M signal to generate di""erent control signals "or the memory and I01. Machine .yesnarayanan. In the 80856 an instruction cycle may consist o" 3 to 6 machine cycles. This cycle may consist o" ' to 6 T-states.-tate* 1ne subdi8ision o" an operation.yesnarayanan. Also6 the A9> includes a temporary register used .+0 A7A0 8085 A9/ www. !eeping in mind the operation o" the I10M signal we can use the "ollowing circuitry to generate the right set o" signals* www.ycle* The time re&uired to complete the e%ecution o" an instruction.yesnarayanan.re8iously we discussed the 8085 "rom a programmerBs perspecti8e.com C cles and States : .ycles and -tates ?rom the abo8e discussion6 we can de"ine terms that will become handy later on* T.blogspot.com %enerating Control Signals : Denerating . . Then when A9/ goes low6 the address is sa8ed and the A+72 A+0 lines can be used "or their purpose as the bi-directional data lines. To ma=e sure we ha8e the entire address "or the "ull three cloc= cycles6 we will use an e%ternal latch to sa8e the 8alue o" A+72 A+0 when it is carrying the address bits. www. 4cloc= cycles5. www.blogspot.com The A'( : The A9> In addition to the arithmetic E logic circuits6 the A9> includes the accumulator6 which is part o" e8ery arithmetic E logic operation. Instruction . A T-state lasts "or one cloc= period. (owe8er6 the signal needs to be used with both memory and I01.yesnarayanan.blogspot.com De!ultiple"ing AD#$AD0 : +emultiple%ing A+7-A+0 Di8en that A9/ operates as a pulse during T36 we will be able to latch the address.blogspot.yesnarayanan. Also6 notice that the low order bits o" the address disappear when they are needed most. www.ycle* The time re&uired to complete one operation o" accessing memory6 I016 or ac=nowledging an e%ternal re&uest.blogspot. An instructionBs e%ecution length is usually measured in a number o" T-states.e use the A9/ signal to enable this latch.com A closer loo& at the 8085 Architecture : A closer loo= at the 8085 Architecture .

5 describes B.arity "lag A"ter an A9> operation i" the result has an e8en G o" 3Bs the p-"lag is set. . 4+.yesnarayanan. 1therwise it is cleared.blogspot.com More on the 8085 !achine c cles : More on the 8085 machine cycles The 8085 e%ecutes se8eral types o" instructions with each re&uiring a di""erent number o" operations o" di""erent types. 4-ection 30.blogspot. The 8085 uses the "irst ' T-states to "etch the opcode.+ operations.rite. This "lag is used only internally "or B.yesnarayanan.com )pcode Fetch Machine C cle : 1pcode ?etch Machine .com The Flags register : The ?lags register There is also the "lags register whose bits are a""ected by the arithmetic E logic operations.yesnarayanan. This "lag is a""ected by operations on the accumulator as well as other registers.+ addition including the +AA instruction5. 1therwise is reset.blogspot.-Au%iliary . The three main types are* Memory :ead and . . --sign "lag The sign "lag is set i" bit +7 o" the accumulator is set a"ter an arithmetic or logic operation. (owe8er6 the operations can be grouped into a small set.arry This "lag is set when a carry is generated "rom bit +' and passed to + .yesnarayanan. F-)ero "lag -et i" the result o" the A9> operation is 0.H-carry "lag +iscussed earlier www. www.-.rite. To di""erentiate this machine cycle "rom the 8ery similar Imemory readJ cycle6 the control E status signals are set as "ollows* I10M<06 s0 and s3 are both 3.blogspot.com The Me!or *ead Machine C cle : . It is also possible "or an instruction to ha8e 6 T-states in an opcode "etch machine cycle.: B5. -o6 the "lag can be used to indicate e8en parity. This temporary register is not accessible by the programmer. I01 :ead and . www. T is used to decode and e%ecute it. www. A.com Me!or *ead Machine C cle : Memory :ead Machine . In this cycle6 the microprocessor brings in the instructionBs 1pcode "rom memory."or holding data temporarily during the e%ecution o" the operation. www.ycle The memory read machine cycle is e%actly the same as the opcode "etch e%cept* It only has ' T-states The s0 signal is set to 0 instead. These can be "urther di8ided into 8arious operations 4machine cycles5.blogspot.ycle The "irst step o" e%ecuting any instruction is the 1pcode "etch cycle. This machine cycle has "our T-states. :e&uest Ac=nowledge.yesnarayanan.

To illustrate lets loo= at the machine cycles needed to e%ecute the "ollowing instruction.yesnarayanan.:. (owe8er6 the :1M does not ha8e a . The "irst machine cycle is the opcode "etch discussed earlier.laces the contents o" the accumulator on the data bus and asserts the signal . . The second machine cycle is the Memory :ead . A000( A003( '/ 'A www.blogspot.rite 1peration In a memory write operation* The 8085 places the address 4A065(5 on the address bus Identi"ies the operation as a memory write 4I10M<06 s3<06 s0<35.ycle To understand the memory read machine cycle6 letBs study the e%ecution o" the "ollowing instruction* M$I A6 'A In memory6 this instruction loo=s li=e* The "irst byte '/( represents the opcode "or loading a byte into the accumulator 4M$I A56 the second byte is the data to be loaded. The machine code will be stored in memory as shown to the right This instruction re&uires the "ollowing machine cycles* 1pcode "etch to "etch the opcode 4'A(5 "rom location A030(6 decode it and determine that A more bytes are needed 4 T-states5. +uring the last T-state6 the contents o" the data bus are sa8ed into the memory location. www. There"ore6 it will need at least two machine cycles. The microprocessor has its re&uirements as well. www. ?igure '.blogspot.com Me!or structure 1 its require!ents : Memory structure E its re&uirements The process o" inter"acing the abo8e two chips is the same.yesnarayanan. Memory read to read the low order byte o" the address 465(5 4' T-states5. The 8085 needs to read these two bytes "rom memory be"ore it can e%ecute the instruction.blogspot. -u!. Memory has its re&uirements on control signals and their timing.er o/ .yesnarayanan.com . Cumber o" bytes in the instruction Machine cycles and instruction length6 do not ha8e a direct relationship. Memory read to read the high order byte o" the address 4A0(5 4' T-states5.com Me!or inter/acing : Memory inter"acing There needs to be a lot o" interaction between the microprocessor and the memory "or the e%change o" in"ormation during program e%ecution.blogspot.com Machine C cles +s. tes in the instruction : Machine .yesnarayanan. :1M www.ycle. -TA A065( This is a '-byte instruction re&uiring machine cycles and 3' T-states.com The Me!or 0rite )peration : The Memory . A030( A033( A03A( 'A( 65( A0( www. A memory write to write the contents o" the accumulator into the memory location.: signal.The Memory :ead Machine .30 page 8'.blogspot. The inter"acing operation is simply the matching o" these re&uirements.yesnarayanan.ycles 8s.

com .utting all o" the concepts together6 we get* www.com The )+erall Picture : The 18erall .blogspot.art o" the address bus will select the chip and the other part will go through the address decoder to select the register. This can be done either using logic gates or a decoder. Translating this to microprocessor domain* The microprocessor places a 36-bit address on the address bus. www. .yesnarayanan. /nable the appropriate bu""er. The signals I10M and :+ combined indicate that a memory read operation is in progress.icture . www.blogspot. A large part o" the address bus is usually connected directly to the address inputs o" the memory chip. .com Address decoding : Address decoding The result o" address decoding is the identi"ication o" a register "or a gi8en address.Inter/acing Me!or : Inter"acing Memory Accessing memory can be summari)ed into the "ollowing three steps* -elect the chip.hat concerns us is the other part that must be decoded e%ternally to select the chip. The M/M: signal can be used to enable the :+ line on the memory chip.yesnarayanan. This portion is decoded internally within the chip. Identi"y the memory register.yesnarayanan.blogspot.