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EL4583, EL4584, EL4585 Demo Board

Technical Brief February 24, 2004 TB430

Video Sync Separator, Horiz Genlock switches should be labeled 1, 2, 3, 4. Dip-SW4 controls pin
B, SW3 controls C, SW2 controls A, and SW1 controls DIV
EL4583 and EL4584 SEL pin 7 on the EL4584. Refer to the data sheet for a table
The EL4583, EL4584, EL4585 demo of divisors for each switch setting and the operation of DIV
board is designed to demonstrate the SEL. If using a NTSC signal, setting all switches ON will
operations of Intersil’s family of sync separators and produce a CLK OUT frequency of 14.318MHz, and an EXT
horizontal genlocks. The board as assembled is designed to DIV frequency of 15.734kHz, and the EL4584 will lock.
accept NTSC standard video through A4, Video In. The
To convert the oscillator to work with the standard PAL
EL4583 separates H-sync and sends it through jumper R10
frequency of 17.734MHz, simply substitute an inductor of
to the EL4584. H-sync can be monitored at A1, H-sync. On
about 8.2µH to bring the center frequency up closer to PAL
the board settings, the internal divider mode is selected and
frequency of 17.734MHz, and reset the dip switches to
the divider N is set to 910. The EL4584 uses its internal
A = 0, B = 1, C = 1. Remember that LC VCOs have a wide
divider to extract a clock pulse of the same H-sync input
pull range so they are very tolerant of component variations.
frequency from the oscillator and adjusts the on-board LC
In some cases the 10µH inductor may be able to produce
VCO to phase lock this signal to the input horizontal
the necessary PAL frequency as well as the NTSC
frequency. This divided clock signal can be monitored at A2,
frequency.
EXT DIV. The full clock frequency (which should equal to
H-sync (15.734kHz)*divider (910) = 14.318MHz) is available Crystal VCXOs and 4-pin VCXO hybrids can also be used.
at A3, CLK OUT. Each board has been tested with a NTSC See the accompanying schematics and data sheet for more
signal and C17 adjusted so EXT DIV locks to the H-sync. info.
SW1 has 3 positions. LEFT grounds COAST and puts the
EL4584 into normal mode (see data sheet for mode EL4585
descriptions). CENTER floats COAST and is fast lock mode, An EL4585 can be used in place of the EL4584 provided.
and RIGHT pulls COAST to VDD and is coast mode. The With R1 changed to 3.3µH and the same settings as in the
signal should lock in normal mode. The DIP switches at the EL4584 section, The signal frequency at CLK OUT is
top of the board works as follows: from right to left, the 28.636MHz.

1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2004. All Rights Reserved. Elantec is a registered trademark of Elantec Semiconductor, Inc.
All other trademarks mentioned are the property of their respective owners.
Technical Brief 430

EL4583, EL4584, EL4585 Schematic


VDD

4
3
2
1
SW2
PROGRAM

5
6
7
8
R8
10K
U2 EL4584CS/EL4585CS
R5 1 16 R9
B PROG A
10K 10K A3
CLK-OUT
R7 2 15
C HSYNC
10K
C17
3 14
OSC OUT DIG GND
A2
5pF-30pF L1/R2 OPEN C10
VDD
EXT-DIV
Y1 4 13
10uH ANALOG VDC EXT DET
VDD
Note: Values for L1 0.1uF
For EL4584, L1=10uH, Fosc = 14.318MHz. 5 12
OSC IN LOCK DET TP7
For EL4585, L1=3.3uH, Fosc = 28.636MHz

14
VDD

8
C12
Y2 6 11

VcomVCC

GNDOUT
ANALOG GND DG VDD A1
C6 VCXO
0.1uF H-SYNC
220pF OPEN
7 10
CHARGE PUMP HSYNC IN
VDD R10

7
8 9 SW1 1 0
DV SEL COAST
R4 2
3
SMV1212-001 100K
C5
0.01uF
V1 C1
R1 0.001uF
30K

R12 13K 1 16
FLT CUT OFF
ANALOG GND
R13 82K
2 15
0.1uF LEV DET HSYNC
C7
VDD
C14
3 U1 14
TP1 CSYNC VDD
A4 EL4583CS
CSYNC 0.1uF
VIDEO IN C8
R3 TP3
4 13
FLTER IN ODD/EVEN
0 ODD/EVEN
R6 0.1uF
75 C2 5 12
OPENTP2 VSYNC RSET
VSYNC R15
6 11 680K C9
GND BP CLAMP TP6 0.1uF Error : intersil.bmp file not found.
VDD BP CLAMP
Title
VDD
7
FILTER OUT NO SIGNAL
10
TP5 EL1881/4581/3/4/5 DEMO BOARD
C11 NO SIGNAL
GND Size: Revision:
0.1uF 8
VIDEO IN LEVEL OUT
9
TP4 A B
LEVEL OUT
Date: 12/17/03 Sheet 1 of 1
File: EL4583 4 Sch Drawn By:

2
Technical Brief 430

The VCO and loop filter section of the EL4583/4/5 demo board can be implemented in the
following configurations:
(1) VCXO

VSUPPLY

Charge Pump CONTROL


Output
C5 R4 1 14
C1
GND TO OSC IN
R1 7 8
PIN 5

IN OUT
(2) XTAL PIN 5 PIN 3

R2

Y1

C6
PIN 7 R4
Charge Pump
Output C17

C5 C1 V1
R1

(3) LC Tank IN OUT


PIN 5 PIN 3

L1

10µH
C6
220pF

PIN 7 R4
Charge Pump
Output C17
C5 100K 5.5 - 30pF
0.01µF
C1 V1
R1 0.001µF SMV1212-001
30K

Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to
verify that the Application Note or Technical Brief is current before proceeding.

For information regarding Intersil Corporation and its products, see www.intersil.com

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