Medical Engineering & Physics 24 (2002) 695701 www.elsevier.

com/locate/medengphy

Technical note

Universal application-specic integrated circuit for bioelectric data acquisition

Bernhard Fuchs, Sven Vogel, Dietmar Schroeder
TU Hamburg-Harburg, Department of Microelectronics, Eissendorfer Str. 38, 21071 Hamburg, Germany Received 19 February 2002; received in revised form 29 May 2002; accepted 4 July 2002

Abstract Use of highly integrated application specic circuits (ASICs) in bioelectric data acquisition systems promise important new insights into the origin of a large variety of health problems by providing light-weight, low-power, low-cost medical measurement devices that allow long-term studies. They also promise signicant cost reduction in medical care, as patients in principle become mobile and do not have to be hospitalized for observation. We report on the development and successful implementation of a universal ASIC, designed to meet key characteristics of a broad variety of bioelectric signals in terms of their dynamic range, sampling rate and input referred noise; e.g. electrocardiogram (ECG), electroencephalogram (EEG) and, most constringently, evoked potentials (EPs). Our approach for the rst time makes cost-effective use of state-of-the-art microelectronics in medical measurement equipment, thus offering to replace discrete, single application devices used at present. 2002 IPEM. Published by Elsevier Science Ltd. All rights reserved.
Keywords: Bioelectric signals; Electrocardiogram; Electroencephalogram; Data acquisition; Low noise; Integrated circuits

1. Introduction Detailed measurements of bioelectric signals, such as electrocardiogram (ECG), electroencephalogram (EEG) and evoked potentials (EPs), represent a cornerstone of modern patient care and preventive medicine. Easy-touse, mobile medical measurement systems additionally offer new insights into the origin of a large number of health problems. In contrast, the physical size and cost of devices currently used make them intrusive and in many cases entirely impractical to the majority of patients, who are in principle mobile and do not need to be hospitalized for observation. The development of an ASIC that may be universally employed in a large variety of differing medical applications may provide a solution to this situation. Although state-of-the-art microelectronics implemented in modern telecommunication apparatus show the potential for light-weight, lowpower, low-cost medical measurement equipment, large

Corresponding author. Tel.: +49-40-42878-2885; fax: +49-4042878-2877. E-mail address: d-schroeder@tu-harburg.de (D. Schroeder).

multi-national electronics suppliers have shown little inclination for developing ASICs for the medical sector because of marketable quantities that are too small for mass production. As a consequence, cost and expenditure of medical measurement equipment are high, and the performance of mobile applications is extremely limited. Because of the expected benets, a bioelectric data acquisition ASIC for biomedical instruments has been developed. The potential advantages of such a universal ASIC are improvements of the quality of the data obtained and an increased turnaround time in the development of new instruments. This development will also provide greater opportunities for homecare, allowing part-time monitoring, remote patient supervision, and thus a reduction in pressures on hospital bed space. Highly integrated electronic devices could contribute to self-monitoring by patients and especially improve the quality of high-risk patients in critical situations. Portability of the head-top-box of EEG instruments would enable EEG studies of disturbed children over a prolonged period. The increased integration level reduces manufacturing costs and has benets in terms of improved performance, smaller size/weight and lower power consumption of medical instruments.

1350-4533/02/$22.00 2002 IPEM. Published by Elsevier Science Ltd. All rights reserved. PII: S 1 3 5 0 - 4 5 3 3 ( 0 2 ) 0 0 1 1 7 - 0

696

B. Fuchs et al. / Medical Engineering & Physics 24 (2002) 695701

Present day equipment in the detection of bioelectric signals is designed for only one application at a time. The basic architecture is composed of (i) signal amplication by low noise op-amps or J-FET transistors, (ii) analogue lters composed of capacitors and op-amps, and (iii) an A/D converter (typically 16 bit) switching between multiple channels. Past attempts, known to make use of highly integrated electronics, include a four-channel ASIC presented in 1990 by Analog Devices for the detection of ECG and EEG [1], which suffers from a non-adaptable input amplication stage, xed sampling rate, insufcient number of sampling channels and, most importantly, high power consumption. The latter point is particularly important for the development of wireless transmission of data in mobile equipment, which is currently available for ECG systems only and which is in general strongly hampered by the large power consumption of these devices. A nine-channel ASIC for the detection of ECG was rmann Medizintechnik in Zwo presented in 1993 by Ho nitz [2]. The maximum sampling frequency was 2.5 kHz per channel. The sampled voltages were multiplexed consecutively to the input of a single 13-bit successive approximation A/D-converter. A supply voltage of 10 V was required. Another chip design for the readout of bioelectric signals was reported in [3]. This chip is able to capture signals in the frequency range of 0.5200 Hz and contains a two-stage amplier and a sampling low-pass lter, while analog/digital conversion is not included. Application of SigmaDelta modulation for the A/Dconversion of cardiac signals was described in [4]. In this paper, the design and simulation of a preamplier followed by a -A/D-converter in switched op-amp technique including the decimation lter were reported. Emphasis was put on very low-voltage and low-power operation, because the design was aimed at the utilization in a pacemaker. Only 8-bit resolution has been accomplished. In the present paper we report for the rst time on the design and properties of a dedicated ASIC developed to satisfy the requirements outlined above through a very high degree of integration. The development took place in co-operation with Schwarzer GmbH, a company for medical diagnostic equipment, under the support of the European Union within the First Users Action (FUSE) project. The ASIC is dedicated to substitute the signalprocessing circuitry that is similar in different medical instruments for bioelectric signals. Hence, the ASIC reduces production and development costs and shortens development cycles. The device is able to acquire and process a variety of bioelectric signals. In order to be useful as a versatile component, key features include adaptable elementary signal processing in terms of digitization, amplication and ltering of the signals

recorded by skin electrodes. As output, the ASIC delivers digital signals conventionally transmitted to a personal computer or strip chart recorder. The outline of this paper is as follows. In Section 2 fundamental characteristics of bioelectric signals are described. These provide the key design criteria in terms of the dynamic range, sampling rate and ltering that a universal ASIC has to satisfy. The basic architecture of the ASIC is presented in Section 3. Important details of the design are described in Section 4 for the interested reader. Section 5 focuses on applications of the ASIC, demonstrating its versatility. The paper concludes in Section 6 with an outlook on developments currently under way and a brief summary.

2. Characteristics of bioelectric signals Bioelectric signals are generated by nerve cells and muscle cells. They can be classied by their sources, the biomedical application, or their signal characteristics. The latter is done in Table 1 [5]. It shows a list of the signals and their basic signal characteristics. Three major groups of these are of predominant interest for our ASIC design approach. These are the ECG, the EEG and the EPs. In the following sections they are described in more detail. 2.1. Electrocardiography The ECG is one of the most common bioelectric signals. A full ECG (12 lead) needs nine signal channels. The required resolution is about 45 V, with an input range of 1020 mV, the sampled data should have 12bit resolution. The main information of the signal lies in a frequency range from 0.05 to 150 Hz. A convenient sampling rate to satisfy this frequency range is 500 Hz. A common technique with ECG is to feed back a signal by a skin electrode that is the average potential of three other skin electrodes. This technique reduces the common mode voltage by using a negative feedback loop and is described in [6]. Later on, this dedicated part of the analog circuits is called the reference channel.
Table 1 Bioelectric signal properties Signal Electrocardiogram Electroencephalogram Evoked potentials Electroneurogram Electroretinogram Electrooculogram Electrocorticogram Electromyogram Frequency 0.05150 Hz 0.5100 Hz 2 Hz5 kHz 100 Hz1 kHz 0.2200 Hz dc100 Hz 100 Hz5 kHz 0.01 Hz10 kHz Range 5 V8 mV 2200 V 10 nV20 V 5 V10 mV 0.5 V1 mV 10 V5 mV 5 V10 mV 50 V10 mV

B. Fuchs et al. / Medical Engineering & Physics 24 (2002) 695701

697

2.2. Electroencephalography The EEG is another well known signal, used for diagnosis of brain disturbances. The frequency range lies below 70 Hz. The resolution is about 1 V with an input range of 510 mV, so a 16-bit resolution is required. EEGs need at least eight channels but in medical practice 32128 channels are standard. Similarly to the ECG, a reference channel is used to feed back the average potential of two skin electrodes. 2.3. Evoked potentials The EPs are classied by means of excitation [5], which can be e.g. auditory (AEP), visual (VEP), somatosensory (SEP), by laser (LEP), magnetical (MEP), or event correlated (ERP). Amplitudes and frequency ranges impose the strongest requirements on the electronics. In existing equipment, a usual value of input referred noise voltage is less than 2 Vpp in a bandwidth of several kHz. Often signals of a few nanovolts are of interest, so digital post-processing is used to reduce noise. One digital sample must provide at least 16 bits, and sampling rates of approximately 100 kHz and more (with an oversampling factor of 20) are required. These signals are taken with a reduced number of channels compared with the EEG. Typically two to four channels are used [5].

of medical devices, clinic staff and chip designers. The following characteristics of the ASIC had to be dened in close relation to the target applications: number of channels; input referred noise per channel; resolution per channel; dynamic range per channel; additional electronics; supply voltage; digital interfaces; power consumption; size of the chip related to nal costs per chip.

3. Basic architecture The purpose of the mixed-signal ASIC is amplication and digitalisation of almost all known multi-channel bioelectric body signals, thus constituting a universal sensor interface. It was aimed to satisfy the combined requirements of the formerly described bioelectric signals with a convenient number of channels. The ASIC provides nine low-noise preampliers, variable postampliers and lters and 10 -A/D-converters with a dynamic range up to 110 dB. Its dedicated parallel interface facilitates digital post-processing with standard digital signal processors (DSPs) or eld-programmable gate arrays (FPGAs). Low noise and high dynamic range are the predominant features of the ASIC. The basic properties have been specied in an interactive process of more than two years between suppliers

The architecture of one channel is depicted in Fig. 1. An input stage (preamplier) is followed by an external high pass lter as usual in bioelectric data acquisition, which can be omitted when DC coupling is required. The next stage (postamplier) is used for variable amplication of the AC signal. A low pass lter follows as anti-aliasing lter for the analog-to-digital converter. For dynamic ranges of 16 bit and more and moderate sampling rates, -converters are the right choice. -converters consist of an analog modulator and a digital decimation lter [7]. The nal architecture for the chip is shown in Fig. 2. It provides nine identical signal channels with variable amplication and a 10th channel with xed amplication. An analog reference channel, congurable to generate the sum of two or three analog signals, completes the analog part of the chip. To satisfy the extremely high data rates for the evoked potentials, the data interface is designed in a similar way as for data memories. An eight-bit data bus and 5-bit address bus are provided. The most signicant characteristics of the ASIC are shown in Table 2. The chip area is 60 mm2; it resides in a PQFP SMD package with 100 pins. A chip photograph is shown in Fig. 3.

4. Technical details and distinct properties Concerning overall circuit design the ASIC shows a conservative approach. Nevertheless, every part of the ASIC provides unique properties which will be described in the following chapter.

Fig. 1.

Block diagram of one channel.

698

B. Fuchs et al. / Medical Engineering & Physics 24 (2002) 695701

Fig. 2. Table 2 ASIC technical summary Description Input referred noise Input referred noise ADC dynamic range ADC dynamic range DC input range AC input ranges Maximum frequency range Number of signal channels Power consumption Power supply Value

Block diagram of the ASIC.

Notes 070 Hz bandwidth 100 Hz3 kHz bandwidth 010 Hz bandwidth 0150 Hz bandwidth

1 Vpp 3 Vpp 110 dB 85 dB 300 mV 1, 5, 20, 166 mVpp 15 kHz 9 320 mW 5 V (2.5 V)

xed anti-aliasing lter 500 Hz sampling rate

4.1. Preampliers The preamplier of any stage must provide a very high input impedance for the skin electrodes. It is designed as a noninverting amplier with an amplication factor of 6. Signals in the range of 300 mV can be processed. The relative tolerance of the amplication factor between two channels has been specied to be smaller than 0.1%. The reason for this is the common practice to feed the inverting inputs of the preampliers with the output of the reference channel (average of three electrode signals). The consequence is that the reference signal is subtracted from the electrode signal of this channel. This subtraction must be very precise, otherwise the reference signal disturbs the electrode signal. For integrated ampliers such low tolerances are near to the technological limit. Special design measures were

Fig. 3.

Photograph of the ASIC.

B. Fuchs et al. / Medical Engineering & Physics 24 (2002) 695701

699

taken to reach this limit: large areas of the resistors, common centroid structure, and shielding. Thanks to the small tolerance of the amplication, a residue signal of 60 dB below the electrode signal could be achieved. Special care has been taken with respect to the noise of the preampliers. The preampliers consist of a differential stage at the input, followed by a class AB stage. For the suppression of low-frequency noise (e.g. 1/fnoise), the differential stage is operating in chopper modulation [8]. Since low noise requires small resistors in the amplier circuit, which in turn implies large currents that must be delivered by the amplier, the nal stage consists of a class-AB stage [9]. As a result, we obtained 3 Vpp equivalent input noise at a bandwidth of 3 kHz (EP) and less than 1 Vpp at a bandwidth of 70 Hz (EEG) for the whole signal channel. 4.2. Postampliers A classic low-noise amplier approach (large transistor areas, high transconductance [9]) has been used for the postampliers. The amplication of these ampliers is online congurable. The AC signal range of the input can be changed online between 1, 5, 20 and 166 mV. The corresponding amplication factors are 2000, 400, 100, and 12. The tolerance of these amplication factors is 1%. 4.3. Anti-aliasing-lter and -A/D-converters For sampling rates of 500 Hz and below, the corner frequency of the anti-aliasing lter must be below 250 Hz. An integrated lter with such a low corner frequency requires a large chip area. Thanks to the -A/D-converters used in the ASIC this problem is avoided. converters oversample the signal, so the corner frequency of the lter can be much higher (15 kHz). Another consequence is that the order of the lter can be lower (second order). The -converters work with an oversampling rate of 256, so the signal is sampled with 128 kHz at the lowest data rate of 500 Hz. The modulators are of second order. Twenty bits are available at the output of the -converters. The dynamic range in a bandwidth of 10 Hz is 110 dB, hence the effective number of bits is 18. In a bandwidth of 150 Hz (ECG), the number of bits is 13.8. 4.4. Digital interface The philosophy of the ASIC is that it is used together with a DSP or FPGA that provides a data bus and an address bus. Eight bits in parallel can be read from the ASIC arbitrarily from any channel, which are addressed by a 5-bit address bus. To congure the ASIC for different applications, data are written into 32 internal registers through the same interface.

4.5. Multi-channel synchronization The ASIC provides an input for synchronization of multiple ASICs. EEG processing requires the use of up to 15 ASICs and more in parallel. One ASIC is congured as master and the other as slaves. Thus, a large number of channels can be sampled synchronously. 4.6. Power consumption and power supply The power consumption of the ASIC is dominated by the analog part, and within the analog part by the preampliers. The reason is the requirement for extremely low noise preampliers, which must be paid for by increased power consumption. The overall power consumption and the power consumption of the different parts of the ASIC are listed in Table 3, where the respective signal sampling rate is denoted. Also indicated in Table 3 is the possibility of individual powerdown of each part. For the sake of universality, the ASIC is oversized for applications with relaxed technical requirements such as ECG and consumes more power than necessary for these applications. Hence, with moderate battery capacities only 12 h of non-stop operation are possible, which is too short for a number of telemetric applications. This limitation will be overcome in future designs of the ASIC. 4.7. Congurability Internal conguration is done by 32 8-bit registers. Five registers are dedicated to online conguration. Each of these 40 bits can be set during operation. Depending on the master clock, 12 different sampling rates can be selected. With a 10.24 MHz master clock the resulting sampling rates are 500 Hz, 1, 2, 4, 5, 8, 10, 16, 20, 40, 80 and 160 kHz. The four input ranges (1, 5, 20, 166 mV) are adjusted by the amplication of the postampliers. It is standard to use external high pass lters between the preampliers and postampliers with very low corner frequencies. The capacitors of these lters
Table 3 ASIC power consumption (2.5 V supply) Part description ASIC total Digital total Digital total Analog total One signal channel Tenth channel Preamplier Reference channel AD-converter Power consumption 320 mW (500 Hz) 5 mW (500 Hz) 170 mW (40 kHz) 315 mW 28 mW (500 Hz) 15 mW (500 Hz) 23 mW 53 mW 5 mW (500 Hz) Power down modus no no no no yes yes yes yes yes

700

B. Fuchs et al. / Medical Engineering & Physics 24 (2002) 695701

can be discharged in the case of external disturbance by setting the corresponding bits in the conguration registers. Another bit selects the averaging of either two or three electrodes in the reference channel. For multichannel applications, the ASIC can be congured as master or slave for synchronization. As mentioned in Table 3 it is possible to put every part individually into power down mode.

5. Performance and applications The ASIC is dedicated to three major types of medical devices, i.e. ECG, EEG and EPs. Since 1998, medical instruments for cardiology have been equipped with the ASIC. Fig. 4 shows a to-scale comparison of the former ECG equipment and a board using the new ASIC. A new instrument that utilizes this board is shown in Fig. 5. This low-cost instrument has a size of only 9163 cm3. Together with a laptop computer for control and display it replaces the former instrument shown in Fig. 4. It can be easily carried together with the laptop computer to arbitrary usage sites or installed as homecare equipment. Because the new instrument has a much smaller number of components, substantial reductions of manufacturing costs have been achieved. The design of the printed circuit board (PCB) could be simplied considerably, which leads to a shorter manufacturing time and improved production throughput. The reduced number of solder joints substantially improved the system reliability. In the sector of neurology, the production of 32-channel EEG instruments started in 2001. The evoked potentials impose the highest requirements to electronics, so development of devices dedicated to these using the ASIC is still under way. Input referred noise has to be lower than 2 Vpp, while the ASIC shows 3 Vpp in the interesting frequency range of 3 kHz. However, the

Fig. 5.

New ECG instrument.

noise generated in each channel of the ASIC is only slightly correlated, and averaging of two channels of the ASIC reduces the noise by a factor of 2. So development and implementation of EP instruments with the ASIC is possible and just a question of digital post-processing. Averaging of the nine channels of the ASIC reduces the noise by a factor of 3, resulting in an input referred noise of 1 Vpp. Even compared with discrete solutions, this is an impressive result.

6. Summary and future developments A mixed-signal ASIC for the acquisition of bioelectrical signals has been developed that offers the following benets: reduced product and test costs, reduction of size and weight, portability of instruments, and higher system reliability. The ASIC has improved the features of existing products and not only offers a route to lower cost and size, but also enables an increase in complexity and sophistication of the products, e.g. more EEG channels for better diagnosis. Availability of the ASIC for third parties can be negotiated. Although the ASIC already has outstanding properties, it is just a rst step towards more sophisticated electronics for medical devices. In the middle of year 2001, another European project in this area started. During this project the Technical University of Hamburg-Harburg will improve the existing ASIC in cooperation with four European suppliers of medical instruments. The project will end in 2003, and its purpose is further reduction of power consumption and noise of the ASIC. This improved ASIC in particular will enable the construction of extremely small-size mobile medical equipment.

Fig. 4.

Photograph of ECG boards.

B. Fuchs et al. / Medical Engineering & Physics 24 (2002) 695701

701

Acknowledgements The authors like to thank Manfred Joppich and Dr Manfred Jaschke for many inspiring discussions, and the development department of Schwarzer GmbH for implementation and support of the test circuits. Funding by the European Union within the FUSE project is gratefully acknowledged.
[4]

[5] [6]

References
[1] McGlinchey G, et al. A programmable medical data acquisition system chip. In: Proceedings of IEEE 1988 Custom Integrated Circuits Conference (CICC), Rochester, NY, 1988. p. 9.4/16. [2] Desel T, Reichel T, Rudischhauser S, Hauer H. A CMOS nine channel ECG measurement IC. In: Proceedings of Second International Conference on ASIC, Shanghai, 1996. p. 1158. [3] Chung W-Y, Lin K-P, Yen C-J, Tsai C-L, Chen T-S. Analog pro-

[7] [8]

[9]

cessor chip for the bio-signal readout circuit application. In: Proceedings of First Joint BMES/EMBS Conference, Atlanta, GA, 1999. p. 881. Gerosa A, Novo A, Neviani A. Low-power sensing and digitization of cardiac signals based on SigmaDelta conversion. In: Proceedings of 2000 International Symposium on Low Power Electronics and Design (ISLPED), Rapallo, Italy, 2000. p. 2168. Bronzino JD. The biomedical engineering handbook. IEEE Press, 1995. Spinelli EG, Martinez NH, Mayosky MA. A transconductance driven-right-leg circuit. IEEE Trans Biomed Eng 1999;46(12):146670. Norsworthy SR, Schreier R, Temes GC, editors. DeltaSigma data converters. IEEE Press; 1997. Enz ChC, Temes GC. Circuit techniques for reducing the effects of Op-Amp imperfections: autozeroing, correlated double sampling, and chopper stabilization. Proc. IEEE 1996;84(11). Holman WT, Conelly JA, Perez JO, Motchenbacher CD. A low noise CMOS operational amplier in a 1.2 m digital technology. In: Newcomb RW, editor. Proceedings of 35th Midwest Symposium on Circuits and Systems, Washington, DC, 1992. p. 11203.