IEEJ TRANSACTIONS ON ELECTRICAL AND ELECTRONIC ENGINEERING IEEJ Trans 2012; 7: 7480 Published online in Wiley Online Library

(wileyonlinelibrary.com). DOI:10.1002/tee.21698

Paper Common-Mode Gain Reduction Technique and its Applications

Nawatt Silawan , Non-member Nicodimus Retdian , Member Shigetaka Takagia , Member
This paper proposes a common-mode gain reduction technique and a new approach for a balanced-type system design. Two design examples of a balanced-type operational transconductance amplier and a balanced-type lter are given. The proposed scheme employs the proposed common-mode gain reduction technique together with the common-mode feedback (CMFB) network, which is used only to set a bias, to meet requirements of common-mode rejection. Compared with the conventional method, which uses the CMFB that has a higher gain than the one used in the proposed scheme, the proposed method shows reduction in design complexities and relaxation of the stability conditions. 2011 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.
Keywords: balanced-type system, operational transconductance amplier (OTA), lter, common-mode feedback (CMFB)

Received 16 March 2010; Revised 18 October 2010

1. Introduction
Conventionally, a balanced-type system uses a common-mode feedback (CMFB) circuit to lower an undesirable common-mode gain. However, the technique leads to many problems including complexities in design and stability issues. To relax design complexities, the common-mode gain reduction technique proposed by our group [1][3] is applied for system implementation to achieve low common-mode gain over a desired frequency range, while the DC bias setting is attained by the CMFB, which has a low gain. This CMFB gain does not need to be high since it is not aimed for common-mode gain rejection but only for DC bias setting. To show the effectiveness of the proposed technique, rst the technique is applied for a balanced-type operational transconductance amplier (OTA) implementation, and then the designed OTA is employed in a balanced-type OTA-C lter realization. Section 2 states the problems of the balanced-type system design using a CMFB. To relax those problems, the common-mode gain reduction technique is derived in Section 3. Section 4 shows design examples of a balanced-type OTA and a balanced-type OTA-C lter. Finally, Sections 5 and 6 summarize simulation results and conclusions.

the transfer function of the CMFB be HCMFB (s ). These transfer functions are approximated by rst-order transfer functions as ACM 1 HCM (s ) = 1+ s s Z

(1)

CM ACMFB HCMFB (s ) = 1+ s
CMFB

(2)

The zero in HCM (s ) is caused by a parasitic capacitor connected between the feedback path input of the main system and the output, and is usually the cause of instability since it contributes a negative phase shift [4]. For stability, the loop gain of this feedback must be considered, and it is written as ACM ACMFB 1 HCM (s )HCMFB (s ) = 1+ s CM s Z s 1+ CMFB

(3)

2. Complexities in Design Using CMFB

Consider the balanced-type system operating with commonmode inputs shown in Fig. 1. To reduce undesirable commonmode output signals, a CMFB is employed. Let the transfer function of the main system in the CMFB path be HCM (s ) and
a

The open-loop gain determines the common-mode gain reduction of the system. To achieve a low common-mode gain output, the loop gain should be high. Also, an open-loop phase margin needs to be high enough to conrm stability [5] despite some mismatch effects are included. As a result, both the gain and bandwidth of the CMFB must be properly chosen. To relax the design complexities, the proposed common-mode gain reduction technique described in Section 3 is used to decrease the common-mode gain instead of the high-gain CMFB while the DC bias setting is achieved by the CMFB that has low gain as shown in Fig. 2. Note that the word low-gain CMFB will be used for this kind of CMFB throughout this paper.

Correspondence to: Shigetaka Takagi. E-mail: takagi@ec.ss.titech.ac.jp

3. Common-Mode Gain Reduction Technique

In this analysis, we are interested only in the common-mode gain due to a common-mode signal. Consider a differential pair and its common-mode half circuit as shown in Fig. 3.

* Department of Communications and Integrated Systems, Tokyo Institute of Technology, 2-12-1 Ookayama, Meguro-ku, Tokyo 152-8550, Japan ** Global Edge Institute, Tokyo Institute of Technology, 2-12-1 Ookayama, Meguro-ku, Tokyo 152-8550, Japan

2011 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.

COMMON-MODE GAIN REDUCTION TECHNIQUE AND ITS APPLICATIONS

Fig. 4. Small-signal model of the MOSFET operating in the saturation region Fig. 1. Balanced-type system with a CMFB

Fig. 2. Balanced-type system using the common-mode gain reduction technique with the low-gain CMFB

Fig. 5. Differential pair (a) small signal equivalent circuit (b) Thevenins equivalent circuit representation

Fig. 3. Differential pair and its common-mode half circuit Before going to the next step, a small-signal model of a metaloxidesemiconductor eld-effect transistor (MOSFET) should be considered. Based on the voltagecurrent relationship of a MOSFET in the saturation region, i.e. iDS = K (vGS VTH )2 (1 + vDS ) (4) Fig. 6. Common-mode signal cancellation circuit in Fig. 5(b) is equivalent to the circuit in Fig. 5(a), and it implies that the common-mode output is caused by the coupling of the input signal to the output by the voltage-controlled voltage source. Assume that an additional voltage source can be inserted in series to the former but in the opposite direction as shown in Fig. 6 where the voltage source is enclosed by the dashed line. The insertion will result in no coupling path from the input signal to the output when the circuit operates in the common mode. To realize this idea, consider Fig. 7. The representation in Fig. 7(a) can be transformed into Fig. 7(b) where gds and gmC are equal to gdy + gdc and gds gmX /gdX , respectively.
75 IEEJ Trans 7: 7480 (2012)

where K = n Cox W /2L and is the channel length modulation coefcient, the small-signal representation of the MOSFET can be modeled by a voltage-controlled current source with a conductance between drain and source terminals as shown in Fig. 4. The body effect is neglected in this derivation. Practically, the triple-well process can be used, or the use of PMOS transistors instead of NMOS transistors can eliminate the body effect problem. The small-signal parameters in Fig. 4 can be derived using (4) and their values are gm = 2IDS VGS VTH (5) (6)

gd IDS

Use of this model changes the common-mode half circuit in Fig. 3 into the small-signal represention shown in Fig. 5(a). The

N. SILAWAN, N. RETDIAN, AND S. TAKAGI

Fig. 9. Differential pair using the common-mode gain reduction technique Fig. 7. Common-mode gain reduction technique derivation

Fig. 10. OTA using the DC bias offset technique technique [6,7] shown in Fig. 10 is chosen as the basic cell for modication. Note that M1 M4 have the same channel width and channel length. To consider the operation principle of this OTA, it is assumed that vDS << 1 in (4). As a result, iDS becomes iDS = K (vGS VTH )2 Fig. 8. Realization of the common-mode gain reduction technique It is apparent from the small-signal model in Fig. 4 that the circuit in Fig. 7(b) can be implemented using MOSFETs as shown in Fig. 8 where subscripts X, C, and Y refer to those of the main transistor, the compensating transistor, and the tail current-source transistor. From the derivation, the condition for common-mode signal cancellation is gmC = gmX (gdC + gdY ) gdX (7) (9)

From (9), the relationship between a differential output current and a differential input voltage of the circuit in Fig. 10 can be written as iO + iO = Gm (vIN+ vIN ) (10)

Substitution of (5) and (6) into (7) gives IDSX X C Y = IDSC Y (8)

where IDS stands for a drain-to-source bias current. Also, the design parameter for the tail current source is changed from gdS to gdY . The overall circuit of the differential pair with the commonmode gain reduction technique circuitry is presented in Fig. 9 without loading for generalization. Equation (8) shows that the technique is more or less dependent on the parameter mismatches. However, the reduction of commonmode gain is still achieved at some level even if parameter mismatches occur.

4. Applications 4.1. Balanced-type OTA An example of a balancedtype OTA design is presented. The OTA using the DC bias offset
76

where Gm = 2KVB and VB is the offset voltage inserted between gate terminals of two transistors. Transconductance of the OTA can be tuned by varying the value of VB . To implement the common-mode gain reduction technique into this basic OTA, consider (8). The right-hand side of this equation is dependent on the characteristics of the transistors only while the opposite side is the current ratio, which can be changed by the tuning voltage VB . Therefore, to design the compensation part, which can maintain the current ratio despite the changes of VB , two compensation transistors are used. Figure 11 shows the common-mode half circuit of the OTA with its common-mode gain reduction technique circuitry. MC1 and MC4 are designed to have the same channel width and channel length. Equation (8) now can be modied by substituting IDSX = IDS1 + IDS4 and IDSC = IDSC1 + IDSC4 . However, the design in Fig. 11 is not compact, and the additional circuit for common-mode gain reduction results in higher power consumption. To compromise this problem, assume that the tuning voltage VB and its tuning range are small compared to the biased gate-to-source voltage. By this assumption, the effect of the tuning voltage on the current ratio is low, and can be neglected. Thus, only one transistor can be used to compensate for the common-mode signals of M1 and M4 . The improved balancedtype OTA circuit is shown in Fig. 12.
IEEJ Trans 7: 7480 (2012)

COMMON-MODE GAIN REDUCTION TECHNIQUE AND ITS APPLICATIONS

Fig. 11. Common-mode half circuit of the OTA with the commonmode gain reduction technique circuitry

Fig. 15. Transconductance cell using the basic OTA

Fig. 16. Transconductance cell using the balanced-type OTA with the common-mode gain reduction technique circuitry Fig. 12. Balanced-type OTA using the common-mode gain reduction technique Figs 10 and 12 to a xed-biased PMOS transistor with another PMOS transistor that is used for the CMFB, the resulting circuits are shown in Figs 15 and 16, respectively. By using all transconductance cells with the same value Gm , the lter transfer function is given by Hdiff (s ) = (Gm /CL )2 s 2 + s (Gm /CL ) + (Gm /CL )2 (11)

4.2. Balanced-type OTA-C lter Figure 13 shows a typical balanced-type second-order low-pass lter structure. The dashed line in Fig. 13 indicates the CMFB network. Gm s in Fig. 13 represent transconductance cells, and their differential inputoutput conversion is shown in Fig. 14. Each transconductance cell can be realized using the OTAs in Section 4.1. By connecting each output port of OTAs in

The transfer function shows the characteristic of the second-order low-pass lter which has unity quality factor and a bandwidth of Gm /CL . To implement the balance-type OTA-C lter, conventionally the OTA in Fig. 15 is used for all transconductance cells in Fig. 13 with the the CMFB circuits that have high DC gains. However, as mentioned in the Section 2, the CMFB circuit may cause design problems including design complexities and stability issues. To reduce complexities in design, the balanced-type OTAs using the common-mode gain reduction technique are used for the input and output stage transconductance cells of the lter instead of the basic OTAs. The resulting circuit is shown in Fig. 17. Since the common-mode gain is reduced by the common-mode gain reduction technique circuitry, the CMFBs with high gain are not required. The only requirement of the CMFB circuit is setting the DC bias. Thus, the low-gain CMFBs are used. Consequently, the design complexities and the stability conditions due to the CMFB can be relaxed.

5. Simulation Results
Fig. 13. Filter structure A 0.18-m CMOS BSIM3 model was used in the simulations, and the triple-well process was assumed. The supply voltage was set to 2.5 V.

Fig. 14. Transconductance cell

77

5.1. Balanced-type OTA The conventional OTA in Fig. 10 and the proposed OTA in Fig. 12 were designed using the parameters as shown in the Tables I and II, respectively. These two OTAs were designed to have the same total current owing in the main transistors M1 to M4 , which is 109.5 A. The
IEEJ Trans 7: 7480 (2012)

N. SILAWAN, N. RETDIAN, AND S. TAKAGI

OTA common-mode gain

0 Conventional Proposed 20 dB

Amplitude (dB) : f(Hz) Conventional Proposed

10.0

30.0

40 24.77dB
50.0

60 1 10 100 1k 10k 100k 1M 10M 100M 1G

f(Hz)

Fig. 17. Balanced-type lter using the proposed scheme Table I. Design parameters of the OTA in Fig. 10 Transistor M1,2,3,4 (Fig. 10) MS L (m) 0.18 1.25 W (m) 1 10.23

Fig. 19. Common-mode gain compared between the OTA using the common-mode gain reduction technique and the conventional OTA both OTAs were set to 0.08 V. The common-mode gains are plotted in Fig. 19 along with comparisons between the conventional OTA and the proposed OTA. The results show an improvement in common-mode gain reduction of about 24.77 dB from low frequencies to around 1 MHz, and this difference gradually decreases to zero at around 100 MHz.

Table II. Design parameters of the OTA in Fig. 12 Transistor M1,2,3,4 (Fig. 12) MC MY L (m) 0.18 1 1.25 W (m) 1 1 12

total current drawn by two compensation transistors in Fig. 12 is equal to 19.0 A or around 17.4% of the total current in the main transistors.

5.1.3. Effects of Mismatches To show the effects of mismatches, a Monte Carlo analysis was carried out for the proposed OTA in Fig. 12 with 20 k resistors attached to its outputs. In this analysis, channel lengths and channel widths of all transistors in Fig. 12 were set to be varied independently and each variable had a uniform distribution. The Monte Carlo analysis was run with 100 iterations. The results show that the common-mode gain reduction is changed from 24.77 to 12.87 dB and 4.02 dB for 1 and 5% variation, respectively, for the worst case. 5.2. Balanced-type OTA-C lter The conventional approach and the proposed scheme were used for lter implementation as suggested in Section 4.2 to make comparisons between their performances. 5.2.1. Differential mode response Second-order low-pass lters with a 100-MHz cut-off frequency and a unity quality factor were designed by setting all transconductance and CL s in Figs 13 and 17 to 117.4 S and 187 fF, respectively. From simulation results shown in Fig. 20, all lters have more or less the same characteristic in the differential mode. Extracted from the simulation data, the conventional lter has 101.4 MHz bandwith with a quality factor of 0.66, while the proposed lter has 99.2 MHz bandwith with a quality factor of 0.67. The degradation of the quality factor and the shift of the cutoff frequency are due to the nite output resistance of OTAs and parasitic capacitance at the OTAs output. 5.2.2. Common-mode response The circuit in Figs 21 and 22 are used for the CMFBs in the conventional lter and the low-gain CMFBs in the proposed lter, respectively. At DC bias, the circuit in Fig. 22 acts like a voltage shifter that shifts the output voltage at the node FB from the voltage at inputs by a constant value. When it is used in a feedback topology with transconductance cells in Figs 15 or 16, it gives a voltage shift between a transconductance cell output and a CMFB node. Hence, the DC bias level at the output of the transconductance cell can be justied, and a reference voltage is not required. For the common-mode signal, the circuit in Fig. 22 will make the feedback
78 IEEJ Trans 7: 7480 (2012)

5.1.1. Linearity The linearity is evaluated in terms of the linearity error dened as
Gm (vIN+ vIN ) (iO + iO ) 100% Error = Gm (vIN+ vIN ) (12)

where Gm is the transconductance of the OTAs. By connecting the output terminals of each OTA to the appropriate voltage sources for probing the output current when OTAs operate in a differential mode, the results show that both types of OTA have approximately the same differential characteristics, that is, linearity errors of both OTAs are less than 1% over 80 mV input range and their Gm s are equal to 1.467 VB [mS] while VB can be tuned from 0.05 to 0.08 V. Note that the small value of the tuning voltage VB can be achieved by the circuit shown in Fig. 18.

5.1.2. Common-mode gain To observe the commonmode gain of OTAs, 20-k resistors were used as loads connected to the output terminals of OTAs in Figs 10 and 12 while VB s in

Fig. 18. Circuit used to synthesize small offset voltage

COMMON-MODE GAIN REDUCTION TECHNIQUE AND ITS APPLICATIONS

0
20.0

Filter characteristic

(dBV) : f(Hz) Conventional Proposed

30
40.0

Filter common-mode gain

Conventional Proposed

(dBV) : f(Hz) Conventional Proposed

dB

40.0

50.0

60.0

60
70.0
(deg) : (Hfz) Conventional Proposed

80 0

dB
80.0

90

deg

100.0

100.0 110.0

180 200.0 1meg

120

f(Hz) 1 10 100 1k 10k 100k 1M 10M 100M 1G

10M

100M

1G

f(Hz)

Fig. 20. Differential mode response of the conventional and proposed lters

Fig. 23. Common-mode gains compared between the lters using proposed and conventional methods their unity gain frequencies are 8.41 and 3.13 MHz, respectively. Phase margins of both CMFB loops are about 45 . The proposed lter consumes 490 A of total current. The open-loop gains of internal and output nodes CMFB loops are 16.91 and 15.00 dB, while their unity gain frequencies are 66.17 and 28.77 MHz, respectively. Furthermore, phase margins of internal and output nodes CMFB loops are 53.58 and 82.33 , respectively. Note that the bandwidth of CMFBs in the conventional lter have to be limited by inserting CB as shown in Fig. 21 owing to the conditions of phase margin, desired DC common-mode gain, and limitation in current consumption. The simulation results in Fig. 23 show the comparison between the common-mode gain of the conventional and proposed lters. With the same power consumption, the proposed technique shows advantages over the conventional approach by providing a wider frequency band of common-mode gain regulation. In addition, the proposed scheme is easier to be designed since the stability condition for CMFB design is relaxed.

Fig. 21. CMFB topology

6. Conclusions
A common-mode gain reduction technique has been proposed. The derivation of the proposed technique has been presented in detail and two applications have been given. The balanced-type OTA using the common-mode gain reduction technique shows the advantage over the conventional circuit with an improvement in the common-mode gain reduction about 24.77 dB from low frequencies to around 1 MHz, and the gap gradually decreases to zero at about 100 MHz. Monte Carlo simulation shows the effects of variations in channel lengths and channel widths of the transistors on the common-mode rejection. A variation of 1% in the parameter reduced the improvement in common-mode gain from 24.77 to 12.87 dB for the worst case. For balance-type OTA-C lter design, the proposed scheme can help in reducing design complexities and stability problems since a low-gain CMFB and additional compensating transistors are used instead of a high-gain CMFB, which may easily cause instability. Also the proposed scheme shows the advantage over the conventional approach as suggested in the design example in Section 5.2; that is, for the same power consumption and DC common-mode gain, the proposed scheme shows a wider frequency range of common-mode gain regulation. Compared to a conventional cascade structure used for commonmode gain reduction, the proposed technique can serve the same purpose without effects on an output swing.
79 IEEJ Trans 7: 7480 (2012)

Fig. 22. Low-gain CMFB topology transistors of the transconductance cells act like diode-connected PMOS transistors, which lower the circuits common-mode gain. In the opposite way, these PMOS transistors operate as current sources in a differential mode. Thus, the circuits differential gain is still high. To make fair comparisons between the conventional and proposed methods, two lters were designed with the same power consumption and DC common-mode gain. To guarantee the stability of the lters, phase margin of each controlled loop in the lters is required to be at least 45 or more. The designed conventional lter consumes 489 A of total current. Stability is justied by the open-loop gains of CMFB loops, which determine the common-mode levels of internal and output nodes of the lter. Each CMFB loop consists of a CMFB amplier and a PMOS feedback transistor. The open-loop gains of internal and output nodes CMFB loops are 32.84 and 33.50 dB, while

N. SILAWAN, N. RETDIAN, AND S. TAKAGI

However, there are some issues to be discussed. First, linearity of the OTA used in this paper is limited to the small-input range since the OTA struture has been derived using the Square Law while the short-channel device does not perfectly follow this characteristic. However, this issue does not strongly affect the performances derived by our proposed technique. Alternatively, other techniques for highly linear OTA implementation based on a differential pair can be used. Second, realization of the offset voltage VB using the circuit in Fig. 18 may have some problems from the variation of threshold voltages of both PMOS and NMOS transistors since the requied offset voltage is very low. However, this can be solved by an alternative structure of OTA without offset voltage insertion. For the future work, the effects due to mismatches on the proposed technique should be improved, and the use of the proposed technique in other circuit blocks should be considered.

Nawatt Silawan (Non-member) was born in Bangkok, Thailand, in 1983. He received the B.E. degree (rst class honours) from Chulalongkorn University, Thailand, in 2006. In the same year, he joined as a coresearcher in the biosensor project for peritoneal dialysis machine at the Institute of Biomedical Engineering, Imperial College, London. Since 2009, he has been pursuing the Masters degree at the Tokyo Institute of Technology, Japan. His main research interests include analog integrated circuits and low power biomedical electronics. Nicodimus Retdian (Member) was born in Malang, Indonesia, on March 3, 1976. He received the B.E., M.E., and Doctor of Engineering degrees from the Tokyo Institute of Technology, in 2000, 2002 and 2005, respectively. From 2005, he worked as an Assistant Professor in the Department of Communications and Integrated Systems, the Graduate School of Science and Engineering, Tokyo Institute of Technology, and since 2009 is with The Global Edge Institute of the same university. His main research interests include analog integrated circuits. Dr Nicodimus is a member of the Institute of Electrical and Electronics Engineers. Shigetaka Takagi (Member) was born in Tokyo. He received the B.E., M.E., and Doctor of Engineering degrees from the Tokyo Institute of Technology, in 1981, 1983, and 1986, respectively. Then he became a Research Associate at the Tokyo Institute of Technology, where he is now a Professor in the Department of Communications and Integrated Systems. In 1998, he was a Visiting Associate Professor at Osaka University, Japan. His main research interests include analog integrated circuits. He is the author of Analog MOS Electronic Circuits, Linear Circuit Theory, and Analog Electronic Circuits, as well as a co-author of Introduction to Digital Integrated Circuits (in Japanese). Prof. Takagi is a member of the Institute of Electronics, Information and Communication Engineers and the Institute of Electrical and Electronics Engineers. He received the Best Paper Awards in 1996 and 2001 from the Institute of Electronics, Information, and Communication Engineers, Japan.

Acknowledgments
This work was supported by the VLSI Design and Education Center(VDEC), University of Tokyo, in collaboration with Synopsys, Inc.

References
(1) Uehara K, Retdian N, Takagi S. Common-mode noise rejection techniques in mixed-signal SoC. IEEJ The Papers of Technical Meeting on Electronic Circuits 2009; 51:7984. (2) Silawan N, Retdian N, Takagi S. Balanced-type OTA using commonmode gain reduction technique. IEEJ The Papers of Technical Meeting on Electronic Circuits 2009; 65:1318. (3) Silawan N, Retdian N, Takagi S. Balanced-type lter using commonmode gain reduction technique. Proceedings of the 2009 (12th) IEEJ International Analog VLSI Workshop 2009;107112. (4) Razavi B. Design of Analog CMOS Integrated Circuits. McGrawHill: Singapore; 2001. (5) Nise NS. Control Systems Engineering. 4th ed. John Wiley & Sons (Asia) Pte. Ltd: 2004. (6) Bult K, Wallinga H. A class of analog CMOS circuits based on the square-law characteristic of an MOS transistor in saturation. IEEE Journal of Solid-State Circuits 1987; 3:357365. (7) Wang Z, Guggenbuhl W. A voltage-controllable linear MOS transconductor using bias offset technique. IEEE Journal of SolidState Circuits 1990; 25(1):315317.

80

IEEJ Trans 7: 7480 (2012)