Digital design

Digital design using hardware description language(HDL)

Digital world
Digital world in 2050

Design methodologies
 Ad-hoc  Structured - Top-Down - Bottom-Up - Mixed

Why structured design?
 Over a million-transistor designs cannot be done easily - Today’s designs require better tools - Today’s designs require better planning - Today’s designs require better strategy

From concept to silicon Concept Algorithmic design Architecture design Logic (gate) design Circuit (transistor) design Physical (layout) design Verification must be done at each phase. Tape-out .

Cheaper  Lower time and cost than prototyping  CAD support from concept to silicon .Why using HDL?  Very difficult to design directly on hardware  Exploring different design options .Easier .

Key features of HDLs  HDLs have high-level programming language constructs  HDLs allow designers to describe their designs at different levels of abstraction  HDLs allow designers to describe functionality as well as timing  HDLs are concurrent languages in nature .

VHDL Government Developed Ada based Strongly Type Cast Difficult to learn More Powerful vs. Verilog Commercially Developed C based Mildly Type Cast Easy to Learn Less Powerful .

Two competing implementation approaches ASIC Application Specific Integrated Circuit  Designed all the way from behavioral description to physical layout  Designs must be sent for expensive and time consuming fabrication in semiconductor foundry FPGA Field Programmable Gate Array  No physical layout design. design ends with a bitstream used to configure a device  Bought off the shelf and reconfigured by designers themselves .

ASICs vs. FPGAs Off-the-shelf High performance Low power Low cost (but only in high volumes) Low development costs Short time to the market Reconfigurability .

Synthesis Physical Layout (Place & Route) Back End Configuration On chip testing Configuration Fabrication ASIC FPGA . Synthesis Front End Post-synthesis sim. RTL Description Functional Verification Gate Level Simulation Implementation Timing sim.ASIC and FPGA flow Specs System Level Design Specification VHDL description Functional sim.

Logic synthesis RTL code (Verilog/ VHDL) Gate-level netlist (Verilog/ VHDL) Area report Timing report Power consumption report Logic synthesis Constraints .

END PROCESS . Q : OUT STD_LOGIC ).all . Synthesis ARCHITECTURE Behavior_1 OF flipflop IS BEGIN PROCESS ( Clock ) BEGIN IF Clock'EVENT AND Clock = '1' THEN Q <= D . ENTITY flipflop IS PORT ( D. Clock : IN STD_LOGIC . END flipflop .) LIBRARY ieee . END Behavior_1 . D Clock Q . USE ieee.std_logic_1164. END IF .Logic synthesis(Cont.

Review of digital system structure .

Structure of a typical digital system Data Inputs Control Inputs Execution Unit (Data path) Control Signals Control Unit (Control) Data Outputs Control Outputs .

. memories.) Execution unit (Data path)  Manipulates and processes data  Interprets control signals from the Controller and generates status signals for the Controller  Provides all necessary resources and interconnects among them to perform specified task  Examples of resources – Adders. registers. multipliers. etc.Structure of a typical digital system(Cont.

) Control Unit (Controller)  Controls data movements in an operational circuit by switching multiplexers and enabling or disabling resources  Follows some ‘program’ or schedule  Often implemented as finite state machine or collection of finite state machines .Structure of a typical digital system(Cont.

) Control Unit (Cont. implements the same functionality – Another term is a “hardwired state machine” or “hardwired instructions” .Structure of a typical digital system(Cont.)  Controller can be programmable or nonprogrammable  Programmable – Has a program counter which points to next instruction – Instructions are held in a RAM or ROM externally – Microprocessor is an example of programmable controller  Non-Programmable – Once designed.

Finite state machines refresher  Any circuit with memory Is a finite state machine – Even computers can be viewed as huge FSMs  Design of FSMs involves – Defining states – Defining transitions between states – Optimization / minimization  Above approach is practical for small FSMs only .

) Moore FSM  Output is a function of a present state only Inputs Next State function Next State clock reset Present state register Present State Output function Outputs .Finite state machines refresher(Cont.

) Mealy FSM  Output is a function of a present state and inputs Inputs Next State function Next State clock reset Present State Register Present State Output function Outputs .Finite state machines refresher(Cont.

) Moore vs. Mealy FSM  Moore and Mealy FSMs can be functionally equivalent – Equivalent Mealy FSM can be derived from Moore FSM and vice versa transition condition 1 state 1 / output 1 transition condition 2 state 2 / output 2  Mealy FSM has richer description and usually requires smaller number of states – Smaller circuit area transition condition 1 / output 1 state 1 transition condition 2 / output 2 state 2 .Finite state machines refresher(Cont.

Finite state machines refresher(Cont.) Moore vs.)  Mealy FSM computes outputs as soon as inputs change – Mealy FSM responds one clock cycle sooner than equivalent Moore FSM  Moore FSM has no combinational path between inputs and outputs – Moore FSM is more likely to have a shorter critical path . Mealy FSM(Cont.

) Sequence ”10” recognizer example  Moore FSM that recognizes sequence “10” 0 S0 / 0 reset Meaning of states: S0: No elements of the sequence observed 1 1 S1 / 0 0 1 S2 / 1 0 S1: “1” observed S2: “10” observed .Finite state machines refresher(Cont.

)  Mealy FSM that recognizes sequence “10” 0/0 S0 reset Meaning of states: S0: No elements of the sequence observed 0/1 S1: “1” observed 1/0 S1 1/0 .) Sequence “10” recognizer example(Cont.Finite state machines refresher(Cont.

) Sequence “10” recognizer example(Cont.Finite state machines refresher(Cont.) clock 0 input 1 0 0 0 S0 Moore S0 Mealy S1 S1 S2 S0 S0 S0 S0 S0 .

Finite state machines refresher(Cont.) Sequence ” 11 ” recognizer example resetn w = 1 w = 0 A z = 0 w = 0 w = 0 B z = 0 w = 1 C z = 1 resetn w = 1 w = 1 z = 0 A w = 0 z = 0 B w = 0 z = 0 w = 1 z = 1 .

VHDL .

VHDL  VHDL is a language for describing digital hardware used by industry worldwide  VHDL is an acronym for VHSIC (Very High Speed Integrated Circuit) Hardware Description Language .

Genesis of VHDL  Multiple design entry methods and hardware description languages in use  No or limited portability of designs between CAD tools from different vendors  Objective: shortening the time from a design concept to implementation .

Different uses of VHDL VHDL for Specification VHDL for Simulation VHDL for Synthesis .

Features of VHDL  Technology/vendor independent  Portable  Reusable .

Two points of view for a given component  External view of component as seen by others  Multiple internal views describing component function .

One entity can have many different architectures.Design entity Design Entity Entity Declaration Architecture 1 Architecture 2 Design Entity .most basic building block of a design. Architecture 3 .

input and output ports. END nand_gate. No Semicolon Reserved words Port modes (data flow directions) . i. Entity name Port names Port type Semicolon ENTITY nand_gate IS PORT( a : IN STD_LOGIC. b : IN STD_LOGIC.Entity declaration  Entity Declaration describes the interface of the component.e. z : OUT STD_LOGIC ).

…………. port_name : signal_mode signal_type).Simplified syntax of entity declaration ENTITY entity_name IS PORT ( port_name : signal_mode signal_type. port_name : signal_mode signal_type. . END entity_name.

Architecture  Describes an implementation of a design entity. END model.  Architecture example: ARCHITECTURE model OF nand_gate IS BEGIN z <= a NAND b. .

.Simplified syntax of architecture ARCHITECTURE architecture_name OF entity_name IS [ declarations ] BEGIN code END architecture_name.

nand_gate. END model.Entity declaration and architecture LIBRARY ieee.all. USE ieee. z : OUT STD_LOGIC ). ARCHITECTURE model OF nand_gate IS BEGIN z <= a NAND b. b : IN STD_LOGIC. .std_logic_1164.vhd ENTITY nand_gate IS PORT( a : IN STD_LOGIC. END nand_gate.

Naming and labeling  VHDL is not case sensitive Example: Names or labels databus Databus DataBus DATABUS are all equivalent .

etc. +..) General rules of thumb 1. ?. All names should start with an alphabet character (a-z or AZ) Use only alphabet characters (a-z or A-Z) digits (0-9) and underscore (_) Do not use any punctuation or reserved characters within a name (!. 4. . -. Sel__A is invalid) All names and labels in a given entity and architecture must be unique 3. &. .. 2.) Do not use two or more consecutive underscore characters (__) within a name (e. 5.g.Naming and labeling (Cont.

such as spacing or indentation imposed by VHDL compilers. Space and carriage return treated the same way. Example: if (a=b) then or if (a=b) then or if (a = b) then are all equivalent .Free format  VHDL is a “free format” language No formatting conventions.

No method for commenting a block extending over a couple of lines Examples: -.Comment indicator can be placed anywhere in the line .Carriage return terminates a comment .Comments  Comments in VHDL are indicated with a “double dash”.Any text that follows in the same line is treated as a comment . i..main subcircuit Data_in <= Data_bus.reading data from the input FIFO . “--” . -.e.

not just in a header .Comments(Cont. not just restatement of code  Locate close to code described – Put near executable code.)  Explain function of module to other designers  Explanatory.

Port modes Port signal Entity Entity Port signal Port signal Entity Signal can be read inside the entity a z c Driver resides outside the entity Can’t read out within an entity a Driver resides inside the entity c <= z Driver may reside both inside and outside the entity IN mode OUT mode INOUT mode .

) Entity Port signal Entity Port signal z x Port signal Z can be read inside the entity z Signal can be read inside the entity c Driver resides inside the entity c c <= z Driver resides z <= inside the entity x c <= x BUFFER mode OUT mode with signal .Port modes(Cont.

The value of the signal can be used inside the entity.  Out: The value of an output port can only be updated within the entity.Port modes(Cont. It can appear only on the right side of a signal or variable assignment.)  In: Data comes in this port and can only be read within the entity. It cannot be read.  Inout: The value of a bi-directional port can be read and updated within the entity model. It can appear on both sides of a signal assignment. which means that in an assignment statement the signal can appear on the left and right sides of the <= operator .  Buffer: Used for a signal that is an output from an entity. It can only appear on the left side of a signal assignment.

USE ieee. END model. ARCHITECTURE model OF nand_gate IS BEGIN z <= a NAND b. Library declaration Use all definitions from the package std_logic_1164 . END nand_gate.all. ENTITY nand_gate IS PORT( a : IN STD_LOGIC.std_logic_1164. z : OUT STD_LOGIC ). b : IN STD_LOGIC.Library declarations LIBRARY ieee.

.package_name.package_parts.Syntax of library declaration LIBRARY library_name. USE library_name.

Fundamental parts of a library LIBRARY PACKAGE 1 TYPES CONSTANTS FUNCTIONS PROCEDURES COMPONENTS PACKAGE 2 TYPES CONSTANTS FUNCTIONS PROCEDURES COMPONENTS .

). BOOLEAN. basic type conversion functions. Visible by default  work Current designs after compilation . etc. etc.Libraries  Ieee Specifies multi-level logic system. SIGNED. arithmetic operations. UNSIGNED. and STD_LOGIC_VECTOR data types Need to be explicitly declared  Std Specifies pre-defined data types (BIT. basic text i/o functions. including STD_LOGIC. INTEGER. REAL.

ARCHITECTURE model OF nand_gate IS BEGIN z <= a NAND b. ENTITY nand_gate IS PORT( a : IN STD_LOGIC. END model.std_logic_1164. What is STD_LOGIC you ask? . b : IN STD_LOGIC. END nand_gate.all. z : OUT STD_LOGIC ). USE ieee.STD_LOGIC type LIBRARY ieee.

Weak (Weakly driven) 1. Don't Care ‘L’ ‘H’ ‘-’ . Models a pull down. Models a pull up.STD_LOGIC type demystified Value Meaning ‘U’ Not Initialized ‘X’ ‘0’ ‘1’ Forcing (Strong driven) Unknown Forcing (Strong driven) 0 Forcing (Strong driven) 1 ‘Z’ ‘W’ High Impedance Weak (Weakly driven) Unknown Weak (Weakly driven) 0.

STD_LOGIC type demystified(Cont.) Value of all signals at the beginning of simulation Value of all signals that remain un-driven throughout simulation U ‘1’ ‘X’ Contention on the bus X ‘0’ .

) Z 0 .STD_LOGIC type demystified(Cont.

STD_LOGIC type demystified(Cont.) VDD VDD ‘H’ ‘1’ ‘L’ ‘ 0’ .

Use with caution ‘-’ .) Do not care.STD_LOGIC type demystified(Cont. Can be assigned to outputs for the case of invalid inputs(may produce significant improvement in resource utilization after synthesis).

Resolving of STD_LOGIC levels X 0 X 0 X 0 0 0 0 X 1 X X 1 1 1 1 1 X Z X 0 1 Z W L H X W X 0 1 W W W W X L X 0 1 L W L W X H X 0 1 H W W H X X X X X X X X X X 0 1 Z W L H - X X X X X X X X .

b 8 bus .Signals SIGNAL a : STD_LOGIC. a 1 wire SIGNAL b : STD_LOGIC_VECTOR (7 DOWNTO 0).

e <= X”AF67”. b: STD_LOGIC_VECTOR( 3 DOWNTO 0).You can use ‘_’ to increase readability -.Standard logic vectors SIGNAL SIGNAL SIGNAL SIGNAL SIGNAL SIGNAL a: STD_LOGIC . -.Octal base a <= ‘1’. c: STD_LOGIC_VECTOR( 3 DOWNTO 0). f: STD_LOGIC_VECTOR( 8 DOWNTO 0). .Binary base assumed by default -. e: STD_LOGIC_VECTOR(15 DOWNTO 0). d: STD_LOGIC_VECTOR( 7 DOWNTO 0).Hexadecimal base -. d <= ”0110_0111”. f <= O”723”. ………. c <= B”0000”.Binary base explicitly specified -. b <= ”0000”.

d <= ”00001111” -. c <= a & b. -. d.Vectors and concatenation SIGNAL a : STD_LOGIC_VECTOR(3 DOWNTO 0).c <= ”00001111” -. e: STD_LOGIC_VECTOR(7 DOWNTO 0). a <= ”0000”. SIGNAL c. b <= ”1111”. d <= ‘0’ & ”0001111”. e <= ‘0’ & ‘0’ & ‘0’ & ‘0’ & ‘1’ & ‘1’ &‘1’ & ‘1’. SIGNAL b : STD_LOGIC_VECTOR(3 DOWNTO 0).e <= ”00001111” .

Fixed 16-bit rotation example a(15) a(14) a(13) a(12) a(11) a(10) a(9) a(8) a(7) a(6) a(5) a(4) a(3) a(2) a(1) a(0) <<< 3 a(12) a(11) a(10) a(9) a(8) a(7) a(6) a(5) a(4) a(3) a(2) a(1) a(0) a(15) a(14) a(13) a(15) a(14) a(13) a(12) a(11) a(10) a(9) a(8) a(7) a(6) a(5) a(4) a(3) a(2) a(1) a(0) <<< 5 a(10) a(9) a(8) a(7) a(6) a(5) a(4) a(3) a(2) a(1) a(0) a(15) a(14) a(13) a(12) a(11) .

PORT ( a : IN STD_LOGIC_VECTOR (15 DOWNTO 0).std_logic_1164. END dataflow . y : OUT STD_LOGIC_VECTOR (15 DOWNTO 0) ). USE ieee. . END fixed_rotator_left_16 .Fixed 16-bit rotation example(Cont.) LIBRARY ieee .all . ARCHITECTURE dataflow OF fixed_rotator_left_16 IS BEGIN y <= a(15-L downto 0) & a(15 downto 15-L+1). ENTITY fixed_rotator_left_16 IS GENERIC ( L : INTEGER := 1).

VHDL design styles VHDL Design Styles Dataflow Concurrent statements Structural Components and interconnects Behavioral Sequential statements  Registers  State machines  Test benches Subset most suitable for synthesis .

END XOR3. A B C XOR3 RESULT .XOR3 Example Entity ENTITY XOR3 IS PORT( A : IN STD_LOGIC. C : IN STD_LOGIC. RESULT : OUT STD_LOGIC ). B : IN STD_LOGIC.

. BEGIN U1_OUT <= A XOR B.XOR3 Example(Cont. END XOR3_DATAFLOW. RESULT <= U1_OUT XOR C.) Dataflow architecture ARCHITECTURE XOR3_DATAFLOW OF XOR3 IS SIGNAL U1_OUT: STD_LOGIC.

order of these statements doesn’t matter. Concurrent statements are evaluated at the same time.  Data Flow uses series of concurrent statements to realize logic. thus. .Dataflow description  Describes how data moves through the system and the various processing steps.  Data Flow is most useful style when series of Boolean equations can represent a logic.

I2 : IN STD_LOGIC. BEGIN U1: XOR2 PORT MAP (I1 => A. COMPONENT XOR2 IS PORT( I1 : IN STD_LOGIC. END COMPONENT. U2: XOR2 PORT MAP (I1 => U1_OUT. END XOR3_STRUCTURAL.) Structural architecture ARCHITECTURE XOR3_STRUCTURAL OF XOR3 IS SIGNAL U1_OUT : STD_LOGIC.XOR3 Example(Cont. Y => RESULT). . I2 => B. Y => U1_OUT). I2 => C. Y : OUT STD_LOGIC ).

Y => U1_OUT). Y : OUT STD_LOGIC ).Component and instantiation  Named association connectivity (recommended) COMPONENT XOR2 IS PORT( I1 : IN STD_LOGIC. . U1: XOR2 PORT MAP (I1 => A. I2 => B. I2 : IN STD_LOGIC. END COMPONENT.

)  Positional association connectivity (Not recommended) COMPONENT XOR2 IS PORT( I1 : IN STD_LOGIC. . Y : OUT STD_LOGIC ).Component and instantiation (Cont. B. END COMPONENT. I2 : IN STD_LOGIC. U1_OUT). U1: XOR2 PORT MAP (A.

 Components are interconnected in a hierarchical manner.Structural description  Structural design is the simplest to understand.  Structural descriptions may connect simple gates or complex. . This style is the closest to schematic capture and utilizes simple building blocks to compose logic functions.  Structural style is useful when expressing a design that is naturally composed of sub-blocks. abstract components.

XOR3 Example(Cont. ELSE RESULT <= '0'.C) BEGIN IF ((A xor B xor C) = '1') THEN RESULT <= '1'.) Behavioral architecture ARCHITECTURE XOR3_BEHAVIORAL OF XOR3 IS BEGIN XOR3_BEHAVE: PROCESS (A. END PROCESS XOR3_BEHAVE.B. END IF. . END XOR3_BEHAVIORAL.

.  This style uses Process statements in VHDL.Behavioral description  It accurately models what happens on the inputs and outputs of the black box (no matter what is inside and how it works).

 The same Test bench can be easily adapted to test different implementations (i. it is not restricted to a single simulation tool (portability). . different architectures) of the same design.  Since test bench is written in VHDL.Test bench  Test bench applies stimuli (drives the inputs) to the Design Under Test (DUT) and (optionally) verifies expected outputs.  The results can be viewed in a waveform window or written to a file.e.

) Test bench block diagram Test bench Environment TB Processes Generating Stimuli Stimuli All DUT Inputs Design Under Test (DUT) Simulated Outputs Rule of Thumb: Usually ports from DUT entities are declared as signals within test bench .Test bench(Cont.

Java. Matlab ) expected results .Test bench(Cont.) Possible sources of expected results used for comparison Test bench Representative Inputs actual results VHDL Design = ? Manual Calculations or Reference Software Implementation (C.

Test bench(Cont. Architecture N ..) The same test bench can be used to test multiple implementations of the same circuit (multiple architectures) Test bench Design entity Architecture 1 Architecture 2 ...

TestComp(archName)--Specify entity/arch pair --(OPTIONAL) BEGIN testSequence: PROCESS --Main test process END PROCESS. END arch_TB. -------------------------------------------------------------------------------FOR DUT:TestComp USE ENTITY WORK. END COMPONENT.Test bench(Cont. ARCHITECTURE arch_TB OF TB IS --Local signals and constants COMPONENT TestComp --All Design Under Test component declarations PORT ( ). DUT:TestComp PORT MAP( --Port map all the DUTs ).) Test bench anatomy Entity TB is --TB entity has no ports End TB. .

. RESULT => TEST_RESULT). RESULT : OUT STD_LOGIC ). WAIT FOR 10 ns. ENTITY XOR3_TB IS END XOR3_TB.XOR3 Example(Cont. WAIT FOR 10 ns. END PROCESS TESTING. WAIT FOR 10 ns. WAIT FOR 10 ns. -. C => TEST_VECTOR(2). WAIT FOR 10 ns. ACHITECTURE XOR3_TB_ARCHITECTURE OF XOR3_TB IS -. TEST_VECTOR<="011". B => TEST_VECTOR(1). TEST_VECTOR<="110".Component declaration of the tested unit COMPONENT xor3 PORT( A : IN STD_LOGIC. TEST_VECTOR<="010". END XOR3_TB_ARCHITECTURE. TEST_VECTOR<="101". TEST_VECTOR<="001". SIGNAL TEST_RESULT :STD_LOGIC. C : IN STD_LOGIC.Stimulus signals SIGNAL TEST_VECTOR:STD_LOGIC_VECTOR(2 DOWNTO 0). WAIT FOR 10 ns.std_logic_1164. WAIT FOR 10 ns. B : IN STD_LOGIC. USE ieee.all. TEST_VECTOR<="100". WAIT FOR 10 ns. BEGIN UUT : xor3 PORT MAP ( A => TEST_VECTOR(0). END COMPONENT. TEST_VECTOR<="111".) Test bench LIBRARY ieee. TESTING: PROCESS BEGIN TEST_VECTOR<="000".

the control is again passed to the beginning of the process. WAIT FOR 10 ns.  After execution of the last statement. END PROCESS. WAIT FOR 10 ns.Execution of statements in a PROCESS Testing: PROCESS BEGIN test_vector<=“00”. Program control is passed to the first statement after BEGIN Order of execution . test_vector<=“10”. test_vector<=“11”. WAIT FOR 10 ns. test_vector<=“01”. WAIT FOR 10 ns.  The execution of statements continues sequentially till the last statement in the process.

WAIT FOR 10 ns. WAIT FOR 10 ns.  This will cause the PROCESS to suspend indefinitely when the WAIT statement is executed. test_vector<=“10”. test_vector<=“11”.PROCESS with a WAIT Statement  The last statement in the PROCESS is a WAIT instead of WAIT FOR 10 ns. WAIT. END PROCESS. Order of execution Program execution stops here . Testing: PROCESS BEGIN test_vector<=“00”. WAIT FOR 10 ns.  This form of WAIT can be used in a process included in a test bench when all possible combinations of inputs have been tested or a nonperiodical signal has to be generated. test_vector<=“01”.

WAIT WAIT FOR: waveform will keep repeating itself forever 0 1 2 3 0 1 2 3 … WAIT : waveform will keep its state after the last wait instruction.WAIT FOR vs. … .

test_vector <= "001". END behavioral...... ...Test bench signals generation Generating selected values of one input SIGNAL test_vector : STD_LOGIC_VECTOR(2 DOWNTO 0). WAIT FOR 10 ns.. WAIT FOR 10 ns. testing: PROCESS BEGIN test_vector <= "000". test_vector <= "010"... test_vector <= "100". WAIT FOR 10 ns. WAIT FOR 10 ns. .. BEGIN . WAIT FOR 10 ns. test_vector <= "011".. END PROCESS testing..

testing: PROCESS BEGIN WAIT FOR 10 ns...) Generating all values of one input SIGNAL test_vector : STD_LOGIC_VECTOR (3 DOWNTO 0):="0000". . test_vector <= test_vector + 1. BEGIN ..Test bench signals generation(Cont.. END behavioral... . END PROCESS testing........

.) Generating all possible values of two inputs SIGNAL test_ab : STD_LOGIC_VECTOR (1 DOWNTO 0). .. . END PROCESS double_loo.Test bench signals generation(Cont... BEGIN .... FOR I IN 0 TO 3 LOOP FOR J IN 0 TO 3 LOOP WAIT FOR 10 ns... SIGNAL test_sel : STD_LOGIC_VECTOR (1 DOWNTO 0).. END behavioral. test_sel <= test_sel + 1. END LOOP. test_ab <= test_ab + 1. test_sel <="00". END LOOPl. double_loo: PPROCESS BEGIN test_ab <="00"....

END behavioral.. CONSTANT clk2_period : TIME := 200 ns. WAIT FOR clk1_period/2. clk2 <= not clk2 AFTER clk2_period/2.... clk1_generator: PROCESS clk1 <= ‘0’. SIGNAL clk1 : STD_LOGIC.Test bench signals generation(Cont... .. clk1 <= ‘1’.. END PROCESS.. .. SIGNAL clk2 : STD_LOGIC := ‘0’.. WAIT FOR clk1_period/2. BEGIN ..) Generating periodical signals CONSTANT clk1_period : TIME := 20 ns.

WAIT. reset1 <= ‘0’. CONSTANT reset2_width : TIME := 150 ns... reset2_generator: PROCESS WAIT FOR reset_width..) Generating one-time signals CONSTANT reset1_width : TIME := 100 ns... WAIT FOR reset_width... END PROCESS reset1_generator. reset1_generator: PROCESS reset1 <= ‘1’. SIGNAL reset2 : STD_LOGIC := ‘1’. reset2 <= ‘0’. END PROCESS. BEGIN . WAIT... SIGNAL reset1 : STD_LOGIC.Test bench signals generation(Cont. ... END behavioral. ..

The simulator is instructed to continue simulation or halt.  Depending on the SEVERITY of the problem. .ASSERTs and REPORTs ASSERT  ASSERT is a non-synthesizable statement whose purpose is to write out messages on the screen when problems are found during simulation.

) ASSERT syntax ASSERT condition [REPORT "message“] [SEVERITY severity_level ].ASSERTs and REPORTs(Cont. . WARNING. or FAILURE.  Severity_level can be: NOTE.  The message is written when the condition is FALSE. ERROR (default).

) Examples for ASSERT ASSERT initial_value <= max_value REPORT "initial value too large" SEVERITY ERROR.ASSERTs and REPORTs(Cont. ----------------------------------------------------------ASSERT packet_length /= 0 REPORT "empty network packet received" SEVERITY WARNING. . ----------------------------------------------------------ASSERT false REPORT "Initialization complete" SEVERITY NOTE.

ASSERTs and REPORTs(Cont.) REPORT syntax REPORT "message" [SEVERITY severity_level ]. WARNING.  The message is always written. or FAILURE. . ERROR.  Severity_level can be: NOTE (default).

------------------------------------------------------------REPORT "Incorrect branch" SEVERITY ERROR. .) Examples for REPORT REPORT "Initialization complete". ------------------------------------------------------------REPORT "Current time = " & time'image(now).Asserts and reports(Cont.

Dataflow design style VHDL Design Styles Dataflow Concurrent statements Structural Components and interconnects Behavioral Sequential statements  Registers  State machines  Test benches .

) Dataflow VHDL Design Style Dataflow VHDL Design Style VHDL code synthesizable VHDL code synthesizable .Dataflow design style(Cont.

)     Concurrent signal assignment () Conditional concurrent signal assignment (WHEN-ELSE) Selected concurrent signal assignment (WITH-SELECT-WHEN) Generate scheme for equations (FOR-GENERATE) .Dataflow design style(Cont.

. END fulladd_dataflow .std_logic_1164. ENTITY fulladd IS PORT ( x : IN STD_LOGIC . cout : OUT STD_LOGIC ).Dataflow design style(Cont. ARCHITECTURE fulladd_dataflow OF fulladd IS BEGIN s <= x XOR y XOR cin . cin : IN STD_LOGIC .) Full adder example LIBRARY ieee . USE ieee. cout <= (x AND y) OR (cin AND x) OR (cin AND y) .all . END fulladd . s : OUT STD_LOGIC . y : IN STD_LOGIC .

Logic operators  Logic operators and or nand nor xor not xnor  Logic operators precedence Highest and Lowest or not nand nor xor only in VHDL-93 xnor .

) No Implied Precedence Wanted: y = ab + cd Incorrect y <= a and b or c and d . equivalent to y = (ab + c)d Correct y <= (a and b) or (c and d) . equivalent to y <= ((a and b) or c) and d . .Logic operators(Cont.

Arithmetic operators  To use basic arithmetic operations involving std logic vectors you need to include the following library packages: LIBRARY ieee. SIGNAL b : STD_LOGIC_VECTOR (3 DOWNTO 0). * operators to perform addition.all. C <= A + B.all. SIGNAL c : STD_LOGIC_VECTOR (3 DOWNTO 0).  You can use standard +. subtraction. or USE ieee.std_logic_1164. USE ieee.all.std_logic_unsigned. USE ieee.std_logic_signed. and multiplication: SIGNAL a : STD_LOGIC_VECTOR (3 DOWNTO 0). -. .

USE ieee. S : OUT STD_LOGIC_VECTOR (15 DOWNTO 0) . Cout : OUT STD_LOGIC ). END adder16 . X.Dataflow design style(Cont.all . ENTITY adder16 IS PORT ( Cin : IN STD_LOGIC . END Behavior . BEGIN Sum <= ('0' & X) + Y + Cin . Y : IN STD_LOGIC_VECTOR (15 DOWNTO 0) . Cout <= Sum(16) . USE ieee. S <= Sum(15 DOWNTO 0) .all . ARCHITECTURE Behavior OF adder16 IS SIGNAL Sum : STD_LOGIC_VECTOR (16 DOWNTO 0) .) 16-bit Unsigned adder example LIBRARY ieee . 16 16 X Y Cin S 16 Cout .std_logic_unsigned.std_logic_1164.

) 16-bit Signed adder example LIBRARY ieee . SIGNED (15 DOWNTO 0) . END adder16 .Dataflow design style(Cont.all . Cout <= Sum(16) . END Behavior . STD_LOGIC ARCHITECTURE Behavior OF adder16 IS SIGNAL Sum : SIGNED (16 DOWNTO 0) . USE ieee. Overflow <= Sum(16) XOR X(15) XOR Y(15) XOR Sum(15) . Overflow ). USE ieee.std_logic_arith.std_logic_1164. S <= Sum(15 DOWNTO 0) . Y S Cout. SIGNED (15 DOWNTO 0) . ENTITY adder16 IS PORT ( Cin X. : IN : IN : OUT : OUT STD_LOGIC .all . BEGIN Sum <= ('0' & X) + Y + Cin . .

Dataflow design style(Cont.) 16-bit Signed adder example(Cont.)

ENTITY adder16 IS PORT ( X, Y S ); END adder16 ;

: IN : OUT

INTEGER RANGE -32768 TO 32767 ; INTEGER RANGE -32768 TO 32767

ARCHITECTURE Behavior OF adder16 IS BEGIN S <= X + Y ; END Behavior ;

Dataflow design style(Cont.)

WHEN-ELSE
target_signal <= value1 value2
. . . WHEN condition1 WHEN condition2 ELSE ELSE

valueN-1 WHEN conditionN-1 ELSE valueN;

Value N Value N-1 Value 2 Value 1 Condition 2 Condition 1

Condition N-1

Relational operators
 Relational operators
= /= < <= > >=

 Logic and relational operators precedence
Highest Lowest

= and

/= or

not < <= nand nor

> xor

>= xnor

Relational operators(Cont.)
compare a = bc

Incorrect … WHEN a = b and c ELSE … equivalent to … WHEN (a = b) and c ELSE …
Correct … WHEN a = (b and c) ELSE …

VHDL operators .

) 2-to-1 Multiplexer example LIBRARY ieee . ARCHITECTURE Behavior OF mux2to1 IS BEGIN f <= w0 WHEN s = '0' ELSE w1 . END Behavior .std_logic_1164. s w0 w1 f .all . ENTITY mux2to1 IS PORT ( w0. f : OUT STD_LOGIC ). w1. s : IN STD_LOGIC . END mux2to1 . USE ieee.Dataflow design style(Cont.

output : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) ).std_logic_1164. input END tri_state. ARCHITECTURE tri_state_dataflow OF tri_state IS BEGIN output <= input WHEN (ena = ‘1’) ELSE (OTHERS => ‘Z’).Dataflow design style(Cont.all. input : IN STD_LOGIC_VECTOR (7 DOWNTO 0). END tri_state_dataflow.) Tri-state buffer example LIBRARY ieee. output ena . USE ieee. ENTITY tri_state IS PORT ( ena : IN STD_LOGIC.

4 4 A B AeqB AgtB AltB . AltB <= '1' WHEN A < B ELSE '0' .std_logic_unsigned.) 4-bit Unsigned number comparator example LIBRARY ieee .Dataflow design style(Cont. STD_LOGIC ARCHITECTURE Behavior OF compare IS BEGIN AeqB <= '1' WHEN A = B ELSE '0' . USE ieee. USE ieee. STD_LOGIC_VECTOR (3 DOWNTO 0) . AltB : OUT ).all . B : IN AeqB.std_logic_1164. END Behavior . AgtB. AgtB <= '1' WHEN A > B ELSE '0' . ENTITY compare IS PORT ( A. END compare .all .

STD_LOGIC ARCHITECTURE Behavior OF compare IS BEGIN AeqB <= '1' WHEN A = B ELSE '0' . B AeqB. AltB <= '1' WHEN A < B ELSE '0' . END Behavior .std_logic_signed. AltB ).all . ENTITY compare IS PORT ( A.) 4-bit Signed number comparator example LIBRARY ieee . USE ieee. END compare . AgtB <= '1' WHEN A > B ELSE '0' .std_logic_1164. : IN : OUT STD_LOGIC_VECTOR (3 DOWNTO 0) .Dataflow design style(Cont. . AgtB.all . USE ieee.

USE ieee. z : OUT STD_LOGIC ) . ENTITY priority IS PORT ( w : IN STD_LOGIC_VECTOR (3 DOWNTO 0) .all . END priority .std_logic_1164. z <= '0' WHEN w = "0000" ELSE '1' . ARCHITECTURE Behavior OF priority IS BEGIN y <= "11" WHEN w(3) = '1' ELSE "10" WHEN w(2) = '1' ELSE "01" WHEN w(1) = '1' ELSE "00" . END Behavior .Dataflow design style(Cont. y : OUT STD_LOGIC_VECTOR (1 DOWNTO 0) . w0 w1 w2 w3 y0 y1 z .) Priority encoder example LIBRARY ieee .

.Dataflow design style(Cont. expression1 expression2 choices_1 choices_2 target_signal expressionN choices_N choice expression . expressionN WHEN choices_N.) WITH-SELECT-WHEN WITH choice_expression SELECT target_signal <= expression1 WHEN choices_1. expression2 WHEN choices_2. . .

. | value N WITH sel SELECT y <= a WHEN "000"..Dataflow design style(Cont. b WHEN "011" to "110". . c WHEN "001" | "111".) WITH-SELECT-WHEN(Cont..) Allowed formats of choices expressions WHEN value WHEN value_1 to value_2 WHEN value_1 | value_2 | . d WHEN OTHERS.

Dataflow design style(Cont. w3 s f ). w1 WHEN "01". STD_LOGIC ARCHITECTURE Behavior OF mux4to1 IS BEGIN WITH s SELECT f <= w0 WHEN "00". w1. END mux4to1 . ENTITY mux4to1 IS PORT ( w0. STD_LOGIC_VECTOR (1 DOWNTO 0) . USE ieee. w2. : IN : IN : OUT STD_LOGIC . w3 WHEN OTHERS .) 4-to-1 Multiplexer example LIBRARY ieee . . w2 WHEN "10". END Behavior .all .std_logic_1164.

END dec2to4 .Dataflow design style(Cont. "0001" WHEN "111". : IN : IN : OUT STD_LOGIC_VECTOR (1 DOWNTO 0) . "0010" WHEN "110".std_logic_1164. WITH Enw SELECT y <= "1000" WHEN "100". "0000" WHEN OTHERS .) 2-to-4 Decoder example LIBRARY ieee . ENTITY dec2to4 IS PORT ( w En y ). BEGIN Enw <= En & w . STD_LOGIC . . END Behavior . USE ieee.all . STD_LOGIC_VECTOR (0 TO 3) ARCHITECTURE Behavior OF dec2to4 IS SIGNAL Enw : STD_LOGIC_VECTOR (2 DOWNTO 0) . "0100" WHEN "101".

Dataflow design style(Cont.) FOR-GENERATE label: FOR identifier IN range GENERATE BEGIN {Concurrent Statements} END GENERATE. .

all. USE ieee.Dataflow design style(Cont. END parity.) 8-Bits parity example LIBRARY ieee. parity_out : OUT STD_LOGIC ). . ENTITY parity IS PORT( parity_in : IN STD_LOGIC_VECTOR (7 DOWNTO 0).std_logic_1164.

END GENERATE G2.) 8-Bits parity example(Cont.Dataflow design style(Cont. . BEGIN xor_out(1) <= parity_in(0) XOR parity_in(1).) ARCHITECTURE parity_dataflow_1 OF parity IS SIGNAL xor_out: STD_LOGIC_VECTOR (6 DOWNTO 1). G2: FOR i IN 1 TO 5 GENERATE xor_out(i+1) <= xor_out(i) XOR parity_in(i+1). END parity_dataflow_1. parity_out <= xor_out(6) XOR parity_in(7).

END GENERATE G2. END parity_dataflow_2. . parity_out <= xor_out(7). BEGIN xor_out(0) <= parity_in(0).) ARCHITECTURE parity_dataflow_2 OF parity IS SIGNAL xor_out: STD_LOGIC_VECTOR (7 DOWNTO 0).) 8-Bits parity example(Cont.Dataflow design style(Cont. G2: FOR i IN 0 TO 6 GENERATE xor_out(i+1) <= xor_out(i) XOR parity_in(i+1).

Structural design style VHDL Design Styles Dataflow Concurrent statements Structural Components and interconnects Behavioral Sequential statements  Registers & counters  Finite state machines  Test benches .

)  Component instantiation (PORT MAP)  Generate scheme for component instantiations (FOR-GENERATE)  Component instantiation with generic (GENERIC MAP. PORT MAP) .Structural design style(Cont.

Structural design style(Cont.)

Example
s(0) r(0) r(1) p(1) r(2) r(3) r(4) r(5) s(1) p(0)

w0 w1 w2 w3
priority

y0 y1 z

q(0) q(1) ena

w w

0
1

y y y

0
1 2

z(0) z(1)
z(2) z(3)

p(2)

p(3)

En

y

3

dec2to4

Structural design style(Cont.)
Example(Cont.)
LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY priority_resolver IS PORT (r : IN s : IN z : OUT ); END priority_resolver;

STD_LOGIC_VECTOR (5 DOWNTO 0) ; STD_LOGIC_VECTOR (1 DOWNTO 0) ; STD_LOGIC_VECTOR (3 DOWNTO 0)

ARCHITECTURE structural OF priority_resolver IS SIGNAL p : STD_LOGIC_VECTOR (3 DOWNTO 0) ; SIGNAL q : STD_LOGIC_VECTOR (1 DOWNTO 0) ; SIGNAL ena : STD_LOGIC ;

Structural design style(Cont.) Example(Cont.)
COMPONENT mux2to1 PORT (w0, w1, s : IN f : OUT ); END COMPONENT ; COMPONENT priority PORT (w : IN y : OUT z : OUT ); END COMPONENT ; COMPONENT dec2to4 PORT (w : IN En : IN y : OUT END COMPONENT ; STD_LOGIC ; STD_LOGIC

STD_LOGIC_VECTOR (3 DOWNTO 0) ; STD_LOGIC_VECTOR (1 DOWNTO 0) ; STD_LOGIC

STD_LOGIC_VECTOR (1 DOWNTO 0) ; STD_LOGIC ; STD_LOGIC_VECTOR (0 TO 3) ) ;

Structural design style(Cont.) Example(Cont.)
BEGIN u1: mux2to1 PORT MAP (w0 => r(0) , w1 => r(1), s => s(0), f => p(0)); p(1) <= r(2); p(1) <= r(3); u2: mux2to1 PORT MAP (w0 => r(4) , w1 => r(5), s => s(1), f => p(3)); u3: priority PORT MAP (w => p, y => q, z => ena);

u4: dec2to4 PORT MAP (w => q, En => ena, y => z);
END structural;

Structural design style(Cont.) Example(Cont.)
 Named association connectivity recommended in majority of cases, prevents ommisions and mistakes  Positional association connectivity allowed, especially for the cases of
– Small number of ports – Multiple instantiations of the same component, in regular structures

CONSTANT strobe_period : TIME := 333. CONSTANT ANDA_EXT : STD_LOGIC_VECTOR (7 DOWNTO 0) := X"B4". CONSTANT counter_width : INTEGER := 16. CONSTANT buffer_address : INTEGER := 16#FFFE#.333 ms. .CONSTANTs CONSTANT name : type := value. CONSTANT clk_period : TIME := 20 ns. CONSTANT init_value : STD_LOGIC_VECTOR (3 DOWNTO 0) := "0100".

it is visible only within this ARCHITECTURE. for the package can be used in several entities. CONSTANT can be used in all ARCHITECTUREs associated with this ENTITY.  When declared in an ARCHITECTURE. i. CONSTANT is local.. CONSTANT is truly global. ARCHITECTURE  When declared in a PACKAGE.CONSTANTs features  CONSTANTs can be declared in a PACKAGE. ENTITY. .  When declared in an ENTITY declaration.e.

ROM LIBRARY ieee. PORT ( addr: IN INTEGER RANGE 0 TO words-1. END rom. -.all.std_logic_1164. -----------------------------------------------------------------------------------------------ENTITY rom IS GENERIC (bits : INTEGER:=8. . data: OUT STD_LOGIC_VECTOR (bits – 1 DOWNTO 0) ). USE ieee.# of bits per word words: INTEGER:=8 -.# of words in the memory ).

. CONSTANT memory: vector_array := ("0000_0000". "0100_0000". BEGIN data <= memory(addr).ROM (Cont. END rom. "0000_0100". "1000_0000"). "0000_0010". "0010_0000".) ARCHITECTURE behavioral OF rom IS TYPE vector_array IS ARRAY (0 TO words-1) OF STD_L OGIC_VECTOR (bits – 1 DOWNTO 0). "0000_1000". "0001_0000".

END COMPONENT . s : IN f : OUT ). USE ieee. y : OUT STD_LOGIC_VECTOR (0 TO 3) ) . STD_LOGIC ) . COMPONENT dec2to4 PORT (w : IN STD_LOGIC_VECTOR (1 DOWNTO 0) . En : IN STD_LOGIC . STD_LOGIC STD_LOGIC_VECTOR (3 DOWNTO 0) . STD_LOGIC . w1. COMPONENT priority PORT (w : IN y : OUT z : OUT END COMPONENT .all . STD_LOGIC_VECTOR (1 DOWNTO 0) . . END COMPONENT .Package declaration Example LIBRARY ieee .std_logic_1164. PACKAGE GatesPkg IS COMPONENT mux2to1 PORT (w0.

CONSTANT NOTA : STD_LOGIC_VECTOR (3 DOWNTO 0) := "0100". CONSTANT NOTM : STD_LOGIC_VECTOR (3 DOWNTO 0) := "0110". END GatesPkg.) Example(Cont. . CONSTANT SUBAM : STD_LOGIC_VECTOR (3 DOWNTO 0) := "0011". CONSTANT ANDAB : STD_LOGIC_VECTOR (3 DOWNTO 0) := "0111".Package declaration(Cont. CONSTANT ADDAM : STD_LOGIC_VECTOR (3 DOWNTO 0) := "0001". CONSTANT NOTB : STD_LOGIC_VECTOR (3 DOWNTO 0) := "0101".) CONSTANT ADDAB : STD_LOGIC_VECTOR (3 DOWNTO 0) := "0000". CONSTANT SUBAB : STD_LOGIC_VECTOR (3 DOWNTO 0) := "0010".

STD_LOGIC_VECTOR (5 DOWNTO 0) .GatesPkg.all .) Example(Cont.all. ENTITY priority_resolver IS PORT (r : IN s : IN z : OUT ). STD_LOGIC_VECTOR (1 DOWNTO 0) . END priority_resolver. USE work.Package declaration(Cont. STD_LOGIC_VECTOR (3 DOWNTO 0) ARCHITECTURE structural OF priority_resolver IS SIGNAL p : STD_LOGIC_VECTOR (3 DOWNTO 0) . USE ieee.) LIBRARY ieee . SIGNAL ena : STD_LOGIC .std_logic_1164. SIGNAL q : STD_LOGIC_VECTOR (1 DOWNTO 0) . .

u2: mux2to1 PORT MAP (w0 => r(4) .) Example(Cont. w1 => r(5). f => p(3)). u3: priority PORT MAP (w => p. u4: dec2to4 PORT MAP (w => q.) BEGIN u1: mux2to1 PORT MAP (w0 => r(0) . s => s(0).Package declaration(Cont. p(1) <= r(2). s => s(1). END structural. . z => ena). y => z). En => ena. f => p(0)). p(1) <= r(3). y => q. w1 => r(1).

Configuration declaration CONFIGURATION SimpleCfg OF priority_resolver IS FOR structural FOR ALL: mux2to1 USE ENTITY work. END FOR.mux2to1(dataflow). FOR u4: dec2to4 USE ENTITY work. FOR u3: priority USE ENTITY work. END FOR. END FOR. END SimpleCfg.dec2to4(dataflow).priority(dataflow). . END FOR.

) 16-to-1 Multiplexer example s0 s1 w0 w3 w4 w7 s2 s3 f w8 w 11 w 12 w 15 .Structural design style(Cont.

) Straightforward code LIBRARY ieee . ENTITY Example1 IS PORT ( w : IN s : IN f : OUT ). STD_LOGIC_VECTOR (0 TO 15) .Structural design style(Cont. STD_LOGIC .all . USE ieee.) 16-to-1 Multiplexer example(Cont.std_logic_1164. END Example1 . STD_LOGIC_VECTOR (3 DOWNTO 0) .

w(3). m(2). s(1 DOWNTO 0). m(1). w(15). s(1 DOWNTO 0). w2. Mux2: mux4to1 PORT MAP ( w(4). BEGIN Mux1: mux4to1 PORT MAP ( w(0). s(3 DOWNTO 2). . Mux5: mux4to1 PORT MAP ( m(0). Mux4: mux4to1 PORT MAP ( w(12). w(11).) ARCHITECTURE Structure OF Example1 IS COMPONENT mux4to1 PORT ( w0. w(10). Mux3: mux4to1 PORT MAP ( w(8). : IN : IN : OUT STD_LOGIC . f ) . m(3). END COMPONENT . STD_LOGIC w(1). m(0) ) . w(7). w(2). w(9). STD_LOGIC_VECTOR (1 DOWNTO 0) .Structural design style(Cont. w3 s f ). m(1) ) . w(6). SIGNAL m : STD_LOGIC_VECTOR (0 TO 3) . m(2) ) . w(5). m(3) ) . s(1 DOWNTO 0). s(1 DOWNTO 0). w(13).) 16-to-1 Multiplexer example(Cont.) Straightforward code(Cont. w1. w(14). END Structure .

w(4*i+1). s(1 DOWNTO 0). w3 s f END COMPONENT . BEGIN G1: FOR i IN 0 TO 3 GENERATE Muxes: mux4to1 PORT MAP ( w(4*i). w(4*i+2). m(3). : IN : IN : OUT STD_LOGIC . s(3 DOWNTO 2). SIGNAL m : STD_LOGIC_VECTOR (0 TO 3) . Mux5: mux4to1 PORT MAP ( m(0). END GENERATE . f ) .Structural design style(Cont. m(1). m(2).) Modified code ARCHITECTURE Structure OF Example1 IS COMPONENT mux4to1 PORT ( w0. STD_LOGIC ) . . w1. w2. m(i) ) . END Structure . w(4*i+3).) 16-to-1 Multiplexer example(Cont. STD_LOGIC_VECTOR (1 DOWNTO 0) .

std_logic_1164.all .) Variable 16-bit rotator example LIBRARY ieee . USE ieee. B : IN STD_LOGIC_VECTOR ( 3 DOWNTO 0).Structural design style(Cont. C : OUT STD_LOGIC_VECTOR (15 DOWNTO 0) ). END variable_rotator_16. ENTITY variable_rotator_16 is PORT( A : IN STD_LOGIC_VECTOR (15 DOWNTO 0). 4 A 16 B A <<< B 16 C .

STD_LOGIC_VECTOR (15 DOWNTO 0). STD_LOGIC_VECTOR(15 DOWNTO 0) COMPONENT fixed_rotator_left_16 GENERIC ( L : INTEGER := 1).all .std_logic_1164.) LIBRARY ieee . PORT ( a : IN STD_LOGIC_VECTOR (15 DOWNTO 0). END COMPONENT .) Variable 16-bit rotator example(Cont. STD_LOGIC_VECTOR (15 DOWNTO 0). y : OUT STD_LOGIC_VECTOR (15 DOWNTO 0) ). STD_LOGIC . END COMPONENT . USE ieee. .Structural design style(Cont. ARCHITECTURE structural OF variable_rotator_16 IS COMPONENT mux2to1_16 PORT ( w0 : IN w1 : IN s : IN f : OUT ).

G: FOR i IN 0 TO 3 GENERATE ROT_I: fixed_rotator_left_16 GENERIC MAP (L => 2** i) PORT MAP ( a => Al(i) . END GENERATE.) Variable 16-bit rotator example(Cont. SIGNAL Ar : array2. w1 => Ar(i). BEGIN Al(0) <= A. y => Ar(i)). s => B(i). SIGNAL Al : array1. END variable_rotator_16. MUX_I: mux2to1_16 PORT MAP (w0 => Al(i). f => Al(i+1)). TYPE array2 IS ARRAY (0 TO 3) OF STD_LOGIC_VECTOR (15 DOWNTO 0). .) TYPE array1 IS ARRAY (0 TO 4) OF STD_LOGIC_VECTOR (15 DOWNTO 0). C <= Al(4).Structural design style(Cont.

Behavioral design style VHDL Design Styles Dataflow Concurrent statements Structural Components and interconnects Behavioral Sequential statements Registers & counters Finite state machines Test bench .

Behavioral design style(Cont.) PROCESSes  PROCESSes describe sequential behavior  PROCESSes in VHDL are very powerful statements – Allow to define an arbitrary behavior that may be difficult to represent by a real circuit – Not every process can be synthesized  Use PROCESSes with caution in the code to be synthesized  Use PROCESSes freely in test benches .

test_vector<=“10”. Hence. the order of statements is important  A process must end with the keywords END PROCESS testing: PROCESS BEGIN test_vector<=“00”.Behavioral design style(Cont. WAIT FOR 10 ns. test_vector<=“01”. test_vector<=“11”. END PROCESS. WAIT FOR 10 ns. WAIT FOR 10 ns. WAIT FOR 10 ns.) What is a PROCESS? A process is a sequence of instructions referred to as sequential statements. The keyword PROCESS  A process can be given a unique name using an optional LABEL  This is followed by the keyword PROCESS  The keyword BEGIN is used to indicate the start of the process  All statements within the process are executed SEQUENTIALLY. .

) Anatomy of a Process OPTIONAL [label:] PROCESS [(sensitivity list)] [declaration part] BEGIN statement part END PROCESS [label].Behavioral design style(Cont. .

 WAIT statements are not allowed in a PROCESSes with sensitivity list. label: PROCESS (sensitivity list) declaration part BEGIN statement part END PROCESS. the process fire  Every time the process fires.Behavioral design style(Cont. . it will run in its entirety.) Process with a sensitivity list  List of signals to which the process is sensitive  Whenever there is an event on any of the signals in the sensitivity list.

) Statement Part  Contains sequential statements to be executed each time the process Is activated  Analogous to conventional programming languages .Behavioral design style(Cont.

 ELSE and ELSIF are optional .)  IF statement IF boolean expression THEN statements ELSIF boolean expression THEN statements ELSE boolean expression THEN statements END IF.) Statement Part(Cont.Behavioral design style(Cont.

Behavioral design style(Cont.)  CASE statement  Choices have to cover all possible values of the condition – Use OTHERS to specify all remaining cases CASE condition IS WHEN choice_1 => statements WHEN choice_2 => statements WHEN OTHERS => statements END CASE.) Statement Part(Cont. .

 Repeats a section of VHDL code .) Statement Part(Cont.)  Loop Statement FOR i IN range LOOP statements END LOOP.Behavioral design style(Cont.

w.Component Equivalent of a Process priority: PROCESS (clk) BEGIN IF w(3) = '1' THEN y <= "11" . c  All signals which appear in the sensitivity list are inputs e. a. b. END IF . y.g. ELSE z <= "00" . z  All signals which appear on the right of signal assignment statement (<=) or in logic expressions are inputs e.g. ELSIF w(1) = c THEN y <= a and b. clk  Note that not all inputs need to be included in the sensitivity list . END PROCESS . clk w a b c y priority z  All signals which appear on the left of signal assignment statement (<=) are outputs e.g. ELSIF w(2) = '1' THEN y <= "10" .

ENTITY latch IS PORT ( D. END PROCESS . END latch .Behavioral design style(Cont. Clock) BEGIN IF Clock = '1' THEN Q <= D .std_logic_1164. USE ieee. STD_LOGIC ARCHITECTURE Behavior OF latch IS BEGIN PROCESS ( D.) D latch LIBRARY ieee .all . D Clock Q . STD_LOGIC . Clock : IN Q : OUT ). END Behavior. END IF .

Clock : IN STD_LOGIC . ARCHITECTURE Behavior_1 OF flipflop IS BEGIN PROCESS ( Clock ) BEGIN IF Clock'EVENT AND Clock = '1' THEN Q <= D . END Behavior_1 .) D flip-flop LIBRARY ieee . END IF . D Clock Q . USE ieee.all .std_logic_1164.Behavioral design style(Cont. Q : OUT STD_LOGIC ). ENTITY flipflop IS PORT ( D. END flipflop . END PROCESS .

Behavioral design style(Cont. USE ieee.std_logic_1164. D Clock Q . END Behavior_2 . ENTITY flipflop IS PORT ( D. END PROCESS . ARCHITECTURE Behavior_2 OF flipflop IS BEGIN PROCESS BEGIN WAIT UNTIL Clock'EVENT AND Clock = '1' .) Another architecture for D flip-flop LIBRARY ieee . Q : OUT STD_LOGIC ). Clock : IN STD_LOGIC . Q <= D . END flipflop .all .

all . END IF . : IN : OUT STD_LOGIC . D Clock Resetn Q . END PROCESS . END Behavior . ENTITY flipflop IS PORT ( D.Behavioral design style(Cont. Clock Q ). END flipflop . Resetn. Clock ) BEGIN IF Resetn = '0' THEN Q <= '0' .) D flip-flop with asynchronous reset LIBRARY ieee . USE ieee.std_logic_1164. STD_LOGIC ARCHITECTURE Behavior OF flipflop IS BEGIN PROCESS ( Resetn. ELSIF Clock'EVENT AND Clock = '1' THEN Q <= D .

USE ieee. D Clock Resetn Q . IF Resetn = '0' THEN Q <= '0' . END flipflop . ELSE Q <= D . END Behavior . END PROCESS . : IN : OUT STD_LOGIC . END IF . Clock Q ). ENTITY flipflop IS PORT ( D.Behavioral design style(Cont.) D flip-flop with synchronous reset LIBRARY ieee .std_logic_1164. STD_LOGIC ARCHITECTURE Behavior OF flipflop IS BEGIN PROCESS BEGIN WAIT UNTIL Clock'EVENT AND Clock = '1' .all . Resetn.

all . : IN STD_LOGIC . 8 Resetn 8 D Q Clock reg8 . : IN STD_LOGIC_VECTOR (7 DOWNTO 0) .) 8-bit Register with asynchronous reset LIBRARY ieee .std_logic_1164. ELSIF Clock'EVENT AND Clock = '1' THEN Q <= D . : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) ARCHITECTURE Behavior OF reg8 IS BEGIN PROCESS ( Resetn. Clock ) BEGIN IF Resetn = '0' THEN Q <= "00000000" . Clock Q ). END IF . END reg8 . ENTITY reg8 IS PORT ( D Resetn. END Behavior . END PROCESS .Behavioral design style(Cont. USE ieee.

D Q ELSIF Clock'EVENT AND Clock = '1' THEN Q <= D . Clock END PROCESS . Q : OUT STD_LOGIC_VECTOR (N-1 DOWNTO 0) ). USE ieee. END IF . PORT ( D : IN STD_LOGIC_VECTOR (N-1 DOWNTO 0) .Behavioral design style(Cont. Clock : IN STD_LOGIC . regn END Behavior . END regn .) N-bit Register with asynchronous reset LIBRARY ieee . ARCHITECTURE Behavior OF regn IS BEGIN PROCESS ( Resetn.all . . Resetn.std_logic_1164. ENTITY regn IS GENERIC ( N : INTEGER := 16 ) . Clock ) BEGIN IF Resetn = '0' THEN N Resetn N Q <= (OTHERS => '0') .

ARCHITECTURE Behavior OF regn IS BEGIN PROCESS (Clock) BEGIN IF (Clock'EVENT AND Clock = '1' ) THEN N Enable N IF Enable = '1' THEN Q D Q <= D . Clock : IN STD_LOGIC . END regn . END IF. ENTITY regn IS GENERIC ( N : INTEGER := 8 ) . Clock END PROCESS . regn .std_logic_1164. END IF . PORT ( D : IN STD_LOGIC_VECTOR (N-1 DOWNTO 0) . Enable. USE ieee.Behavioral design style(Cont.) N-bit Register with enable LIBRARY ieee . END Behavior . Q : OUT STD_LOGIC_VECTOR (N-1 DOWNTO 0) ).all .

) 2-bit Up-counter with synchronous reset LIBRARY ieee . USE ieee.std_logic_1164. END PROCESS. USE ieee. ENTITY upcount IS PORT ( Clear. Clock END Behavior .all . END upcount . ARCHITECTURE Behavior OF upcount IS BEGIN upcount: PROCESS ( Clock ) BEGIN IF (Clock'EVENT AND Clock = '1') THEN IF Clear = '1' THEN Q <= "00" .all . END IF . upcount END IF. 2 .std_logic_unsigned. Clock : IN STD_LOGIC .Behavioral design style(Cont. ELSE Clear Q Q <= Q + “01” . Q : BUFFER STD_LOGIC_VECTOR (1 DOWNTO 0) ).

STD_LOGIC_VECTOR (3 DOWNTO 0) Enable Q Clock Resetn 4 upcount . USE ieee.) 4-bit Up-counter with asynchronous reset LIBRARY ieee .std_logic_unsigned. : IN : OUT STD_LOGIC . USE ieee. ENTITY upcount IS PORT ( Clock. END upcount .std_logic_1164. Resetn.Behavioral design style(Cont.all .all . Enable Q ).

Q END Behavior .Behavioral design style(Cont. END PROCESS . BEGIN PROCESS ( Clock. ELSIF (Clock'EVENT AND Clock = '1') THEN IF Enable = '1' THEN Count <= Count + 1 . END IF . 4 Clock Resetn upcount . Resetn ) BEGIN IF Resetn = '0' THEN Count <= "0000" . END IF .) ARCHITECTURE Behavior OF upcount IS SIGNAL Count : STD_LOGIC_VECTOR (3 DOWNTO 0) .) 4-bit Up-counter with asynchronous reset(Cont. Enable Q <= Count .

Behavioral design style(Cont.) 4-bit Shift register with parallel load Load D(3) Sin D D(2) D(1) D(0) Q D Q D Q D Q Clock Enable Q(3) Q(2) Q(1) Q(0) .

PORT ( D : IN STD_LOGIC_VECTOR (N-1 DOWNTO 0) . Enable : IN STD_LOGIC . USE ieee. Clock : IN STD_LOGIC . Load : IN STD_LOGIC . Sin : IN STD_LOGIC . . END shiftn . Q : BUFFER STD_LOGIC_VECTOR (N-1 DOWNTO 0) ). ENTITY shiftn IS GENERIC ( N : INTEGER := 8 ) .Behavioral design style(Cont.all .) N-bit Shift register with parallel load LIBRARY ieee .std_logic_1164.

) N-bit Shift register with parallel load(Cont. END Behavior . END PROCESS . Q(N-1) <= Sin . END IF.) ARCHITECTURE Behavior OF shiftn IS BEGIN PROCESS (Clock) BEGIN IF (Clock'EVENT AND Clock = '1' ) THEN IF Load = '1' THEN Q <= D . . END LOOP . ELSIF Enable = ‘1’ THEN Genbits: FOR i IN 0 TO N-2 LOOP Q(i) <= Q(i+1) .Behavioral design style(Cont. END IF .

Behavioral design style(Cont. ELSIF (clock = ‘1’ AND clock’EVENT) THEN CASE Moore_state IS WHEN S0 => IF input = ‘1’ THEN Moore_state <= S1. WHEN S2 => IF input = ‘0’ THEN Moore_state <= S0. ELSE Moore_state <= S1. END IF. SIGNAL Moore_state: state. U_Moore: PROCESS (clock. END IF.) Sequence ”10” recognizer TYPE state IS (S0. WHEN S1 => IF input = ‘0’ THEN Moore_state <= S2. END CASE. ELSE Moore_state <= S1. Output <= ‘1’ WHEN Moore_state = S2 ELSE ‘0’. END IF. END PROCESS. S2). reset) BEGIN IF(reset = ‘1’) THEN Moore_state <= S0. ELSE Moore_state <= S0. S1. END IF. .

SIGNAL Mealy_state: state. END PROCESS.) TYPE state IS (S0. reset) BEGIN IF (reset = ‘1’) THEN Mealy_state <= S0. ELSE Mealy_state <= S1. . ELSIF (clock = ‘1’ AND clock’EVENT) THEN CASE Mealy_state IS WHEN S0 => IF input = ‘1’ THEN Mealy_state <= S1. END IF. ELSE Mealy_state <= S0. END IF. WHEN S1 => IF input = ‘0’ THEN Mealy_state <= S0. U_Mealy: PROCESS(clock.) Sequence ”10” recognizer(Cont. END IF. Output <= ‘1’ WHEN (Mealy_state = S1 AND input = ‘0’) ELSE ‘0’. END CASE. S1).Behavioral design style(Cont.

: OUT STD_LOGIC ARCHITECTURE Behavior OF simple IS TYPE State_type IS (A. END PROCESS . clock ) BEGIN IF resetn = '0' THEN y <= A . WHEN C => IF w = '0' THEN y <= A . C) . WHEN B => IF w = '0' THEN y <= A .Behavioral design style(Cont. ELSE y <= B . END simple . END Behavior .all . SIGNAL y : State_type .std_logic_1164. : IN STD_LOGIC . : IN STD_LOGIC . . END CASE . END IF . B. ELSIF (Clock'EVENT AND Clock = '1') THEN CASE y IS WHEN A => IF w = '0' THEN y <= A .) Sequence ”11” recognizer USE ieee. ELSE y <= C . ENTITY simple IS PORT ( clock resetn w z ). ELSE y <= C . BEGIN PROCESS ( resetn. : IN STD_LOGIC . z <= '1' WHEN y = C ELSE '0' . END IF . END IF . END IF .

Behavioral design style(Cont. ELSE BEGIN y_next <= C . SIGNAL y_present. PROCESS ( w. y_next <= A . END PROCESS . y_present <= A . WHEN A => IF w = '0' THEN PROCESS (clock. BEGIN END CASE . C) . END IF . ELSE y_next <= C . y_next : State_type . END Behavior2 . END IF . . CASE y_present IS END PROCESS . y_next <= A . B. IF w = '0' THEN END IF .) Alternative sequence ”11” recognizer architecture WHEN C => ARCHITECTURE Behavior2 OF simple IS IF w = '0' THEN TYPE State_type IS (A. z <= '1' WHEN y_present = C ELSE '0' . ELSIF (clock'EVENT AND clock = '1') THEN WHEN B => y_present <= y_next . y_present ) END IF . resetn) y_next <= A . BEGIN ELSE IF resetn = '0' THEN y_next <= B .

ELSE y <= B . WHEN B => IF w = '0' THEN y <= A . END IF .std_logic_1164. WHEN A => IF w = '0' THEN y <= A . END PROCESS . BEGIN PROCESS ( resetn.) CASE y IS LIBRARY ieee . END IF . ELSIF (clock'EVENT AND clock = '1') THEN . clock ) BEGIN IF resetn = '0' THEN y <= A . STD_LOGIC . END Behavior .all . USE ieee. ENTITY Mealy IS PORT ( clock resetn w z ). END Mealy . WITH y SELECT z <= w WHEN B. END CASE . STD_LOGIC ARCHITECTURE Behavior OF Mealy IS TYPE State_type IS (A. B) . STD_LOGIC . : IN : IN : IN : OUT STD_LOGIC .) Sequence ”11” recognizer(Cont. ELSE y <= B . z <= ‘0’ WHEN others.Behavioral design style(Cont. END IF . SIGNAL y : State_type .

) State encoding problem  State encoding can have a big influence on optimality of the FSM implementation – No methods other than checking all possible encodings are known to produce optimal circuit – Feasible for small circuits only  Using enumerated types for states in VHDL leaves encoding problem for synthesis tool .Behavioral design style(Cont.

Behavioral design style(Cont.) Types of state encoding  Binary (Sequential) – states encoded as consecutive binary numbers – Small number of used flip-flops – Potentially complex transition functions leading to slow implementations  One-Hot – only one bit Is active – Number of used flip-flops as big as number of states – Simple and fast transition functions – Preferable coding technique in FPGAs .

Behavioral design style(Cont.) Types of state encoding(Cont.) State S0 S1 S2 S3 S4 S5 S6 S7 Binary Code One-Hot Code 000 001 010 011 100 101 110 111 10000000 01000000 00100000 00010000 00001000 00000100 00000010 00000001 .

. C) . ATTRIBUTE ENUM_ENCODING OF State_type : TYPE IS "00 01 11" . y_next : State_type . SIGNAL y_present.) Manual state assignment using attributes --(ENTITY declaration not shown) ARCHITECTURE Behavior OF simple IS TYPE State_type IS (A. B. . ATTRIBUTE ENUM_ENCODING : STRING .. BEGIN con’t .Behavioral design style(Cont.

ELSE y_next <= B .Behavioral design style(Cont. CONSTANT A CONSTANT B CONSTANT C : ABC_STATE := "00" .) Manual state assignment using constants ARCHITECTURE Behavior OF simple IS SUBTYPE ABC_STATE IS STD_LOGIC_VECTOR (1 DOWNTO 0). : ABC_STATE := "11" . y_present ) BEGIN CASE y_present IS WHEN A => IF w = '0' THEN y_next <= A . END IF . SIGNAL y_present. … con’t . y_next : ABC_STATE. : ABC_STATE := "01" . ------------------------------------------------------------------------------------------BEGIN PROCESS ( w.

) Arbiter circuit Reset 000 Idle 0xx 1xx reset x0x gnt1 g 1 = 1 1xx 01x r1 r2 r3 g1 Arbiter g2 g3 xx0 gnt2 g 2 = 1 x1x 001 gnt3 g 3 = 1 clock xx1 .Behavioral design style(Cont.

Mixed design style ARCHITECTURE ARCHITECTURE_NAME OF ENTITY_NAME IS – Here you can declare signals. procedures… – Component declarations BEGIN Concurrent statements: • Concurrent simple signal assignment • Conditional signal assignment • Selected signal assignment • Generate statement • Component instantiation statement • Process statement – inside process you can use only sequential statements Concurrent Statements END ARCHITECTURE_NAME. constants. functions. .

SIGNALs and concurrent statements  Multiple concurrent assignment to one signal is not allowed in tools without resolved logic support  Inside PROCESS: If multiple assignments occur to SIGNAL X. the last assignment “X <= ?“ overrides previous ones  In fact there is no effect even if we put synchronous inputs in the sensitivity list in case of clocked processes with synchronous inputs .

 VARIABLEs are sequential. A2 := B2 and C2. • := VARIABLE assignment. their values change intermediately. A1<= B1 or C1.  SIGNAL representing an internal wire or an in/out/buffer signal in port.  <= SIGNAL assignment. .SIGNALs and VARIABLEs  SIGNALs are global(declared outside PROCESSes)  VARIABLEs live inside PROCESSes only(declared inside PROCESSes only).

Subprograms  Include FUNCTIONs and PROCEDUREs Commonly used pieces of code Can be placed in a library. the same as processes      . and then reused and shared among various projects Abstract operations that are repeatedly performed Type conversions Use only sequential statements.

) Typical locations of subprograms PACKAGE PACKAGE BODY LIBRARY global FUNCTION / PROCEDURE ENTITY local for all architectures of a given entity ARCHITECTURE Declarative part local for a given architecture .Subprograms(Cont.

variables are not allowed.FUNCTIONs  FUNCTIONs always return a single value as a result  FUNCTIONs are called using formal and actual parameters the same way as components  FUNNCTIONs never modify parameters passed to them  Parameters can only be constants (including generics) and signals (including ports). and not called on their own . the default is a CONSTANT  When passing parameters. or TO/DOWNTO for STD_LOGIC_VECTOR)  FUNCTIONs are always used in some expression. no range specification should be included (for example no RANGE for INTEGERS.

) FUNCTION syntax FUNCTION function_name (<parameter_list>) RETURN data_type IS [declarations] BEGIN (sequential statements) END function_name.FUNCTIONs(Cont. .

FUNCTIONs(Cont. b: INTEGER.) FUNCTION parameters Example FUNCTION f1 (a. . SIGNAL c: STD_LOGIC_VECTOR) RETURN BOOLEAN IS BEGIN (sequantial statements) END f1.

b) LOOP . IF x > maximum(a. WHILE minimum(a...FUNCTIONs(Cont. b) THEN ..) FUNCTION calls Examples x <= conv_integer(a).

ARCHITECTURE behavioral OF powerOfFour IS ENTITY powerOfFour IS PORT( X : IN INTEGER. BEGIN FOR i IN 1 TO Exp LOOP Result := Result * N. Exp : INTEGER) RETURN INTEGER IS VARIABLE Result : INTEGER := 1.std_logic_1164.all. END LOOP. BEGIN Y <= Pow(X. USE IEEE. . 4). END behavioral. END powerOfFour. FUNCTION Pow ( SIGNAL N: INTEGER. RETURN( Result ). Y : OUT INTEGER ).) Example LIBRARY IEEE.FUNCTIONs(Cont. END Pow.

FUNCTIONs(Cont.std_logic_1164. Exp : INTEGER) RETURN INTEGER. PACKAGE specialFunctions IS FUNCTION Pow( SIGNAL N: INTEGER.all.) Example: PACKAGE containing a FUNCTION LIBRARY IEEE. END specialFunctions . USE IEEE.

) PACKAGE BODY specialFunctions IS FUNCTION Pow (SIGNAL N: INTEGER. RETURN( Result ). END LOOP. END Pow.FUNCTIONs(Cont. BEGIN FOR i IN 1 TO Exp LOOP Result := Result * N. END specialFunctions .) Example: PACKAGE containing a FUNCTION(Cont. Exp : INTEGER) RETURN INTEGER IS VARIABLE Result : INTEGER := 1.

USE ieee. END my_package.std_logic_1164. -------------------------------------------------------------------------------------PACKAGE my_package IS FUNCTION conv_integer ( SIGNAL vector: STD_LOGIC_VECTOR) RETURN INTEGER.FUNCTIONs(Cont. .) Example: Type conversion FUNCTION LIBRARY ieee.all.

END IF. .) Example: Type conversion FUNCTION(Cont. IF (vector(i) = ‘1’ THEN result := result+1.) PACKAGE BODY my_package IS FUNCTION conv_integer (SIGNAL vector: STD_LOGIC_VECTOR) RETURN INTEGER. ELSE result := 0. VARIABLE result: INTEGER RANGE 0 TO 2**vector’LENGTH . RETURN result. FOR i IN (vector’HIGH-1) DOWNTO (vector’LOW) LOOP result := result*2. END my_package.FUNCTIONs(Cont. BEGIN IF (vector(vector’HIGH)=‘1’ THEN result:=1. VARIABLE carry: STD_LOGIC. END conv_integer.1.

y: OUT INTEGER RANGE 0 TO 15).all. END my_arch.) LIBRARY ieee.FUNCTIONs(Cont.all. ---------------------------------------------------------ARCHITECTURE my_arch OF conv_int2 IS BEGIN y <= conv_integer(a).my_package.std_logic_1164. ---------------------------------------------------------ENTITY conv_int2 IS PORT ( a: IN STD_LOGIC_VECTOR (0 TO 3). USE ieee. USE work. END conv_int2.) Example: Type conversion FUNCTION(Cont. .

signals (including ports). and TO/DOWNTO for STD_LOGIC_VECTOR)  Procedure calls are statements on their own . OUT. the default for inputs (mode in) is a constant. and variables.PROCEDUREs  PROCEDUREs do not return a value  PROCEDUREs are called using formal and actual parameters the same way as components  PROCEDUREs may modify parameters passed to them  Each parameter must have a mode: IN. the default for outputs (modes out and inout) is a variable  When passing parameters. range specification should be included (for example RANGE for INTEGERS. INOUT  Parameters can be constants (including generics).

PROCEDUREs(Cont.) PROCEDURE syntax PROCEDURE procedure_name (<parameter_list>)IS [declarations] BEGIN (sequential statements) END procedure_name. .

c: IN BIT. SIGNAL y : INOUT INTEGER RANGE 0 TO 99) IS BEGIN (sequantial statements) END my_procedure. SIGNAL b.) Examples: PROCEDURE parameters PROCEDURE my_procedure ( a : IN BIT. . SIGNAL x : OUT BIT_VECTOR(7 DOWNTO 0).PROCEDUREs(Cont.

IF (a > b) THEN compute_min_max(in1. divide(dividend. out2). out1. .. . in2.. out2). in3. quotient. divisor. remainder). out1.PROCEDUREs(Cont. in2..) Examples: PROCEDURE calls compute_min_max(in1.. in3...

std_logic_1164. min_out. PORT ( ena : IN BIT. max_out: OUT INTEGER RANGE 0 TO limit ). . inp1. END min_max. USE ieee.PROCEDUREs(Cont. inp2 : IN INTEGER RANGE 0 TO limit.) Example LIBRARY ieee. ENTITY min_max IS GENERIC (limit: INTEGER := 255).all.

PROCEDUREs(Cont.) Example(Cont.)
ARCHITECTURE my_architecture OF min_max IS PROCEDURE sort (SIGNAL in1, in2: IN INTEGER RANGE 0 TO limit; SIGNAL min, max: OUT INTEGER RANGE 0 TO limit) IS BEGIN

IF (in1 > in2) THEN max <= in1; min <= in2; ELSE max <= in2; min <= in1; END IF; END sort;
BEGIN PROCESS (ena) BEGIN IF (ena=‘1’) THEN sort (inp1, inp2, min_out, max_out); END IF; END PROCESS; END my_architecture;

Operator as a FUNCTION
LIBRARY ieee; USE ieee.std_logic_1164.al; ---------------------------------------------------------PACKAGE my_package IS FUNCTION "+" (a, b: STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR; END my_package;

Operator as a FUNCTION(Cont.)
PACKAGE BODY my_package IS FUNCTION "+" (a, b: STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR; VARIABLE result: STD_LOGIC_VECTOR; VARIABLE carry: STD_LOGIC; BEGIN carry := ‘0’; FOR i IN a’REVERSE_RANGE LOOP result(i) := a(i) XOR b(i) XOR carry; carry := (a(i) AND b(i)) OR (a(i) AND carry) OR (b(i) AND carry)); END LOOP; RETURN result; END "+" ; END my_package;

Operator overloading
 Operator overloading allows different argument types for a given operation (function)  The VHDL tools resolve which of these functions to select based on the types of the inputs  This selection is transparent to the user as long as the function has been defined for the given argument types.

. FUNCTION “+” ( L: STD_LOGIC_VECTOR. R: STD_LOGIC) RETURN STD_LOGIC_VECTOR. FUNCTION “+” ( L: STD_LOGIC_VECTOR.Operator overloading(Cont.) Example FUNCTION “+” ( L: STD_LOGIC_VECTOR. R: STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR. R: integer) RETURN STD_LOGIC_VECTOR.

.Operator overloading(Cont. You can use count <= count + “0000_0001”. or count <= count + ‘1’. or count <= count + 1.) Examples SIGNAL count: STD_LOGIC_VECTOR (7 DOWNTO 0).

Read about  Array attributes  Records  Physical data types .

partition them well  Separate designs on functional boundary  Keep block sizes to a reasonable size .Recommended rules for Synthesis  When implementing combinational paths do not have hierarchy  Register all outputs  Do not implement glue logic between blocks.

) Avoid hierarchical combinational blocks Block A Combinatorial Logic1 Block B Combinatorial Logic2 Block C Combinatorial Logic3 reg1 reg2 Not recommended Design Practice  The path between reg1 and reg2 is divided between three different block  Due to hierarchical boundaries. optimization of the combinational logic cannot be achieved .Recommended rules for Synthesis(Cont.

Recommended rules for Synthesis(Cont.) Recommend way to handle Combinational Paths Block A reg1 Block C Combinatorial Logic1 & Logic2& Logic3 reg2 Recommended practice  All the combinational circuitry is grouped in the same block that has its output connected the destination flip flop  It allows the optimal minimization of the combinational logic during synthesis  Allows simplified description of the timing interface .

.) Register all outputs Block X reg1 Block Y Block Y reg2 reg3 Register all outputs  Simplifies the synthesis design environment: Inputs to the individual block arrive within the same relative delay (caused by wire delays)  Don’t really need to specify output requirements since paths starts at flip flop outputs.Recommended rules for Synthesis(Cont.

and a bug found that can be simply be fixed by adding some simple glue logic. RESIST THE TEMPTATION!!!  At this level in the hierarchy. . no matter what the temptation  Due to time pressures. this implementation will not allow the glue logic to be absorbed within any lower level block.Recommended rules for Synthesis(Cont.) NO glue logic between blocks Top Block X reg1 reg3 Block Y No Glue Logic between Blocks.

hence will have different optimization constraints reg3 may be driven by slow logic. hence no need to constrain it for speed Slow Logic reg3 .Recommended rules for Synthesis(Cont.) Separate design with different goals Top Time reg1 critical path reg1 may be driven by time critical function.

Recommended rules for Synthesis(Cont.) Top Optimization based on design requirements Time reg1 critical path Speed optimized block  Use different entities to partition design blocks  Allows different constraints during synthesis to optimize for area or speed or both. Area optimized block Slow Logic reg3 .

Recommended rules for Synthesis(Cont.) Separate FSM with random logic Top Use FSM optimization tool  Separation of the FSM and the random logic allows you to use FSM optimized synthesis FSM reg1 Standard optimization techniques used Random Logic reg3 .

) Maintain a reasonable block size  Larger the blocks. .Recommended rules for Synthesis(Cont. longer the run time -> quick iterations cannot be done.

thanks digital design .