Verilog interview Questions & answers

Verilog interview Questions & answers for FPGA & ASIC.
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Verilog gate level expected questions.

1) Tell something about why we do gate level simulations?

a. Since scan and other test structures are added during and after synthesis, they are not checked by the rtl simulations and therefore need to be verified by gate level simulation. b. Static timing analysis tools do not check asynchronous interfaces, so gate level simulation is required to look at the timing of these interfaces. c. Careless wildcards in the static timing constraints set false path or mutlicycle path constraints where they don't belong. d. Design changes, typos, or misunderstanding of the design can lead to incorrect false paths or multicycle paths in the static timing constraints. e. Using create_clock instead of create_generated_clock leads to incorrect static timing between clock domains. f. Gate level simulation can be used to collect switching factor data for power estimation. g. X's in RTL simulation can be optimistic or pessimistic. The best way to verify that the design does not have any unintended dependence on initial conditions is to run gate level simulation.
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Verilog interview Questions & answers

f. It's a nice "warm fuzzy" that the design has been implemented correctly.

2) Say if I perform Formal Verification say Logical Equivalence across Gatelevel netlists(Synthesis and post routed netlist). Do you still see a reason behind GLS.?

If we have verified the Synthesized netlist functionality is correct when compared to RTL and when we compare the Synthesized netlist versus Post route netlist logical Equivalence then I think we may not require GLS after P & R. But how do we ensure on Timing . To my knowledge Formal Verification Logical Equivalence Check does not perform Timing checks and dont ensure that the design will work on the operating frequency , so still I would go for GLS after post route database.

3)An AND gate and OR gate are given inputs X & 1 , what is expected output? AND Gate output will be X OR Gate output will be 1.

4) What is difference between NMOS & RNMOS? RNMOS is resistive nmos that is in simulation strength will decrease by one unit , please refer to below Diagram.

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To add further detail. Parameters that can be modelled are T_rise. each of the three values can have minimum. typical and maximum values file:///C|/Users/sumit/Desktop/verilog_interview_questions4. T_fall and T_turnoff.htm (3 of 23)2/18/2011 11:00:35 AM .Verilog interview Questions & answers 4) Tell something about modeling delays in verilog? Verilog can model delay types within its specification for gates and buffers.

typ and max. t_fall_min:t_fall_typ:t_fall_max. t_rise = t_fall = t_off = 3. typ and max for both delay types. and #(3) gate1 (out1. 4:5:6) gate1 (out1. the first value represents the rise time. the first value represents t_rise. Here. When only 1 delay is specified. in2). then all 3 MUST be scpecified.3) gate2 (out2. in4). When two delays are specified.3) gate3 (out3. typ and max values The general syntax for min. gate_type #(t_rise. in3. in4). t_fall and t_off Delay modelling syntax follows a specific discipline. the value is used to represent all of the delay types. in5). Similar rules apply for th especifying order as above. This shows all values necessary for rise and fall times and gives values for min. certain rules are followed. and #(1:2:3. in3.htm (4 of 23)2/18/2011 11:00:35 AM . 5) With a specify block how to defining pin-to-pin delays for the module ? file:///C|/Users/sumit/Desktop/verilog_interview_questions4. An example of specifying two delays. the second value represents t_fall and the last value the turn off time. It is incorrect to specify two values as the compiler does not know which of the parameters the value represents. t_fall. Another acceptable alternative would be.2.B. 5) gate2 (out2. If only one t_rise value is specified then this value is applied to min. the second value represents the fall time. or #(6:3:9. T_off is only applicable to tri-state logic devices. However. Turn off time is presumed to be 0.e.Verilog interview Questions & answers T_rise. or #(2. 5 represents min. N. in2). enable. When three delays are specified. in1. t_off_min:t_off_typ:t_off_max) gate_name (paramteters). it does not apply to primitive logic gates because they cannot be turned off. If specifying more than one number. buf #(1. typ and max delay modelling is. i. in1. typ and max for the fall time. Min. gate_type #(t_rise_min:t_ris_typ:t_rise_max. t_off) gate_name (paramters). When specifiying the delays it is not necessary to have all of the delay values specified. in this example.

htm (5 of 23)2/18/2011 11:00:35 AM . b. e. b. f ). c. a. // delay from a to q ( b => q ) = 7. c. // delay form c to q ( d => q ) = 6. d. // delay from b to q ( c => q ) = 7. // specify block containing delay statements specify ( a => q ) = 6. wire e. output q. c. endmodule module A( q. d ) input a. output q. a. exor ex1( q. // delay from d to q endspecify // module definition or o1( e. b. b ). c. or o2( f. a. file:///C|/Users/sumit/Desktop/verilog_interview_questions4. f. b. d. d ) input a. c. d ).Verilog interview Questions & answers module A( q.

// specify block containing full connection statements specify ( a. or any bit-select or part-select of these. e. b. locally defined registers or nets. logical. a. c *> q ) = 7. a. d ). endmodule 6) What are conditional path delays? Conditional path delays.Verilog interview Questions & answers wire e. The operands can be scalar or vector module input or inout ports. are used to model delays which are dependent on the values of the signals in the circuit. wire e.htm (6 of 23)2/18/2011 11:00:35 AM . sometimes called state dependent path delays. endspecify // module definition or o1( e. or o2( f. concatenation. b ). f. input a. f. b. d *> q ) = 6. output q. c. // specify block with conditional timing statements file:///C|/Users/sumit/Desktop/verilog_interview_questions4. f ). This type of delay is expressed with an if conditional statement. The else construct cannot be used. or reduction operator. conditional. ( b. c. c. d ). exor ex1( q. d. // delay from a and d to q // delay from b and c to q //Conditional path delays Module A( q. The conditional statement can contain any bitwise. compile time constants (constant numbers or specify block parameters).

if ( ~( b & c )) ( b => q ) = 9. or o2( f. endmodule 6) Tell something about Rise.Verilog interview Questions & answers specify // different timing set by level of input a if (a) ( a => q ) = 12. endspecify or o1( e. three. f ). file:///C|/Users/sumit/Desktop/verilog_interview_questions4. b ). a. // using the concatenation operator and full connections if ( {c. fall. e. d *> q ) = 12. two. six. exor ex1( q. fall. if ~(a) ( a => q ) = 14. c. and turn-off delay values. d} != 2'b10 ) ( c. One. d *> q ) = 15. and turn-off delays? Timing delays between pins can be expressed in greater detail by specifying rise. // delay conditional on b and c // if b & c is true then delay is 7 else delay is 9 if ( b & c ) ( b => q ) = 7. or twelve delay values can be specified for any path. d ). d} = 2'b10 ) ( c.htm (7 of 23)2/18/2011 11:00:35 AM . The order in which the delay values are specified must be strictly followed. if ( {c.

tzx = 9. fall for 1-0. t1z = 12. 1-0. tz0 = 13. z-1. tz1 = 11. specparam t0x = 11. txz = 8. tzx ). x-1. fall. tz0 ). t1x = 12. z-0 // strictly in that order specparam t01 = 8. tx0 = 10. and z-0. z-0. ( a => q ) = ( rise. tz0. fall ). toff ). t10 = 9. tx1 = 14. // Six delays specifies transitions 0-1. toff = 8. tx1. // Twelve delays specifies transitions: // 0-1. tx0. t1x. t0z. t0z = 10. t1z. 0-z. ( a => q ) = ( t01. and z-1. t1z = 12. t0z = 10. 0-z. fall = 11. 1-z. and turn-off for 0-z. and 1-z. t0z. t10. fall and turn-off // rise is used for 0-1. 1-z. fall = 11. ( a => q ) = ( t01. t10. x-0. 1-x. ( a => q ) = ( rise.htm (8 of 23)2/18/2011 11:00:35 AM .Verilog interview Questions & answers // One delay used for all transitions specparam delay = 15. 1-0. // Three delays gives rise. ( a => q ) = delay. tz1. tz1 = 11. z-1. 7)Tell me about In verilog delay modeling? file:///C|/Users/sumit/Desktop/verilog_interview_questions4. tz0 = 13. tz1. t1z. x-z. t10 = 9. specparam rise = 10. 0-x. // Two delays gives rise and fall times specparam rise = 10. z-x // again strictly in that order specparam t01 = 8. txz. t0x.

each of the or-gates in the circuit above has a delay assigned to it: • gate 1 has a delay of 4 • gate 2 has a delay of 6 file:///C|/Users/sumit/Desktop/verilog_interview_questions4. An example circuit is shown below.htm (9 of 23)2/18/2011 11:00:35 AM .Verilog interview Questions & answers Distributed Delay Distributed delay is delay assigned to each gate in a module. Figure 1: Distributed delay As can be seen from Figure 1.

c. b. a. for example for gate 1.) The above or_circ modules results in delays of (4+3) = 7 and (6+3) = 9 for the 4 connections part from the input to the output of the circuit. a. c. wire e. is delayed by 4 from the inputs a and b. assign #6 e = c & d. A delay of 4 is assigned to the or-gate. output out. or #6 a2 (f. e. b. Lumped Delay file:///C|/Users/sumit/Desktop/verilog_interview_questions4. b). The module explaining Figure 1 can be of two forms: 1) Module or_circ (out.htm (10 of 23)2/18/2011 11:00:35 AM . c. This means that the output of the gate. f. or #3 a3 (out. endmodule 2) Module or_circ (out. //Delay distributed to each gate or #4 a1 (e. b). b. This means that the assign statement does not contain any modules with port connections. The gate function and delay. d. e. endmodule Version 1 models the circuit by assigning delay values to individual gates. the output of the gate changes after the delay value specified. wire e. c. can be described in the following manner: or #4 a1 (e. d). (An assign statement allows us to describe a combinational logic function without regard to its actual structural implementation. input a. f).Verilog interview Questions & answers • gate 3 has a delay of 3 When the input of any gate change. //Delay distributed to each expression assign #4 e = a & b. a. d). output out. assign #3 e = e & f. while version 2 use delay values in individual assign statements. input a. b. a. d. f. d). c.

gate 3 has got a delay of 9. but with the sum delay of the longest path assigned to the output gate: (delay of gate 2 + delay of gate 3) = 9. a. When the input of this gate changes. e. is very similar to the one for distributed delay. c. Figure 2: Lumped delay As can be seen from Figure 2. input a. b. f). f. or a2 (f. The difference is that only or . the output of the gate changes after the delay value specified. c. The program corresponding to Figure 2. This figure is similar as the figure of the distributed delay.htm (11 of 23)2/18/2011 11:00:35 AM . b. b). The cumulative delay of all paths is lumped at one location. or a1 (e.Verilog interview Questions & answers Lumped delay is delay assigned as a single delay in each module. d). c.gate 3 has got a delay assigned to it: 1) Module or_circ (out. a. d). d. file:///C|/Users/sumit/Desktop/verilog_interview_questions4. //delay only on the output gate endmodule This model can be used if delay between different inputs is not required. The figure below is an example of lumped delay. wire e. or #9 a3 (out. output out. mostly to the output gate of the module.

c. input a. wire e. delay = 7 path c .to Pin Delay Pin .e . d. delay = 9 Figure 3: Pin .e .f .out. f. delay = 9 path d . file:///C|/Users/sumit/Desktop/verilog_interview_questions4. path a .out. output out. The module for the above circuit is shown beneath: Module or_circ (out. d).Pin delay. c. b.htm (12 of 23)2/18/2011 11:00:35 AM . The same example circuit as for the distributed and lumped delay model is used. b. This means that the sum delay from each input to each output is the same. a.to .out. delay = 7 path b . is delay assigned to paths from each input to each output. //Blocks specified with path delay specify (a => out) = 7.out.Verilog interview Questions & answers Pin .f . An example circuit is shown below. also called path delay.to Pin delay The total delay from each input to each output is given.

the setup time is the minimum allowed time between a change in the input d and a positive clock edge. In the example. or a2(f. discusses some of the various system tasks that exist for the purposes of timing checks. a. (d => out) = 9. and are especially important in the simulation of high-speed sequential circuits such as microprocessors. is written as (a => out) = delay. (c => out) = 9. as seen from the example above. Verilog contains many timing-check system tasks. Similarly.Pin delays for standard parts can be found from data books. the program speed will increase. rather than the internals of the module. e. needs to know only the input / output pins of the module.pin delay can be easier to model than distributed delay. this is the time between a negative transition and the transition back to 1.to . the final part of the delay modeling chapter. or a3(out. For larger circuits. $hold and $width. An example of delay from the input. where delay sets the delay between the two ports. out. endspecify //gate calculations or a1(e. The path delays for digital circuits can be found through different simulation programs.htm (13 of 23)2/18/2011 11:00:35 AM . b). Keywords: $setup. the hold time is the minimum allowed time between a positive clock edge and a change in the input d. but only the three most common tasks are discussed here: $setup. 8) Tell something about delay modeling timing checks? Delay Modeling: Timing Checks. file:///C|/Users/sumit/Desktop/verilog_interview_questions4. c. All timing checks must be contained within specify blocks as shown in the example below. to the output. f).to . the pin . The $setup and $hold tasks are used to monitor the setup and hold constraints during the simulation of a sequential circuit element. endmodule Path delays of a module are specified incide a specify block. a. d). $hold. The $width task is used to check the minimum width of a positive or negative-going pulse. The gate calculations are done after the path delays are defined. Pin . Timing checks are used to verify that timing constraints are upheld. $width This section. for instance SPICE. In the example. By using the path delay model. This is because the designer writing delay models.Verilog interview Questions & answers (b => out) = 7.

htm (14 of 23)2/18/2011 11:00:35 AM . data_change. reference: signal used as reference data_change: signal that is checked against the reference time_limit: minimum time required between the two events. time_limit). $setup(data_change. data_change: signal that is checked against the reference reference: signal used as reference time_limit: minimum time required between the two events.Verilog interview Questions & answers Syntax: NB: data_change.Tdata_change < time_limit. $hold(reference. Violation if: Treference . file:///C|/Users/sumit/Desktop/verilog_interview_questions4. reference and reference1 must be declared wires. time_limit). reference.

Treference < time_limit $width(reference1. time_limit).htm (15 of 23)2/18/2011 11:00:35 AM . reference1: first transition of signal time_limit: minimum time required between transition1 and transition2. d. always @(posedge clk) q = d. output q. input clk. d). clk.Treference1 < time_limit Example: module d_type(q. file:///C|/Users/sumit/Desktop/verilog_interview_questions4.Verilog interview Questions & answers Violation if: Tdata_change . Violation if: Treference2 . endmodule // d_type module stimulus. reg q.

wire q. assign clk2=clk." %b %b %b". d. assign d2=d. clk.Verilog interview Questions & answers reg clk. #1 d=1. #7 d=0. clk. d=1. clk=0. #5 d=1. d_type dt_test(q. // causes hold violation #2 d=0. q).htm (16 of 23)2/18/2011 11:00:35 AM . initial begin $display ("\t\t clock d q"). d). $display ($time. #7 d=1. // causes width violation file:///C|/Users/sumit/Desktop/verilog_interview_questions4. d2. // causes setup violation #3 d=0. d. clk2.

2).Verilog interview Questions & answers end // initial begin initial #26 $finish. always #1 $display ($time. 2)." %b %b %b". clk. d. specify $setup(d2. always #3 clk = ~clk.htm (17 of 23)2/18/2011 11:00:35 AM . endspecify endmodule // stimulus Output: clock d q 0 x xx file:///C|/Users/sumit/Desktop/verilog_interview_questions4. $width(negedge d2. q). d2. posedge clk2. $hold(posedge clk2. 2).

46: Timing violation in stimulus $setup( d2:14.htm (18 of 23)2/18/2011 11:00:35 AM .Verilog interview Questions & answers 1 0 1x 2 0 1x 3 1 1x 4 1 11 5 1 11 6 0 11 7 0 01 8 0 01 9 1 01 10 1 0 0 11 1 0 0 12 0 0 0 13 0 0 0 14 0 1 0 15 1 1 0 "timechecks. 16 1 1 1 17 1 0 1 file:///C|/Users/sumit/Desktop/verilog_interview_questions4. posedge clk2:15. 2 ).v".

9) Draw a 2:1 mux using switches and verilog code for it? 1-bit 2-1 Multiplexer file:///C|/Users/sumit/Desktop/verilog_interview_questions4. d2:22.Verilog interview Questions & answers 18 0 0 1 19 0 0 1 20 0 0 1 21 1 0 1 22 1 1 0 "timechecks. 2 ). : 25.v". 23 1 1 0 24 0 0 0 25 0 1 0 "timechecks. 48: Timing violation in stimulus $width( negedge d2:24. 2 ).htm (19 of 23)2/18/2011 11:00:35 AM . 47: Timing violation in stimulus $hold( posedge clk2:21.v".

out=in1. ctrl=1. input ctrl.htm (20 of 23)2/18/2011 11:00:35 AM . output out. out=in2 module mux21_sw (out. ctrl. in1. // mux output // mux inputs // internal wire file:///C|/Users/sumit/Desktop/verilog_interview_questions4.Verilog interview Questions & answers This circuit assigns the output out to either inputs in1 or in2 depending on the low or high values of ctrl respectively. // Switch-level description of a 1-bit 2-1 multiplexer // ctrl=0. in2. in1. wire w. in2).

Again. which is instantiated from the previously defined module. 10)What are the synthesizable gate level constructs? The above table gives all the gate level constructs of only the constructs in first two columns are synthesizable.[nmosgate]. file:///C|/Users/sumit/Desktop/verilog_interview_questions4. endmodule An inverter is required in the multiplexer circuit.Verilog interview Questions & answers inv_sw I1 (w. // instantiate cmos switches cmos C2 (out. ctrl.htm (21 of 23)2/18/2011 11:00:35 AM . in the format cmos [instancename]([output]. in1. w. the instance name is optional. w). // instantiate inverter module cmos C1 (out. are implemented with the cmos statement. of instance names C1 and C2. ctrl). Two transmission gates. in2.[pmosgate]). ctrl).[input].

Verilog interview Questions & answers VLSI & ASIC Digital design interview questions Verilog FAQ Synthesis FAQ Digital FAQ Timing FAQ ASIC FAQ Cmos FAQ Misc FAQ Home file:///C|/Users/sumit/Desktop/verilog_interview_questions4.htm (22 of 23)2/18/2011 11:00:35 AM .

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