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V L S I T R A I N E R S

Pr o d u c t C a t a l o g u e

V i M i c r o s y s t e m s P v t . L t d . ,
P l o t N o : 7 5 , E l e c t r o n i c s E s t a t e , P e r u n g u d i , C h e n n a i 6 0 0 0 9 6 P h : 9 1 4 4 2 4 9 6 1 8 4 2 , 2 4 9 6 1 8 5 2 , F a x : 9 1 4 4 2 4 9 6 1 5 3 6 E Ma i l : s a l e s @v i m i c r o s y s t e m s . c o m , We b : w w w . v i m i c r o s y s t e m s . c o m

X i l i n x S p a r t a n3 EF P GAT r a i n e r K i t : ( V S KS p a r t a n3 E )

F E A T UR E S
*X i l i n x X C 3 S 5 0 0 E F T 2 5 6S p a r t a n3 EF P GA *5 0 0 Kg a t e s &1 0 , 4 7 6L o g i c c e l l s *1 6N o s o f d i g i t a l i n p u t s u s i n g s l i d e s w i t c h e s *1 6N o s o f d i g i t a l o u t p u t s u s i n g d i s c r e t e L E D s *On e R e s e t s w i t c h *F P GAc o n f i g u r a t i o nt h r o u g h #J T A Gp o r t #S l a v e s e r i a l #On b o a r dF l a s hP r o mX C F 0 4 S *S u p p o r t f o r x i l i n x P a r a l l e l c a b l e I V *C a s h e wj a c k e t f o r 5 Vp o w e r s u p p l y *T o t a l 1 9 0I / Op i n s : 8 0p i n s u s e df o r i n t e g r a t i n g p e r i p h e r a l s l i k e L E D s , s w i t c h e s e t c . , b a l a n c e 1 1 0p i n s a v a i l a b l e t ou s e r *3N o s o f 2 0p i nh e a d e r t oi n t e r f a c e V L S I b a s e de x p e r i me n t mo d u l e s ( 3 . 3 Vc o mp a t i b l e ) . *1N oo f 2 6p i nh e a d e r t oi n t e r f a c e V L I Mc a r d s l i k e T r a f f i c L i g h t C o n t r o l l e r ( 5 Vc o mp a t i b l e ) *Onb o a r dp r o g r a mma b l e P L Lo s c i l l a t o r f r o m3 MHz t o2 0 0MHz *6N o s o f 7s e g me n t L E Dd i s p l a y ( t od i s p l a y Hr , Mi n , S e c o f R T CV HD Li mp l e me n t a t i o n ) *2N o s o f 1 0 0p i nh e a d e r w i t h1 1 0I / Op i n s t e r mi n a t i o n s p r o v i d e dt op l u g i nd a u g h t e r b o a r d s . *Ho u s e di na s l e e kp l a s t i c c a b i n e t w i t hb u i l t i nS MP S5 V / 2 A .

A d d i t i o n a l A d d o nF e a t u r e s [ V V S I 2 9 ]
*He a d e r p r o v i d e di nV S K S p a r t a n3 Et oi n t e r f a c e t h e f o l l o w i n g #1 6 2L C Di n t e r f a c e . # 4 4ma t r i x k e y b o a r d . #R e l a y i n t e r f a c e . #S t e p p e r mo t o r i n t e r f a c e . #A D C& D A Ci n t e r f a c e . 2A D C s o f 3MS P Se a c h , 1 2b i t r e s o l u t i o n A n t i a l i a s i n g f i l t e r s a t A D Ci n p u t 8C h a n n e l , 1 2B i t D A C s R e c o n s t r u c t i o nf i l t e r s a t t h e D A Co u t p u t #R S 2 3 2/ S P I S e r i a l P o r t #T e mp e r a t u r e s e n s o r i n t e r f a c e # US B2 . 0C o mp l a i n t i n t e r f a c e ( 4 8 0Mb i t s / s e c )

Very Large Scale Integration (VLSI) is the Science of Integrating millions of transistors
on a silicon chip. Now-a-days VLSI finds applications in all aspects of life in Consumer Electronics, Defence, Computers, Communication, Space, Networking etc., High performance FPGA devices from many vendors are available at affordable price. Very high speed transceiver with superior signal integrity, Embedded 32 bit processors, many 18 18 bit multipliers, PLL, Ethernet PHY and many more high end features are built into the latest FPGA devices. This result in usage of FPGA devices extensively in all the latest equipment introduced in the world market. Xilinx, Altera, Actel, Cypress are Device Vendors. Mentor Graphics, Synplicity, Synopsys, Cadence, Aldec etc., are EDA Companies. These are the Back Bone of VLSI Designs. We have introduced many basic VLSI Trainers, Universal VLSI trainer, Advanced FPGA kits. Evaluation Boards, Experiment Boards, Software IPs, so that the students and the beginners in the VLSI field can set maximum exposure. We have developed many software IPs like 8255, 8279, 8253 and many more, which are made to be available to students, so that they can study the VHDL codes, modify the code and add additional features to these IPs . For example, the student can study 8255 code and add a 16 bit timer. We have developed many software IPs simulation boards for providing the IPs which will be useful for understanding these software IPs codes.

VLSI TRAINER KITS


1. UNIVERSAL FPGA / CPLD TRAINER KIT [VVSM-06] A. Xilinx FPGA Piggy back boards i. ii. iii. iv Spartan 3 Piggy back board (VVSP - 02) Spartan 3E Piggy back board (VVSP-14) Xilinx Virtex II Piggy back board (VVSP - 03) Xilinx Virtex II Pro Piggy back board (VVSP - 05)

B. Xilinx CPLD Piggy back board i Cool runner II CPLD piggy back board (VVSP - 08) C. Altera Based Piggy back boards i. Altera Max II CPLD Piggy back board (VVSP - 10) ii. Altera Cyclone FPGA Piggy back board (VVSP - 07) iii. Altera Stratix II FPGA Piggy back board (VVSP-13) D. Actel proasic plus piggy back board 2. ADVANCED UNIVERSAL FPGA TRAINER (VVSM - 09) Supported Piggy back boards (Daughter board) i. Virtex 4 (XC4VSX25) Piggy Back Board [VAFP-02] ii. Virtex II Pro (XC2VP20) Piggy Back Board [VAFP-03] iii. Spartan 3 (XC3S5000) Piggy Back Board [VAFP-01] iv. Spartan 3 (XC3S1500) Piggy Back Board [VAFP-04] v. Altera Stratix II Piggy Back Board [VAFP-05] vi. Altera Cyclone II Piggy Back Board [VAFP-06] 3. TMS320C6713 + DUAL FPGA BOARD 4. Xilinx BASED STANDALONE TRAINER KITS i. Cool Runner Development kit (VVSM-05) ii. Spartan 3 FPGA main board (VVSM-07) iii. Xilinx Spartan 3E FPGA Trainer Kit : (VSK-Spartan 3E) 5. ALTERA FPGA STANDALONE TRAINER KIT i. Cyclone FPGA Trainer [VVSM-04] 6. COST EFFECTIVE FPGA/CPLD TRAINER i. Spartan 3E Project Card [VPTB-05] 3

7. WIRELESS TRANSMISSION i. EmbeddedBlue eb505-SER OEM Bluetooth trainer ii. ZigBee-ready RF Transceiver iii. 2.4 GHz RF Wireless Module 8. ARM 7 + FPGA + MULTI FUNCTION CARD 9. PLD TRAINER [VSTM-04] 10. EXPERIMENT MODULES 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. 19. 20. 21. 22. Switches Module [VVSI -01] LEDs Module [VVSI-02] 7 Segment LED Display Module [VVSI-04] SRAM Module [VVSI-05] Logic Gates Module [VVSI-10] Modulo - N Synch / Asynch Up / Down Counter Module [VVSI-11] Multiplexer / Demultiplexer Module [VVSI-12] ALU Module [VVSI-13] Digital Clock Module [VVSI-14] ADC & DAC Interface Module [VVSI-15] I/O Card Module [VVSI-16] 18 Keys, 6 Digit 7 Segment Display Module [VVSI-18] Data Acquisition Module [VVSI-23] SDRAM Module [VVSI-26] Stepper Motor, DC Motor, Temperature and Relay Card [VVSI - 25] Flash Memory Interface [VBMB/VIPAC-01] Opto-Isolated I/O Card [VBMB / VVSI-01] Traffic Light Controller [TRAF] AD73322 Based Audio CODEC 5.7" VGA STN Monochrome Display Interface Board [VBMB-VIPAC-04] Add-on Board [ VVSI - 29 ] Memory Interface Board [VVSI-30]

11. VHDL SOFTWARE IP SOFTWARE IP 1. 2. 3. 4. 5. 8255 Software IP Core in VHDL 8279 Software IP Core in VHDL 32 Bit Timer / Counter 8253 Software IP Core in VHDL PWM Generation for Power Electronics Applications HARDWARE REQUIRED 8255 Simulation Module (VVSI-21) 8279 Simulation Module (VVSI-22) VVSM-07, VVSI-01,VVSI-02 8253 Simulation Module VPE-Spartan 3

12. INTERFACING EMBEDDED CONTROLLER CARDS TO FPGA TRAINER 1. Adapter to interface embedded CPU card with FPGA trainer 2. 8051 CPU Card (VPC-51) 3. PIC16F877 CPU Card (VPIC-87X) 4. PHILIPS LPC2148 Evaluation Board 13. POWER ELECTRONICS MODULES 1. FPGA Power Electronics Adapter [VVSI-28] 2. MOSFET Module [VPC-01] 3. IGBT Module [VPC-02] 4. SCR Module [VPC-03] 5. TRIAC Module [VPC-04] 6. AC/DC Source and R-L Load [VPC-05] 7. Power Electronics Application Software [VPL-SOFT 100F] 14. SOFTWARE SOLUTIONS FOR VLSI 1. ISE Foundation 2. System Generator for Simulink 3. Embedded Development Kit (EDK) 4. Chipscope - Pro

1. UNIVERSAL FPGA/CPLD TRAINER [VVSM-06]

The universal VLSI trainer consists of a Main board with many peripheral devices like LED, parallel printer port, VGA port etc. The main board has 4 Nos. of 48 pin Euro connector for plugging in the Daughter boards, which contains the FPGA or CPLD of any manufacturer. UNIVERSAL VLSI MAIN BOARD * * VVSM-06 supports various FPGA / CPLD devices like Xilinx, Altera, Actel etc., Features : # Accomodates any 1.2V, 1.5V, 1.8V, 2.5V, 3.3V and 5.0 V devices # Upto 180 user definable Input/output (I/O) pins available at 10 Nos of 20 Pin Headers # On board PLL circuitry to generate different clock frequencies (User can select by jumpers) # Work upto 100 MHZ Frequency # On board Features: - VGA Interface - PS-2 Keyboard/Mouse Interface - 4 4 Matrix push button keyboard - 20 4 Alpha Numeric LCD display - One 8 bit 8 channel ADC - 8 Bit Two channel DAC - One RS232 Serial port interface, One parallel printer port - 4 Digit 7 Segment LED display - 32 Input DIP Switches & 32 Output LEDs.

Note : Any one of the following Piggy back boards must be purchased to work with the above VVSM-06 Main board 6

A. Xilinx FPGA Piggy back boards:


i. Spartan-3 Piggy back board

iv. Virtex-II pro piggy back board

* * * * *

400K usable gates Devise Used : XC3S400 2MB Flash PROM to configure JTAG Interface facility Compatible with Xilinx ISE Foundation / WebPACK software * * Device used : XC2VP4 One Built in IBM 400 MHZ Power PC Processor 4MB Flash PROM to configure JTAG Interface facility Compatible with Xilinx ISE Foundation / WebPACK Software

ii. Spartan -3E Piggy back board

* * *

B. Xilinx CPLD Piggy back board i Cool runner II CPLD Piggy back board

* * * * *

500K usable gates Device used : XC3S500E 4MB Flash PROM to configure JTAG Interface facility Compatible with Xilinx ISE Foundation / WebPACK software * * * * Device used : XC2C256 6000 system gates, 256 Macro cells JTAG Interface facility Compatible with Xilinx ISE Foundation / WebPACK Software

iii. Virtex-II piggy back board * * * Device used : XC2V250 250k gates Compatible with Xilinx ISE Foundation / WebPACK Software

C. Altera based Piggy back boards


i. Altera Max II CPLD Piggy back board

* * * * * * *

Device Used : EP2S15F484C5 Logical elements : 15,600 DSP Blocks : 12 48 Multipliers Onboard 4 Mbit configuration serial PROM JTAG Interface facility ALTERA QUARTUS II Web edition software compatible

D. ACTEL PROASIC PLUS Piggy back board * * * * * Device Used : EPM1270T144C5ES Logical elements : 1270 JTAG Interface facility Macro cells : 980 ALTERA QUARTUS II Web edition software compatible

ii. Altera Cyclone FPGA Piggy back board * * * * * Device Used : APA300-PQ208 300K Usable gates Flash FPGA Family device JTAG Interface facility Libero IDE design Web edition software compatible

* * * * *

Device Used : EP1C6Q240C8 100K usable gates Onboard 1 Mbit configuration serial PROM JTAG Interface facility ALTERA QUARTUS II Web edition software compatible

Programmer : * Flash Pro Lite Programmer should necessarily be purchased to download the program to Flash FPGA of ACTEL PROASIC PLUS.

iii. Altera Stratix II Piggy back board

2. ADVANCED UNIVERSAL FPGA TRAINER (VVSM - 09)


Refer Page - 30

3. TMS320C6713 + DUAL FPGA BOARD


Many applications require a integrated solution of DSP & FPGA. This board is designed for one Main board with TMS320C6713 DSP Processor and an Add-on board with that dual FPGA devices. Many peripherals like 2 MSPS ADC, 8 channel DAC, USB etc., have been included in the board for various applications 6713 BOARD FEATURES On chip Features * Highest performance floating point DSP operating at 150 MHz * 32 bit EMIF, 16 bit HPI * Two multichannel Audio serial ports (MCASPs) & Buffered serial ports (MCBPs) * 4KB LIP Program cache memory, 4 KB LID data cache memory * 256KB L2 unified cache mapped RAM On-board Features: * 256K 16 bit flash for monitor & 4 Mb 16 bit SDRAM for program & Data memory * One RS232 interface for Host support terminated at 9 pin D male connector * One USB interface for Host support in full speed mode (12mbits/sec) * One 12 bit, 12 channel, 2 MSPS SPI based ADC * One 12 bit, 8 channel, 30 MHz SPI based DAC * One 16 / 20 bit stereo CODEC operating upto 48 KHz. * 16 digital I/O * 2 96 pin Euro connected for fast CODEC, 12/14/16 bit ADC & DAC in serial / parallel communication through VDSP-Link bus & memory expansion (Optional) * Powerful windows based debugger facility DUAL FPGA BOARDS * 1st FPGA Board Features # 16 PWM outputs (Isolated) # 24 Isolated Digital I/Os # 8 Capture Isolated Inputs # 16 Output LEDs * 2nd FPGA with ADC # 16 channel, 12 bit serial ADCs - 4 Nos of AD7266, each has dual 12 bit ADC. - 2 MSPS throughput for each ADC 9

4. XILINX BASED STANDALONE TRAINER KITS


XILINX CPLD STANDALONE TRAINER KIT i. Cool Runner Development Kit [VVSM-05] * * * * * * * * * * * * 128 Macro Cell XCR3128XL Cool Runner Xilinx CPLD. 16 Inputs using dip switches. 16 outputs with LED indication. Two Nos 7 segment display. 20 4 LCD Display. Built-in 1149.9 JTAG interface. User selectable clock frequency [ 1 to 100 MHz]. 4 4 Matrix Keyboard. 25 pin D type connector for printer interface. Two 20 pin connectors provided to interface our Add-on cards. Compatible with Xilinx ISE Foundation / WebPACK Software. Parallel cable is provided for downloading.

XILINX FPGA STANDALONE TRAINER KIT ii. Spartan 3 FPGA Main Board [VVSM - 07]: Device : XC3S400 - 4PQ208. 400K gate Xilinx Spartan 3 device. Upto 137 user I/Os. JTAG and serial mode configuration facility. Can be used with a variety of add-on cards (Switches, LEDs, 7-Segment, SRAM etc). * Onboard Programmable oscillator [ 1 to 100 MHz]. * Termination : All pins are terminated at 8 Nos. of 20 Pin Connector. * Compatible with Xilinx ISE Foundation / WebPACK Software. * Parallel cable is provided for down loading. OPTIONAL: * On board 2MBit flash for configuring the FPGA. * Device used : XCF02SVO20C. iii. Xilinx Spartan 3E FPGA Trainer Kit : (VSK - Spartan 3E) Refer Page - 1 10 * * * * *

5. ALTERA FPGA STANDALONE TRAINER KIT


i. Cyclone FPGA Trainer [VVSM-04] * Device used : EP1C6Q240C8 (Cyclone Family).
* 100K usable gates.

* * *
* *

Upto 180 user I/O Pins. 32 Input switches & 24 output LEDs. 2 Nos. of 7 segment Display.
1 No. of 20 4 LCD Module. 2 Keys for Clock and Reset.

* *

* *

JTAG/Serial Configuration facility. Software : # Altera Quartus II Web edition software compatible. Byteblaster MV cable All 180 I/O pins are either used for on board peripheral interface like switches, LEDs, LCD etc and also terminated at 8 groups of 20 pin header, selectable by jumpers.

Optional * On board 1 Mbit Serial PROM to configure the FPGA. * Byteblaster II cable

6. COST EFFECTIVE FPGA/CPLD TRAINER


i. Spartan 3E Project Card [VPTB-05] * * * *
* *

Xilinx XC3S100E-4TQ144C Spartan 3E FPGA 100k gates & 2,160 logic cells. 108 User I/Os 3 numbers of 20 pin header to interface VLSI based experiment modules.
8 numbers of digital inputs & outputs On board programmable oscillator [3 to 200 MHz]

* * * * * * * * * *

One 16 2 alphanumeric LCD display One RS232 UART 4 Channel, 8 bit, I2C ADC & single channel DAC Onboard variable preset for giving input to 1st ADC. 8 numbers of 5V compatible PWM (Pulse Width Modulation) / Capture One PS/2 keyboard / Mouse Interface Connector Prototyping Area FPGA configuration through JTAG port On board configuration through Xilinx Flash PROM XCF01S. Built in a sleek plastic cabinet with built in SMPS-5V/ 2A

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7. WIRELESS TRANSMISSION
i. EmbeddedBlue eb505-SER OEM Bluetooth trainer Simple serial UART communications and control * Seamless connectivity with any Bluetooth devicetr * Fully embedded solution with no Bluetooth host stack required * Low current consumption for long battery life 2.4GHz FHSS (Frequency Hopping Spread Spectrum) technology ensures high reliability and is robust to interference Standard 0.1 headers for simple prototyping and integration Complete with sample applications and source code. Interface with any of our VLSI Trainers *

* * * *

ii. ZigBee-ready RF Transceiver * True single-chip 2.4 GHz IEEE 802.15.4 compliant RF transceiver with baseband modem and MAC support DSSS baseband modem with 2MChips/s and 250 kbps effective data rate. Digital RSSI / LQI support

* * * * *

* Suitable for both RFD and FFD operation I/Q low-IF receiver & I/Q direct upconversion transmitter 128(RX) + 128(TX) byte data buffering Hardware MAC encryption (AES-128) Interface with any of our VLSI Trainers

iii. 2.4 GHz RF Wireless Module * * * * World wide 2.4 GHz ISM Band Compliance with FCC and CE / BZT requirements High efficient FM -FM Modulation / Demodulation scheme Transmitting and Receiving of wide band video and two audio subcarrier

* *

User specified RF transmitting power upto 100mV Optional user pre-programmed micro

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8. ARM 7 + FPGA + MULTIFUNCTION CARD

ARM 7 + FPGA Board Features * The LPC2292 - based on a 16/32 bit ARM7TDMI-S CPU * 16 kB on-chip Static RAM * 256 kB on-chip Flash Program Memory * 128-bit wide interface/accelerator enables high speed 60 MHz operation * 4 Mbit External Flash RAM * Two interconnected CAN interfaces with advanced acceptance filters * Serial interfaces 1. Two UARTs 2. Fast I2C (400 kbits/s) 3. Two SPIs * Eight channel 10-bit A/D converter with conversion time as low as 2.44 ms * Configurable external memory interface with up to four banks, each up to 16 Mb and 8/16/32 bit data width. * 4 Mbit External SRAM * 9 edge/level sensitive external interrupt pins available. * 10 Mbps Ethernet Interface * 51 I/O Lines of FPGA, Ethernet etc., are terminated at 50 pin connector * Xilinx Spartan 3 Device :XC3S400 # System Gates : 400K # 288 Kbits of total Block RAM # 326 MHz system clock rate # 56 Kbits of total Distributed RAM # 16 Dedicated 18 x 18 multipliers # 4 Digital Clock Manager Multifunction Card Features * One 16 2 LCD & 4 4 Matrix Keyboard * Stepper Motor Interface * 2 ADCs of 3 MSPS each, 14 bit resolution * 4 Channel, 12 Bit DACs * RS232 / SPI Serial Port * Temperature Sensor Interface * USB 2.0 Compliant interface (480 Mbits/Sec) Adapter Card Features
* RJ45 Connector for Ethernet Connectivity * Connector for upto 1 GB SD card / MMC / CF upto 1GB * FPGA lines are terminated at 3 Nos of 20 pin connector integrating with many add-on cards

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9. PLD TRAINER [VSTM-04]


PLD Trainer [VSTM-04] is a complete training and development package for PAL/GAL device. It consists of i) Programming Section ii) Training Section iii) Software * The programming section features a ZIF Socket for easy device insertion and designed for ATMEL FLASH PLDs. The Training section provides a 20 pin ZIF Socket and I/O devices like LED, Swit ches et c. , fo r implement ing t he students reference designs. Software section consist of Atmel Win CUPL compiler, Editor and programming software.

Programmer Supports * * * Atmel ATF16V8B, ATF16V8BQL, ATF16V8C Atmel ATF20V8B Atmel ATF22V10C

Training Board * * * 8 input switches 8 Output LEDs and 7segment LED display Push Button switches are supplied for clock and output enable functions

Operating System * Win 98, Win 2000 , Win ME, Win XP

Experiments * * * * * * * All logic gates D-Type Flip flops, Latches 7 Segment Display Decoder Decade up down counter 7 segment to Hex decoder Multiplexer & Demultiplexer Adder & Subtractor etc.,

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10. EXPERIMENT MODULES


The following experiment boards are designed to be compatible with the CPLD & FPGA Trainer & Development boards through 20 pin headers. 1. Switches Module [VVSI-01]

* * * *

32 DIP switches Easy input to your designs - data settings, control Easy viewable settings Designed to pair up with the LEDs, 7 Segment Displays.

2. LEDs Module [VVSI-02]

* * *

32 Surface mounded red LEDs Invaluable for demonstrating, testing and debugging circuit Designed to pair up with switches (or) 7 segment displays

3. 7 Segment LED Display Module [VVSI-04] * Four high brightness Seven Segment LED Displays * Display data values (Decimal, Hex,...etc) and diagnostic codes * Invaluable for demonstrating, testing and debugging circuits * Designed to pair up with switches, LEDs

4. SRAM Module [VVSI-05]

* * * *

2 Mbits of very fast 15ns static RAM Accessible as 128K x 16 bit, 256K x 8 bit Store and process data streams for any applications Simple Interface, no complex controller - required in the FPGA

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5. Logic Gates Module (VVSI-10) * * * LEDs are provided to see the output status of the experiment All the inputs and outputs are terminated at patch connectors. Drivers are provided to drive the LEDs, Switches are provided for logical input as a high or low with LED indication Using this trainer we can study about the gates like AND, OR, NOT, NAND, NOR, XOR The mimic diagram and the truth table of the gates are shown on the front side of the PCB

* *

6. Modulo-N Synchronous / Asynchronous up / down Counter Module(VVSI-11)

* * * *

Switches are provided to set the starting data for counter with LED indication Outputs of the counter is indicated by LEDs One switch is provided to reset the counter. The mimic diagram and the truth table are shown in the front side of the PCB

7. Multiplexer / Demultiplexer Module (VVSI-12)

* * *

Switches are provided for giving the input to the Multiplexer LEDs are provided to see the output status of the Demultiplexer Using this trainer we can study the logic of Multiplexer/Demultiplexer

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8. ALU Module (VVSI-13) * * Switches are provided for giving input to the ALU unit Using this ALU unit, we can operate the arithmetic operations like Addition, Subtraction, Multiplication and Logic Operations like AND, OR, NOT gates. LEDs are provided to see the output status of the ALU unit One switch is provided to give the input to the ALU unit for selecting Arithmetic or Logic unit

* *

9. Digital Clock Module (VVSI-14)

* * *

6 Digit 7 segment display is provided to see the digital clock Switches are provided to set the time as per our requirement One switch is provided to reset or start the digital clock

10. ADC & DAC Module (VVSI-15) * * * * * * * * * 4 Channel high speed 12 bit ADC (AD7862) LED is connected to the output of ADC Input Voltage Range : 10V, 2.5V Conversion speed : 250KHz Analog Inputs terminated in J801 Connector Single channel 12 bit DAC (AD7392) Output Range : (0-5V) DAC Output is terminated in J801 Connector This board can be interfaced to any one of our FPGA / CPLD trainer through two numbers of 20 pin Header

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11. I/O Card Module (VVSI-16)

* * *

16 nos. of switches are provided to give the inputs with LED indication 16 nos. of LEDs are provided to see the outputs of the data The inputs and outputs are terminated at a patch connector for our usage

12. 18 Keys, 6 Digit 7 Segment Display Module (VVSI-18)

* * *

18 keys keyboard is provided 6 digit 7 segment display is provided to display message and roll the message Keys & 7 Segments are terminated at a connector

13. Data Acquisition Module [VVSI-23]: a. 12 Bit Integrating ADC * 8 Channel single ended Analog voltage inputs (Range : 0-5V) * Dual slope, Ramp type, 7 samples/sec (conversion) * Single channel can be configured as current input (4-20mA) b. 12 Bit DAC : * Single channel Digital to Analog converter using AD7392 * Can be configured as current output (4-20mA) * 12 bit resolution * Output voltage range (0-5V) c. Digital I/O : * 8 digital outputs with edge connector terminations and LED indication * 8 Digital inputs with edge connector terminations with SPDT Switches. 14. SDRAM Module [VVSI-26] * * * * 4MBit very fast Synchronous Dynamic RAM Accessible as 4M 16 bit JEDEC Standard 3.3V power supply All inputs are sampled at the edge of the system clock.

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15. Stepper Motor, DC Motor, Temperature and Relay Card (VVSI - 25) * * This board can be interfaced to any of our FPGA / CPLD trainer through 20-pin header Driver for controlling a stepper motor ranging from 2Kg to 20Kg and provided with 2 Kg Stepper motor with the board One 12V DC motor provided with driver
Provision for connecting Internal or External power supply selectable by jumpers

*
*

* *

Relay driver provided to activate the 12V relay One AD590 Sensor is provided to measure the temperature.

Accessories: * Multi output SMPS +12V, -12V,5V

16. Flash Memory Interface (VBMB/VIPAC - 01)

* * * * *

Compatible for VXT Bus and VVSI-Bus 1Mbit of Uniform sector flash memory Erase, Read and Write operation at 5V 120ns maximum access time Accessible as 128KB X 8 bit

17. Opto-Isolated I/O Card (VBMB/ VVSI-01) * * * * * Compatible for VXT Bus and VVSI-Bus 8 Nos. of Isolated inputs. 8 Nos. of Isolated outputs. Isolated Inputs and outputs are terminated at the J801 connector External Isolation Voltage: Upto 24V DC.

18. Traffic Light Controller (TRAF)

* * * *

Connected to VLSI port 32 LEDs provided to simulate traffic control system Buffers provided for individual LEDs Application : Traffic Light Simulation

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19. AD73322 Based Audio CODEC * * * * Based on AD73322 a general purpose dual & analog front end processor for speech, telephony, vibration etc., Programmable Input/Output sample rate (8 kb, 16kb, 32kb, 64kb) Application like low bit rate high quality compression, speech enhancement, recognition, synthesis etc., are possible. All analog signals are terminated at connectors.

20. 5.7" VGA STN Monochrome Display Interface Board [VBMB-VIPAC-04] * * * This Board consists of Mitsubishi graphic display controller. 15 Pin connector to Interface with Monochrome LCD. Two 20 pin connectors to interface this Board with VLSI Boards.

Controller Details: * The M66271FP from Mitsubishi is a graphic display only controller for Displaying a high duty Dot matric LCD. * Monochrome LCD of upto 76800 dots * Built in 9600-byte (76800 bit) VRAM [equivalent to one screen of 320 240 dotsLCD]. TFT LCD Details: * Hitachi LCD of SP14Q002-A1 is used * Dot number : 320 (W) 240 (H) * LCD Type : 128MB Flash SD LARD * BACK lights : Cold cathode Fluorescent lamp. 21. Add-on Board [VVSI-29] * * * * * * * One 16 2 LCD & 4 4 matrix keyboard Relay & Stepper Motor interface 2 ADCs of 3 MSPS each, 12 bit resolution 4 Channel, 12 Bit DACs RS232 / SPI Serial Port Temperature sensor interface USB 2.0 Compliant interface (480 Mbits/Sec)

22. Memory Interface Board [VVSI-30] * * * * 8MB 16 bit SDRAM 32MB 16 bit DDR SDRAM 128 MB Flash SD CARD 4MB 16 bit Flash Memory.

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11. VHDL SOFTWARE IP


The following hardware IC's VHDL Code (IP) have been developed and made it available to students. The students can modify or add more features to the existing IC features. For example, you can add 16 bit Timer to 8255 core. 1. 8255 Software IP Core in VHDL Overview The C-8255 core is the VHDL model of the Intel 8255 Programmable Peripheral Interface device designed for use in Intel microcomputer systems. It reduces the external logic normally needed to interface peripheral devices. Its function is that of a general purpose I/O component to interface peripheral equipment to the microcomputer system bus. Features * * * Functionally based on the Intel 8255A device Three 8-bit peripheral ports: PA, PB, PC Three programming modes for peripheral ports i. Basic input/output mode. ii. Strobed input/output mode. iii. Bi-Directional bus mode. Total of 24 programmable I/O lines 8-bit bidirectional system data bus with standard microprocessor interface controls Direct bit set/reset capability, easy control application interface.

* * *

RECOMMENDED HARDWARE Simulation of 8255 Module [VVSI-21]. * The add-on board consist of following features # 50 pin header to interface the board with Microprocessor / Microcontroller. # Zip socket is provided to compare & learn the functions of 8255 IC.

Note: * Need any one FPGA Main Board like VVSM-06 with FPGA Piggy Back, VVSM-09, VVSM-07, VVSM-04, VSK-Spartan 3E * Any one our make (Vi Micro) :P or :C Trainer kit should be provided by the institution to conduct the above experiment * 8255 Bit file only supplied at the time of delivery * 8255 IP Core will be sent upon License Agreement with the college

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2. 8279 Software IP Core in VHDL Overview The C-8279 Core is the VHDL model of the Intel 8279 Programmable Keyboard/Display Interface device designed for use with Intel microprocessors. The keyboard portion provides a scanned interface to 64-contact key matrix while the display portion provides an interface for popular display technologies (e.g. LED). Features * Functionally based on the Intel 8279 device * Simultaneous keyboard display operations * Scanned keyboard and sensor modes * Strobed input entry mode * 8-character keyboard FIFO * 2-key lockout or N-key roll over with contact debounce * Dual 8- or 16-numerical display * Single 16-character display RAM * Programmable scan timing and mode * Interrupt output on key entry * Complete simulation of 8279 # Simultaneous keyboard display operations # 8 character FIFO # 2 key lock out or N - key roll over with contact debounce. # 6 Numeric and character display. RECOMMENDED HARDWARE: 8279 Simulation Module [VVSI-22] * * * * * * 50 pin header to interface the board with Microprocessor & Microcontroller. 4 4 matrix keyboard. 6 digit 7 segment LED display. One ZIF socket provision for testing the functions of a Intel 8279 IC. To check the simulation functions the Output downloadable file will be given. Sample source code will be given for keyboard & Display Accessing.

Note: * Need of any one FPGA Main Board like VVSM-06, with FPGA Piggy Backs, VVSM-09, VVSM-07, VVSM-04, VSK-Spartan 3E * Any one of our make (Vi Micro) :P or :C trainer kit should be provided by the institution to conduct the above experiment.

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3. 32 Bit Timer / Counter * * * * * * 6 Channel 32 bit timer / counter Start with a preset value and count Up / Down Capture the 32 bit count value by Software command / Hardware signal Enable or Disable count by Software command / Hardware signal Status register bits is set, when threshold value is reached and counter overflows after reaching ...FFH while counting Up and ..00H while counting down. Clear the content of the Counter by Software / Hardware signal

RECOMMENDED HARDWARE VVSM-07 or VVSM-09 or VVSM-06 and Experiment Board of VVSI-01 & VVSI-02 4. 8253 Software IP Core in VHDL * * * * 3 Channel 16 bit timer/counter Input clock from DC to 2 MHz. Programmable counter modes Count Binary or BCD.

Note 8253 IP Protocol is verified by interfacing with Intel 8051 or Philips 89C51 Microcontroller or any of our VXT bus interface connector. RECOMMENDED HARDWARE 8253 Simulation Board * * * * * * * * * XilinxXC3S500E - FT256 Spartan 3E FPGA 500K gates & 10,476 Logic cells FPGA configuration through JTAG Complete Simulation of 8253 3 Channel Decrement Counter 50 pin header to interface the board with Microprocessor/ Microcontroller One NCNO Switch is provided to give the manual clock. One ZIP Socket provision for testing the functions of a INTEL 8253IC. Sample source code will be given.

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5. PWM Generation for Power Electronics Applications * Implementation of Event Manager Modules(EVA & EVB) consists of - Two General Purpose (GP) Timers. - Three Compare Units, Three Capture Units. - Event Manager Interrupt Logic. - PWM Circuits Speed & Resolution is high Can be interfaced to a powerful 32 bit Embedded controller or a DSP Processor.

* *

RECOMMENDED HARDWARE 1. VPE-SPARTAN 3 FPGA CONTROLLER This board is specially designed for Power Electronics applications, based on the latest FPGA Spartan-3 family, XC3S400-4PQ208 of 400K gates. The board comes with high speed 12-bit ADC & DAC for closed loop control. This will be a useful FPGA development board for Power Electronics & Drives Applications. * 12-Channel, 12 bit serial ADC: # Dual 12 bit ADC using AD7266. # Each ADC offers 6 channel singleended or 3 channel Differential inputs # 2 Channel simultaneous sampling. * 8-Channel, 12-bit serial DAC (AD5328) * PWM, Capture and GPIO lines. # 8 Nos of I/O lines of the FPGA are used as PWM output lines. # 6 Nos of I/O lines of the FPGA are used as 6 capture inputs for interfacing Encoder. # 8 Nos of I/O lines of the FPGA can be used as General- purpose I/O Lines. * I2C based key pad & LCD display. A separate board with, # 4 4 keys keypad for select , Increment, Decrement, Reset functions. # 16 2 alphanumeric LCD Display to select the program as well as to display the firing angle, etc., * Configuration # Slave serial and JTAG Mode # Onboard Serial Flash PROM XCF02S. * Drives Power Module connectivity # One 34 Pin header is provided to terminate PWM output and capture Inputs. # One 26 Pin header is provided for the ADC input signals.

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12. INTERFACING EMBEDDED CONTROLLER CARDS TO FPGA TRAINER


1. Adapter to interface Embedded CPU card with FPGA trainer * * * Used to interface the embedded controller based CPU cards with any of our FPGA trainer If the FPGA trainer is connected to these CPU cards, it will act as VAPC or VIPAC series of add-on cards Students can program FPGA as RTC/8255 / 8279 / 8253 or any other applications and use it as an add-on card to the CPU card.

Note : This board should be purchased to interface the following Embedded Controller Cards 2. 8051 CPU Card (VPC-51) * * * * * * * * 8051 CPU operating at 11.0592 MHz 32KB EPROM & 64KB SRAM for program & data memory RS232/RS485 serial port to interface with PC 4 channel 8 bit serial ADC & 1 channel 8 bit serial DAC 2 Numbers of 50 PIN expansion connectors to interface Memory/IO mapped series of add-on cards RS 232 cable with Downloader software to download programs from PC to target card. 8051 C compiler Example programs in assembly & embedded C with documentation

3. PIC16F877 CPU Card (VPIC-87X) * * Microchip PIC 16F877, 8bit RISC CPU Operating at 20 MHz 8K 14 words on-chip Flash memory

* * * * * * * * *

RS232 serial port to interface with PC 8 Channel 10 bit ADC 2 Channel 10 bit PWM 50 PIN expansion connectors to interface I/O mapped series of add-on cards SPI & I2C serial interface support In system programming facility to download hex code from PC to target card RS232 cable with Downloader software to download programs from PC to target card.

MPLAB Assembler & C compiler Example programs in assembly & embedded C with documentation.

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4. PHILIPS LPC2148 Evaluation Board * * * * * * * Philips LPC 2148 ARM7TDMI core CPU On-chip 512KB ISP flash memory On chip USB, I2C & SPI support On-chip 10 bit ADC & 10 bit DAC 50 PIN expansion connectors to interface I/O mapped series of add-on cards RS232 serial port to interface with PC SPI & I2C serial interface support

* * * *

In system programming facility to download hex code from PC to target card Downloading cable with Downloader software to load programs from PC to target card. ARM C compiler Example programs in assembly & embedded C with documentation

13. POWER ELECTRONICS MODULES


1. POWER ELECTRONICS APPLICATION BOARDS The following power modules can be interfaced to any of our FPGA/CPLD trainers through "FPGA POWER ELECTRONICS ADAPTER". i. FPGA Power Electronics Adapter [VVSI-28] * * 20 pin input connector from FPGA Trainer board 6 output lines ( PWM lines generated by VHDL program) are terminated at screw type connector to interface with various power modules.

ii. MOSFET Module (VPC-01)

* *

One number of IRF840 MOSFET with snubber circuit and heat sink provided for power circuit One number of IR2110 driver IC used as driver with opto isolation

One 2 pin Screw type phoenix connector for MOSFET terminals Drain & source and another 2 pin connector for PWM input from FPGA controller. # PWM input : 0-5V/0-3V level # Power input : 0-24V DC @ 2Amp

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iii. IGBT Module (VPC-02) * One number of IRGBC20S IGBT with snubber circuit & heat sink provided for power circuit * One number of IR2110 driver IC used for IGBT driver with opto isolation. * One 2 Screw type phoenix driver IC used for IGBT terminals Cathode & Emitter and another 2 pin connector for PWM input from FPGA Controller. * PWM input : 0-5V/0-3V level * Power input : 0-24V DC @ 2 Amp iv. SCR Module (VPC-03) * One number of TYN612 SCR with snubber circuit & heat sink provided for power circuit * One number of pulse amplifier circuit with pulse transformer provided for SCR pulse isolation * One 2 pin Screw type phoenix connector for SCR terminals Anode & cathode and another 2 pin connector for SCR pulse input from FPGA Controller. * One number of step down transformer with ZCD circuit provided for supply synchronization and terminated at screw type terminals * PWM input : 0-5 V/0-3V level * Power input : 0-24V AC/DC @ 1A v. TRIAC Module (VPC-04) * One number of BTA12 TRIAC with snubber circuit with heat sink provided for power circuit * One number of pulse amplifier circuit with pulse transformer provided for TRIAC pulse isolation * One 2 pin Screw type phoenix connector for TRIAC terminals MT1 & MT2 and another 2 pin connector for SCR pulse input from FPGA controller. * One number of step down transformer with ZCD circuit provided for supply synchronization and terminated at screw type terminals to FPGA controller. * PWM input : 0-5V/0-3V level * Power input: 0-24V AC,1 Amp vi. AC/DC Source and R-L Load [VPC-05]: * One number of fixed resistor provided for R- load * One number of inductor provided for L-load. * One number of 24V DC,1 Amp supply provided for power circuit input. * One number of 24V AC,1 Amp provided for power circuit input * One number of +15V DC supply provided for control card * Necessary connector provided for supply and load output * Fuse provided for protection 27

vii. Power Electronics Application Software (VPE-SOFT 100F) The application program are written in VHDL language using XILINX-ISE foundation software Sample programs provided for the following experiments. * Single phase SCR AC Voltage Regulator with R-RL load * Single phase TRIAC AC Voltage Regulator with R-RL load * Single phase Half-Fully Controlled Converter with R, RL load * IGBT/MOSFET based Single/Two/Four quadrant chopper with R, RL load * IGBT/MOSFET based single phase sine PWM inverter with RL load * MOSFET based Fly-Back Converter * MOSFET based Buck Converter * MOSFET based Boost Converter * MOSFET based Buck-Boost Converter * Open Loop Speed Control of three phase AC Induction Motor using V/F control (SPWM) * Closed Loop Speed Control of three phase AC induction Motor using V/F control (SPWM)

14. SOFTWARE SOLUTIONS FOR VLSI


1. ISE FOUNDATION The industrys most complete programmable logic design solution for optional performance, power management, cost reduction, and productivity support for all Xilinx leading FPGAs and CPLDs including Virtex-4/5 multi-platform FPGAs.. * Devices : Supports all series * Design Entry : Schematic & HDL Editor, State Diagram Editor, Xilinx Core Generator System, RTL & Technology Viewers, PACE * Synthesis : Xilinx Synthesis Technology * Implementation : Floor Planner, Modular design, PlanAhead [Sold as an Option] Timing Driven Place & Route, Back Annotate, Timing Improvement Wizard & Xplorer * Programming : Impact/system ACE * Verification : ChipScope Pro (Evaluation Package), Graphical Testbench Editor & ChipViewer, ISE Simulator & Xpower (Power Analysis), ModelSim XE III Starter, ModelSim XE III [Sold as an Option] 2. SYSTEM GENERATOR FOR SIMULINK The leading edge, modeling and implementation tool for high performance DSP Systems. System Generator for DSP is fast becoming the preferred framework for developing and debugging high-performance DSP systems using the industrys most advanced FPGAs. KEY FEATURES * Performance - Easily build and generate high-performance DSP Systems. * Embedded system design Build DSP co-processors for the Xilinx MicroBlaze processor * High-bandwidth hardware co-simulation for accelerating simulations. * MATLAB to RTL capabilities. * Mixed-language design - Import HDL modules and co-simulate them using ModelSim. * In-system debugging at system speed. 28

3. EMBEDDED DEVELOPMENT KIT (EDK) Encompassing solution for designing embedded Programmable systems. * Platform Studio Integrated Development Environment * Platform Studio Software Development Kit (SDK) * Embedded Systems Compiler and Debugger Tools * Board Support Package Generation * Processor IP library * MicroBlaze soft processor core license 4. CHIPSCOPE PRO ChipScope Pro delivers in-circuit real-time debug for any signal on the FPGA, streamlining your design debug ChipScope Pro inserts logic analyzer, bus analyzer, and Virtual I/O low-profile software cores directly into your design, allowing you to view any internal signal or node, including embedded hard or soft processors. * Analyze any internal FPGA signal, including embedded processor busses * Built-in software logic analyzer helps identify and debug problems, including advanced triggering, filter, and display options * Verify your FPGA on the board at or near operating speed * Change probe points without re-synthesizing * Using the Pattern Generator & Logic Analyzer features, the FPGA hardware implementation can be verified and debugged very easily. Hence no need for a separate expensive hardware Logic analyzer. * Debug over an internet connection using remote debug, from your office to the lab, or across the globe Note 1. Price for the above software are university package price. To avail this price, user should provide a letter on their institution letterhead - stating that, the software will be used only for educational purpose. 2. All the software will come in DVD format only. For the installation DVD drive is needed, it should be provided by the institution. 3. All the software is having one year free up gradation from the date of sale made by our principle. Also Xilinx will release number of new VLSI processors, which will be supported by the latest version software only. Every year it is advisable to up grade the software. Approximately the up gradation charges will be 50% of the original value 4. If you are purchasing the other software from Xilinx like Chipscope Pro, EDK, System Generator & Forge Compiler ,it will work with Xilinx ISE Foundation Series original version only. The version of the software also should be same. For example if your purchasing EDK tool version 8.2, then the ISE SERIES also should be 8.2 version. 5. For Systems Generator it require MATLAB version 7.1.0.246 (R14) service pack 3 and above.

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A D V A N C E DU N I V E R S A LF P G AT R A I N E R[ V V S M0 9 ]
T h e u n i v e r s a l F P GAt r a i n e r c o n s i s t s o f a ma i nb o a r dw i t hma n y p e r i p h e r a l s l i k e US B , Ho s t &P e r i p h e r a l , E t h e r n e t , S e r i a l p o r t s , P a r a l l e l P o r t , V GAp o r t , Gr a p h i c s L C D , S w i t c h e s , L E D s , A D C& D A Ce t c .T h i s mo t h e r b o a r dh a s 4N o s o f h i g hs p e e dc o n n e c t o r s f o r p l u g g i n g t h e d a u g h t e r b o a r d s , w h i c hc o n t a i n s t h e F P GAo f a n y ma n u f a c t u r e r s .S e p a r a t e 2 N o s o f 1 0 0p i nh i g hs p e e dc o n n e c t o r s p r o v i d e df o r h a r d w a r e e x p a n s i o na s p l u g i nb o a r d s .

F E A T U R E S * I n d u s t r y s t a n d a r di n t e r c o n n e c t i o n * A d d i t i o n a l F e a t u r e s # # # # # # # # # # # # # 3 0 On e 2 4 01 2 8Gr a p h i c s L C D 1 6N o s o f D i pS w i t c h e s 1 6D i s c r e t e L E D s 4d i g i t 7S e g me n t L E DD i s p l a y 4 4Ma t r i x K e y b o a r d On e V GAP o r t a t 1 5p i n D c o n n e c t o r On e P a r a l l e l P o r t a t 2 5p i n D C o n n e c t o r f o r P r i n t e r c o n n e c t i o n On e P S 2c o n n e c t o r f o r K e y b o a r da n d Mo u s e . R e s e t S w i t c h 2 I CR e a l t i me C l o c k On e p i e z oB u z z e r On e 5 VR e l a y 2k g S t e p p e r Mo t o r I n t e r f a c e

# 1 0/ 1 0 0Mb p s E t h e r n e t # US B2 . 0h o s t p e r i p h e r a l # T w oR S 2 3 2p o r t s On e c o n n e c t e da t 9p i nD c o n n e c t o r a n da n o t h e r o n e c o n n e c t e da t 5p i n c o n n e c t o r . * Me mo r y S u bs y s t e m # # # # 8MB 1 6B i t S D R A M 3 2MB 1 6B i t D D RS D R A M 4 MB 1 6b i t f l a s hE E P R OM 2 5 6 K BI 2 CE E P R OM

* A n a l o g I n p u t & Ou t p u t # # # # 2 MS P SS P I B a s e dA D C( 1 2C h a n n e l ) 8 0 0n s S P I B a s e dD A C( 2c h a n n e l ) T e mp e r a t u r e s e n s o r i n t e r f a c e On e 1 6b i t s t e r e oC OD E C

* 2N o s o f 1 0 0p i nh i g hs p e e dc o n n e c t o r s p r o v i d e df o r h a r d w a r e e x p a n s i o nc a nb e u s e d a s h a r d w a r e b u s . * Mu l t i l a y e r b o a r df o r s u p e r i o r s i g n a l i n t e g r i t y * 5 4I / Op i n s t e r mi n a t e da t 3N o s o f 2 0p i nF R Cc o n n e c t o r f o r e x t e r n a l i n t e r f a c i n g . * US B Ho s t a n dP e r i p h e r a l I n t e r f a c i n g # US Bh o s t a n dp e r i p h e r a l I mp l e me n t a t i o nt h r o u g hC y p r e s s C Y 6 7 3 0 0d e v i c e . # On e US Bp e r i p h e r a l p o r t a t f u l l s p e e d( 1 2Mb p s ) # 2Ho s t US Bp o r t s f o r c o n n e c t i n g t oUS BP e r i p h e r a l s l i k e P r i n t e r s / K e y b o a r d/ C a me r a e t c . , P e nD r i v e f o r o t h e r US BP e r i p h e r a l ) # F u l l d r i v e r s o f t w a r e p r o v i d e dt ot h e p e nd r i v e . * On e I D EC o n n e c t o r f o r i n t e r f a c i n g h a r dd i s k # F u l l D r i v e r s o f t w a r e f o r HD D

4 0 MH ZA D CI N T E R F A C EB O A R D( V V S M0 9 # 1 )
A d d o nC a r df o r A d v a n c e dU n i v e r s a l F P G AT r a i n e r ( V V S M0 9 )

A D C * 2C h a n n e l , s i n g l e e n d e dA n a l o g v o l t a g e * S a mp l i n g r a t e i s 4 0MS P S * R e s o l u t i o n: 1 2B i t s * T h e i n p u t s i g n a l c a nb e g i v e ne i t h e r t h r o u g h a l o wf r e q u e n c y d i f f e r e n t i a l A D Cd r i v e r o r a h i g hf r e q u e n c y d r i v e r t r a n s f o r me r s . * T h e i n p u t s i g n a l s a r e t e r mi n a t e da t S MA c o n n e c t o r s .

D A C * 2C h a n n e l c u r r e n t o u t p u t D A C * R e s o l u t i o n : 1 4b i t s * 1 2 5MS P Su p d a t e t i me * S e t t l i n g t i me : 3 0n s * Ou t p u t r a n g e: 2 . 5 Vt o+2 . 5 V * D A Co u t p u t s a r e t e r mi n a t e da t S MAc o n n e c t o r s

N o t e : A n y o n e o f t h e f o l l o w i n g P i g g y b a c kb o a r d s mu s t b e p u r c h a s e dt ow o r kw i t ht h e a b o v e V V S M0 9Ma i nB o a r d

3 1

S u p p o r t e dP i g g y B a c k s
i . V i r t e x 4( X C 4 V S X 2 5 ) [ V A F P 0 2 ]
* V i r t e x 4F a mi l y D e v i c e * 2 3 , 0 4 0L o g i c c e l l s * 4 4 8I / Ol i n e s * D e v i c e u s e d : X C 4 V S X 2 5F F 6 6 8 * On b o a r dc o n f i g u r a t i o ns e r i a l P R OM * J T A GC o n n e c t o r * C o mp a t i b l e w i t hX i l i n x I S Ef o u n d a t i o ns o f t w a r e

i i . V i r t e x I I P r o( X C 2 V P 2 0 ) [ V A F P 0 3 ]
* V i r t e x I I P r oF a mi l y D e v i c e * 2 0 , 8 8 0L o g i c c e l l s * 4 0 4I / Ol i n e s * D e v i c e u s e d: X C 2 V P 2 0 * On b o a r dc o n f i g u r a t i o ns e r i a l P R OM * J T A GC o n n e c t o r * C o mp a t i b l e w i t hX i l i n x I S Ef o u n d a t i o ns o f t w a r e

i i i . S p a r t a n3( X C 3 S 5 0 0 0 ) [ V A F P 0 1 ]
* S p a r t a n3F a mi l y D e v i c e * 5Mi l l i o nS y s t e m Ga t e s * 6 3 3I / Ol i n e s * D e v i c e u s e d: X C 3 S 5 0 0 0 4 F G9 0 0 * On b o a r dc o n f i g u r a t i o ns e r i a l P R OM * J T A GC o n n e c t o r * C o mp a t i b l e w i t hX i l i n x I S Ef o u n d a t i o ns o f t w a r e

i v . S p a r t a n3( X C 3 S 1 5 0 0 ) [ V A F P 0 4 ]
* S p a r t a n3F a mi l y D e v i c e * 1 . 5Mi l l i o nS y s t e m Ga t e s * D e v i c e u s e d: X C 3 S 1 5 0 0 4 F G6 7 6 * On b o a r dc o n f i g u r a t i o ns e r i a l P R OM * J T A GC o n n e c t o r * C o mp a t i b l e o n l y w i t hX i l i n x I S EF o u n d a t i o ns o f t w a r e

3 2

v . A l t e r a S t r a t i x I I [ V A F P 0 5 ]
* D e v i c e Us e d: E P 2 S 3 0 F 6 7 2 * On b o a r dc o n f i g u r a t i o ns e r i a l P R OM * J T A GC o n n e c t o r * L o g i c a l E l e me n t s : 3 3 , 8 8 0 * 5 0 0I / Ol i n e s * A L T E R AQU A R T USI I We be d i t i o ns o f t w a r e c o mp a t i b l e

v i . A l t e r a C y c l o n e I I [ V A F P 0 6 ]
* D e v i c e Us e d: E P 2 C 3 5 F 6 7 2 * On b o a r dC o n f i g u r a t i o nS e r i a l P R OM * J T A GC o n n e c t o r * L o g i c a l E l e me n t s : 3 2 , 2 1 6 * 4 7 5I / OL i n e s * A l t e r a Qu a r t u s I I We be d i t i o ns o f t w a r e c o mp a t i b l e

US BT O J T A G P R OGR A MME R[ V UJ P 0 1 ]
US Bt oJ T A GP r o g r a mme r i s a h i g h p e r f o r ma n c e d o w n l o a dc a b l e t h a t a t t a c h e s t oy o u r h a r d w a r e f o r t h e p u r p o s e o f p r o g r a mmi n g o r c o n f i g u r i n g a n y o f t h e f o l l o w i n g d e v i c e s : * I S PC o n f i g u r a t i o nP R OMs * C P L D s * F P GA s

I t h a s i n d u s t r y l e a d i n g p e r f o r ma n c e a n di s c o mp a t i b l e w i t hF u l l S p e e d( US B1 . 1 ) a n dHi S p e e d( US B2 . 0 ) p o r t s .

Ho s t C o mp u t e r R e q u i r e me n t s
Wh e nu s i n g t h e P l a t f o r mC a b l e US B , t h e h o s t c o mp u t e r mu s t c o n t a i na US Bh o s t c o n t r o l l e r a n dr o o t h u bw i t ho n e o r mo r e US Bp o r t s . T h e h o s t o p e r a t i n g s y s t e m mu s t b e e i t h e r Wi n d o w s 2 0 0 0( S P 4o r l a t e r ) o r Wi n d o w s X P( S P 1o r l a t e r ) .

D e v i c e F a mi l y S u p p o r t
* A l l X i l i n x F P GAa n dC P L Dd e v i c e s * A l l A l t e r aJ T A G d e v i c e s

K e y F e a t u r e s
* T r u e p l u g a n d p l a y * B u s p o w e r e dUS Bd e v i c e ( n op o w e r s u p p l y r e q u i r e d ) * C o mp a t i b l e w i t hF u l l S p e e da n dHi S p e e dUS Bp o r t s * T a r g e t p o w e r s t a t u s L E D * S u p p o r t s B o u n d a r y S c a nmo d e 3 3