CSE45401 VLSI Design Lab

Spring 2004

CSE45401 VLSI Design Lab
Lab #3 – Standard Cell Design This lab has to be completed in one lab session

Creating a custom design for a complex logic function may prove to be quite expensive and time consuming. So, a number of relatively inexpensive design methods have been adopted to create complex designs that minimize the design time. One of the most popular design methods is the standard cell methodology. The rationale for using standard cells relates to the desire to minimize the time-to-market for a new IC design; hence, a premium is placed upon “reuse”. Most complex logic functions can be implemented using a limited number of gates (NAND, NOR, Inverter, etc). These gates are laid out in L-Edit using strict guidelines and are called standard cells. A few hundred of these standard cells are usually designed, verified, documented and then placed in a standard cell library. A typical library may contain cells such as inverters, NAND gates, NOR gates, complex AOI, OAI gates, D-latches, and flip-flops. These gates can be interconnected with each other to create a more complex logic function with little effort. This hierarchical design process allows the designer to save time and cost by using the standard cells for many designs. This also allows the process of designing complex logic functions to be highly automated. However, this approach does not allow a designer to fine tune the design for best performance. In this laboratory you will first learn about standard cell layouts using the Tanner Research Standard Cell Library. Next you design an inverter in standard cell format. Then a timing analysis of the inverter will be made using Spice simulation. Finally, the new cell that you designed will be added to the standard cell library.

Dissect a Standard Cell
To learn how to layout standard cells in L-Edit, you will first dissect one of Tanner’s standard cells. To begin, start L-Edit and then open the library.tdb file. This file contains a number of circuits in standard cell format that can be used repeatedly in large circuits. Use the cell browser to open the cell “Inv” [View > Cell Browser > Inv]. This cell contains a digital inverter. You will use this cell to learn how and why a standard cell is constructed. Print out a copy of this cell to take notes. Move your cursor to the very bottom of the circuit. The bottom edge is at y = -8λ. The blue metal 1 line running horizontally is the GS2 line, one of two unidirectional signal lines in the cell, the other one, the GS1 line runs along the top of the circuit at y = 74λ. Both are 5λ wide and run the length of the cell. Label both of these lines on your printout. Next note the Vdd and GND lines. They also run horizontally and are just inside the GS2 and GS1 lines. Use your cursor to determine their locations and widths, and label them on your printout. In every standard cell in this library, these four lines are in the same positions and have the
SUNY at New Paltz

Do this by flattening the cell [Cell > Flatten]. Create a new cell [Cell > New] and name it “ABCInv. Note: this notation specifies the lower left-hand corner and the upper right hand corner of the rectangle. Now 2 . the pMOS bulk N-Select. The common nodes of each will line up to create connections. Now you can begin your inverter. Now active regions need to be placed over the N-Select and P-Select regions to create the sources and drains of the nMOS and pMOS transistors. Create a new cell for this template [Cell > New] and name the new cell “ABCtempl”. the N-Well and select layers must also line up. select “Celltempl” and click [OK]. It opens up a list of all the cells in the library file.28).tdb [Click the Browse button and select library.6). All of the basic layers are included with the proper heights and placement. where you replace ABC with your initials and click “OK”. For this Lab you will be laying out a CMOS inverter in standard cell format. As above the layers of the cell must be paced at the proper coordinates within the cell. VDD. This completes the Active for the nMOS transistor. You should now have an instance of the cell “Celltempl” in your ABCtempl” cell.0). label the top and bottom y-coordinate of the N-Well. Draw a rectangle of Poly reaching from y = -2λ to y = 68λ with a width of 2λ and center it in the x-direction (Bottom left corner of Poly at (8. The GND. Consider the structure of the inverter circuit. You will also see ports labeled in this cell. and another from (14. the pMOS source and drain P. On your printout. . Along with having the signal and power lines align. while the port “Abut” defines the outline of the circuit so that L-Edit may place the standard cell into a circuit automatically during an Autoroute.Spring 2003 same widths. Layout of a Standard Cell Open a new file based on library. and GS2 ports define the circuit connections for Spice. By following this standard.28).tdb file. Only their lengths will change to fit each unique cell. Since many of the pieces of a standard cell are universal.Select. First draw the active of the nMOS by placing a rectangle of Active from (2. You are now ready to layout the gate and active regions of the inverter. one from (0. move the circuit so that the bottom left hand corner of the GND bus is at (0.0) >( 2. it saves time to start with a template that contains these pieces. Add two more rectangles of Active.” Instance your template cell into the new cell. position the circuit at the origin and flatten the cell.-2)). and then click “OK”. To do this. Now open one of the other circuit cells in the library and verify that these layers are in the same location. the nMOS source and drain N-Select. Now you have a template for designing custom standard cells.tdb file.10) > (16. Since a rectangle is symmetric this completely defines the rectangle and will be the notation used from now on to specify rectangular elements. larger circuits can be created simply by placing standard cells adjacent to one another in a new cell. the nMOS bulk P-Select. Now the instance must be broken so that this cell is independent of the others.tdb for “Copy TDB setup from file:”]. The gates of both transistors are connected and constructed of the same material so let’s start with the gates of both the transistors. Open the instancing menu [Cell > Instance] the select library. GS1. To copy the template from the library.0) > (14.

this is the connection between the two drains and is already on Metal 1.38) > (14.36).66) and the other from (14. and y= 52λ. y= 48λ.2) > (4.55).11) > (15. Start with the Out signal. Now add two more rectangles in Active. Ports are used to specify where Metal 2 can be placed for connecting the circuit. This is done using a Via.39) > (7. Place eight 2×2λ squares of Active Contacts centered on this vertical Metal 1 layer at y= 12λ. Next place a 2×2λ Poly Contact over this Poly from (5. Either the left or right sides of your transistors could be used as the source. y= 48λ. Now place a square of Metal 2 with the dimensions 4×4λ directly over the Via. At this point run the DRC to insure that you have not violated any design rules. one from (2. y= 44λ.37). Thus any port that will be connected outside of the circuit must be placed on Metal 2.33) > (7. y= 40λ. if the circuit were left as is. Finally place a square of Metal 2 with the dimensions 4×4λ directly over the Via. This will be more difficult. The In signal is on the gates of the transistor. 3 .31) > (8. In standard cell design vertical lines of Metal 2 are used to make signal connections to and between standard cells. first draw a Metal1 rectangle from (3.58) and then place four 2×2λ squares of Active Contacts centered on this vertical Vdd Metal 1 layer at y= 40λ. and should be left to the judgment of the designer in future cells. so now it needs to be brought up to Metal 2. then fix those violations before continuing.66). Now the sources of the transistors need to be connected to their respective rails (GND and Vdd).20) and then place three 2×2λ squares of Active Contacts centered on this vertical GND Metal 1 layer at y= 9λ. and y= 52λ.38) > (16. If there are any violations. so instead we will go from Poly to Metal 1 and then from Metal 1 to Metal 2. contacts need to be placed on the Active to connect to Metal 1. Now the In signal must be brought to Metal 2. y= 44λ. Place a square of Via in the center of the Metal 1 rectangle connecting the two drains. Vias are similar to contacts as they connect between two layers and must be 2×2λ. This is an arbitrary decision. Draw Metal 1 from (11.62) > (4. y= 24λ.24) > (6. This is done by placing 2×2λ squares of two Active contacts. To connect from Metal 1 rails to the sources. Lastly. draw a Metal 1 rectangle from (3.26). it would be difficult to connect it to other circuits.60) > 2. Now the drains of both the nMOS and pMOS need to be connected together.Spring 2003 draw the Active of the pMOS from (2. however.56). y= 20λ. Add a 5λ wide Metal 1 rectangle from (3.8) > (7. however.35). y= 13λ. To make the nMOS connections.64). and y= 17λ. which are on Active. For the pMOS connections. The basic circuit is now complete. For an inverter these are the In and Out signals. but for now we will choose the left side to be the source and the right side to be the drain. Now place a 2×2λ square of Via from (4. There is no way to go directly from Poly to Metal 2. one from (0. which are on the Poly layer.4) and the other from (2. This completes the Active for pMOS.23) > (8. First we need to create an area of Poly for the contact. the bulk contacts for the pMOS and nMOS transistors are to be made. Place a rectangle of Poly from (3. y= 16λ.

select [Tools > Extract] from the main menu. There are three steps in creating a signal port. Create a New Library Now that you have a custom circuit it needs to be placed into a library with other cells. Now use the port tool to draw a port over the same rectangle. Repeat this for the Out connection and your circuit is complete. Open the instancing menu and instance your inverter from the file you created above. Vdd.Spring 2003 The last layers to be added to the circuit are the port layers. A dialog box will appear after you have drawn the port. Select this tool and select Metal2 from the palette and draw a horizontal line through the center of Metal 2 of In. You will see that your circuit has been copied into this file. This inverter is functionally correct. re-save the file under the name ABClib. Using the two metals allow connections to be made without creating short circuits. If you are unsure on where to place your ports. This leaves the ports for In and Out to be placed. It is an A with a box above it. Find the “Port” tool on the toolbar. The Global ports (GND. and Vdd ports that are already present in the circuit. These layers do not change the circuit in any way. Examine this inverter and suggest ways in which it can be improved. The circuit-extraction window will appear 4 . look at your printout of Tanner’s standard inverter. We will use the Tanner Library as the base and add your cell to it. GS1. They are used only to help the program in making connections and extracting netlists. Run the DRC to verify that there are no violations in your design. This layer and associated port tell L-Edit where your circuit is. Give the Port name as In. however it is far from ideal. These ports will be different from the others since they are signal ports. To extract a Spice netlist of this circuit. GS2. The signal ports run vertically and are on Metal 2. Another will go from the line to the bottom of GND. Now you can delete the cell “Temp”. File > Save once. Scroll through the list of cells and look for ABCInv. where ABC has been replaced with your initials. Give the same port name In for both. This can be done by clicking [File > Save As]. Draw a rectangle of Icon/Outline layer from (0. Extract Netlist Re-open your inverter cell if you have closed it. Now draw vertical rectangles 4λ wide centered on this line. One will go from the line to the top of Vdd. Now create a new cell and call it “Temp”. etc. Open up library.tdb. Now view the Cell Browser [View > Cell Browser].66). Many of the ports are already defined.) run horizontally and are placed on the edges of Metal 1.tdb in L-Edit. The first is to draw a port line through the center of the port. Look for the GND. Since we do not want to change the original file. Place the port on Icon/Outline layer and name the port “Abut”. The last step to meet standard cell requirements is the placement of the subcircuit ID layer and the “Abut” port. not Global ports.0) > 18.

There is no formal report submission for this lab.spc extracted text file. Spice Simulation Once the circuit is extracted add additional statements as required (refer to Lab #1 handout) and perform Spice analysis.spc extracted text file.1ns steps for a total duration of 30ns. In “Extract Output Filename” enter the entire path for the location you would like the file placed. This will allow you to relate specific devices on output listing to the physical layout.Spring 2003 as an overlay to the Working area.sp portion of the *. along with filename ending in *. • Always select the “Write Node Names” in Comments option. This will assist you in error checking. but everything has to be entered in your lab notebook. Vin In 0 Pulse (0 5 0 0. These will then be the node names in the extracted *. • Select the “Write Verbose Spice” option.01n 0. the name of the file must be kept under 8 characters with no spaces. a significant number of comment statements are added to the output file to help understand the relationship between the original Spice netlist and the extracted netlist.spc extracted text file. 5 . Select the “Write Device Coordinates (Locator Units)” option. Set the options in this window (as in your Lab#1 handout) and extract the circuit. With this option.01n 10n 20n) And run simulation at 0. Select “Names” in the Write Nodes As option. use the following input signal. It also helps provide good documentation so that others can evaluate the designed circuit. Measure the propagation delay (tPHL and tPLH ) and the rise and fall times of the output waveform. For timing analysis. This is very helpful because it places these comment lines in the *. To avoid problems.