Silicon solar cells efficiency improvement with Nano Imprint

Lithography technology
S. Landis
, M. Pirot
, R. Monna
, Y. Lee
, P. Brianceau
, J. Jourdan
, S. Mialon
, P.J. Ribeyron
CEA-LETI, Minatec Campus, 17 rue des martyrs Grenoble, 38054 Cedex 9, France
CEA-INES, 50 avenue du Lac Léman, BP332, 73370 Le Bourget du Lac, France
MPO Energy, Domaine de Lorgerie, 53700 Averton, France
a r t i c l e i n f o
Article history:
Available online 8 April 2013
Solar cell
Multi crystalline Si
Nano Imprint Lithography
Anti-Reflective surface
a b s t r a c t
A large scale patterning processes to produce patterned silicon surfaces with low reflectivity were devel-
oped for silicon solar cells. Optical design, sample manufacturing, optical characterizations and cell effi-
ciency measurements were conducted. Optical simulations were carried out to compute the reflectivity of
the patterned surface to target the optimum shape to be manufactured in the silicon substrate. Patterned
surfaces were manufactured using thermal Nano Imprint Lithography over 125 Â 125 mm
Si-c and Si-
mc wafer and proportional dry etching. A high aspect ratio inverted pyramid shapes were achieved in
both Si-c & Si-mc substrates. An effective reflectivity (Rw) of about 3% was achieved on multi-crystalline
silicon with the inverted pyramid pattern. The patterning process uniformity over the substrate was bet-
ter than 97%. I(V) measurements of standard Si-mc KOH textured and Si-mc inverted pyramidal textured
using Nano imprint and dry etching revealed that a drop of about 3% were induced in the open-circuit
voltage, a drop of about 3.4% for the fill factor, however with an increase of about 8.3% for the short-cir-
cuit current. A gain of 0.33% absolute efficiency is obtained on the Si-mc Nano-imprinted cell compared to
the KOH textured Si-mc cell. The gain of the short-circuit current is directly connected to the gain of
reflectivity (8%) obtained on the finished solar cell.
Ó 2013 Elsevier B.V. All rights reserved.
1. Introduction
Nanostructuredsurfaces are widely expectedtoplay a significant
role in photonics, especially in wide-spread products like imaging
sensors, solar cells, lightning devices and micro displays. Those
expectations are related to two kinds of benefits: improvement of
the conversion efficiency fromphoton to electron (solar cells, photo
detectors and image sensors) or from electron to photon (lightning,
displays) and reduction of fabrication cost. The performance of a
solar cell is critically dependent on the absorption of incident
photons and their conversion to current. Several approaches have
been proposed to improve the solar cell efficiency: light conversion
approaches [1], the light-mater interactionimprovement using light
concentration solutions [2], increasing the absorption [3] or lower-
ing the surface reflectivity [4]. Inasmuch as more than 30% of inci-
dent light is reflected from the silicon surface back to the air,
surface treatments are required to manufacture high-efficiency
siliconsolar cells. Anti-ReflectiveCoating(ARC) is usuallyperformed
on Si surface to reduce light reflection and to increase light absorp-
tion. Acid [5] or alkaline [6] wet chemical etching approaches were
also proposed. Texturing of monocrystalline silicon (Si-c) is usually
done in aqueous solutions of potassiumor sodiumhydroxide result-
ing in a surface that is covered with inverted pyramids. Wet chemi-
cal etchings are simple and low cost processes, however alkaline
process suffers from the silicon crystalline orientations. For textur-
ing of multicrystalline silicon (Si-mc) such crystal orientation
dependent techniques are not efficient enough. An alternative to
thin-filmcoatings and wet chemical etching is to patternthe surface
witha periodicallystructuredarray [7,8]. However most of solutions
proposed today required high resolution and very expensive lithog-
raphy techniques., Nano Imprint Lithography (NIL), considered as
cost efficiency patterning technique, has already beenused to create
patterns over organic solar cell [9,10], or manufacturephotonic crys-
tal over thinsolar cells [11] toincrease light couplingwithinthinwa-
fer thickness. However fewattends were made to combine NIL with
dry plasma etching to offer a new attractive process flow to lower the
surface reflectivity of crystalline or multi crystalline solar cells [12]. In
this paper we proposed a patterning process over 125 Â 125 Si-mc
cells using NIL with soft stamps and dry etching processes. We report
the implementation of a micron scale antireflection pattern. The over-
all anti-reflective effects were compared with a typical KOHwet etch-
ing and I–V characteristics were carried out.
2. Experimental
P-type 1–2 mc-Si substrates with a thickness of 220 lm
were used. First of all wafers were polished in an acidic bath in
0167-9317/$ - see front matter Ó 2013 Elsevier B.V. All rights reserved.

Corresponding author. Tel.: +33 0 4 38 78 44 03; fax: +33 0 4 38 78 50 46.
E-mail address: (S. Landis).
Microelectronic Engineering 111 (2013) 224–228
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order to remove damages related to the saw. A 6.2 lm thick JSR re-
sist where then spin coated on multi crystalline Si square wafers.
The imprint process was performed in EVG520HE set-up with h-
PDMS/PDMS composite stamp manufactured from a 200 mm
diameter Si crystalline wafer patterned with wet KOH etching
(Fig. 1a). A silicon dioxide layer deposited on (100) silicon sub-
strate was first patterned with DUV lithography and reactive ion
etching processes. Then this patterned mask was used to carry
out a selective wet alkaline etching of silicon. The master silicon
stamp was then coated with anti-adhesive layer, Optool DSX from
DAIKIN [13] and a 32 lm thick h-PDMS layer were spin coated on
the top of inverted pyramid shape (Fig. 1b) and finally cover by
3 mm thick PDMS layer (Fig. 1c,d). This soft composite stamp
was then demolded from the Si master stamp and coated with Op-
tool DSX anti-sticking layer lowering the surface energy down to
11 mJ/m
. The stamp was then printed at 135 °C under 2 bars for
5 min into the resist to shape the inverted pyramid features
(Fig. 2a & b). Thanks to the low stiffness of the composite mold
and the micrometer scale of the pyramid shape, printings over Si
grain boundaries for Si-mc substrate, even for 4 lm to 5 lm steps
between two neighbouring grains, were possible without deform-
ing the printed patterns. Dry etching was then performed in ICP
mode using chlorine based chemistry in Centura AP from Applied
Material to remove the residual layer thickness and transfer the
printed shape within the Si-mc substrate (Fig. 2c & d). Low and
uniform residual layer thickness (210 nm) compared to the feature
height (6.17 lm) was achieved over Si-c substrates thanks to the
planarity of surfaces. However, this was not possible for Si-mc sub-
strates which presented from 4 lm to 5 lm mesa height at grain
boundaries. The etching process was therefore developed to free
Fig. 1. (a) SEM cross section picture of inverted pyramid shapes wet etched in Si-c 200 mm wafer. (b) SEM cross section image of 32 lm thick h-PDMS layer coated on the Si
master. (c) Optical micrograph of the composite stamp and (d) optical image of the h-PDMS pyramid shapes over the PDMS back plane.
Fig. 2. SEM cross section pictures of pyramid shapes printed in the resist on Si-c (a) & Si-mc (b) substrates. Corresponding SEM cross section pictures of pyramid shapes,
etched patterns within the Si substrates for Si-c (c) & Si-mc substrates (d).
S. Landis et al. / Microelectronic Engineering 111 (2013) 224–228 225
our self from the non-uniform residual layer thickness distribution
observed over the Si-mc substrate (Fig. 2b). It led also to an ampli-
fication of the pyramid aspect ratio. Indeed, starting with an initial
side wall angle of pyramid of about 54.74° (KOH wet etching of Si,
Fig. 1a) with respect to the surface plane, the final side wall angle
was ranging between 71° up to 85°, leading to much more deeper
inverted pyramid shape, up to 15 lm deep for a pyramid with a
square base of 9.5 lm (Fig. 2c and d). The remaining resist was
stripped away with oxygen plasma and HF treatment was then
performed. The final process leads to excellent results in structur-
ation with similar results for both flat single-crystal silicon and
multi crystalline substrates. The wafers were submitted to a POCl3
diffusion in an open quartz tube furnace. The diffusion process re-
sults in the formation of n++ surfaces on both sides with a sheet
resistance value of 75 O/sq. Anti-reflection coating (72 nm thick
SiN) and metallization by screen printing were carried out in order
to fit to the surface topography. The whole process flow is summa-
rize in Fig. 3 and is also compared with a standard alkaline patter-
ing process scheme. Finally illuminated and dark I (V)
measurements were done. A reference group, with standard alka-
line wet pattering process, was also manufactured to underline
the impact of the patterning on the cell efficiency.
3. Patterns characterizations
Optical reflectivity measurements of the patterned substrates
were carried out. The characterizations were performed without
anti-reflective coating above the patterned sample and were con-
ducted over samples prepared with different patterning processes
(Fig. 4): KOH wet etching over multi crystalline (KOH mc-Si) and
crystalline silicon (KOH c-Si) substrates; acid etching over multi
crystalline silicon (acid mc-Si); KOH wet etching over a periodic
patterned SiO2 mask on crystalline silicon substrate (pyr. inv. C-
Si); and imprint & dry etching process over multi crystalline sam-
ple (imprint). The weighted reflectivity, Rw (weighted by the solar
spectrum on the range of 350 to 1000 nm), for all patterning pro-
cess, are listed in Fig. 4a. The KOH mc-Si patterning configuration
presented the lowest performance, with a Rw of about 30.8%, since
for some Si grain orientations the alkaline wet etching process is
not optimum and created some large flat mesas (see corresponding
SEM picture on Fig. 4a). Acid wet patterning slightly decreases the
Rw down to 26.5% with some micro scale rounded shapes over the
surface. KOH wet etching over crystalline substrate, either ran-
domly or periodically arranged, present much lower reflectivity,
with a dark gray aspect and a Rw of about 12.2% to 13.1%. Finally,
the imprint and dry etching process led to the lowest Rw, of about
2.2%, 10% lower than the wet KOH etching process performed over
Si-c samples. The textured mc-Si wafers present a deep black as-
pect compared to un patterned substrate, confirmed by a 3%
weighted reflectivity, with a homogeneity better than 97% on the
whole wafer (Fig. 4b and c). The exact shape of the inverted pyra-
mid pattern appeared to be a key parameter to tune the optical
reflectivity of the sample.
We performed optical simulation in order to compute the
reflectivity of the patterned surface to point out the impact of
the pyramid angle (with respect to the surface plan) onto its opti-
cal reflectivity. Ray-tracing method using Zemax software [14] has
been used. For the calculation, a bundle of rays is emitted from an
imaginary surface in front of the 3D textured model. Each ray has a
single wavelength. Using Snell-Descartes law and considering re-
flected and multi reflected, transmitted and absorbed rays, the
reflection coefficient is computed by an external code with abeles
matrix. The silicon material was described by its refractive spectral
index and its spectral absorption coefficient. The reflection prop-
erty of the surface with respect to the design was then computed.
The course for one ray is considered to be finished when the ray is
totally absorbed by the Si or if there is no newpossible interception
(ray goes too far from the 3D object). The reflected light is com-
puted by a virtual detector (hemispherical in order to collect all re-
flected light into the 2pi-steradiant volume) which lies in front of
the textured surface. We found that an array of 9.6 lm period
made of inverted pyramid shape showed an optical reflectivity
decreasing from 40% for a pyramid angle of 40° down 2% for a pyr-
amid angle of 80°. The optical reflectivity is about 13% when the
pyramid angle is 54.7° (obtained with. the KOH patterning). There-
fore, sharpening the pyramid shape within the silicon substrate
will drastically reduce the optical reflectivity thanks to light trap-
ping and multiple reflections on the surface.
4. Cells characterization
The reflectivity of the finished cells after the anti-reflective
coating and the screening printing was measured as low as 4.3%.
This corresponds to 8.3% reduction of the weighted reflectivity
compared to the finished cell patterned with KOH process. This sig-
nificant reduction of the overall reflectivity was mainly observed in
the 300–600 and 1000–1200 nm wavelength regimes. Due to the
higher aspect ratio of the etched pyramid, both screen printing
and firing processes have been optimized to the new surface topol-
ogy. As consequence, the width of the line, contact resistance
) and line resistance (0.35 are then equiv-
alent to those obtained on the classic KOH textured references cells
and 0.15 respectively).
I(V) measurements under sun illumination were performed to
characterize the short-circuit current, Jsc, and the open-circuit
voltage, V
, the maximum voltage available from a solar cell
(Fig. 5). The short-circuit current is due to the generation and col-
lection of light-generated carriers. The open-circuit voltage corre-
sponds to the amount of forward bias on the solar cell due to the
bias of the solar cell junction with the light-generated current.
From I(V) curves, the ‘‘fill factor’’, more commonly known by its
abbreviation ‘‘FF’’ with Voc and Jsc, determines the maximum
power from a solar cell can be determined. The FF is defined as
the ratio of the maximum power from the solar cell (Fig. 5) to
the product of Voc and Jsc. Graphically, the FF is a measure of
the squareness of the solar cell and is also the area of the largest
rectangle which will fit in the IV curve.
Fig. 3. Process flow for the patterned Si-mc solar cell manufacturing with NIL or
KOH wet etching approaches.
226 S. Landis et al. / Microelectronic Engineering 111 (2013) 224–228
We observe a higher recombination current on the Si-mc in-
verted pyramidal texturized using nano-imprint and dry etching,
and a lower open circuit voltage (Fig. 6). In our case, we found that
Fig. 4. (a) Reflectance measurements of patterned Si, either Si-c or Si-mc substrates without anti-reflective coating. Acid (acid mc-Si) or alkaline (mc-Si, c-Si, c-Si poly)
patterning approaches are compared to imprint/etching processes. Optical photograph of 125 Â 125 square Si-mc substrate, without pattering (b), and covered by inverted
pyramid shapes (c) shown in Fig. 1d.
Fig. 5. Graph of cell output current (solid line for imprint, dotted line for KOH
etching) as function of voltage. Also shown are the cell short-circuit current (Jsc @
V = 0 mV) and open-circuit voltage (Voc @ I = 0 mA) points, as well as the power
curves (solid line with filled rounds for imprint, dotted line with crosses for KOH
Fig. 6. (a) Short-circuit current (Jsc), (b) open-circuit voltage (Voc), (c) fill factor and
(d) cell efficiency measurements of a patterned Si-mc solar cells either with KOH
wet etching or imprint & dry etching processes. The increase or decreases of cell’s
characteristics between the two patterning processes are underline.
S. Landis et al. / Microelectronic Engineering 111 (2013) 224–228 227
the gain in short circuit current (Jsc) gain was correlated to reflec-
tivity decrease. However, lower values are observed for both the
opened circuit voltage (À15 mV, i.e. À3%) and the Fill Factor
(À2.5, i.e. À3.4%) in the case of the imprinted and dry etched pat-
tern compared to the alkaline one. The lower Voc is probably re-
lated to a degradation of the front surface due to the plasma
etching process. Dark current–voltage curve (not shown) indicated
a twice higher recombination current on the imprint textured cells,
what highlights a strong recombination in the space charge region,
leading to the observed Voc drop. We also performed measure-
ments of the minority carrier diffusion length by LBIC measure-
ments to check the influence of the dry patterning process on the
electrical quality of the bulk. No significant impact of the pattern-
ing process was observed as since the minority carrier’s diffusion
length was of about 530 lm for the KOH patterning process and
590 lm for the imprinting process respectively. The small increase
of the minority carrier diffusion length on the imprinted cells may
come from a better optical confinement, which induce a generation
of minority carriers closer to the surface. Regarding the FF the
small decrease is probably related to a lower shunt resistance for
imprinted substrate. As a consequence an absolute efficiency gain
of 0.33% was obtained applying the imprinting process on Si-mc
solar cells compared to KOH patterning (Fig. 6). This gain is quite
low compared to the theoretical gain which may be obtained. As
mentioned previously, the current under illumination is directly
proportional to the reflectivity. Therefore a 1% gain in reflectivity
results in a 1% gain in short circuit current. As a consequence, keep-
ing both V
and FF parameters constants, a decrease of 8% of the
reflectivity should lead to a gain of absolute efficiency over 1%.
5. Conclusions
We developed a patterning process, based on Nano Imprint
Lithography with soft stamp and dry etching, over non flat and
fragile multi-crystalline silicon substrate, to create inverted pyra-
mid shapes. The transfer of the inverted pyramid shape in the Si-
mc provided by plasma etching showed an amplified aspect ratio
compared to the stamp manufactured with standard KOH wet
etching process. A very low optical reflectivity property, lower than
3%, was achieved whatever the crystalline orientation of the silicon
grain. This lowreflectance is associated to light trapping and multi-
ple reflections in the very sharp pyramid shape manufactured
within the silicon. Compared to other wet patterning approaches,
our process presents the lowest weighted reflectivity over the solar
spectrum with a gain at least of 8%. We also showed that the short
circuit current gain, 8.3%, was directly associated to the reflectivity
gain. An absolute 0.33% efficiency gain is demonstrated on Si-mc
solar cells (16.8% compared to 16.5% with our reference alkaline
process). These promising results are however below those ex-
pected in terms of efficiency due to losses in open circuit voltage
(À3%) and fill factor (À3.4%). This open circuit voltage degradation
might be generated by the plasma etching and/or by the aggressive
patterned profile. Further works are ongoing for dry etching opti-
mization and also both the screen printing and firing steps. Lower-
ing the Voc and FF drops, an efficiency gain of 1% may be targeted,
if the reflectivity gain is completely transformed in efficiency gain.
The partial support from the PV20 project supported by the
OSEO funding is gratefully acknowledged.
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