EEE598: Final Project

December 5, 2013

EEE598: Fall 2013 – Final Project

Munaf Hussain Shaik (ASU ID: 1202751779)
Alfonso Albason (ASU ID: 1206976273)

Submission date: 12/05/2013

Shaik, Albason
EEE598: Final Project

Table of Contents
1.

Introduction ................................................................................................................................................4

2.

Problem description ....................................................................................................................................4

3.

Top-level architecture .................................................................................................................................6
3.1

Filter choices ..........................................................................................................................................6

3.1.1.

High-pass filter ...............................................................................................................................6

3.1.2.

Low-pass filter ................................................................................................................................6

3.1.3.

Notch filter......................................................................................................................................8

3.2

Bi-quad design ........................................................................................................................................9

3.2.1.

LPF .................................................................................................................................................9

3.2.2.

HPF ...............................................................................................................................................10

3.2.3.

Notch filter....................................................................................................................................11

3.3
4.

Z-domain analysis ................................................................................................................................12
Subsystem design and descriptions ..........................................................................................................13

4.1

Amplifier ..............................................................................................................................................13

4.1.1.

Introduction ..................................................................................................................................13

4.1.2.

Design ...........................................................................................................................................13

4.1.3.

Schematics ....................................................................................................................................13

4.1.4.

Output waveforms – spec verification ..........................................................................................14

4.2

Switch ...................................................................................................................................................15

4.2.1.

Introduction ..................................................................................................................................15

4.2.2.

Design ...........................................................................................................................................15

4.2.3.

Schematics ....................................................................................................................................15

4.2.4.

Output waveforms – spec verification ..........................................................................................16

4.3

Digital blocks – gates, non-overlapping clock generator .....................................................................17

4.3.1.

Introduction ..................................................................................................................................17

4.3.2.

Design ...........................................................................................................................................17

4.3.3.

Schematics ....................................................................................................................................17

4.3.4.

Output waveforms – spec verification ..........................................................................................19

4.4

High-pass filter – 2 kHz........................................................................................................................20

4.4.1.

Introduction ..................................................................................................................................20

4.4.2.

Schematics ....................................................................................................................................20

4.4.3.

Output waveforms – spec verification ..........................................................................................23

4.5

Low-pass filter – 20 kHz ......................................................................................................................24

1

2

Introduction
4.5.1.

Introduction ..................................................................................................................................24

4.5.2.

Schematics ....................................................................................................................................24

4.5.3.

Output waveforms – spec verification ..........................................................................................26
Notch filter – 32.99 kHz .......................................................................................................................27

4.6
4.6.1.

Introduction ..................................................................................................................................27

4.6.2.

Schematics ....................................................................................................................................27

4.6.3.

Output waveforms – spec verification ..........................................................................................30

5.

System integration ....................................................................................................................................31
5.1

Schematic of full filter ..........................................................................................................................31

5.2

Results ..................................................................................................................................................31

5.2.1.
6.

Filter gain......................................................................................................................................31

Performance..............................................................................................................................................33
6.1

Operation vs. supply .............................................................................................................................33

6.2

Layout area estimate .............................................................................................................................34

7.

Conclusion ................................................................................................................................................34

8.

Appendix ..................................................................................................................................................35
8.1

Appendix A: spectre Netlist .................................................................................................................35

8.2

Appendix B: References .......................................................................................................................41

List of Figures
Figure 1: Filter Transfer function ..............................................................................................................................5
Figure 2: HPF Transfer function ...............................................................................................................................6
Figure 3: LPF Transfer function................................................................................................................................7
Figure 4: Notch filter Transfer function ....................................................................................................................8
Figure 5: Bi-quad LPF implementation (2nd order) ...................................................................................................9
Figure 6: Switched-cap implementation of LPF .....................................................................................................10
Figure 7: Bi-quad HPF implementation (2nd order) ................................................................................................10
Figure 8: Bi-quad notch filter implementation (2nd order) ......................................................................................11
Figure 9: s- to Z-domain conversion .......................................................................................................................12
Figure 10: Amplifier schematic...............................................................................................................................13
Figure 11: Amplifier test bench & Iq ......................................................................................................................13
Figure 12: Amplifier gain vs. supply ......................................................................................................................14

Shaik, Albason
EEE598: Final Project
Figure 13: Amplifier parameters vs. supply ............................................................................................................14
Figure 14: T-gate switch schematic ........................................................................................................................15
Figure 15: T-gate switch test bench ........................................................................................................................16
Figure 16: Switch Ron simulation - Ron = 428 Ohms ............................................................................................16
Figure 17: Non-overlapping clock generator schematic .........................................................................................17
Figure 18: Inverter schematic..................................................................................................................................18
Figure 19: NOR gate schematic ..............................................................................................................................18
Figure 20: Non-overlapping clock generation ........................................................................................................19
Figure 21: Non-overlapping clocks - zoomed .........................................................................................................19
Figure 22: HPF continuous-time (CT) implementation ..........................................................................................20
Figure 23: Non-optimized switch version of HPF ..................................................................................................21
Figure 24: HPF implementation with optimized switch usage ...............................................................................22
Figure 25: HPF gain plot .........................................................................................................................................23
Figure 26: HPF implementation with non-optimized switches ...............................................................................24
Figure 27: LPF implementation with optimized switch implementation ................................................................25
Figure 28: LPF gain plot (@ 20kHz) ......................................................................................................................26
Figure 29: Notch filter - CT implementation ..........................................................................................................27
Figure 30: Notch filter implementation with non-optimized switches....................................................................28
Figure 31: Notch filter implementation with switch optimization ..........................................................................29
Figure 32: Notch filter gain response ......................................................................................................................30
Figure 33: Filter transfer characteristics..................................................................................................................31
Figure 34: Filter transfer characteristics shown on a linear frequency axis ............................................................32
Figure 35: Filter transfer function vs. supply ..........................................................................................................33
Figure 36: Sweep showing all required parameters vs. supply ...............................................................................34

List of Tables
Table 1: Project specifications ..................................................................................................................................4

3

2 dB Passband gain variation -2/3 dB Low frequency rolloff 40 dB/dec Carrier frequency 32.7 – 3. A crystal oscillator of 3. PAC).99 kHz We have chosen to implement the filter as 3 parts: High-pass filter (@ 2kHz). Low-pass filter (@ 20kHz) and a notch filter (@ 32.99 kHz. simulate and verify an audio-band filter. Also. It has been simulated in Cadence using SpectreRF (PSS. . it is assumed that a current reference of 5µA is available along with a reference voltage at .3 V Supply current 4 mA Passband 2 – 20 kHz Passband ripple +/. The technology used for this project is tsmc35 which has transistors at a process node of 400nm. The filter has been implemented using standard switched-capacitor topologies and cascade based design methodology. The major purpose of the filter is to suppress non-audio frequencies – especially the carrier signal at 32.6864 MHz is also assumed to be available. mobile phones.4 Introduction 1.99 kHz). The application for such an audio band filter can be found in voice communication systems such as cordless phones. Introduction The purpose of the project is to design. Walkietalkies etc. Problem description The filter for the project has been designed according to the following specifications: Table 1: Project specifications Specification Value Units Supply voltage 2. 2.

5 .Shaik. This can be implemented using switched-capacitor implementation using 2 amplifiers per 2nd order section. This project requires 4 such sections (at least 8 amplifiers). Albason EEE598: Final Project The implemented transfer function has the following AC gain characteristics: Figure 1: Filter Transfer function All the filters have been implemented using standard Tow-Thomas bi-quad topology.

6 Top-level architecture 3. 3.1. The filter transfer function (prototype) for a fast transition band is: .1. High-pass filter The low-pass filter at 2 kHz has been designed as a 2nd order Butterworth filter. The filter transfer function (prototype) for maximally flat high-pass response is: ( ) √ The bode plots for the above transfer function is as follows: Figure 2: HPF Transfer function A Butterworth filter has been chosen as it gives a flat response and linear gain drop in stop band. Top-level architecture 3.1.2. Low-pass filter The low-pass filter at 20 kHz has been designed as a 4th order Chebyshev filter.1 Filter choices 3.

Shaik. A flat transition band is important in this case as this filter is adjacent to a notch filter at a frequency very close to the transition band. Albason EEE598: Final Project ( ) The bode plots for the above transfer function is as follows: Figure 3: LPF Transfer function A Chebyshev filter has been chosen as it gives a flat transition band. 7 .

1. The filter transfer function (prototype) is: ( ) √ The bode plots for the above transfer function is as follows: Figure 4: Notch filter Transfer function Care has been taken in the actual design to be able to put together all the filter blocks accounting for additional attenuation from the other stages.99 kHz has been designed as a 2th order Butterworth filter. .3. Notch filter The notch filter at 32.8 Top-level architecture 3.

the filters can be scaled to higher frequencies from prototype operation as follows: The value of R is assumed to be and . thus 3. LPF R R*Q R C R VIN R C R VLPF Figure 5: Bi-quad LPF implementation (2nd order) For the LPF. Albason EEE598: Final Project 3. Also.1.2.Shaik. Thus. 9 . .2 Bi-quad design All the bi-quad based filters can be converted for switched capacitor implementation by replacing R’s with switch-capacitor.

1. HPF R R*Q R VIN C R R C R R Q*R R R VHPF Figure 7: Bi-quad HPF implementation (2nd order) . 3.1. = VCM CR 2 C 2 CR C 2 1 2 1 1 VIN 1 10 VLPF Figure 6: Switched-cap implementation of LPF The number of switches has also been optimized by re-using switches with same clock phases and terminal connections.Top-level architecture 1 2 CR/Q 2 CR 1 1 Switch-cap implementation of LPF 2 2 1 3.2.2.2.

3. 11 .2. The notch filter and HPF have also been implemented in switched capacitor form in a similar fashion as the LPF. .Shaik. Thus. . Notch filter R R*Q C R R VIN R C R Q*R R R Vnotch Figure 8: Bi-quad notch filter implementation (2nd order) For the LPF. 3. Thus. Albason EEE598: Final Project For the LPF.

71 fF R 1 1M 2 1 2 C = 271.to Z-domain conversion Since the sampling frequency .3 Z-domain analysis s to Z conversion C = 271. .71 fF -R 1M 2 1 1 2 12 Figure 9: s.Top-level architecture 3. the system is oversampled at is much greater than the highest frequency of interest .

1. Subsystem design and descriptions 4.1.2. The amplifier has a typical gain of 65 dB and GBW of about 80 MHz with a quiescent current of . 4.Shaik. A folded cascode amplifier would be a good choice because the output impedance of the amplifier is very high and would suit this application. 4. Design The amplifier designed for this project is a standard nMOS input folded-cascode amplifier enabled by a reference current of approximately .1.1.1 Amplifier 4. Albason EEE598: Final Project 4. Introduction The amplifier for the current design/application has to be capable of driving a value resistor or a capacitor of .3. Schematics Figure 10: Amplifier schematic Figure 11: Amplifier test bench & Iq 13 .

1. Output waveforms – spec verification Figure 12: Amplifier gain vs. supply Figure 13: Amplifier parameters vs.14 Subsystem design and descriptions 4. supply .4.

3.2 Switch 4. Albason EEE598: Final Project 4. 4. The nMOS is of size . 4.2.1. Design A transmission gate switch has been designed with an size .Shaik. Introduction The switch is the most important component of a Switch-cap circuit.2. A transmission gate switch has been chosen for this design as it enables use with wide input signal range.2.2. Schematics Figure 14: T-gate switch schematic and pMOS is of 15 .

2. Output waveforms – spec verification Figure 16: Switch Ron simulation .4.16 Subsystem design and descriptions Figure 15: T-gate switch test bench 4.Ron = 428 Ohms .

Albason EEE598: Final Project 4. Design The design is shown below. Introduction In order for the switched capacitor circuit to function properly.3.3.3. These nonoverlapping clock phases are generated using cross-coupled NOR gates with delay.3 Digital blocks – gates. non-overlapping clock generator 4.1. we require non-overlapping clocks. 4.Shaik.3. 4. Schematics Figure 17: Non-overlapping clock generator schematic 17 .2.

18 Subsystem design and descriptions Figure 18: Inverter schematic Figure 19: NOR gate schematic .

Shaik. Albason EEE598: Final Project 4.zoomed 19 .3. Output waveforms – spec verification Figure 20: Non-overlapping clock generation Figure 21: Non-overlapping clocks .4.

4.4. 4.2. Introduction The High-pass filter has been designed as a 2nd order Butterworth bi-quad. Continuous-time implementation Figure 22: HPF continuous-time (CT) implementation .4.20 Subsystem design and descriptions 4. Schematics The design makes use of standard capacitors and the MOS switches and amplifier discussed above.1. The output gain plot shows the gain to be because the output is available during one clock phase. the average value of output is half of the actual output voltage.4 High-pass filter – 2 kHz 4. The design and parameter values have been discussed above.1.2. 4. Thus.

4.2.2. Albason EEE598: Final Project 4.Shaik. Switched-capacitor implementation Figure 23: Non-optimized switch version of HPF 21 .

22 Subsystem design and descriptions Figure 24: HPF implementation with optimized switch usage .

3. the average value of output is half of the actual output voltage. 23 . Thus.4.Shaik. This is taken care of by designing the subsequent stages accordingly. Albason EEE598: Final Project 4. Output waveforms – spec verification Figure 25: HPF gain plot The output gain plot shows the gain to be because the output is available during one clock phase.

5 Low-pass filter – 20 kHz 4. Thus.5.5.2. The output gain plot shows the gain to be because the output is available during one clock phase. 4.5.2. Introduction The High-pass filter has been designed as a 2nd order Butterworth bi-quad. The design and parameter values have been discussed above. the average value of output is half of the actual output voltage.1. Switched-capacitor implementation Figure 26: HPF implementation with non-optimized switches .24 Subsystem design and descriptions 4. Schematics The design makes use of standard capacitors and the MOS switches and amplifier discussed above.1. 4.

Shaik. Albason EEE598: Final Project Figure 27: LPF implementation with optimized switch implementation 25 .

26 Subsystem design and descriptions 4.3.5. Output waveforms – spec verification Figure 28: LPF gain plot (@ 20kHz) The peak at 20kHz is intentional as the notch filter has been designed to have a wide notch bandwidth and has an attenuation of 10 dB at 20 kHz. The notch characteristics are shown in the subsequent section. .

Continuous-time implementation Figure 29: Notch filter .6 Notch filter – 32.6.1. Thus. The design and parameter values have been discussed above. 4. the average value of output is half of the actual output voltage. Introduction The High-pass filter has been designed as a 2nd order Butterworth bi-quad.6.2. Albason EEE598: Final Project 4.CT implementation 27 . 4.6.1.2.99 kHz 4. Schematics The design makes use of standard capacitors and the MOS switches and amplifier discussed above.Shaik. The output gain plot shows the gain to be because the output is available during one clock phase. The design makes use of a CDS style last gain stage as it is important to have the output available during both clock phases.

Switched-capacitor implementation Figure 30: Notch filter implementation with non-optimized switches .28 Subsystem design and descriptions 4.2.2.6.

Albason EEE598: Final Project Figure 31: Notch filter implementation with switch optimization 29 .Shaik.

30 Subsystem design and descriptions 4. Output waveforms – spec verification Figure 32: Notch filter gain response .3.6.

Filter gain Figure 33: Filter transfer characteristics 31 .2.2 Results 5.Shaik.1 Schematic of full filter 5.1. Albason EEE598: Final Project 5. System integration 5.

32 System integration Figure 34: Filter transfer characteristics shown on a linear frequency axis .

Performance 6. supply 33 .Shaik. Albason EEE598: Final Project 6. supply Figure 35: Filter transfer function vs.1 Operation vs.

supply 6. routing etc. Contacts etc. Conclusion Thus.34 Conclusion Iq Figure 36: Sweep showing all required parameters vs. Drain.) Complete area of transistors = Area of Capacitors (at 5fF/µm2) ≈ (includes additional area for contacts. the complete filter has been designed and simulated according to the given specifications. .2 Layout area estimate Sum of area of all transistors = which is approximately 20% of total transistor area (Source.) Total Area ≈ 7.

6e-12 ad=3.6u l=400n as=3.6u m=1 region=sat N15 (Vbn Vbn 0 0) tsmc35N w=1.m" // Library name: EEE598_Amp // Cell name: amp_101 // View name: schematic subckt amp_101 Vinm Vinp Vout C0 (Vout 0) capacitor c=750.6e-12 \ ps=9.6u l=400n as=3.2u pd=9.2e-12 ad=1.2e-12 ps=4.6e-12 ps=9.2u l=8u as=1.0u m=1 region=sat N11 (net0113 net0163 0 0) tsmc35N w=1.4u m=1 region=sat 35 .Shaik.6e-12 ad=3.4u \ pd=4.6e-11 ps=74.2u m=1 region=sat P10 (net0101 Vbp2 vdd! vdd!) tsmc35P w=30u l=400n as=3e-11 ad=3e-11 \ ps=62.4u m=1 region=sat N8 (net0101 Vinp net0104 0) tsmc35N w=36.00f I0 (vdd! net0184) isource dc=5u type=dc P11 (net075 Vbp2 vdd! vdd!) tsmc35P w=3.6u l=800n as=3.2e-12 \ ps=4.6e-12 \ ad=3.4u m=1 region=sat N17 (net0108 net0110 0 0) tsmc35N w=1.2u pd=9.4u m=1 region=sat N16 (net0110 Vbn net0108 0) tsmc35N w=1.2e-12 \ ad=1.6u pd=5.0u m=1 region=sat P2 (net095 Vbp2 vdd! vdd!) tsmc35P w=3.6e-12 ad=3.8e-12 \ ps=5.8e-12 ad=1.2u pd=9.0u m=1 region=sat P7 (Vout Vbp1 net093 vdd!) tsmc35P w=20u l=1u as=2e-11 ad=2e-11 \ ps=42.2u l=1u as=1.6e-12 ps=9.2u m=1 region=sat P12 (Vbn Vbp1 net075 vdd!) tsmc35P w=3.m" include "/home/ncsu-cdk-1.2u l=400n as=1.6u l=800n as=3.6e-12 \ ps=9.6e-12 \ ad=3.5.2u pd=9.0u pd=42.2u m=1 region=sat P14 (net071 Vbp2 vdd! vdd!) tsmc35P w=3.0u l=400n as=3.2u m=1 region=sat P0 (Vbp1 Vbp1 vdd! vdd!) tsmc35P w=1.6864M vdd=3 vcm=vdd/2 include "/home/ncsu-cdk-1.spectre" parameters Ron=1k Roff=100M Fin=3.6e-12 \ ps=9.0u pd=74.0u pd=42.6u l=400n as=3.2e-12 ad=1. Appendix 8.1/models/spectre/standalone/tsmc35P.2u l=400n as=1.4u pd=4.0u m=1 region=sat P9 (net0163 Vbp1 net0101 vdd!) tsmc35P w=20u l=1u as=2e-11 ad=2e-11 \ ps=42.2u m=1 region=sat P13 (net0110 Vbp1 net071 vdd!) tsmc35P w=3.6e-12 ps=9.1 Appendix A: spectre Netlist // Generated for: spectre // Generated on: Nov 27 21:37:11 2013 // Design library name: EEE598_Amp // Design cell name: filter_test // Design view name: schematic simulator lang=spectre global 0 vdd! include "/home/eda/cadence/ic5141/tools/dfII/samples/artist/ahdlLib/quantity.6e-11 \ ad=3.0u pd=62.1/models/spectre/standalone/tsmc35N.8u l=2.2u pd=9.2u m=1 region=sat P1 (Vbp2 Vbp1 net095 vdd!) tsmc35P w=3.2e-12 ad=1.6e-12 \ ad=3.2e-12 \ ps=4.5.2e-12 ps=4.4u pd=4. Albason EEE598: Final Project 8.0u pd=62.6u l=800n as=3.2u pd=9.8u as=1.4u pd=4.0u m=1 region=sat P8 (net093 Vbp2 vdd! vdd!) tsmc35P w=30u l=400n as=3e-11 ad=3e-11 \ ps=62.

0u m=1 region=sat ends not_gate // End of subcircuit definition.27f C12 (net90 net86) capacitor c=271.27f .0000u l=400n as=1e-10 ad=1e-10 \ ps=202.0u \ pd=12. // Library name: EEE598_Amp // Cell name: switch_mos // View name: schematic subckt switch_mos S1 S2 Vctrl P0 (S2 VctrlZ S1 vdd!) tsmc35P w=10u l=400n as=1e-11 ad=1e-11 ps=22. // Library name: EEE598_Amp // Cell name: not_gate // View name: schematic subckt not_gate A Y N0 (Y A 0 0) tsmc35N w=3u l=400n as=3e-12 ad=3e-12 ps=8u pd=8u m=1 \ region=sat P0 (Y A vdd! vdd!) tsmc35P w=12.27f C26 (net90 net92) capacitor c=(1/0.0u m=1 region=sat N0 (S2 Vctrl S1 0) tsmc35N w=5u l=400n as=5e-12 ad=5e-12 ps=12.27f C56 (net078 net077) capacitor c=(1/1.4e-12 ps=6.2u \ pd=3.4e-12 \ ps=6.4u pd=4.6e-11 ps=74.4u l=400n as=2.8u pd=6.1)*271.0u m=1 region=sat I4 (Vctrl VctrlZ) not_gate ends switch_mos // End of subcircuit definition.2e-12 ad=1.0u pd=74.8u m=1 region=sat N9 (net093 Vinm net0104 0) tsmc35N w=36.2u pd=3.2e-11 \ ps=26.2e-12 ad=1.8u m=1 region=sat N7 (net0104 net0184 0 0) tsmc35N w=100.27f C74 (net0111 net075) capacitor c=(1/0.4u pd=4.0u pd=26.0u \ pd=22.2u l=400n as=1.26)*271.27f C25 (net151 net90) capacitor c=271.4e-12 \ ad=2.4u m=1 region=sat N1 (Vbp1 net0184 0 0) tsmc35N w=600n l=400n as=6e-13 ad=6e-13 ps=3.0u l=400n as=1.1)*271.26)*271.2u m=1 region=sat N0 (net0184 net0184 0 0) tsmc35N w=600n l=400n as=6e-13 ad=6e-13 \ ps=3.2e-12 \ ps=4. // Library name: EEE598_Amp // Cell name: notch_33k_opt // View name: schematic subckt notch_33k_opt Vcm Vin Vout ph1 ph2 I172 (net0102 Vcm Vout) amp_101 I32 (net142 Vcm net84) amp_101 I31 (net169 Vcm net187) amp_101 C53 (net075 net079) capacitor c=(1/1.000000u m=1 region=sat N13 (net0105 net0163 0 0) tsmc35N w=1.2e-11 ad=1.4e-12 ad=2.2u l=1u as=1.27f C13 (net184 net88) capacitor c=271.2u m=1 region=sat ends amp_101 // End of subcircuit definition.000000u pd=202.2e-12 \ ps=4.8u pd=6.0u l=400n as=3.6e-11 \ ad=3.36 Appendix N12 (net0163 Vbn net0105 0) tsmc35N w=2.4u m=1 region=sat N10 (Vout Vbn net0113 0) tsmc35N w=2.27f C73 (net0129 net075) capacitor c=271.4u l=400n as=2.0u m=1 region=sat N2 (Vbp2 net0184 0 0) tsmc35N w=1.

27f C75 (net0123 net078) capacitor c=(1/0.5p C72 (net099 net078) capacitor c=271.26)*271. Albason EEE598: Final Project C10 (net142 net84) capacitor c=4.27f I236 (Vcm net078 ph1) switch_mos I173 (net079 Vout ph1) switch_mos I187 (net077 Vout ph2) switch_mos I186 (Vcm net077 ph1) switch_mos I224 (Vcm net099 ph1) switch_mos I229 (Vcm net075 ph2) switch_mos I105 (net86 net187 ph2) switch_mos I86 (net84 net184 ph2) switch_mos I85 (Vcm net86 ph1) switch_mos I83 (Vcm net88 ph2) switch_mos I64 (Vcm net92 ph1) switch_mos I54 (net88 net169 ph1) switch_mos I45 (Vcm net184 ph1) switch_mos I42 (Vcm net151 ph1) switch_mos I41 (Vin net151 ph2) switch_mos I40 (Vcm net90 ph1) switch_mos I39 (net92 net84 ph2) switch_mos I38 (net90 net142 ph2) switch_mos I227 (Vcm net078 ph1) switch_mos I231 (net075 net0102 ph1) switch_mos I226 (Vin net0129 ph1) switch_mos I176 (Vcm net079 ph2) switch_mos I232 (net075 net0102 ph1) switch_mos I228 (net078 net0102 ph2) switch_mos I239 (Vcm net0123 ph1) switch_mos I237 (net84 net0111 ph1) switch_mos I238 (Vcm net0111 ph2) switch_mos I225 (Vcm net0129 ph2) switch_mos I230 (Vin net099 ph2) switch_mos I235 (net078 net0102 ph2) switch_mos I233 (net84 net0123 ph2) switch_mos I234 (Vcm net075 ph2) switch_mos ends notch_33k_opt // End of subcircuit definition. // Library name: EEE598_Amp // Cell name: lpf_20k_opt // View name: schematic subckt lpf_20k_opt Vcm Vin Vout ph1 ph2 I67 (net20 net2 ph2) switch_mos I71 (net121 net113 ph2) switch_mos I68 (Vcm net20 ph1) switch_mos I66 (Vin net11 ph2) switch_mos I65 (Vcm net11 ph1) switch_mos I76 (Vcm net44 ph1) switch_mos I75 (net117 net29 ph1) switch_mos I69 (Vcm net121 ph1) switch_mos I77 (Vcm net117 ph2) switch_mos I79 (Vcm net115 ph1) switch_mos I74 (net113 net44 ph2) switch_mos I80 (net115 net47 ph2) switch_mos I102 (net51 net66 ph2) switch_mos I101 (net54 net93 ph2) switch_mos 37 .Shaik.5p C8 (net169 net187) capacitor c=4.

27f C27 (net51 net54) capacitor c=(1/0.1)*271.27f C20 (net11 net20) capacitor c=271.38 Appendix I100 (Vcm net51 ph1) switch_mos I99 (net47 net132 ph2) switch_mos I98 (Vcm net132 ph1) switch_mos I95 (Vcm net130 ph1) switch_mos I93 (net78 net124 ph1) switch_mos I92 (Vcm net54 ph1) switch_mos I91 (Vcm net78 ph2) switch_mos I89 (Vcm net96 ph1) switch_mos I88 (net93 net130 ph2) switch_mos I87 (net96 Vout ph2) switch_mos I78 (net29 Vcm net47) amp_101 I73 (net2 Vcm net113) amp_101 I104 (net124 Vcm Vout) amp_101 I103 (net66 Vcm net93) amp_101 C22 (net29 net47) capacitor c=8p C19 (net2 net113) capacitor c=8p C24 (net20 net115) capacitor c=(1/1)*271.27f C33 (net45 net27) capacitor c=271.27f C32 (net124 Vout) capacitor c=8p C31 (net66 net93) capacitor c=8p C30 (net51 net96) capacitor c=(1/1.27f C34 (net27 net29) capacitor c=(1/1)*271.27f C23 (net44 net117) capacitor c=271.27f C21 (net20 net121) capacitor c=(1/4. // Library name: EEE598_Amp // Cell name: hpf_2k_opt // View name: schematic subckt hpf_2k_opt Vcm Vin Vout ph1 ph2 I31 (net63 Vcm net81) amp_101 I32 (net36 Vcm net17) amp_101 I106 (net120 Vcm Vout) amp_101 C8 (net63 net81) capacitor c=92p C10 (net36 net17) capacitor c=92p C12 (net089 net19) capacitor c=271.27f C13 (net78 net21) capacitor c=271.27f C28 (net132 net51) capacitor c=271.27f I38 (net089 net36 ph2) switch_mos I39 (net25 net17 ph2) switch_mos I40 (Vcm net089 ph1) switch_mos I41 (Vin net45 ph2) switch_mos I42 (Vcm net45 ph1) switch_mos I45 (Vcm net78 ph1) switch_mos I54 (net21 net63 ph1) switch_mos I64 (Vcm net25 ph1) switch_mos I83 (Vcm net21 ph2) switch_mos I85 (Vcm net19 ph1) switch_mos I86 (net17 net78 ph2) switch_mos .707)*271.3)*271.27f C25 (net45 net089) capacitor c=271.27f C29 (net130 net78) capacitor c=271.27f C36 (net27 net33) capacitor c=271.27f C26 (net089 net25) capacitor c=(1/0.707)*271.27f ends lpf_20k_opt // End of subcircuit definition.27f C35 (net25 net27) capacitor c=(1/0.707)*271.

0u l=400n as=1.0u m=1 region=sat P0 (Y B net31 vdd!) tsmc35P w=12.2e-11 \ ps=26.2e-11 \ ps=26.0u l=400n as=1.2e-11 ad=1.0 val1=vdd period=1/Fin rise=100p \ fall=100p width=0.Shaik.5/Fin V9 (Vin 0) vsource dc=vcm pacmag=1 type=dc V2 (Vcm 0) vsource dc=vcm type=dc V1 (vdd! 0) vsource dc=vdd type=dc 39 . // Library name: EEE598_Amp // Cell name: filter_test // View name: schematic I5 (Vcm net020 Vout ph1 ph2) notch_33k_opt I7 (Vcm net029 net020 ph1 ph2) lpf_20k_opt I8 (Vcm Vin net029 ph1 ph2) hpf_2k_opt C11 (Vout 0) capacitor c=1p I1 (net4 ph1 ph2) non_ovl_mos V3 (net4 0) vsource type=pulse val0=0. Albason EEE598: Final Project I105 (net19 net81 ph2) switch_mos I109 (Vcm net27 ph1) switch_mos I110 (net27 net120 ph2) switch_mos I111 (Vcm net29 ph1) switch_mos I113 (net29 Vout ph2) switch_mos I115 (net120 Vout ph1) switch_mos I122 (Vcm net33 ph1) switch_mos I123 (net33 net81 ph2) switch_mos ends hpf_2k_opt // End of subcircuit definition. // Library name: EEE598_Amp // Cell name: non_ovl_mos // View name: schematic subckt non_ovl_mos CLK PH1 PH2 I8 (CLK net21 PH2) nor_gate I9 (PH1 net24 net34) nor_gate I17 (net029 net030) not_gate I10 (net21 net26) not_gate I18 (net030 PH1) not_gate I11 (net26 net029) not_gate I15 (net32 net023) not_gate I16 (net24 net32) not_gate I7 (CLK net34) not_gate I19 (net024 PH2) not_gate I20 (net023 net024) not_gate ends non_ovl_mos // End of subcircuit definition.2e-11 ad=1.0u pd=26.0u pd=26. // Library name: EEE598_Amp // Cell name: nor_gate // View name: schematic subckt nor_gate A Y B N1 (Y B 0 0) tsmc35N w=3u l=400n as=3e-12 ad=3e-12 ps=8u pd=8u m=1 \ region=sat N0 (Y A 0 0) tsmc35N w=3u l=400n as=3e-12 ad=3e-12 ps=8u pd=8u m=1 \ region=sat P1 (net31 A vdd! vdd!) tsmc35P w=12.0u m=1 region=sat ends nor_gate // End of subcircuit definition.

6864M harms=2 errpreset=conservative tstab=10.0 scale=1.1u + annotate=status pac pac sweeptype=absolute start=100 stop=100k dec=200 + values=[32.40 Appendix simulatorOptions options reltol=1e-3 vabstol=1e-6 iabstol=1e-12 temp=27 \ tnom=27 scalem=1.99k 33k 33.11k 33.dc" maxiters=150 maxsteps=10000 annotate=status dcOpInfo info what=oppoint where=rawfile pss pss fund=3.output" \ checklimitdest=psf dcOp dc write="spectre./psf/sens.88k 32..0 gmin=1e-12 rforce=1 maxnotes=5 maxwarns=5 \ digits=5 cols=80 pivrel=1e-3 sensfile=".22k] maxsideband=1 + annotate=status modelParameter info what=models where=rawfile element info what=inst where=rawfile outputParameter info what=output where=rawfile designParamVals info what=parameters where=rawfile primitives info what=primitives where=rawfile subckts info what=subckts where=rawfile save Vin Vout ph1 ph2 net020 saveOptions options save=all .

Van Valkenburg  Lecture notes for EEE598 by Dr. Ken Martin at University of Toronto 41 . David Johns and Prof. Mac E.Shaik.2 Appendix B: References  VLSI Analog Signal Processing Circuits – Hongjiang Song  The Arts of VLSI Circuit Design – Hongjiang Song  Design of Analog Filters – Rolf Schaumann. Hongjiang Song at ASU  Lecture notes for Analog Filter Design by Prof. Albason EEE598: Final Project 8.