1

Ching-Yuan Yang
National Chung-Hsing University
Department of Electrical Engineering
Operational Amplifiers
類比電路設計(3349) - 2004
9-1 Ching-Yuan Yang / EE, NCHU Analog-Circuit Design
Overview
¤ Reading
B. Razavi Chapter 9.
¤ Introduction
Operational amplifiers (op amps) are an integral part of many analog and
mixed-signal systems. Op amps with vastly different levels of complexity are
used to realize functions ranging from dc bias generation to high-speed
amplification or filtering.
This lecture deals with the analysis and design of CMOS op amps.
Following a review of performance parameters, we describe simple op amps
such as telescopic and folded cascode topologies. Next, we study two-stage
and gain-boosting configurations and the problem of common-mode
feedback. Finally, we introduce the concept of slew rate and analyze the
effect of supply rejection and noise in op amps.
2
9-2 Ching-Yuan Yang / EE, NCHU Analog-Circuit Design
Performance parameters
O Gain
O Example: the circuit is designed for a nominal of 10, i.e.,
1 + R
1
/R
2
=10.
O Discussion
The close-loop gain:
1
2
2 1
1
2
2 1
1
2 1
2
1
1 A
R
R R
A
R
R R
A
R R
R
A
V
V
in
out
+
+

+
=
+
+
=
If A
1
>> (R
1
+ R
2
)/R
2
, then
|
|
.
|

\
| +

|
|
.
|

\
|
+ ≈
1 2
2 1
2
1
1
1 1
A R
R R
R
R
V
V
in
out
The term (R
1
+ R
2
)/(R
2
A
1
) = (1 + R
1
/R
2
)/ A
1
represents the relative error.
To achieve a gain error less than 1%, we must have A
1
> 1000.
Simple CS stage – an open-loop implementation:
10 = =
D m
in
out
R g
V
V
However, it is difficult to guarantee an error less than 1%.
The variations in the mobility and gate oxide thickness of the transistor and
the value of the resistor typically yield an error greater than 20%.
9-3 Ching-Yuan Yang / EE, NCHU Analog-Circuit Design
Performance parameters (cont’d)
O Small-signal bandwidth
O Large-signal bandwidth – slew rate
unity-gain
dB
Gain roll-off with frequency
3
9-4 Ching-Yuan Yang / EE, NCHU Analog-Circuit Design
Performance parameters (cont’d)
O Output swing – Most systems employing op
amps require large voltage swings to
accommodate a wide range of signal amplitudes.
O Linearity – Open-loop op amps suffer from
substantial nonlinearity. For example, the input
pair M
1
– M
2
exhibits a nonilinear relationship
between its differential drain current and input
voltage. In many feedback circuits, the linearity
requirement, rather than the gain error
requirement, governs the choice of the open-loop
gain.
O Noise and offset – The input noise and offset of
op amps determine the minimum signal level that
can be processed with reasonable quality.
O Supply rejection – Op amps are often employed
in mixed-signal systems and sometimes
connected to noise digital supply lines. Thus, the
performance of op amps in the presence of supply
noise is quite important. For this reason, fully
differential topologies are preferred.
9-5 Ching-Yuan Yang / EE, NCHU Analog-Circuit Design
One-stage op amps
Simple op amp topologies
Differential input & single-ended output Differential input & differential output
For small-signal:
O Low frequency gain = g
mN
(r
oN
,, r
oP
). In general, this value hardly
exceeds 20 in submicron devices with typical current levels.
O The bandwidth is usually determined by the load capacitance, C
L
.
O The circuits suffer from noise contributions of M
1
-M
4
. In all op amp
topologies, at least four devices contribute to the input noise: two
input transistors and two “load” transistors.
4
9-6 Ching-Yuan Yang / EE, NCHU Analog-Circuit Design
Unit-gain buffer
V
CSS
Input common-mode voltage range
V
in,min
= V
CSS
+ V
GS1
V
in,max
= V
DD
− ,V
GS3
, + V
TH1
If each device has a threshold voltage of 0.7V and an overdrive
of 0.3V, then V
in,min
= 1.3V, and V
in,max
= 2.7V. Thus, the input
CM range equals 1.4V with a 3-V supply.
Output impedance
( )
mN oN oP mN
oN oP
open v
open out
out
g r r g
r r
A
R
R
1
1 1
,
,

+
=
+
=
β
The close-loop output impedance is relatively
independent of the open-loop output impedance.
Allowing us to design high-gain op amps by increasing
the open-loop output impedance while still achieving a
relatively low close-loop output impedance.
9-7 Ching-Yuan Yang / EE, NCHU Analog-Circuit Design
Telescope cascode op amps
In order to achieve a high gain, the differential cascode topologies can be used.
Low-frequency gain A
v
= g
mN
[(g
mN
r
oN
2
) ,, (g
mP
r
oP
2
)], but at the cost of output
swing and adding poles.
5
9-8 Ching-Yuan Yang / EE, NCHU Analog-Circuit Design
(a): The circuit providing a single-ended output suffers from a mirror pole at
node X, creating stability issues.
(b): Fully differential topology, the output swing is given by
2[V
DD
− (V
OD1
+ V
OD3
+ V
CSS
+ ,V
OD5
, + ,V
OD7
,)]
where V
ODj
denotes the overdrive voltage of M
j
.
Another drawback of telescopic cascodes is the difficult in shorting their inputs
and outputs, e.g., to implement a unity-gain buffer.
9-9 Ching-Yuan Yang / EE, NCHU Analog-Circuit Design
Telescope cascode op amps (cont’d)
Cascode op amp with input and output shorted
– unit gain feedback topology
O Output swing: M2 and M4 in saturation:
2 4 4
4
2
TH GS b out TH b
TH b out
TH X out
V V V V V V
V V V
V V V
+ − ≤ ≤ − ⇒
¹
´
¦
− ≥
+ ≤
the voltage range V
max
− V
min
= V
TH4
− (V
GS4
− V
TH2
)
O Since the op amp attempts to force V
out
to be equal to
V
in
, for V
in
< V
b
− V
TH4
, we have V
out
≈ V
in
and M
4
is in
triode region while others are saturated. Under this
condition, the open-loop gain of the op amp is reduced.
O As V
in
and V
out
hence exceed V
b
− V
TH4
, M
4
enters
saturation and the open-loop gain reaches a maximum.
For V
b
− V
TH4
< V
in
< V
b
− (V
GS4
− V
TH2
), both M
2
and
M
4
are saturated and for V
in
> V
b
− (V
GS4
− V
TH2
), M
2
and M
1
enter the triode region, degrading the gain. Thus,
a cascode op amp is rarely used as a unit-gain buffer.
6
9-10 Ching-Yuan Yang / EE, NCHU Analog-Circuit Design
Design of fully differential telescope op amp
Specifications:
V
DD
= 3V, differential output swing = 3V,
power dissipation = 10mW, voltage gain = 2000.
Assume µ
n
C
ox
= 60 µA/V
2
, µ
p
C
ox
= 30 µA/V
2
, λ
n
= 0.1V
−1
, λ
p
= 0.2V
−1
(for an
effective channel length of 0.5 µm), γ = 0, V
THN
= ,V
THP
, = 0.7V.
¤ Power budget:
I
M9
= 3mA, I
Mb1
+ I
Mb2
= 330µA
¤ Output swing:
Node X(Y) swing = 1.5V, M
3
-M
6
in saturation.
For M
9
,
,V
OD7
, + ,V
OD5
, + V
OD3
+ V
OD1
+ V
OD9
= 1.5V
Since M9 carrying largest current,
V
OD9
≈ 0.5V is chosen. ,V
OD5
, = ,V
OD7
, ≈ 0.3V,
V
OD1
= V
OD3
≈ 0.2V.
¤ W/L:
By I
D
= (1/2)µCox(W/L)(V
GS
− V
TH
)
2
, we have
(W/L)
1−4
= 1250, (W/L)
5−8
= 1111, (W/L)
9
= 400.
9-11 Ching-Yuan Yang / EE, NCHU Analog-Circuit Design
¤ Gain:
A
v
≈ gm1[(g
m3
r
o3
r
o1
),, (g
m5
r
o5
r
o7
)]. In order to Increase the gain,
we recognize
where λ ∝ 1/L. We can therefore increase the width or length.
Choose (W/L)
5−8
= 1111µm/1µm,
then A
v
≈ 4000
.
¤ CM level & bias:
Min. allowable input CM level
= V
GS1
+ V
OD9
= 1.4V.
V
b1
,
min
= V
GS3
+ V
OD1
+ V
OD9
= 1.6V.
V
b2
,
max
= V
DD
− (,V
GS5
|+ ,V
OD7
,) = 1.7V.
D D D ox o m
I WL I I L W C r g / ) /( ) / ( 2 ∝ = λ µ
7
9-12 Ching-Yuan Yang / EE, NCHU Analog-Circuit Design
Folded cascode op amps
In order to alleviate the drawbacks
of telescopic cascode op amps. The
primary advantage of the folded
structure lies in the choice of the
voltage levels because it does not
stack the cascode transistor on the
top of the input device.
9-13 Ching-Yuan Yang / EE, NCHU Analog-Circuit Design
Folded cascode op amps (cont’d)
O Two important differences between the two circuits:
Þ In Fig.(a), one bias current, I
SS
, provides the drain current of both the input
transistors and the cascode devices.
In Fig.(b), the input pair requires an additional bias current, I
SS1
= I
SS
/2 + I
D3
.
Þ In Fig.(a), the input CM level cannot exceed V
b1 − V
GS3
+ V
TH1
,whereas in
Fig.(b), it cannot be less than V
b1 − V
GS3
+ ,V
TH1,.
O In Fig.(b), it is possible to tie the n-well of M
1
and M
2
to their common source point.
8
9-14 Ching-Yuan Yang / EE, NCHU Analog-Circuit Design
Folded cascode op amps (cont’d)
Folded cascode op amp with cascode PMOS loads
O Max. output voltage swing: With proper choice of V
b1
and V
b2
,
Peak-peak swing = [V
DD
− (,V
OD7
, + ,V
OD9
,)] − (V
OD3
+ V
OD5
) for one side.
O The swing is lager by the overdrive of the tail current source in the telescopic
cascode.M
5
and M
6
may require a high overdrive voltage if their capacitance
contribution to nodes X and Y is to be minimized.
9-15 Ching-Yuan Yang / EE, NCHU Analog-Circuit Design
Folded cascode op amps (cont’d)
Small-signal voltage gain
Half circuit
,A
v
, = G
m
R
out
Equivalent circuit with
output shorted to ground
Since (g
m3
+g
mb3
)
−1
,,r
o3
<< r
o1
,,r
o5
,
I
out
≈ I
D1
. That is G
m
≈ g
m1
.
Equivalent circuit with
output open
R
OP
≈ (g
m7
+ g
mb7
) r
o7
r
o9
R
out
≈ R
OP
,, [(g
m3
+g
mb3
)r
o3
(r
o1
,,r
o5
)]
Thus, ,A
v
, ≈ g
m1
{[(g
m3
+g
mb3
)r
o3
(r
o1
,,r
o5
)] ,, [(g
m7
+ g
mb7
) r
o7
r
o9
]}
The gain is usually two or three times lower than of a comparable telescopic cascode.
9
9-16 Ching-Yuan Yang / EE, NCHU Analog-Circuit Design
Folded cascode op amps (cont’d)
Effect of device capacitance on the nondominant pole in telescopic and folded cascode
op amps
C
tot
= C
GS3
+ C
SB3
+ C
DB1
+ C
GD1
C
tot
= C
GS3
+ C
SB3
+ C
DB1
+ C
GD1
+ C
GD5
+ C
DB5
The pole at the “folding point,” i.e., the sources of M
3
and M
4
, is quite closer to the
origin than that associated with the source of cascode devices in a telescopic
topology.
9-17 Ching-Yuan Yang / EE, NCHU Analog-Circuit Design
A high-gain folded cascode op amp
The circuit provides a higher gain because of the greater mobility of NMOS
devices, but at the cost of lowering the pole at the folding point,
ω
p,X
≈ (g
m3
+ g
mb3
) / C
tot,X
.
10
9-18 Ching-Yuan Yang / EE, NCHU Analog-Circuit Design
Telescopic- & folded-cascode op amps: Discussion
¤ The overall voltage swing of a folded-cascode op amp is only slightly higher than that of a
telescopic configuration. This advantage comes at the cost of higher power dissipation,
lower voltage gain, lower pole frequencies, and higher noise.
¤ Folded-cascode op amps are used quite widely, even more than telescopic topologies,
because the input and outputs can be shorted together and the choice of the input
common-mode level is easier.
O In a telescopic op amp, three voltages must be defined carefully: the input CM level
and the gate bias voltages of the PMOS and NMOS cascode transistors, whereas in
folded-cascode configurations only the latter two are critical.
O In folded-cascode op amps, the capability of handling input CM levels are close to
one of the supply rails.
9-19 Ching-Yuan Yang / EE, NCHU Analog-Circuit Design
Design of folded-cascode op amp
Specifications:
V
DD
= 3V, differential output swing = 3V,
power dissipation = 10mW, voltage gain = 2000.
Assume µ
n
C
ox
= 60 µA/V
2
, µ
p
C
ox
= 30 µA/V
2
, λ
n
= 0.1V
−1
, λ
p
= 0.2V
−1
(for an
effective channel length of 0.5 µm), γ = 0, V
THN
= ,V
THP
, = 0.7V.
11
9-20 Ching-Yuan Yang / EE, NCHU Analog-Circuit Design
¤ Power budget: I
M11
= 1.5mA, I
M9
+ I
M10
= 1.5mA, I
Mb1
+ I
Mb2
+ I
Mb3
= 330µA.
¤ Output swing: one side o/p swing = 1.5V, M
3
-M
10
in saturation.
Choose ,V
OD5,6
, ≈ 0.5V, ,V
OD3,4
, ≈ 0.4V, V
OD7,8
= V
OD9,10
≈ 0.3V.
¤ W/L:By I
D
= (1/2)µCox(W/L)(V
GS
− V
TH
)
2
, we have
(W/L)
5,6
= 400, (W/L)
3,4
= 313, (W/L)
7−10
= 555.
¤ O/p CM level: CM
min
= 0.6V, CM
max
= 2.1V, thus CM
opt
= 1.35V.
9-21 Ching-Yuan Yang / EE, NCHU Analog-Circuit Design
¤ Determine (W/L)
1,2
: min. input CM level = V
GS1
+ V
OD11
.
If input and output are shorted, then V
GS2
+ V
OD11
= 1.35V,
and V
GS1
= 0.95V = V
OD1,2
= 0.25V = (W/L)
1,2
= 400.
The maximum dimensions of M
1,2
are determined by the tolerable input
capacitance at nodes X and Y.
¤ Gain: g
m
= 2I
D
/(V
GS − V
TH
), we have
g
m1,2
= 0.006 A/V, g
m3,4
= 0.0038 A/V, g
m7,8
= 0.05 A/V.
For L = x µm, find r
o
.
Note |A
v
| ≈ g
m1
{[(g
m3
+ g
mb3
)r
o3
(r
o1 ,, r
o5
)] ,, [(g
m7
+ g
mb7
) r
o7
r
o9
]}
12
9-22 Ching-Yuan Yang / EE, NCHU Analog-Circuit Design
Cascode op amps with single-ended output
Fig(a): V
X
= V
DD − ,V
GS5, − ,V
GS7,,
limiting the maximum value of
V
out
to V
DD − ,V
GS5, − ,V
GS7, −
,V
TH6, and wasting one PMOS
threshold voltage in the swing.
Fig(b): To solve above issue, M
7
and
M
8
are biased at the edge of
the triode region.
¤ Disadvantages: (1) it provides only half the output voltage swing.
(2) it contains a mirror pole at node X, thus limiting the speed
of feedback systems employing such an amplifier.
¤ It is preferable to use the differential topology, although it requires a feedback
loop to define the output CM level.
9-23 Ching-Yuan Yang / EE, NCHU Analog-Circuit Design
Triple-cascode op amp
The “triple cascode” topology provides
a gain on the order of (g
m
r
o
)
3
/2 but
further limits the output swings. With
six overdrive voltages subtracted from
V
DD
in this circuit, it is difficult to
operate the amplifier from a supply
voltage or lower while obtaining
reasonable output swings.
13
9-24 Ching-Yuan Yang / EE, NCHU Analog-Circuit Design
Two-stage op amps
¤ The gain of one-stage topologies is limited to the input pair transconductance
and the output impedance.
¤ Two-stage op amps consist of first stage providing a high gain and the second
providing large swing. The first stage incorporates various amplifier topologies,
but the second stage is typically configured as a simple common- source
stage to allow maximum output swings.
¤ Can we cascade more than two stages to achieve a higher gain?
Each gain stage introduces at least one pole in the open-loop transfer function,
making it difficult to guarantee stability in a feedback system using such an op
amp. For this reason, op amps having more than two stages are rarely used.
9-25 Ching-Yuan Yang / EE, NCHU Analog-Circuit Design
Simple implementation of a two-stage op amp
Gain:
A
v,1st stage
= g
m1,2
(r
o1,2
,, r
o3,4
)
A
v,2nd stage
= g
m5,6
(r
o5,6
,, r
o7,8
)
Overall gain A
v
= A
v,1st stage
× A
v,2nd stage
Output swing = V
DD
− ,V
OD5,6
, − V
OD7,8
14
9-26 Ching-Yuan Yang / EE, NCHU Analog-Circuit Design
Two-stage op amp employing cascoding
To obtain a higher, the first stage incorporate cascode devices. The overall voltage gain is
A
v
≈ {g
m1,2
[(g
m3,4
+ g
mb3,4
)r
o3,4
r
o1,2
] ,, (g
m5,6
+ g
mb5,6
)r
o5,6
r
o7,8
]} × [g
m9,10
(r
o9,10
,, r
o11,12
)]
9-27 Ching-Yuan Yang / EE, NCHU Analog-Circuit Design
Two-stage op amp with single-ended output
Note that if the gate of M
1
is shorted to V
out
to form a unity-gain buffer,
then the minimum allowable output level is equal to V
GS1
+ V
ISS
, severely
limit the output swing.
15
9-28 Ching-Yuan Yang / EE, NCHU Analog-Circuit Design
Gain boosting
Increasing the output impedance by feedback
R
out
= g
m2
r
o2
r
o1
M
1
operates as a degeneration resistor.
O The voltage variations at the drain of M
2
effect V
X
to a
lesser extent because A
1
regulates this voltage. (V
X
= V
b
)
With smaller variations at X, the current through r
o1
and
hence the output current remains more constant,
yielding a higher output impedance.
O R
out
≈ A
1
g
m2
r
o2
r
o1
,
R
out
is booted substantially without stacking more
cascode devices on top of M
2
.
9-29 Ching-Yuan Yang / EE, NCHU Analog-Circuit Design
Gain boosting in cascode stage
For small-signal operation, V
b
is set to zero.
regulated cascode
Gain:
,A
v
, ≈ g
m1
(g
m2
r
o2
r
o1
) (g
m3
r
o3
)
Min. output swing:
Since V
X
= V
GS3
, the min.value of
V
out
is V
OD2
+ V
GS3
. The auxiliary
amplifier limits the output swing.
Note: Min. output swing is V
OD2
+
V
OD1
in a simple cascode.
16
9-30 Ching-Yuan Yang / EE, NCHU Analog-Circuit Design
Boosting output impedance of a differential cascode stage
¤ The minimum level at the drain of M
3
is
equal to V
OD3
+ V
GS5
+ V
ISS2
.
¤ The voltage swing limitation results the fact
that the gain-boosting amplifier incorporates
an NMOS differential pair.
9-31 Ching-Yuan Yang / EE, NCHU Analog-Circuit Design
Folded-cascode circuit used as auxiliary amplifier
Half circuit
¤ If nodes X and Y are sensed by a PMOS pair, the minimum value of V
X
and
V
Y
is not dictated by the gain-boosting amplifier.
¤ The minimum allowable level of V
X
and V
Y
is given by V
OD1,2
+ V
ISS1
.
¤ Output impedance: Since
1 5 out m
X
P
R g
V
V
=
where R
out1
≈ [g
m7
r
o7
(r
o9
,,r
o5
)] ,, (g
m11
r
o11
r
o13
), R
out
≈ g
m3
r
o3
r
o1
g
m5
R
out1
.
17
9-32 Ching-Yuan Yang / EE, NCHU Analog-Circuit Design
Gain boosting applied to both signal path and load devices
Regulated cascodes can also be utilized in the load current sources of a
cascode op amp.
9-33 Ching-Yuan Yang / EE, NCHU Analog-Circuit Design
Comparison of performance of various op amp topologies
Gain
Medium
Medium
High
High
Output
Swing
Medium
Medium
Highest
Medium
Speed
Low
Medium
Highest
High
Low
Medium
Medium
High
Power
Dissipation
Noise
Low
Medium
Low
Medium
Telescopic
Folded-Cascode
Two-stage
Gain-Boosted
18
9-34 Ching-Yuan Yang / EE, NCHU Analog-Circuit Design
Common-mode feedback (CMFB)
¤ Full differential circuits have many advantages over their single-ended
counterparts such as greater output swings, avoiding mirror poles, higher
closed-loop speed. However, high-gain differential circuits require common-
mode feedback.
¤ Simple differential pair
Input & output common-mode
level is equal to V
DD
− I
SS
R
D
/2
9-35 Ching-Yuan Yang / EE, NCHU Analog-Circuit Design
High-gain differential pair with inputs shorted to outputs
¤ What is the common-mode level at nodes X and Y?
Since each of the input transistors carries a current I
SS
/2, the CM level depends on
how close I
D3
and I
D4
are to this value.
¤ Effect of current mismatches: Mismatches in the PMOS and NMOS current mirrors
defining I
SS
and I
D3,4
create a finite error between I
D3,4
and I
SS
/2.
If I
D3,4
> I
SS
/2, then both M
3
and M
4
must enter the triode region so that their drain
currents fall to I
SS
/2. Conversely, If I
D3,4
< I
SS
/2, then both V
X
and V
Y
must drop so
that M
5
enters the triode region, thereby producing only 2I
D3,4
.
19
9-36 Ching-Yuan Yang / EE, NCHU Analog-Circuit Design
Simplified model of high-gain amplifier
In high-gain amplifiers, we wish a p-type current source to balance an n-type current
source.
( )( )
N P N P
R R I I V − = ∆
O Since the current error depends on mismatches and R
P
,,R
N
is quite high, the voltage
error may be large, thus driving the p-type or n-type current source into triode region.
O As a general rule, if the output CM level cannot be determined by “visual inspection”
and requires calculations based on device properties, then it is poorly defined.
O In high-gain amplifiers, the output CM level is quite sensitive to device properties and
mismatches and it cannot be stabilized by means of differential feedback. Thus a
CMFB network must be added to sense the CM level of the two outputs and
accordingly adjust one of the bias currents in the amplifier.
9-37 Ching-Yuan Yang / EE, NCHU Analog-Circuit Design
Conceptual topology for CMFB
In high-gain amplifiers, the output CM level is quite sensitive to device properties and
mismatches and it cannot be stabilized by means of differential feedback. Thus a CMFB
network must be added to sense the CM level of the two outputs and accordingly adjust
one of the bias currents in the amplifier.
20
9-38 Ching-Yuan Yang / EE, NCHU Analog-Circuit Design
CMFB with resistive sensing
¤ Output CM level: V
out,CM
= (V
out1
+ V
out2
)/2
¤ Resistive divider level: V
out,CM
= (R
1
V
out2
+ R
2
V
out1
)/(R
1
+ R
2
)
= (V
out1
+ V
out2
)/2, if R
1
= R
2
.
¤ R
1
and R
2
must be much larger than the output impedance of the op amp
so as to avoid lowering the open-loop gain.
9-39 Ching-Yuan Yang / EE, NCHU Analog-Circuit Design
CMFB using source followers
Current starvation of source followers for large swings
¤ This technique produces a CM level
that is lower than the output CM
level by V
GS7,8
, but this shift can be
taken into account in the
comparison operation.
¤ R
1
and R
2
or I
1
and I
2
must be large
enough to ensure that M
7
or M
8
is
not starved when a large differential
swing appears at the output.
¤ If V
out2
is quite higher than V
out1
, then I
1
must sink both I
X ≈ (V
out2 − V
out1
)/(R
1
+ R
2
)
and I
D7
. Consequently, if (R
1
+ R
2
) or I
1
is
not sufficiently large, I
D7
drops to zero
and V
out
,
CM
no longer represents the true
output CM level.
¤ This sensing method limits the differential
output swings. The swing at each output is
reduced by approximately V
TH
, a significant
value in low-voltage design.
21
9-40 Ching-Yuan Yang / EE, NCHU Analog-Circuit Design
CMFB using MOSFET operating in deep triode region
( ) ( )
( )
TH out out ox n
TH out ox n TH out ox n
on on P
V V V
L
W
C
V V
L
W
C V V
L
W
C
R R R
2
1
1 1
2 1
2 1
8 7
− +
=
− −
=
=
µ
µ µ
R
P
is a function of V
out1
+ V
out2
but independent of
V
out2
− V
out1
.
The use of M
7
and M
8
limits the output voltage swings, V
out,min
= V
TH7,8
, which is
relatively close to two overdrive voltages, but the difficulty arises from the assumption
above that both M
7
and M
8
operate in deep triode region. If V
out1
drops from the
equilibrium CM level to one threshold voltage above ground and V
out2
rises by the same
amount, then M
7
enters the saturation region, thus exhibiting a variation in its on-
resistance that is not counterbalanced by that of M
8
.
¤ Identical transistors M7 and M8 operate in deep triode region,
9-41 Ching-Yuan Yang / EE, NCHU Analog-Circuit Design
Sensing and controlling output CM level
¤ We employ a simple amplifier to detect the difference between V
out
,
CM
and a reference
voltage, V
REF
, applying the result to the NMOS current sources with negative feedback.
If the loop gain is large, the feedback network forces the CM level of V
out1
and V
out2
to
approach V
REF
.
¤ Also, the feedback may control only a fraction of the current to allow optimization of the
settling behavior. For example, each M
3
and M
4
can be decomposed into two parallel
devices, one biased at a constant current and the other driven by the error amplifier.
22
9-42 Ching-Yuan Yang / EE, NCHU Analog-Circuit Design
Alternative method of controlling output CM level
¤ In a folded-cascode op amp, the CM feedback may control the tail current
of the input differential pair. This method increases the tail current if V
out1
and V
out2
rise, lowering the drain currents of M
5
−M
6
and restoring the output
CM level.
9-43 Ching-Yuan Yang / EE, NCHU Analog-Circuit Design
CMFB using triode devices
¤ The output CM level sets R
on7
,, R
on8
such that
I
D5
and I
D6
exactly balance I
D9
and I
D10
, respectively.
¤ Assuming I
D9
= I
D10
= I
D
,
R
P
= R
on7
,, R
on8
= (V
b
− V
GS5
)/(2I
D
), and also
( )
TH out out ox n
P
V V V
L
W
C
R
2
1
1 2
8 , 7
− +
|
.
|

\
|
=
µ
where
( )
5
5
5
/
2
TH
ox n
D
GS
V
L W C
I
V + =
µ
¤ Drawbacks:
1.The value of the output CM level is a function of device
parameters.
2.The voltage drop across R
on7
,,R
on8
limits the output voltage swing.
3.To minimize this drop, M
7
and M
8
are usually quite wide devices, introducing
substantial capacitance at the output.
23
9-44 Ching-Yuan Yang / EE, NCHU Analog-Circuit Design
Alternative method of controlling output CM level
¤ If V
b
is higher than expected, the tail current of M
1
and
M
2
increases and the output CM level falls. Since the
feedback through M
7
and M
8
attempts to correct this
error, the overall change in V
out,CM
depends on the loop
gain in the CMFB network.
¤ Determine the sensitivity dV
out,CM
/dV
b
:
M
7,8
in triode region: g
m7,8
= µ
n
C
ox
(W/L)
7,8
V
DS7,8
Feedback factor:
( )( )
TH GS
DS
on on m m
I
V V
V
R R g g
V
V

− = + − = =
=
8 , 7
8 , 7
8 7 8 7
0
1
2
2
β
Thus,
8 , 7
8 , 7 ,
1
DS
TH GS
b
CM out
V
V V
dV
dV −
= ≈
β
Since V
GS7,8
(i.e., the output CM level) is typically
in the vicinity of V
DD
/2, the above equation
suggests that V
DS7,8
must be maximized.
9-45 Ching-Yuan Yang / EE, NCHU Analog-Circuit Design
Modification of CMFB for more accurate definition of output MC level
¤ The idea is to define V
b
by a current mirror arrangement such that I
D9
tracks I
1
and I
REF
.
¤ Suppose (W/L)
15
= (W/L)
9
and (W/L)
16
= (W/L)
7
+ (W/L)
8
.
Thus, I
D9
= I
1
only if V
out
,
CM
= V
REF
.
The circuit produces an output CM level equal to a reference but it requires no resistors in
sensing V
out
,
CM
.
¤ In practice, since V
DS15 ≠ V
DS9
, channel-length modulation results in a finite error.
24
9-46 Ching-Yuan Yang / EE, NCHU Analog-Circuit Design
Modification to suppress error due to channel-length modulation
¤ Transistors M
17
and M
18
reproduce at the drain of M
15
a voltage equal to the
source voltage M
1
and M
2
, ensuring that V
DS15
= V
DS9
.
9-47 Ching-Yuan Yang / EE, NCHU Analog-Circuit Design
Another CM feedback topologies
¤ Differential pair using diode-connected loads
O The input CM level, V
DD
− V
GS3,4
, is relatively
well-defined, but the voltage gain is quite low.
¤ Resistive CMFB
O To increase the differential gain, the PMOS
device must operate as current sources for
differential signals.
O For differential change at Vout1 and V
out2
, node
P is a virtual ground and the gain can be
expresses as
A
v
= g
m1,2
(r
o1,2
,,r
o3,4
,,R
F
)
O For CM levels, M
3
and M
4
operate as diode-
connected devices.
25
9-48 Ching-Yuan Yang / EE, NCHU Analog-Circuit Design
Input range limitations
¤ Limitation: While the differential input swings are usually much smaller, the input
common-mode level may need to vary over a wide range in some applications.
¤ Unity-gain buffer
O The voltage swings are limited by the input differential pair rather than the
output cascode branch. Specifically, V
in
,
min ≈ V
out
,
min
= V
GS1,2
+ V
ISS
, approximately
one threshold voltage higher than the allowable minimum provided by M
5
-M
8
.
O If V
in
< V
in
,
min
: The MOS transistor operating as I
SS
enters the triode region,
decreasing the bias current of the differential pair and hence lowering the
transconductance.
9-49 Ching-Yuan Yang / EE, NCHU Analog-Circuit Design
Extension of input CM range
Variation of equivalent transconductance with
the input CM level.
¤ A simple approach to extending the
input CM range is to incorporate
both NMOS and PMOS differential
pairs such that when one is “dead”,
the other is “alive”. This idea is to
combine two folded-cascode op amps
with NMOS and PMOS input
differential pairs.
¤ As the input CM level approaches the
ground potential, the NMOS pair’s
transconductance drops, eventually
falling to zero. Nonetheless, the PMOS
pair remains active, allowing normal
operation. Conversely, if the input CM
level approaches V
DD
, M
1P
and M
2P
begin to turn off but M
1
and M
2
function
properly.
26
9-50 Ching-Yuan Yang / EE, NCHU Analog-Circuit Design
Slew rate
¤ Response of a linear circuit to input
step
O dV
out
/dt: Since V
out
= V
0
[1 − exp(−t/τ)], where τ = RC, we have
τ τ
t V
dt
dV
out

= exp
0
O dV
out
/dt ∝ V
0
; if we apply a larger input step, the output rises more rapidly.
9-51 Ching-Yuan Yang / EE, NCHU Analog-Circuit Design
Slew rate (cont’d)
¤ Response of a linear op amp to step response
O Assume op amp is linear,
s C V
R R
V
R
V A
R R
R
V V
L out
out
out
out out in
+
+
=
(
¸
(

¸


|
|
.
|

\
|
+

2 1 2 1
2
1
Assume R
1
+ R
2
>> R
out
, we have
( )
( )
(
¸
(

¸

+ +
+
|
|
.
|

\
|
+
+

s
R R AR
C R
R R
R
A
A
s
V
V
L out in
out
2 1 2 2 1
2
1
1 1
The step response is given by
( )
( ) t u
R R AR
R C
t
R R
R
A
A
V V
out L
out
|
|
|
|
.
|

\
|
+ +


+
+
=
2 1 2 2 1
2
0
1
exp 1
1
indicating that the slope is proportional to the final value.
This type of response is called “linear settling.”
27
9-52 Ching-Yuan Yang / EE, NCHU Analog-Circuit Design
Slew rate (cont’d)
¤ Slewing in an op amp circuit
( )
( ) t u
R R AR
R C
t
R R
R
A
A
V V
out L
out
|
|
|
|
.
|

\
|
+ +


+
+
=
2 1 2 2 1
2
0
1
exp 1
1
O The response to sufficiently small inputs follows the exponential of Eq.(A), but
with large input steps, the output displays a linear ramp having a constant slope.
Under this condition, we say the op amp experiences slewing and call the slop of
the ramp the “slew rate.”
……..(A)
9-53 Ching-Yuan Yang / EE, NCHU Analog-Circuit Design
Small-signal operation of a simple op amp
¤ Assuming that R
1
+ R
2
is quite large.
If V
in
experiences a change of ∆V, the total small-signal current provided
by the op amp equals g
m
∆V. This current begins to change C
L
, but as V
out
rises, so does V
X
, reducing the difference between V
G1
and V
G2
and hence
the output current of the op amp.
28
9-54 Ching-Yuan Yang / EE, NCHU Analog-Circuit Design
Slewing during large signal transition
¤ Slewing during low-to-high transition
M1 absorbs all of I
SS
and M
2
turns off.
So long as M
2
remains off, the feedback
loop is broken and the current charging
C
L
is constant and independent of the
input level.
¤ Slewing during high-to-low transition
Slope = I
SS
/C
L
9-55 Ching-Yuan Yang / EE, NCHU Analog-Circuit Design
Discussion of slew rate
¤ While the small-signal bandwidth of a circuit may suggest a fast time-domain
response, the large-signal speed may be limited by the slew rate simply
because the current available to charge and discharge the dominant
capacitor in the circuit is small.
¤ Since the input/output relationship during slewing is nonlinear, the output of
a skewing amplifier exhibits substantial distortion.
O For example, if a circuit is to amplify a sinusoid V
0
sinω
0
t (in the steady
state), then its slew rate must exceed V
0
ω
0
.
29
9-56 Ching-Yuan Yang / EE, NCHU Analog-Circuit Design
Slewing in telescopic op amp
V
out1
and V
out2
appear as a ramps with slopes equal to ±I
SS
/(2C
L
), and
consequently V
out1
− V
out2
exhibits a slew rate equal to I
SS
/C
L
.
9-57 Ching-Yuan Yang / EE, NCHU Analog-Circuit Design
Slewing in folded-cascode op amp
¤ If I
P
≥ I
SS
, the slew rate is equal to I
SS
/C
L
, independent of I
P
.
30
9-58 Ching-Yuan Yang / EE, NCHU Analog-Circuit Design
Slewing in folded-cascode op amp (cont’d)
¤ If I
SS
> I
P
, then during slewing M
3
turns off and V
X
falls to a low level such that M
1
and the tail current source enters the triode region. Thus, for the circuit to return to
equilibrium after M
2
turns on, V
X
must experience a large swing, slow down the
settling.
9-59 Ching-Yuan Yang / EE, NCHU Analog-Circuit Design
Slewing in folded-cascode op amp (cont’d)
¤ Clamp circuit to limit swings at X and Y
The difference between I
SS
and I
P
flows through
M
11
, or M
12
, requiring only enough drop in V
X
or
V
Y
to return on one of these transistors.
M
11
and M
12
clamp the two nodes directly to V
DD
.
Since the equilibrium value V
X
and V
Y
is usually
higher than V
DD
− V
THN
, M
11
and M
12
are off
during small signal-signal operation.
31
9-60 Ching-Yuan Yang / EE, NCHU Analog-Circuit Design
Power supply rejection
¤ If the circuit in the figure is perfectly symmetric, V
out
= V
X
.
Since the diode-connected device “clamps” node X to V
DD
V
X
and hence V
out
experience approximately the same
change as does V
DD
. In other words, the gain from V
DD
to
V
out
is
1 ≈


DD
out
V
V
¤ The power supply rejection ratio (PSRR) is defined as
the gain from the input to the output divided by the gain
from the supply to the output. At low frequencies:
( )
oN oP mN
DD out
in out
r r g
V V
V V
PSRR ≈
∂ ∂
∂ ∂
=
9-61 Ching-Yuan Yang / EE, NCHU Analog-Circuit Design
Noise in a telescopic op amp
¤ Guide: With many transistors in an op amp, it may seem difficult to intuitively identify
the dominant sources of noise. A simple rule for inspection is to change the gate
voltage of each transistor by a small amount and predict the effect at the output.
At relatively low frequency, the
cascode devices contribute negligible
noise, leaving M
1
-M
2
and M
7
-M
8
as the
primary noise sources.
The input-referred noise voltage per unit bandwidth is given by
( ) ( )
2
2 , 1
2
8 , 7
8 , 7 2 , 1
2
2 , 1
8 , 7
2 , 1
2
2 2
3
2
2
3
2
2 4
m
m
ox
P
ox
N
m
m
m
n
g
g
f C WL
K
f C WL
K
g
g
g
kT V ⋅ + +
|
|
.
|

\
|
+ =
where K
N
and K
P
denote the 1/f noise coefficients of NMOS
and PMOS devices, respectively.
32
9-62 Ching-Yuan Yang / EE, NCHU Analog-Circuit Design
Noise in a fold-cascode op amp
¤ The noise of the cascode devices is negligible at low frequencies,
leaving M
1
-M
2
, M
7
-M
8
, and M
9
-M
10
as potentially significant sources.
¤ Thermal noise:
|
|
.
|

\
|
=
2 2
8 , 7
8 , 7
8 , 7
2
,
3
2
4 2
out m
m
M out n
R g
g
kT V
|
|
.
|

\
|
=
2 2
10 , 9
10 , 9
10 , 9
2
,
3
2
4 2
out m
m
M out n
R g
g
kT V
|
|
.
|

\
|
=
2 2
2 , 1
2 , 1
2 , 1
2
,
3
2
4 2
out m
m
M out n
R g
g
kT V
and A
v
= g
m1,2
R
out
.
Total input-referred thermal noise:
|
|
.
|

\
|
+ + = =
2
2 , 1
10 , 9
2
2 , 1
8 , 7
2 , 1
2
2
, , 2
,
3
2
3
2
3
2
8
m
m
m
m
m v
tot out n
in n
g
g
g
g
g
kT
A
V
V
, (uncorrelated noise)
where the factor 2 accounts for noise of M7 and M8, and
Rout denotes the open-loop output resistance of the op
amp.
9-63 Ching-Yuan Yang / EE, NCHU Analog-Circuit Design
Noise in a fold-cascode op amp (cont’d)
( )
|
|
.
|

\
|
=
2 2
8 , 7
8 , 7
8 , 7
2
,
1
2
out m
ox
P
M out n
R g
f WL C
K
V
( )
|
|
.
|

\
|
=
2 2
10 , 9
10 , 9
10 , 9
2
,
1
2
out m
ox
N
M out n
R g
f WL C
K
V
( )
|
|
.
|

\
|
=
2 2
2 , 1
2 , 1
2 , 1
2
,
1
2
out m
ox
N
M out n
R g
f WL C
K
V
( ) ( ) ( )
2
2 , 1
2
8 , 7
8 , 7
2
2 , 1
2
10 , 9
10 , 9 2 , 1
2
2
, , 2
,
1 2 1 1 2
m
m
ox
P
m
m
ox
N
v
tot out n
in n
g
g
WL f C
K
g
g
WL WL f C
K
A
V
V
+
|
|
.
|

\
|
+ =
=
and A
v
= g
m1,2
R
out
.
Total input-referred flicker noise:
¤ Flicker noise:
33
9-64 Ching-Yuan Yang / EE, NCHU Analog-Circuit Design
Noise in a fold-cascode op amp (cont’d)
¤ The overall noise:
( ) ( ) ( )
2
2 , 1
2
8 , 7
8 , 7
2
2 , 1
2
10 , 9
10 , 9 2 , 1
2
2 , 1
10 , 9
2
2 , 1
8 , 7
2 , 1
2
,
1 2 1 1 2
3
2
3
2
3
2
8
m
m
ox
P
m
m
ox
N
m
m
m
m
m
in n
g
g
WL f C
K
g
g
WL WL f C
K
g
g
g
g
g
kT V
+
|
|
.
|

\
|
+ +
|
|
.
|

\
|
+ + =
¤ Discussion:
O The noise contribution of the PMOS and NMOS
current sources increases in proportion to their
transconductance. This trend results in a trade-off
between output voltage swings and input-referred
noise: for a given current, as implied by
g
m
= 2I
D
/(V
GS
− V
TH
), if the overdrive voltage of
the current sources is minimized to allow large
swings, then their transconductance is maximized.
9-65 Ching-Yuan Yang / EE, NCHU Analog-Circuit Design
Noise in a two-stage op amp
( )( )
( )
2
3 1
2
5
2
1
7 5
2
2
7 5 7 5
2
3
16 1
3
2
4 2
8 5
o o m m
m m
v
o o m m M n
r r g g
g g kT
A
r r g g kT V
+
= ⋅ + × =

¤ In the 1
st
stage:
2
1
3 1 2
3
2
4 2
4 1
m
m m
M n
g
g g
kT V
+
× =

¤ Total input-referred thermal noise:
( )
(
(
¸
(

¸

+
+ + =
2
3 1
2
5
7 5
3 1 2
1
2
,
1
3
16
o o m
m m
m m
m
tot n
r r g
g g
g g
g
kT
V
O Note the noise resulting from the second
stage is usually negligible because it is
divided by the gain of the first stage when
referred to the main input.
¤ Total voltage gain: A
v
= g
m1
(r
o1,,r
o3
)× g
m5
(r
o5,,r
o7
).
¤ In the 2nd stage: The noise current of M5 and M7 flows through ro5,,ro7.