July 4, 2006

Fundamentals of Semiconductor
Test for Physical Failure Analysis
Dr. Burnell G. West, IEEE Life Fellow
Chief Architect, Credence Systems
2
Fundamentals of IC Test: Course Outline
 Session 1 – The Structure of a Semiconductor Test
– What to test? Why? What tests work? How do tests work?
– Digital !i"ed Signal and Analog Tests
– Functional Structural and Alternate Tests
– AT# Architecture and test e"ecution
– Patterns failure detection and res$onse logging
– Test %aria&les – %oltage fre'uency D(T tem$erature
 Session ) – A$$lying Tests for Physical Failure Analysis
– What goes on when a de%ice fails a test?
– Defects %s Parametric Failures *%s Design #rrors+
– How do we isolate locate and e"hi&it a defect?
– Analy,ing and modifying tests to o&ser%e a failure mode
– #diting $hysical de%ices to demonstrate cause
– The role of AT# in $hysical failure analysis – case studies
 -eferences
– !. /. 0ushnell and 1. D. Agrawal, Essentials of Electronic Testing for Digital,
Memory and Mixed-Signal VLSI Circuits, 0oston2 S$ringer )334
– /. 5. Wagner ed. Failure Analysis of Integrated Circuits Tools and Tec!ni"ues,
0oston2 6luwer 1777

Semiconductor Technology Overview
#afer$
De%ice
Data
Semiconductor Fabrication Data Network
&assi%ate &ro'e Singulate &ac(age Test
E)D
*SE+
&attern ,a(e Ins-ect
Metali.e
Ins-ect
Im-lant
/
FA FA FA
!
Why Test?
 Design is not $erfectly relia&le
– Test can hel$ detect and locate design errors *8&ugs9+
– Test can hel$ esta&lish design margins
 !anufacturing is not $erfectly relia&le
– Test can esta&lish $erformance limits
– Test can detect $rocess e"cursions
 Things &reak : where w"s the we"# lin#$
 Things wear out : wh"t %couldn&t t"#e the he"t'$
 ;o&ody wants to shi( &ad $roduct
 ;o&ody wants to 'uild &ad $roduct
)
IC Test and Measurement O!ectives
 "esign deug
– Circuit edit to su##ort deug
 "esign validation
 "evice characteri$ation
 "efect detection
– Faulty circuit uilt%in re#air
 "efect isolation
 Infant mortality acceleration
 &rom#t #rocess feedac'
 (uality assurance through #roduct lifetime
 Overall test cost control
– What to test and when to test it
– Minimi$e the cost of each test a##lied
– Ma)imi$e the return from each test
 Test cost reduction cannot com-romise test "uality
Early
Silicon
Al0ays
&roduction
Testing
*
What *inds of Test?
D*T
S
t
r
u
c
t
u
r
a
l

t
e
s
t
?
I
"
"
(

t
e
s
t
?
Static Functional Test?
+
t
%
s
#
e
e
d

f
u
n
c
t
i
o
n
a
l

t
e
s
t
?
,IST?
-
o
w
%
.

f
u
n
c
t
i
o
n
a
l

t
e
s
t
?
O
n
%
l
i
n
e

t
e
s
t
?
/
/
/
/
/
/
/
/
-
a
u
n
c
h
%
c
a
#
t
u
r
e

t
e
s
t
?
+nalog / mi)ed signal test?
"
C

#
a
r
a
m
e
t
r
i
c

t
e
s
t
?
+
d
a
#
tiv
e
te
s
t?
+
1 << )=3
>=
<7
? >1
1@?<
1@
<
3
@4
>@
ADDB
ADDB
F(;5
F(;5
Scan
?
Delay
@7
Sematec! Study S121 314456
Scan - 44758 fault co%erage
F*)C - 928 fault co%erage
IDD: - 1;5< =non-o-erational>
3of 15?; IDD: failures@ 21;5 total6
Test Coverage and 0sca#es
,
Test in &hysical Failure +nalysis
 C&ser%ation is key
– /1P $rocesses
– Photon emissions
– Cther electromagnetic or $hoto:o$tic effects
 C&ser%ation takes TA!#
– #ffects are weak
– ;oise le%els are large
 Tests must &e /CCP#D
– 6ey to satisfactory defect $henomena o&ser%ation
-
Test O#eration Overview
Test Setu#
Test Controller
1esults
Test Instrument +t the I/O ,oundary Inside the Chi#
0)ecute test
Transmit ne)t
test data
Start test
1eceive and evaluate
test results
Install test
1eceive and organi$e
test se2uence/#atterns
Transmit re2uired
test cloc'ing
Test 0)ecute
??
0valuate
test result
ra0 data
-og fail
fail
Identify ne)t
test data set
-ass
??
-og fail
fail
-ass
Incor-orate t!e
&FA Loo-
./
The 1elevance of "igital Test
 !ost of todayDs de%ices *e%en So5+ are 8mostly9 digital
 Digital acti%ity stimulates de%ices or e%aluates results for almost
all test ty$es including
– Digital functional tests
– Scan:&ased structural tests
– /aunch:5a$ture tests
– 0AST tests
– ADDB tests
– !emory tests *and re$airs+
– Ada$ti%e tests
..
The Structure of "igital Test &rocesses
 Princi$al use – sorting
 Ancillary use – defect isolation and PFA
 Tests are not necessarily designed with PFA in mind
– So how are tests designed?
– !oti%ation Am$lementation and Ada$tation to PFA
.2
"igital Test 3 t!e classic model
F
D
M
D*T &I)
FAIL
T!e Classic ATE Model 3ATLAS A 14?? $ 145? $ 14<; $ 2BBB6
Allo0s tests to 'e 0ritten sim-ly as ta'les of =%ectors>
0it! dri%e and stro'e timing a'stracted
ATE Timing Su'system
.
"igital Test 4.ectors5
0 - 01001011 : xxxxxxxx
1 - 11001010 : xxxx0110
2 - 00110101 : 11001101
3 - 10100101 : 01001011
4 - 11010001 : 0010zzzz
5 - 00101101 : 0011zzzz
6 - 11010010 : xx1z0x1z
test -attern
res-onse functional 3or ex-ect6 data
test %ector num'er
stimulus functional data
F-data
in<0:7>out<0:7>
0 1 2 3 4 5 6 0 1 2 3 4 5 6
0
1
2
3
4
5
6
7
.!
"igital Test 4.ectors5
0 - 01001011 : xxxxxxxx
1 - 11001010 : xxxx0110
2 - 00110101 : 11001101
3 - 10100101 : 01001011
4 - 11010001 : 0010zzzz
5 - 00101101 : 0011zzzz
6 - 11010010 : xx1z0x1z
Digital Test System
D*T

3 - 10100101 : 01010011
5 - 00101101 : 001z0zzz
6 - 11010010 : xx1z0x00
fail datalog test -attern
in<0:7>out<0:7>
in<0:7>out<0:7>
.)
"igital Test 4.ectors5 and STI-
 !ost testing today and for the foreseea&le future will &e digital
– (nam&iguous s$ecification of com$le" test re'uirements
– (nam&iguous e%aluation of $ass or fail result
– 0i1hly com(ut"2le – growth for multi$le generations
 ;on:digital re'uirements can ha%e digital manifestations –
– AD5 tests 0AST structures etc
 Hence STA/ – St"nd"rd 3est Interf"ce L"n1u"1e – A### 1@43
– Standard descri$tion of digital $atterns
– Standard descri$tion of logic transitions – 8e%ents9
– Standard descri$tion of &asic digital test wa%eforms
.*
Where .ectors Come From
 Stored Pattern *8functional9+ 1ectors
– Eenerated &y hand simulation sometimes ATPE
 S5A; 1ectors
– Eenerated mainly &y ATPEF re'uire scan:chain DFT
– (sed for structural tests
– (sed for $ath delay tests
– -e'uires launch:ca$ture clocking
 Algorithmic generation
– (sed mainly for memory arrays
 0uilt:in Self Test *0AST+ generators
.+
6ow STI- E%ent Streams come from .ectors
 1ariety of ways to re$resent digital tests
 All result in s$ecific acti%ity at each D(T $in
 Acti%ity at each D(T $in is a se4uence of e5ents
– An$ut $ins2 D1Gtime D3Gtime
– Cut$ut $ins2 T1Gtime T3Gtime HGtime
– AIC $ins2 D1Gtime D3Gtime DJGtime T1Gtime T3Gtime
TJGtime
 F:data translates to D1Ds D3Ds DJDs or T1Ds T3Ds TJDs
de$ending on AIC Definition
.,
0vent se2uences to test a fli#%flo#
D e%ent stream2 DFG3
5 e%ent stream2 DFG/# DFKGT#
BB; e%ent streams2 TFGS/# HGST# *window stro&e+
BB; e%ent streams2 TFGstro&eKtime *edge stro&e+
-- 'ut 0e must allo0 for inaccuracies
Stro'e Leading Edge
3SLE6
Stro'e Trailing Edge
3STE6
0 – 01:01
1 – 10:10
2 – 01:01
test -attern
:)
Leading Edge
3LE6
Trailing Edge
3TE6
D
C
:
FCB FCB FC1
:)
in-uts
out-ut
D
C
:
0indo0 stro'es
edge stro'es
out-ut :)
.-
T
E
A E&A
T
E
A E&A
0dge &lacement +ccuracy 70&+8
in-uts
out-ut
D
C
:
D
C
:
FCB FCB FC1
0indo0 stro'es
edge stro'es
out-ut :)
E%ent Time T
E
:) :)
0 – 01:01
1 – 10:10
2 – 01:01
test -attern
2/
"etermining 0dge &lacement
 #dge $lacement is a com&ination of three terms
– Program %alue within each %ector
– Accumulated %ector start offset
– 5ali&ration corrections
– Static systematic errors
– Pattern:de$endent systematic errors
– 5lock:de$endent systematic errors
 So how is it im$lemented?
2.
6ow a Tester Timing System Wor's
#%ent times further corrected &y cal offset
 corrections for $ath length %ariation *skew+
 corrections for dynamic errors
#%ent times adLusted &y $eriod offset
 transform %ector time to clock $lus inter$olation
 system clock decou(led from %ector rate
#%ent se'uences from F:data and 1ector Ty$e
 each $in has its own e%ent se'uence $er %ector
22
.ector Time Transformation
-eriod one -eriod t0o
e1 e2 e1 e2
cloc(
c171 c172 c272 c271
%171
%172
%271
%272
t171
t172
t271
t272
o1
Transform 1 Add accumulated -eriod offset to -rogram time
Transform 2 Add cali'ration offset 'ased on e%ent ty-e
Transform D Determine cloc( cycle containing e%ent time
and com-ute inter-olation %alue
#!en cloc( cycle occurs, trigger inter-olation delay circuit - - -
2
Ty#ical Tester Timing &ath
C-OC*
fanout
Inter#olator
dri%e mar(ers
F-data
E%ent Ty-es
Vector
ty-e
Inter#olator
stro'e mar(ers
Formatter
Formatter
DEI
DI)E
ACEI
,CLF
Load'oard
D*T
&ogo
&E ca'le
&0IC
Soc(et
MAI)F+AME 3mo%ing to test !ead6 TEST EEAD
E%ent Times
Time-critical -at!s Time-critical de%ices
E%ent Se"uence Generator
2!
Some Timing 0rror Sources
 Can t!ese errors 'e cali'rated/
– Cloc' generation noise
– Cloc' distriution noise
– Inter#olator non%linearity
– Mar'er noise
– Formatter noise
– Timing signal #ath dynamics
– &0 timing non%linearity
– &0%"9T signal #ath dynamics
– Source%cloc'ed "9T trac'ing error
– Caliration error
no
no
ye
ye
no
no
ye
ome
ome
N! ""
Dominant timing errors are
Static systematic errors
Tester clock cycle
de$endent systematic
errors
Pattern de$endent
systematic errors
;oise
Systematic errors are *in
$rinci$le+ correcta&le
)oise is not correcta'le
62ut c"n 2e "5er"1ed7
2)
.ariale Test 1ates
 Pin e%ent timing can change on the fly
– Different %ector ty$es may ha%e different timing
 Test rates can also change on the fly
– For match synchroni,ation
– For s$eed testing
– For characteri,ation and de&ugging
2*
.ariale Test 1ates 3 as used for deugging
Slower
Faster
2+
1ecent Ma!or Technology Shifts
 5lock !ulti$lication
– High:end uProc clocks multi$ly in$ut rate
– Anternal P// controls timing *not AT#+
 High:s$eed AICDs use local clocking
– Forwarded 5locks
– -eference 5locks
– #m&edded 5locks
2,
.ariale Test 1ates 3 with smart &-- cloc'
Slower
Faster
Launch Capture
2-
Fundamentals of IC Test: Summary of Session :
 !anufacturing $rocesses $roduce unshi$$a&le defects
– Wide %ariety of tests can &e a$$lied
– Studies show different tests e"$ose different defects
– Difficult to know " (riori which tests will &e most effecti%e
– #ffecti%e AT# must a$$ly a %ariety of tests in multi$le conditions
 Delay defects more $redominant in ad%anced A5 $rocesses
– Agile timing in AT# hel$ed identify and locate delay defects
– Higher s$eeds in modern de%ices challenge AT# agility
– Delta timing mo%ing on:chi$
 Mield management demands 'uick $rocess feed&ack
– To &e addressed in Session )
/
Fundamentals of IC Test: Course Outline
 Session 1 – The Structure of a Semiconductor Test
– Why test? What tests work? How are tests a$$lied?
– Digital !i"ed Signal and Analog Tests
– Functional Structural and Alternate Tests
– AT# Architecture and test e"ecution
– Patterns failure detection and res$onse logging
– Test %aria&les – %oltage fre'uency D(T tem$erature
 Session ) – A$$lying Tests for Physical Failure Analysis
– What goes on when a de%ice fails a test?
– Design #rrors %s Defects %s Parametric Failures
– How do we isolate locate and e"hi&it a circuit $ro&lem?
– Analy,ing and modifying tests to o&ser%e a failure mode
– #diting $hysical de%ices to demonstrate cause
– The role of AT# in $hysical failure analysis
 -eferences
– !. /. 0ushnell and 1. D. Agrawal, Essentials of Electronic Testing for Digital,
Memory and Mixed-Signal VLSI Circuits, 0oston2 S$ringer )334
– /. 5. Wagner ed. Failure Analysis of Integrated Circuits Tools and Tec!ni"ues,
0oston2 6luwer 1777
.
&hysical Failure +nalysis: Test -oo#s ;eeded
 Defect /ocali,ation -e'uires Amaging
– Frontside or &ackside imaging of $attern acti%ity
– Wa%eforms or circuit acti%ity heating etc.
 1irtually all imaging $rocesses re'uire sta&le re$eata&le tests
– Hundreds of thousands to many millions of re$etitions to collect
– Time:resol%ed emissions re'uire e"treme sta&ility
– Wa%eform ca$ture with >3:$s resolution is %ery demanding
 How does AT# Eenerate test loo$s?
– Functional $atterns
– Scan:&ased $atterns
2
Incor-orate t!e
&FA Loo-
Test O#eration Overview 3 Im-lementing a Loo-
Test Controller Test Instrument Inside the "9T
0)ecute test
+##ly ne)t
test vector
Start test
Com#are "9T
res#onse to tale
Install test
1eceive and organi$e
test se2uence/#atterns
??
-ass$fail
fail
-og fail

IC Test and Measurement O!ectives
 "esign deug
– Circuit edit to su##ort deug
 "esign validation
 "evice characteri$ation
 "efect detection
– Faulty circuit uilt%in re#air
 "efect isolation
 Infant mortality acceleration
 &rom#t #rocess feedac'
 (uality assurance through #roduct lifetime
 Overall test cost control
– What to test and when to test it
– Minimi$e the cost of each test a##lied
– Ma)imi$e the return from each test
 Test cost reduction cannot com-romise test "uality
Early
Silicon
Al0ays
&roduction
Testing
!
Why Integrated Circuit 0dit?
 1ast %ariety of so$histicated #DA tools hel$ designers de&ug
their code
 Test structure are im$lemented into A5 for $ost fa&rication
de%ice ins$ection $erformance N relia&ility assurance
 Design can &e tested simulated N de&ugged &efore fa&rication
 FA0 im$lements test structures for $rocess control N
%erification
 O
 #%ery ste$ starting from 5once$t to Fa&rication is well
monitored thoroughly tested and %erified multi$le times.
 8Cur Silicon is going to &e $erfectO9
 So why 5A-5(AT #DAT ??????
)
;eed of Circuit 0dit
 Test finds the de%ice doesnDt work
– Testing may identify design failure source
 Simulations may %erify $ro$osed fi"
 0(T low confidence in making an e"$ensi%e mask change

 At may take weeks to months &efore an #5CDd A5 would &e
a%aila&le to %alidate design change.
 As it going to work ???

 Therefore FA0 5ircuit #dit is the solution for2
 1alidating design change on Tester
 Proceeding to !ask change with confidence
 Eetting working de%ices to customers ASAP
 5# %ital for fast N cost effecti%e Design:to:!arket solution
"esign
Customer
&roduction
:st Silicon
Test
*
C0 Technology 1oadma#
5ircuit edit sur%ey &y
5redence in early )334
 #dit time increases as num&er of routing layers increase *from >
to 13 in last 13 years+ with technology nodes
 5# tools re'uire constantly de%elo$ing hardware techni'ues N
chemistries to address multi:layer dee$ su&:micron A5s
 5AD na%igation is %ital for effecti%e 5# solutions
+
Case Study
 Fli$chi$ 73nm 5uIlow:k $rocess
 5ircuit issue was that an incorrect $ower su$$ly 1dd1 was on three master
$hase locked loo$ controllers *P//5s+ i.e. the $ull:u$ %oltage on a logic gate
was incorrect.
 -e'uired connecting an !1 line to 1dd) on !> and cutting !1 line to isolate
1dd1 su$$ly.
 The low &eam current used for this o$eration made it successful.
 Cnce Test $ro%ed the edit worked edit was re$eated on the other ) P//5s N
Tested
 An all eight de%ices were edited and Tested good.
,
C0 &lanning for in Silicon .alidation
 Cnce 5# is $art of de&ug then ) doors o$en2
 5# to fine tune analog circuitry
 5ase study2 Design $lanned for edit at critical
$oints
– !1 resistors could &e added to fine:tune design
– Test found $ro&lem in area where e"$ected
– 5# fi" em$loyed N design ad%anced
– Product de%elo$ment time reduced
 !ay not understand where risks are &ut #DA
tools should hel$
 ). 5ircuit edit ena&les %alidation of ne"t silicon
– When com$leted design team mo%es on to the se'uel
– Production silicon &ecomes $rototy$e for new design
– #dits %alidate assum$tions going into new design &efore
first silicon
-
IC Test and Measurement O!ectives
 "esign deug
– Circuit edit to su##ort deug
 "esign validation
 "evice characteri$ation
 "efect detection
– Faulty circuit uilt%in re#air
 "efect isolation
 Infant mortality acceleration
 &rom#t #rocess feedac'
 (uality assurance through #roduct lifetime
 Overall test cost control
– What to test and when to test it
– Minimi$e the cost of each test a##lied
– Ma)imi$e the return from each test
 Test cost reduction cannot com-romise test "uality
Early
Silicon
Al0ays
&roduction
Testing
!/
<ield vs maturity vs com#le)ity
-
e
la
ti%
e
D
e
%
ic
e
5
o
m
$
le
"
ity
=
>
?
>
:
>
>
:
:=
>
:>
=>
@>
A>
B>
?>
C>
D>
E>
:>>
P
r
o
c
e
s
s

!
a
t
u
r
i
t
y
*
B
u
a
r
t
e
r
s
+
M
i
e
l
d

*
P
+
!.
;ew Technologies 3 ;ew &rolems
Ancreasing differences
&etween simulation models
and reality are making it e%er
more im$ractical to simulate
fully new designs
 !ulti:metal interconnects
 ;ew $hysical designs
: 1>3 nm 73 nm =4 nmO
 ;ew materials
: SCA
:
/ow 6 dielectric
:
5o$$er
:
Strained silicon Taur M. and T. H. ;ing *177<+. Fundamentals of !odern 1/SA De%ices.
5am&ridge (6 5am&ridge (ni%ersity Press.
!2
Timing "eug
 Pro&lem2 !otorola *Freescale+ de%ice
 Scan chain was failing at certain s$eeds in new SCA design
– Structural diagnostic software was not a$$lica&le
– Scan $attern loo$ length2 =3 microseconds
– Power su$$ly2 1.<1
 #miSco$e !ethodology
– !easure wa%eforms at key nodes to identify root:cause of failure
!
Timing "eug
 51K5/6 turned off too late to &lock the falling transition at DA;
 #miSco$e timing measurement identified a race condition
 5hanging 51K5/6 timing sol%ed the $ro&lem
A
Courtesy of
!!
1esistive Interconnect -ocali$ation
 5an use imaging tools to locali,e a wide %ariety of faults
– Traditional 8static9 and 8hard9 faults common &elow )43 nm
– Design and 8soft9 faults increasingly common &elow 73 nm
Design Fault
Hard Fault
Dynamic (“Soft”) Fault
Static
Fault
!)
1esistive Fate -ocali$ation
P. Song F. !otika and D. -. 6ne&el QSI>73 E4 5!CS micro$rocessor diagnosticsQ IB8 9ourn"l of
:ese"rch "nd De5elo(ment %ol. @> $$. <77:71@ 1777.
 /ocali,e and 5haracteri,e interconnect faults
!*
"esign 0rror 3 Transistor Mismatch
 Design error of mismatched
transistor in analog circuit
 (sed #miSco$e to locali,e fault
 Simulated o&ser%ed wa%eforms
to identify root:cause
– Eood de%ice to &ad de%ice
com$arison aided analysis
!+
1esistive .ia -ocali$ation
 Information related to failure7s8 was used in fault diagnosis #rocess
: Syno#sys TetraM+G and Cadence 0ncounter Test "iagnostics were used
to locali$e fault
Failing
Fli#%Flo#s
!,
1esistive .ia -ocali$ation 7contHd8
 Failure was li'ely related to the = ;O1 Fates
!-
1esistive .ia -ocali$ation 7contHd8
 Pro&e results clearly identified failing net
 0ased on results one of two %ias was $oint of failure
)/
-ogic "eug
– Test results indicate the &+" is high while e)#ected value is low
– 9se logic state tracing to identify source of failure
F
F 7C-*8
F-I&%F-O&
0 "
C
, +
&+"
).
-ogic "eug 7contHd8
F
E *5/6+
F/AP:F/CP
# D
5
0 A
PAD
EmiScope Data Reconstructed Logic Simulated Logic
A

B

C

D

E

F

G


)2
Ty#ical &ost%Silicon &rolems
 Mield is lower than re'uired on new technology
– Ana&ility to fully model circuit &eha%ior
– Anaccurate design models es$ecially for timing and Litter
 -esisti%e failures
– Ancom$lete %ias electromigration metal &ridges etc.
 Design errors
– C%er 43P of design time is s$ent in %erification
– Met – desi1n errors "re still common
 Ancom$lete success with ATPE methodologies
– Ancom$lete test co%erage
– Ancom$lete fault co%erage
– Scan chain failures
They are e)#ected to get worse elow E> nm
)
:
st
Si Failures %"esign "eug Issues
AI
:@I
:CI
:CI
=>I
=:I
=@I
=BI
=DI
=EI
@BI
?CI
Other
Firmware
&ower
1ace Condition
I1 "ro#s
Mi)ed%Signal Interface
<ield
Cloc'ing
Slow &ath
;oise
+nalog Circuit
-ogic or Functional
HCollett International ;$B2
:st Si 0rror/Flaw "istriution
Sam$le of )41 designs from
;orth America com$leted in )33)
@
or more
>
)
1
13P )3P >3P
;
u
m

e
r

o
f

S
i
l
i
c
o
n

S
#
i
n
s
@3P
HCollett International +esearc! Inc7 from Electronic
,usiness Iun$BD
+t least ?:I of new designs
7or shrin's8 re2uired a res#in
TodayDs A5 $erformance re'uirements and leading:edge $rocesses
make it %ery difficult to se$arate design errors from $rocess margins
)!
design
definition
design
-artitioning
structural
im-lementation
-!ysical
im-lementation
design
-rototy-e
de%ice
%alidation
design
%erification
Firmware 7:@I8
&ower 7:CI8
1ace Condition 7:CI8
I1 "ro#s 7=>I8
Mi)ed%Signal Interface 7=:I8
<ield 7=@I8
Cloc'ing 7=BI8
Slow &ath 7=DI8
-ogic or Functional 7?CI8
;oise 7=EI8
+nalog Circuit 7@BI8
CF*LD D7V7 EAVE
CA*GET TEEM ALL //
Collett Intern"tion"l :ese"rch, A(ril 2//2
"esigns 6aving One or More 1e%s#ins y Ty#e of Flaw
Why didnHt it wor' ??
EFFECTIVE TFFLS A+E
STILL )FT AVAILA,LE JJ
))
The "eug Challenge
 Huge 'uantities of circuitry
 !assi%e %olumes of data to manageIanaly,e
 Parametric de%iations causing more de%ice failures
 Data access limited &y AC &andwidth
– faster data access R shorter de&ug time
 Desired data flow for de&ug
– *may&e+ scan in to esta&lish starting state of entire de%ice
– $attern e"ecution with AC esta&lished &y $attern
– *may&e+ scan dum$ together with standard AC for analysis
 !ulti E0PS data rate RS non:deterministic $atterns
– data collection must co$e with %arying data
– cannot acce$t fi"ed:$rotocol solutions
– reconfigure AT# for s$ecific $rotocols
– dum$ &it $atterns for later software $rotocol analysis
)*
"iffering "eug .iew#oints
 TesterDs:eye 1iew
– dataflow – &oth in and out
– in$ut wa%eforms
– out$ut wa%eforms
 D(TDs:eye 1iew
– high:le%el structure
– -T/
– logical circuit detail
– to$ology
– $hysical im$lementation
)+
"9THs%eye .iew: 6igh%-evel Structure 7:8
),
"9THs%eye .iew: 6igh%-evel Structure 7=8
#include "systemc.h"
void fft::entry()
{ float sample[16][2]
unsi!ned int inde"
#hile(true)
{ data$re%.#rite(false)
#hile( inde" & 16 )
{
data$re%.#rite(true)
#ait$until(data$valid.delayed() '' true)
sample[inde"][(] ' in$real.read()
sample[inde"][1] ' in$ima!.read()
inde"))
data$re%.#rite(false)
#ait()
*
inde" ' (
++,alculate the -.values recursively
#$real ' cos(theta)
#$ima! ' .sin(theta)
#hile(inde" & len.1)
{
#$temp ' #$rec$real/#$real . #$rec$ima!/#$ima!
#$rec$ima! ' #$rec$real/#$ima! ) #$rec$ima!/#$real
#$rec$real ' #$temp
-[inde"][(] ' #$rec$real
-[inde"][1] ' #$rec$ima!
inde"))
*
++0e!in ,omputation
sta!e ' (
len ' 1 incr ' 1
#hile (sta!e & 2)
{
len ' len+2
#hile(i & 1)
{
sample[inde"][(] ' tmp$real
sample[inde"][1] ' tmp$ima!
i ' i ) 2/len
*
sta!e))
*
*
)-
"9THs%eye .iew: 1T-
#include "systemc.h"
void fft::entry()
{ float sample[16][2]
unsi!ned int inde"
#hile(true)
{ data$re%.#rite(false)
#hile( inde" & 16 )
{
data$re%.#rite(true)
#ait$until(data$valid.delayed() '' true)
sample[inde"][(] ' in$real.read()
sample[inde"][1] ' in$ima!.read()
inde"))
data$re%.#rite(false)
#ait()
*
inde" ' (
++,alculate the -.values recursively
#$real ' cos(theta)
#$ima! ' .sin(theta)
#hile(inde" & len.1)
{
#$temp ' #$rec$real/#$real . #$rec$ima!/#$ima!
#$rec$ima! ' #$rec$real/#$ima! ) #$rec$ima!/#$real
#$rec$real ' #$temp
-[inde"][(] ' #$rec$real
-[inde"][1] ' #$rec$ima!
inde"))
*
++0e!in ,omputation
sta!e ' (
len ' 1 incr ' 1
#hile (sta!e & 2)
{
len ' len+2
#hile(i & 1)
{
sample[inde"][(] ' tmp$real
sample[inde"][1] ' tmp$ima!
i ' i ) 2/len
*
sta!e))
*
*
#include "systemc.h"
void fft::entry()
{ float sample[16][2]
unsi!ned int inde"
#hile(true)
{ data$re%.#rite(false)
#hile( inde" & 16 )
{
data$re%.#rite(true)
#ait$until(data$valid.delayed() '' true)
sample[inde"][(] ' in$real.read()
sample[inde"][1] ' in$ima!.read()
inde"))
data$re%.#rite(false)
#ait()
*
inde" ' (
++,alculate the -.values recursively
#$real ' cos(theta)
#$ima! ' .sin(theta)
#hile(inde" & len.1)
{
#$temp ' #$rec$real/#$real . #$rec$ima!/#$ima!
#$rec$ima! ' #$rec$real/#$ima! ) #$rec$ima!/#$real
#$rec$real ' #$temp
-[inde"][(] ' #$rec$real
-[inde"][1] ' #$rec$ima!
inde"))
*
++0e!in ,omputation
sta!e ' (
len ' 1 incr ' 1
#hile (sta!e & 2)
{
len ' len+2
#hile(i & 1)
{
sample[inde"][(] ' tmp$real
sample[inde"][1] ' tmp$ima!
i ' i ) 2/len
*
sta!e))
*
*
void fft::entry()
{ float sample[16][2]
unsi!ned int inde"
#hile(true)
{ data$re%.#rite(false)
#hile( inde" & 16 )
{
data$re%.#rite(true)
#ait$until(data$valid.delayed() '' true)
sample[inde"][(] ' in$real.read()
sample[inde"][1] ' in$ima!.read()
inde"))
data$re%.#rite(false)
#ait()
*
inde" ' (
++,alculate the -.values recursively
#$real ' cos(theta)
#$ima! ' .sin(theta)
#hile(inde" & len.1)
{
#$temp ' #$rec$real/#$real . #$rec$ima!/#$ima!
#$rec$ima! ' #$rec$real/#$ima! ) #$rec$ima!/#$real
#$rec$real ' #$temp
-[inde"][(] ' #$rec$real
-[inde"][1] ' #$rec$ima!
inde"))
*
++0e!in ,omputation
sta!e ' (
len ' 1 incr ' 1
#hile (sta!e & 2)
{
len ' len+2
#hile(i & 1)
{
sample[inde"][(] ' tmp$real
sample[inde"][1] ' tmp$ima!
i ' i ) 2/len
*
sta!e))
*
*
void fft::entry()
{ float sample[16][2]
unsi!ned int inde"
#hile(true)
{ data$re%.#rite(false)
#hile( inde" & 16 )
{
data$re%.#rite(true)
#ait$until(data$valid.delayed() '' true)
sample[inde"][(] ' in$real.read()
sample[inde"][1] ' in$ima!.read()
inde"))
data$re%.#rite(false)
#ait()
*
inde" ' (
++,alculate the -.values recursively
#$real ' cos(theta)
#$ima! ' .sin(theta)
#hile(inde" & len.1)
{
#$temp ' #$rec$real/#$real . #$rec$ima!/#$ima!
#$rec$ima! ' #$rec$real/#$ima! ) #$rec$ima!/#$real
#$rec$real ' #$temp
-[inde"][(] ' #$rec$real
-[inde"][1] ' #$rec$ima!
inde"))
*
++0e!in ,omputation
sta!e ' (
len ' 1 incr ' 1
#hile (sta!e & 2)
{
len ' len+2
#hile(i & 1)
{
sample[inde"][(] ' tmp$real
sample[inde"][1] ' tmp$ima!
i ' i ) 2/len
*
sta!e))
*
*
void fft::entry()
{ float sample[16][2]
unsi!ned int inde"
#hile(true)
{ data$re%.#rite(false)
#hile( inde" & 16 )
{
data$re%.#rite(true)
#ait$until(data$valid.delayed() '' true)
sample[inde"][(] ' in$real.read()
sample[inde"][1] ' in$ima!.read()
inde"))
data$re%.#rite(false)
#ait()
*
inde" ' (
++,alculate the -.values recursively
#$real ' cos(theta)
#$ima! ' .sin(theta)
#hile(inde" & len.1)
{
#$temp ' #$rec$real/#$real . #$rec$ima!/#$ima!
#$rec$ima! ' #$rec$real/#$ima! ) #$rec$ima!/#$real
#$rec$real ' #$temp
-[inde"][(] ' #$rec$real
-[inde"][1] ' #$rec$ima!
inde"))
*
++0e!in ,omputation
sta!e ' (
len ' 1 incr ' 1
#hile (sta!e & 2)
{
len ' len+2
#hile(i & 1)
{
sample[inde"][(] ' tmp$real
sample[inde"][1] ' tmp$ima!
i ' i ) 2/len
*
sta!e))
*
*
#include "systemc.h"
void fft::entry()
{ float sample[16][2]
unsi!ned int inde"
#hile(true)
{ data$re%.#rite(false)
#hile( inde" & 16 )
{
data$re%.#rite(true)
#ait$until(data$valid.delayed() '' true)
sample[inde"][(] ' in$real.read()
sample[inde"][1] ' in$ima!.read()
inde"))
data$re%.#rite(false)
#ait()
*
inde" ' (
++,alculate the -.values recursively
#$real ' cos(theta)
#$ima! ' .sin(theta)
#hile(inde" & len.1)
{
#$temp ' #$rec$real/#$real . #$rec$ima!/#$ima!
#$rec$ima! ' #$rec$real/#$ima! ) #$rec$ima!/#$real
#$rec$real ' #$temp
-[inde"][(] ' #$rec$real
-[inde"][1] ' #$rec$ima!
inde"))
*
++0e!in ,omputation
sta!e ' (
len ' 1 incr ' 1
#hile (sta!e & 2)
{
len ' len+2
#hile(i & 1)
{
sample[inde"][(] ' tmp$real
sample[inde"][1] ' tmp$ima!
i ' i ) 2/len
*
sta!e))
*
*
void fft::entry()
{ float sample[16][2]
unsi!ned int inde"
#hile(true)
{ data$re%.#rite(false)
#hile( inde" & 16 )
{
data$re%.#rite(true)
#ait$until(data$valid.delayed() '' true)
sample[inde"][(] ' in$real.read()
sample[inde"][1] ' in$ima!.read()
inde"))
data$re%.#rite(false)
#ait()
*
inde" ' (
++,alculate the -.values recursively
#$real ' cos(theta)
#$ima! ' .sin(theta)
#hile(inde" & len.1)
{
#$temp ' #$rec$real/#$real . #$rec$ima!/#$ima!
#$rec$ima! ' #$rec$real/#$ima! ) #$rec$ima!/#$real
#$rec$real ' #$temp
-[inde"][(] ' #$rec$real
-[inde"][1] ' #$rec$ima!
inde"))
*
++0e!in ,omputation
sta!e ' (
len ' 1 incr ' 1
#hile (sta!e & 2)
{
len ' len+2
#hile(i & 1)
{
sample[inde"][(] ' tmp$real
sample[inde"][1] ' tmp$ima!
i ' i ) 2/len
*
sta!e))
*
*
void fft::entry()
{ float sample[16][2]
unsi!ned int inde"
#hile(true)
{ data$re%.#rite(false)
#hile( inde" & 16 )
{
data$re%.#rite(true)
#ait$until(data$valid.delayed() '' true)
sample[inde"][(] ' in$real.read()
sample[inde"][1] ' in$ima!.read()
inde"))
data$re%.#rite(false)
#ait()
*
inde" ' (
++,alculate the -.values recursively
#$real ' cos(theta)
#$ima! ' .sin(theta)
#hile(inde" & len.1)
{
#$temp ' #$rec$real/#$real . #$rec$ima!/#$ima!
#$rec$ima! ' #$rec$real/#$ima! ) #$rec$ima!/#$real
#$rec$real ' #$temp
-[inde"][(] ' #$rec$real
-[inde"][1] ' #$rec$ima!
inde"))
*
++0e!in ,omputation
sta!e ' (
len ' 1 incr ' 1
#hile (sta!e & 2)
{
len ' len+2
#hile(i & 1)
{
sample[inde"][(] ' tmp$real
sample[inde"][1] ' tmp$ima!
i ' i ) 2/len
*
sta!e))
*
*
void fft::entry()
{ float sample[16][2]
unsi!ned int inde"
#hile(true)
{ data$re%.#rite(false)
#hile( inde" & 16 )
{
data$re%.#rite(true)
#ait$until(data$valid.delayed() '' true)
sample[inde"][(] ' in$real.read()
sample[inde"][1] ' in$ima!.read()
inde"))
data$re%.#rite(false)
#ait()
*
inde" ' (
++,alculate the -.values recursively
#$real ' cos(theta)
#$ima! ' .sin(theta)
#hile(inde" & len.1)
{
#$temp ' #$rec$real/#$real . #$rec$ima!/#$ima!
#$rec$ima! ' #$rec$real/#$ima! ) #$rec$ima!/#$real
#$rec$real ' #$temp
-[inde"][(] ' #$rec$real
-[inde"][1] ' #$rec$ima!
inde"))
*
++0e!in ,omputation
sta!e ' (
len ' 1 incr ' 1
#hile (sta!e & 2)
{
len ' len+2
#hile(i & 1)
{
sample[inde"][(] ' tmp$real
sample[inde"][1] ' tmp$ima!
i ' i ) 2/len
*
sta!e))
*
*
#include "systemc.h"
void fft::entry()
{ float sample[16][2]
unsi!ned int inde"
#hile(true)
{ data$re%.#rite(false)
#hile( inde" & 16 )
{
data$re%.#rite(true)
#ait$until(data$valid.delayed() '' true)
sample[inde"][(] ' in$real.read()
sample[inde"][1] ' in$ima!.read()
inde"))
data$re%.#rite(false)
#ait()
*
inde" ' (
++,alculate the -.values recursively
#$real ' cos(theta)
#$ima! ' .sin(theta)
#hile(inde" & len.1)
{
#$temp ' #$rec$real/#$real . #$rec$ima!/#$ima!
#$rec$ima! ' #$rec$real/#$ima! ) #$rec$ima!/#$real
#$rec$real ' #$temp
-[inde"][(] ' #$rec$real
-[inde"][1] ' #$rec$ima!
inde"))
*
++0e!in ,omputation
sta!e ' (
len ' 1 incr ' 1
#hile (sta!e & 2)
{
len ' len+2
#hile(i & 1)
{
sample[inde"][(] ' tmp$real
sample[inde"][1] ' tmp$ima!
i ' i ) 2/len
*
sta!e))
*
*
void fft::entry()
{ float sample[16][2]
unsi!ned int inde"
#hile(true)
{ data$re%.#rite(false)
#hile( inde" & 16 )
{
data$re%.#rite(true)
#ait$until(data$valid.delayed() '' true)
sample[inde"][(] ' in$real.read()
sample[inde"][1] ' in$ima!.read()
inde"))
data$re%.#rite(false)
#ait()
*
inde" ' (
++,alculate the -.values recursively
#$real ' cos(theta)
#$ima! ' .sin(theta)
#hile(inde" & len.1)
{
#$temp ' #$rec$real/#$real . #$rec$ima!/#$ima!
#$rec$ima! ' #$rec$real/#$ima! ) #$rec$ima!/#$real
#$rec$real ' #$temp
-[inde"][(] ' #$rec$real
-[inde"][1] ' #$rec$ima!
inde"))
*
++0e!in ,omputation
sta!e ' (
len ' 1 incr ' 1
#hile (sta!e & 2)
{
len ' len+2
#hile(i & 1)
{
sample[inde"][(] ' tmp$real
sample[inde"][1] ' tmp$ima!
i ' i ) 2/len
*
sta!e))
*
*
void fft::entry()
{ float sample[16][2]
unsi!ned int inde"
#hile(true)
{ data$re%.#rite(false)
#hile( inde" & 16 )
{
data$re%.#rite(true)
#ait$until(data$valid.delayed() '' true)
sample[inde"][(] ' in$real.read()
sample[inde"][1] ' in$ima!.read()
inde"))
data$re%.#rite(false)
#ait()
*
inde" ' (
++,alculate the -.values recursively
#$real ' cos(theta)
#$ima! ' .sin(theta)
#hile(inde" & len.1)
{
#$temp ' #$rec$real/#$real . #$rec$ima!/#$ima!
#$rec$ima! ' #$rec$real/#$ima! ) #$rec$ima!/#$real
#$rec$real ' #$temp
-[inde"][(] ' #$rec$real
-[inde"][1] ' #$rec$ima!
inde"))
*
++0e!in ,omputation
sta!e ' (
len ' 1 incr ' 1
#hile (sta!e & 2)
{
len ' len+2
#hile(i & 1)
{
sample[inde"][(] ' tmp$real
sample[inde"][1] ' tmp$ima!
i ' i ) 2/len
*
sta!e))
*
*
void fft::entry()
*/
"9THs%eye .iew: -ogic Circuit "etail
#include "systemc.h"
void fft::entry()
{ float sample[16][2]
unsi!ned int inde"
#hile(true)
{ data$re%.#rite(false)
#hile( inde" & 16 )
{
data$re%.#rite(true)
#ait$until(data$valid.delayed() '' true)
sample[inde"][(] ' in$real.read()
sample[inde"][1] ' in$ima!.read()
inde"))
data$re%.#rite(false)
#ait()
*
inde" ' (
++,alculate the -.values recursively
#$real ' cos(theta)
#$ima! ' .sin(theta)
#hile(inde" & len.1)
{
#$temp ' #$rec$real/#$real . #$rec$ima!/#$ima!
#$rec$ima! ' #$rec$real/#$ima! ) #$rec$ima!/#$real
#$rec$real ' #$temp
-[inde"][(] ' #$rec$real
-[inde"][1] ' #$rec$ima!
inde"))
*
++0e!in ,omputation
sta!e ' (
len ' 1 incr ' 1
#hile (sta!e & 2)
{
len ' len+2
#hile(i & 1)
{
sample[inde"][(] ' tmp$real
sample[inde"][1] ' tmp$ima!
i ' i ) 2/len
*
sta!e))
*
*
void fft::entry()
{ float sample[16][2]
unsi!ned int inde"
#hile(true)
{ data$re%.#rite(false)
#hile( inde" & 16 )
{
data$re%.#rite(true)
#ait$until(data$valid.delayed() '' true)
sample[inde"][(] ' in$real.read()
sample[inde"][1] ' in$ima!.read()
inde"))
data$re%.#rite(false)
#ait()
*
inde" ' (
++,alculate the -.values recursively
#$real ' cos(theta)
#$ima! ' .sin(theta)
#hile(inde" & len.1)
{
#$temp ' #$rec$real/#$real . #$rec$ima!/#$ima!
#$rec$ima! ' #$rec$real/#$ima! ) #$rec$ima!/#$real
#$rec$real ' #$temp
-[inde"][(] ' #$rec$real
-[inde"][1] ' #$rec$ima!
inde"))
*
++0e!in ,omputation
sta!e ' (
len ' 1 incr ' 1
#hile (sta!e & 2)
{
len ' len+2
#hile(i & 1)
{
sample[inde"][(] ' tmp$real
sample[inde"][1] ' tmp$ima!
i ' i ) 2/len
*
sta!e))
*
*.
"9THs%eye .iew: The Circuit "eug &rocess
#include "systemc.h"
void fft::entry()
{ float sample[16][2]
unsi!ned int inde"
#hile(true)
{ data$re%.#rite(false)
#hile( inde" & 16 )
{
data$re%.#rite(true)
#ait$until(data$valid.delayed() '' true)
sample[inde"][(] ' in$real.read()
sample[inde"][1] ' in$ima!.read()
inde"))
data$re%.#rite(false)
#ait()
*
inde" ' (
++,alculate the -.values recursively
#$real ' cos(theta)
#$ima! ' .sin(theta)
#hile(inde" & len.1)
{
#$temp ' #$rec$real/#$real . #$rec$ima!/#$ima!
#$rec$ima! ' #$rec$real/#$ima! ) #$rec$ima!/#$real
#$rec$real ' #$temp
-[inde"][(] ' #$rec$real
-[inde"][1] ' #$rec$ima!
inde"))
*
++0e!in ,omputation
sta!e ' (
len ' 1 incr ' 1
#hile (sta!e & 2)
{
len ' len+2
#hile(i & 1)
{
sample[inde"][(] ' tmp$real
sample[inde"][1] ' tmp$ima!
i ' i ) 2/len
*
sta!e))
*
*
void fft::entry()
{ float sample[16][2]
unsi!ned int inde"
#hile(true)
{ data$re%.#rite(false)
#hile( inde" & 16 )
{
data$re%.#rite(true)
#ait$until(data$valid.delayed() '' true)
sample[inde"][(] ' in$real.read()
sample[inde"][1] ' in$ima!.read()
inde"))
data$re%.#rite(false)
#ait()
*
inde" ' (
++,alculate the -.values recursively
#$real ' cos(theta)
#$ima! ' .sin(theta)
#hile(inde" & len.1)
{
#$temp ' #$rec$real/#$real . #$rec$ima!/#$ima!
#$rec$ima! ' #$rec$real/#$ima! ) #$rec$ima!/#$real
#$rec$real ' #$temp
-[inde"][(] ' #$rec$real
-[inde"][1] ' #$rec$ima!
inde"))
*
++0e!in ,omputation
sta!e ' (
len ' 1 incr ' 1
#hile (sta!e & 2)
{
len ' len+2
#hile(i & 1)
{
sample[inde"][(] ' tmp$real
sample[inde"][1] ' tmp$ima!
i ' i ) 2/len
*
sta!e))
*
*2
 Short channel – 73 nm and =4 nm design rules
– Amage and s$atial resolution
– Short channel modeling is difficult
 Dro$$ing o$erating %oltage le%els
– #mission signals are weaker
– /ower $roducti%ity and effecti%eness of solutions
 !aterials and $rocess challenges
– -esisti%e shorts I &ridges
– Higher leakage $ro&lems
 !ulti$le metal interconnect
– S = metal layers – 8front side o&struction9
– 5a$aciti%e effects and cross talkF difficult modeling
 Physical node le%el de&ug and FA is essential
 #%er increasing $erformance I sensiti%ity is most im$ortant
Challenges of +dvanced &roduct F+ / "eug
;eed for &etter
resolution N
node le%el $ro&ing
;eed for &etter
sensiti%ity
;eed for &etter
sensiti%ity
;eed for &ackside
image resolution N
node le%el $ro&ing
*
0
r
i
d
g
e

D
e
f
e
c
t
s

P
o
$
u
l
a
t
i
o
n
4Test Challenges for "ee# Su%Micron Technologies5J MJ 1odgers, etJ alJ "+C =>>>
Fault Free
S-eed Failure
Soft Fail
Logic Failure
Hard Fail *SIA fault+
Increasing ,ridge
+esistance
D !allett, et al, "#$
Smaller $rocess nodes *1>3 nm N &elow+ are
&ecoming more sensiti%e to higher - &ridges.
Ancreasing num&er of resisti%e defects causing more
1dd tem$ N fre' sensiti%e fails *soft failures+.
/ocali,ing resisti%e defects is %ery difficult using
con%entional techni'ues *mech $ro&es+.
0ffects of 1esistive ,ridges vs &rocess ;ode
*!
0ffective 1esistive "efect -ocali$ation Techni2ues
-aser λ
( 0ffect8
Static -aser Stimulation 7S-S8 "ynamic -aser Simulation
7"-S8
,ias: C. Measure: ∆I
,ias: CI Measure: ∆.
,ias: ;one Measure:
∆. or ∆I
Monitor &ass/Fail
K ::>> nm
7Carrier
In!ection8
-I.+/GI.+, L
"iffusions
GI.+/O,IC, LJ
"iffusions
-+"+/C&+
Marginality isolation y
carrier in!ection
:@>> nm
7Thermal8
TI.+/O,I1C6/GI.+
1esistive vias
Metal shorts
1esistive o#ens
0lectromigration
S00,0C*
Contact o#ens
S"-/C&+
Marginality isolation y
local heating 7soft defects8
1esistive interconnects
1esistive ridges
Elo&alScan /aser Stimulation A$$lications
*)
0ffective 1esistive "efect -ocali$ation Techni2ues
-esisti%e single node
interconnect defect
O,I1C6:
Aneffecti%e
"-S:
High success P
Most difficult to isolate
.dd
F;"
-esisti%e defect to
1dd NIor E;D
O,I1C6:
High success P
"-S:
!edium success P
Classic static use case
-esisti%e defect *&ridges+
&etween internal nodes
O,I1C6:
!edium success P
"-S:
High success P
Challenging to isolate
**
"-S Case Study M: % SI- on E> nm IC

Design meets design rules *73nm $rocess+

Mield T13P

Part sensiti%e to2
U 1oltage
U Tem$erature *would tend to Pass if heated a few degrees+
U Fre'uency

Simulations una&le to isolate
 Sus$ect logic &lock was identified &ut could not &e %erified or
locali,ed to the transistors
#miSco$e and Elo&alScan used to effecti%ely locali,e the
defect area
System &oard was used as stimulus N PassIFail
generation
*+
"-S Case Study M: %SI- on E> nm IC "ata
==>) SI- lens
Thresholding used to
highlight strongest signal
region
==>) SI- lens
SA/ D/S image showing
resolution T)33 nm
433nm
Elo&alScan Thermal D/S !ode *SA/ /ens+
433nm
 Freen indicates &ass
7#asses when heated8
 9sing SI- N "-S, the data
clearly identifies !ust a few
4minimum dimension5
transistors in the sus#ect
areaJ
 4Freen stringers5 follow
the #oly structure
 Standard air ga# lens can
not #rovide this detail
 "ata shows a shar# thermal
sensitivity inside the circuit
area
 "ata collected in minutes
*,
"-S Case Study M= %n.I"I+ +SIC Elo&alScan Thermal D/S !ode :Soft Failure in AP !emory 0lock
 Mield $ro&lem intermittent
read failures from an AP &lock
 Failure at high T high 1
low fre'. *leakage sus$ected+
 Schematics N S&IC0
unavailale from I& vendor
 -esults o&tained in a few hours
of $ro&ing time
D/S 8Fail9 signals *red circles+ highlighting
transistor ;> as defect site o%erlaid with
5AD *green $oly+ N /S! image
*-
"-S Case Study M@ 3 +naly$ing a <ield &rolem
 Mield $ro&lem failure identified on
a frame &uffer using 0AST
 ;o fault found using #miSco$e
 D/S *1>@3+ used to locali,ed fault
 Failure locali,ed to a P// circuit
– Ereen circles identify the section of
the Failing P//
– -ed &o"es are 5AD o%erlay
– &-- was never sus#ected as a
#otential #rolem
– -esults o&tained V1 hour
 Allustrates com$limentary %alue of
Elo&alScan *D/S+ N #miSco$e
*timing+ for efficient defect
locali,ation
+/
"-S Case MA 3 Flash Memory 1esistive Interconnect
"efect
Flash de%ice with failing
-ead o$eration.
De%ice $ass sometimes
when o$erated at
higher 1dd.
(sed D/S to locali,e
what was likely to &e a
resisti%e %ia *green dot+.
+.
Common Causes of Soft "efects
!etalli,ation or interconnect
defects

1ia $ush u$ or %oids

#lectro migration

Stress %oids

!etal 8mouse &ites9

EranularityIErain &oundaries

-esisti%e &ridging
Anter:le%el Dielectric *A/D+

1oids

!etal 8sli%ers9

5ontamination
C"ide Defects

Soft gate o"ide shorts

Hot carrier inLection
Process %ariations

Transistor effects2

1t shifts WW

/eff shift Weff shift

;!CS to P!CS length ratio

Diffusion resistance WW

Anterconnect

!etal thickness %ariations

S$acing or $itch %ariations

Eate C"ide and A/D

Thickness %ariation
Anaccurate li&rary models
;oise -elated effects

E;DI1dd ;oise 1dd sag

5ross talk

5/6IP// Litter
Soft Defect Localization (SDL) on ICs ! "ruce# $ "ruce# %ppes# &ilco'# % Cole#
(an)*un*on)# C +aw,ins IS(FA 2002
Design N $rocess margins are &eing $ushed to the limit N
no longer ha%e distinct 8&oundaries9
OO;on%visile
defects
+2
,are "ie 0lectrical Fi)turing Solution
 D(T 5ard :&ackside %iew
 Form factor of a 8uni%ersal9 41):$in
D(T card
 /ow $rofile JAF socket for 14 " 14 PEA
 /ow cost &oard – only one needed
 D(T 5arrier
 14"14 PEA foot$rint *1.44
inch s'uare+ )@ contacts
 1:inch s'uare clear ,one for
loose die or small fragment
 /ow cost consuma&le
 Wire &ond loose die onto die carrier
 #liminates need for multi$le
mechanical $ro&es
 Sim$ler solution for $ro&ing un$ackaged die
!ount Die
Wire 0ond
+
Fundamentals of IC Test: Summary of Session =
 A5 Test dri%es $hysical failure analysis
– 5ollected test data identify $otential failure locations
– Additional locali,ation re'uired to correct circuit $ro&lems
– 5ircuit edit to %alidate design error hy$othesis and continue de&ug
– Defect site locali,ation to reduce I eliminate wasted milling
– Fi"turing signal management test $rogram mani$ulation are critical
 1ariety of $henomena to dis$lay circuit &eha%ior
– !ost are weak re'uiring millions of test $attern cycles
– !ust kee$ circuit sta&ili,ed during data ac'uisition
– AT# su$$ort for $hysical failure analysis needs synchroni,ation
 ;anoscale $rocesses continue the challenge
– (nending room for inno%ation in PFA tools and techni'ues



July 4, 2006
Fundamentals of Semiconductor
Test for Physical Failure Analysis
Dr. Burnell G. West, IEEE Life Fellow
Chief Architect, Credence Systems


2
Fundamentals of IC Test: Course Outline
 Session 1 – The Structure of a Semiconductor Test
– What to test? Why? What tests work? How do tests work?
– Digital !i"ed Signal and Analog Tests
– Functional Structural and Alternate Tests
– AT# Architecture and test e"ecution
– Patterns failure detection and res$onse logging
– Test %aria&les – %oltage fre'uency D(T tem$erature
 Session ) – A$$lying Tests for Physical Failure Analysis
– What goes on when a de%ice fails a test?
– Defects %s Parametric Failures *%s Design #rrors+
– How do we isolate locate and e"hi&it a defect?
– Analy,ing and modifying tests to o&ser%e a failure mode
– #diting $hysical de%ices to demonstrate cause
– The role of AT# in $hysical failure analysis – case studies
 -eferences
– !. /. 0ushnell and 1. D. Agrawal, Essentials of Electronic Testing for Digital,
Memory and Mixed-Signal VLSI Circuits, 0oston2 S$ringer )334
– /. 5. Wagner ed. Failure Analysis of Integrated Circuits Tools and Tec!ni"ues,
0oston2 6luwer 1777



Semiconductor Technology Overview
#afer$
De%ice
Data
Semiconductor Fabrication Data Network
&assi%ate &ro'e Singulate &ac(age Test
E)D
*SE+
&attern ,a(e Ins-ect
Metali.e
Ins-ect
Im-lant
/
FA FA FA
@

!
Why Test?
 Design is not $erfectly relia&le
– Test can hel$ detect and locate design errors *8&ugs9+
– Test can hel$ esta&lish design margins
 !anufacturing is not $erfectly relia&le
– Test can esta&lish $erformance limits
– Test can detect $rocess e"cursions
 Things &reak : where w"s the we"# lin#$
 Things wear out : wh"t %couldn&t t"#e the he"t'$
 ;o&ody wants to shi( &ad $roduct
 ;o&ody wants to 'uild &ad $roduct
4

)
IC Test and Measurement O!ectives
 "esign deug
– Circuit edit to su##ort deug
 "esign validation
 "evice characteri$ation
 "efect detection
– Faulty circuit uilt%in re#air
 "efect isolation
 Infant mortality acceleration
 &rom#t #rocess feedac'
 (uality assurance through #roduct lifetime
 Overall test cost control
– What to test and when to test it
– Minimi$e the cost of each test a##lied
– Ma)imi$e the return from each test
 Test cost reduction cannot com-romise test "uality
Early
Silicon
Al0ays
&roduction
Testing


*
What *inds of Test?
D*T
S
t
r
u
c
t
u
r
a
l

t
e
s
t
?
I
"
"
(

t
e
s
t
?
Static Functional Test?
+
t
%
s
#
e
e
d

f
u
n
c
t
i
o
n
a
l

t
e
s
t
?
,IST?
-
o
w
%
.

f
u
n
c
t
i
o
n
a
l

t
e
s
t
?
O
n
%
l
i
n
e

t
e
s
t
?
/
/
/
/
/
/
/
/
-
a
u
n
c
h
%
c
a
#
t
u
r
e
t
e
s
t
?
+nalog / mi)ed signal test?
"
C

#
a
r
a
m
e
t
r
i
c

t
e
s
t
?
+
d
a
#
tiv
e
te
s
t?


+
1 << )=3
>=
<7
? >1
1@?<
1@
<
3
@4
>@
ADDB
ADDB
F(;5
F(;5
Scan
?
Delay
@7
Sematec! Study S121 314456
Scan - 44758 fault co%erage
F*)C - 928 fault co%erage
IDD: - 1;5< =non-o-erational>
3of 15?; IDD: failures@ 21;5 total6
Test Coverage and 0sca#es


,
Test in &hysical Failure +nalysis
 C&ser%ation is key
– /1P $rocesses
– Photon emissions
– Cther electromagnetic or $hoto:o$tic effects
 C&ser%ation takes TA!#
– #ffects are weak
– ;oise le%els are large
 Tests must &e /CCP#D
– 6ey to satisfactory defect $henomena o&ser%ation


-
Test O#eration Overview
Test Setu#
Test Controller
1esults
Test Instrument +t the I/O ,oundary Inside the Chi#
0)ecute test
Transmit ne)t
test data
Start test
1eceive and evaluate
test results
Install test
1eceive and organi$e
test se2uence/#atterns
Transmit re2uired
test cloc'ing
Test 0)ecute
??
0valuate
test result
ra0 data
-og fail
fail
Identify ne)t
test data set
-ass
??
-og fail
fail
-ass
Incor-orate t!e
&FA Loo-


./
The 1elevance of "igital Test
 !ost of todayDs de%ices *e%en So5+ are 8mostly9 digital
 Digital acti%ity stimulates de%ices or e%aluates results for almost
all test ty$es including
– Digital functional tests
– Scan:&ased structural tests
– /aunch:5a$ture tests
– 0AST tests
– ADDB tests
– !emory tests *and re$airs+
– Ada$ti%e tests


..
The Structure of "igital Test &rocesses
 Princi$al use – sorting
 Ancillary use – defect isolation and PFA
 Tests are not necessarily designed with PFA in mind
– So how are tests designed?
– !oti%ation Am$lementation and Ada$tation to PFA


.2
"igital Test 3 t!e classic model
F
D
M
D*T &I)
FAIL
T!e Classic ATE Model 3ATLAS A 14?? $ 145? $ 14<; $ 2BBB6
Allo0s tests to 'e 0ritten sim-ly as ta'les of =%ectors>
0it! dri%e and stro'e timing a'stracted
ATE Timing Su'system


.
"igital Test 4.ectors5
0 - 01001011 : xxxxxxxx
1 - 11001010 : xxxx0110
2 - 00110101 : 11001101
3 - 10100101 : 01001011
4 - 11010001 : 0010zzzz
5 - 00101101 : 0011zzzz
6 - 11010010 : xx1z0x1z
test -attern
res-onse functional 3or ex-ect6 data
test %ector num'er
stimulus functional data
F-data
in<0:7>out<0:7>
0 1 2 3 4 5 6 0 1 2 3 4 5 6
0
1
2
3
4
5
6
7


.!
"igital Test 4.ectors5
0 - 01001011 : xxxxxxxx
1 - 11001010 : xxxx0110
2 - 00110101 : 11001101
3 - 10100101 : 01001011
4 - 11010001 : 0010zzzz
5 - 00101101 : 0011zzzz
6 - 11010010 : xx1z0x1z
Digital Test System
D*T

3 - 10100101 : 01010011
5 - 00101101 : 001z0zzz
6 - 11010010 : xx1z0x00
fail datalog test -attern
in<0:7>out<0:7> in<0:7>out<0:7>


.)
"igital Test 4.ectors5 and STI-
 !ost testing today and for the foreseea&le future will &e digital
– (nam&iguous s$ecification of com$le" test re'uirements
– (nam&iguous e%aluation of $ass or fail result
– 0i1hly com(ut"2le – growth for multi$le generations
 ;on:digital re'uirements can ha%e digital manifestations –
– AD5 tests 0AST structures etc
 Hence STA/ – St"nd"rd 3est Interf"ce L"n1u"1e – A### 1@43
– Standard descri$tion of digital $atterns
– Standard descri$tion of logic transitions – 8e%ents9
– Standard descri$tion of &asic digital test wa%eforms


.*
Where .ectors Come From
 Stored Pattern *8functional9+ 1ectors
– Eenerated &y hand simulation sometimes ATPE
 S5A; 1ectors
– Eenerated mainly &y ATPEF re'uire scan:chain DFT
– (sed for structural tests
– (sed for $ath delay tests
– -e'uires launch:ca$ture clocking
 Algorithmic generation
– (sed mainly for memory arrays
 0uilt:in Self Test *0AST+ generators


.+
6ow STI- E%ent Streams come from .ectors
 1ariety of ways to re$resent digital tests
 All result in s$ecific acti%ity at each D(T $in
 Acti%ity at each D(T $in is a se4uence of e5ents
– An$ut $ins2 D1Gtime D3Gtime
– Cut$ut $ins2 T1Gtime T3Gtime HGtime
– AIC $ins2 D1Gtime D3Gtime DJGtime T1Gtime T3Gtime
TJGtime
 F:data translates to D1Ds D3Ds DJDs or T1Ds T3Ds TJDs
de$ending on AIC Definition


.,
0vent se2uences to test a fli#%flo#
D e%ent stream2 DFG3
5 e%ent stream2 DFG/# DFKGT#
BB; e%ent streams2 TFGS/# HGST# *window stro&e+
BB; e%ent streams2 TFGstro&eKtime *edge stro&e+
-- 'ut 0e must allo0 for inaccuracies
Stro'e Leading Edge
3SLE6
Stro'e Trailing Edge
3STE6
0 – 01:01
1 – 10:10
2 – 01:01
test -attern
:)
Leading Edge
3LE6
Trailing Edge
3TE6
D
C
:
FCB FCB FC1
:)
in-uts
out-ut
D
C
:
0indo0 stro'es
edge stro'es
out-ut :)


.-
T
E
A E&A
T
E
A E&A
0dge &lacement +ccuracy 70&+8
in-uts
out-ut
D
C
:
D
C
:
FCB FCB FC1
0indo0 stro'es
edge stro'es
out-ut :)
E%ent Time T
E
:) :)
0 – 01:01
1 – 10:10
2 – 01:01
test -attern


2/
"etermining 0dge &lacement
 #dge $lacement is a com&ination of three terms
– Program %alue within each %ector
– Accumulated %ector start offset
– 5ali&ration corrections
– Static systematic errors
– Pattern:de$endent systematic errors
– 5lock:de$endent systematic errors
 So how is it im$lemented?


2.
6ow a Tester Timing System Wor's
#%ent times further corrected &y cal offset
 corrections for $ath length %ariation *skew+
 corrections for dynamic errors
#%ent times adLusted &y $eriod offset
 transform %ector time to clock $lus inter$olation
 system clock decou(led from %ector rate
#%ent se'uences from F:data and 1ector Ty$e
 each $in has its own e%ent se'uence $er %ector


22
.ector Time Transformation
-eriod one -eriod t0o
e1 e2 e1 e2
cloc(
c171 c172 c272 c271
%171
%172
%271
%272
t171
t172
t271
t272
o1
Transform 1 Add accumulated -eriod offset to -rogram time
Transform 2 Add cali'ration offset 'ased on e%ent ty-e
Transform D Determine cloc( cycle containing e%ent time
and com-ute inter-olation %alue
#!en cloc( cycle occurs, trigger inter-olation delay circuit - - -


2
Ty#ical Tester Timing &ath
C-OC*
fanout
Inter#olator
dri%e mar(ers
F-data
E%ent Ty-es
Vector
ty-e
Inter#olator
stro'e mar(ers
Formatter
Formatter
DEI
DI)E
ACEI
,CLF
Load'oard
D*T
&ogo
&E ca'le
&0IC
Soc(et
MAI)F+AME 3mo%ing to test !ead6 TEST EEAD
E%ent Times
Time-critical -at!s Time-critical de%ices
E%ent Se"uence Generator


2!
Some Timing 0rror Sources
 Can t!ese errors 'e cali'rated/
– Cloc' generation noise
– Cloc' distriution noise
– Inter#olator non%linearity
– Mar'er noise
– Formatter noise
– Timing signal #ath dynamics
– &0 timing non%linearity
– &0%"9T signal #ath dynamics
– Source%cloc'ed "9T trac'ing error
– Caliration error
no
no
ye
ye
no
no
ye
ome
ome
N! ""
Dominant timing errors are
Static systematic errors
Tester clock cycle
de$endent systematic
errors
Pattern de$endent
systematic errors
;oise
Systematic errors are *in
$rinci$le+ correcta&le
)oise is not correcta'le
62ut c"n 2e "5er"1ed7


2)
.ariale Test 1ates
 Pin e%ent timing can change on the fly
– Different %ector ty$es may ha%e different timing
 Test rates can also change on the fly
– For match synchroni,ation
– For s$eed testing
– For characteri,ation and de&ugging


2*
.ariale Test 1ates 3 as used for deugging
Slower
Faster


2+
1ecent Ma!or Technology Shifts
 5lock !ulti$lication
– High:end uProc clocks multi$ly in$ut rate
– Anternal P// controls timing *not AT#+
 High:s$eed AICDs use local clocking
– Forwarded 5locks
– -eference 5locks
– #m&edded 5locks


2,
.ariale Test 1ates 3 with smart &-- cloc'
Slower
Faster
Launch Capture


2-
Fundamentals of IC Test: Summary of Session :
 !anufacturing $rocesses $roduce unshi$$a&le defects
– Wide %ariety of tests can &e a$$lied
– Studies show different tests e"$ose different defects
– Difficult to know " (riori which tests will &e most effecti%e
– #ffecti%e AT# must a$$ly a %ariety of tests in multi$le conditions
 Delay defects more $redominant in ad%anced A5 $rocesses
– Agile timing in AT# hel$ed identify and locate delay defects
– Higher s$eeds in modern de%ices challenge AT# agility
– Delta timing mo%ing on:chi$
 Mield management demands 'uick $rocess feed&ack
– To &e addressed in Session )


/
Fundamentals of IC Test: Course Outline
 Session 1 – The Structure of a Semiconductor Test
– Why test? What tests work? How are tests a$$lied?
– Digital !i"ed Signal and Analog Tests
– Functional Structural and Alternate Tests
– AT# Architecture and test e"ecution
– Patterns failure detection and res$onse logging
– Test %aria&les – %oltage fre'uency D(T tem$erature
 Session ) – A$$lying Tests for Physical Failure Analysis
– What goes on when a de%ice fails a test?
– Design #rrors %s Defects %s Parametric Failures
– How do we isolate locate and e"hi&it a circuit $ro&lem?
– Analy,ing and modifying tests to o&ser%e a failure mode
– #diting $hysical de%ices to demonstrate cause
– The role of AT# in $hysical failure analysis
 -eferences
– !. /. 0ushnell and 1. D. Agrawal, Essentials of Electronic Testing for Digital,
Memory and Mixed-Signal VLSI Circuits, 0oston2 S$ringer )334
– /. 5. Wagner ed. Failure Analysis of Integrated Circuits Tools and Tec!ni"ues,
0oston2 6luwer 1777


.
&hysical Failure +nalysis: Test -oo#s ;eeded
 Defect /ocali,ation -e'uires Amaging
– Frontside or &ackside imaging of $attern acti%ity
– Wa%eforms or circuit acti%ity heating etc.
 1irtually all imaging $rocesses re'uire sta&le re$eata&le tests
– Hundreds of thousands to many millions of re$etitions to collect
– Time:resol%ed emissions re'uire e"treme sta&ility
– Wa%eform ca$ture with >3:$s resolution is %ery demanding
 How does AT# Eenerate test loo$s?
– Functional $atterns
– Scan:&ased $atterns


2
Incor-orate t!e
&FA Loo-
Test O#eration Overview 3 Im-lementing a Loo-
Test Controller Test Instrument Inside the "9T
0)ecute test
+##ly ne)t
test vector
Start test
Com#are "9T
res#onse to tale
Install test
1eceive and organi$e
test se2uence/#atterns
??
-ass$fail
fail
-og fail
>>


IC Test and Measurement O!ectives
 "esign deug
– Circuit edit to su##ort deug
 "esign validation
 "evice characteri$ation
 "efect detection
– Faulty circuit uilt%in re#air
 "efect isolation
 Infant mortality acceleration
 &rom#t #rocess feedac'
 (uality assurance through #roduct lifetime
 Overall test cost control
– What to test and when to test it
– Minimi$e the cost of each test a##lied
– Ma)imi$e the return from each test
 Test cost reduction cannot com-romise test "uality
Early
Silicon
Al0ays
&roduction
Testing
>@

!
Why Integrated Circuit 0dit?
 1ast %ariety of so$histicated #DA tools hel$ designers de&ug
their code
 Test structure are im$lemented into A5 for $ost fa&rication
de%ice ins$ection $erformance N relia&ility assurance
 Design can &e tested simulated N de&ugged &efore fa&rication
 FA0 im$lements test structures for $rocess control N
%erification
 O
 #%ery ste$ starting from 5once$t to Fa&rication is well
monitored thoroughly tested and %erified multi$le times.
 8Cur Silicon is going to &e $erfectO9
 So why 5A-5(AT #DAT ??????
Designs are getting more com$le"
5locks are running faster
Anterference cross talk / N 5 are hard to $redict
5ore %oltages are dro$$ing
Pre:silicon testing is getting e"tremely tedious
Simulations are taking e"cessi%ely longer time:wise
Designs can not &e %erified 133P
Feature si,es are in the nano:meter range
Thinner gate:o"ides are causing une"$ected leakage
-outing layers are increasing in num&er
Dielectric N metal layers are getting thinner
(ltra:high do$ing $recision is needed for acti%es
High accuracy is needed for Analog A5s
Packaging can stress sensiti%e de%ices
O
Therefore Silicon m"y not 2e (erfect XXX
>4

)
;eed of Circuit 0dit
 Test finds the de%ice doesnDt work
– Testing may identify design failure source
 Simulations may %erify $ro$osed fi"
 0(T low confidence in making an e"$ensi%e mask change

 At may take weeks to months &efore an #5CDd A5 would &e
a%aila&le to %alidate design change.
 As it going to work ???

 Therefore FA0 5ircuit #dit is the solution for2
 1alidating design change on Tester
 Proceeding to !ask change with confidence
 Eetting working de%ices to customers ASAP
 5# %ital for fast N cost effecti%e Design:to:!arket solution
"esign
Customer
&roduction
:st Silicon
Test
;ot all suggested and successful 5ircuit #dits work if they did then
5ircuit #dit would &e redundant.
5ircuit edit -CA readily Lustified on &asis of reducing mask
costs
!ask cost sa%ings related to whether design #5C mo%es
forward
Af e%ery design #5C correct then wasteful to do 5#?
5an Lustify doing 5# anyway
5# ena&les further de&ug N diagnostics including AT# or
system &oard testing
!ay&e a )
nd
issue &eyond the 8known9?
Design #5C should &e e"ecuted &y 5# so retesting &efore mask
change
Failure
Known
Failure
Hidden
Failure
Fixed
Failure
Known
>=

*
C0 Technology 1oadma#
5ircuit edit sur%ey &y
5redence in early )334
 #dit time increases as num&er of routing layers increase *from >
to 13 in last 13 years+ with technology nodes
 5# tools re'uire constantly de%elo$ing hardware techni'ues N
chemistries to address multi:layer dee$ su&:micron A5s
 5AD na%igation is %ital for effecti%e 5# solutions
>?

+
Case Study
 Fli$chi$ 73nm 5uIlow:k $rocess
 5ircuit issue was that an incorrect $ower su$$ly 1dd1 was on three master
$hase locked loo$ controllers *P//5s+ i.e. the $ull:u$ %oltage on a logic gate
was incorrect.
 -e'uired connecting an !1 line to 1dd) on !> and cutting !1 line to isolate
1dd1 su$$ly.
 The low &eam current used for this o$eration made it successful.
 Cnce Test $ro%ed the edit worked edit was re$eated on the other ) P//5s N
Tested
 An all eight de%ices were edited and Tested good.
Focused Aon 0eam *FA0+ instrument are used to $hysically edit A5s
Criginal 5# conce$t $ro$osed electron &eams
FA0 more controlla&le N efficient
FA0 instrument are a&le to $erform cuts N de$osits as 8Fa&:In:a:,o"9
FA0 traces work around fa&rication as $er design layout
FA0 N fa& ha%e Vsame challenges
5# addresses modifications mainly in Al 5u I /ow6 and SiC
)
#dits can &e $erformed on $ackaged de%ice &are die or wafer
!ulti$le edits can &e $erformed on a single A5
A5s can &e edited from Front:side or from 0ackside *Fli$5hi$+ Si
><

,
C0 &lanning for in Silicon .alidation
 Cnce 5# is $art of de&ug then ) doors o$en2
 5# to fine tune analog circuitry
 5ase study2 Design $lanned for edit at critical
$oints
– !1 resistors could &e added to fine:tune design
– Test found $ro&lem in area where e"$ected
– 5# fi" em$loyed N design ad%anced
– Product de%elo$ment time reduced
 !ay not understand where risks are &ut #DA
tools should hel$
 ). 5ircuit edit ena&les %alidation of ne"t silicon
– When com$leted design team mo%es on to the se'uel
– Production silicon &ecomes $rototy$e for new design
– #dits %alidate assum$tions going into new design &efore
first silicon
;ew materials $resent new challenges to 5#
-ecently /ow:k and 5u has &een a challenge for 5#
5u grains etch non:uniformly N tend to rede$osit in the %icinity
/ow:k is %ery fragile and can cause to e"$ose circuitry %ery
'uickly
Solution2 FA0 $ro%ides chemistry to e%en out 5u remo%al
without re:de$osition while $rotecting the dielectric
5AD na%igation had &een a $owerful tool for 5ircuit #dit
Dummy fill metal generally added &y foundry due to $rocess
limitations
!erged 5AD with dummy metal often not a%aila&le
Dummy 5AD &eneficial to edit $lanning N e"ecuting
FIB e;(osed Cu dummy fill met"l with (orous CD<
6C"r2on Do(ed <;ide7 low=#
>ote? Irre1ul"r (orosity distri2ution
>7

-
IC Test and Measurement O!ectives
 "esign deug
– Circuit edit to su##ort deug
 "esign validation
 "evice characteri$ation
 "efect detection
– Faulty circuit uilt%in re#air
 "efect isolation
 Infant mortality acceleration
 &rom#t #rocess feedac'
 (uality assurance through #roduct lifetime
 Overall test cost control
– What to test and when to test it
– Minimi$e the cost of each test a##lied
– Ma)imi$e the return from each test
 Test cost reduction cannot com-romise test "uality
Early
Silicon
Al0ays
&roduction
Testing


!/
<ield vs maturity vs com#le)ity
-
e
la
ti%e
D
e
%ice 5
o
m
$le
"ity
=
>
?
>
:
>
>
:
:=
>
:>
=>
@>
A>
B>
?>
C>
D>
E>
:>>
P
r
o
c
e
s
s

!
a
t
u
r
i
t
y
*
B
u
a
r
t
e
r
s
+
M
i
e
l
d

*
P
+
@1

!.
;ew Technologies 3 ;ew &rolems
Ancreasing differences
&etween simulation models
and reality are making it e%er
more im$ractical to simulate
fully new designs
 !ulti:metal interconnects
 ;ew $hysical designs
: 1>3 nm 73 nm =4 nmO
 ;ew materials
: SCA
:
/ow 6 dielectric
:
5o$$er
:
Strained silicon Taur M. and T. H. ;ing *177<+. Fundamentals of !odern 1/SA De%ices.
5am&ridge (6 5am&ridge (ni%ersity Press.
To su$$ort the high integration high s$eed low current re'uired and
tight minimum features si,e todayDs state of the art technology in%ol%es
shrinking gate dimensions multi$le le%el interconnect and host of new
materials. All these changes are e"tremely difficult to model and
simulate. 5om$act models for su&:3.1< um and &elow are e"tremely
com$le" and often do not accurately re$resent the &eha%ior of high:
s$eed circuits Y1 )Z. Andeed accurate SCA models are still emergingY>
@Z. With each new technology generation there is a race &etween the
$rocess maturation and the circuit design community. While designers
are &usy creating the new design the $rocess engineers are still
adLusting the $rocess $arameters. As a result the correlation &etween
simulated results and $hysical im$lementation is weak es$ecially for
early silicon.
There are also growing class of de%ice a&normalities which do not
manifest themsel%es as hard failures &ut rather as 8soft failures9. These
failures manifest themsel%es only under certain conditions of
tem$erature fre'uency or %oltageY4Z. !any failures analysis la&s rely
on $hysical e%idence for their analysis &ut many new failure conditions
are non:%isualY=Z.
This difference &etween simulation and modeling and the actual
$erformance on the chi$ has &een growing more and more $ronounced
from generation to generation and has increased the need for analysis
of finished de%ices to o$timi,e $erformance. Ei%en the im$ortance of
$hysical design %erification – how efficient are the current $rocesses
used in the industry?
@)

!2
Timing "eug
 Pro&lem2 !otorola *Freescale+ de%ice
 Scan chain was failing at certain s$eeds in new SCA design
– Structural diagnostic software was not a$$lica&le
– Scan $attern loo$ length2 =3 microseconds
– Power su$$ly2 1.<1
 #miSco$e !ethodology
– !easure wa%eforms at key nodes to identify root:cause of failure
@>

!
Timing "eug
 51K5/6 turned off too late to &lock the falling transition at DA;
 #miSco$e timing measurement identified a race condition
 5hanging 51K5/6 timing sol%ed the $ro&lem
A
Courtesy of
A. An$ut data sends falling edge through ;!CS at *A+
0. Simultaneously falling edge of P5H at *0+ turns off P!CS
5. 5orrect data sent into /atch at *5+ Y515/6 clock is onZ
D. /ater Hatch data is fli$$ed at *D+
#. Why? As 515/6 falls DA; also falls
F. A rising edge on P5H at *F+ $ro$agates to DA; &efore the 515/6
falls.
Solution2 delay P5H


!!
1esistive Interconnect -ocali$ation
 5an use imaging tools to locali,e a wide %ariety of faults
– Traditional 8static9 and 8hard9 faults common &elow )43 nm
– Design and 8soft9 faults increasingly common &elow 73 nm
Design Fault
Hard Fault
Dynamic (“Soft”) Fault
Static
Fault


!)
1esistive Fate -ocali$ation
P. Song F. !otika and D. -. 6ne&el QSI>73 E4 5!CS micro$rocessor diagnosticsQ IB8 9ourn"l of
:ese"rch "nd De5elo(ment %ol. @> $$. <77:71@ 1777.
 /ocali,e and 5haracteri,e interconnect faults


!*
"esign 0rror 3 Transistor Mismatch
 Design error of mismatched
transistor in analog circuit
 (sed #miSco$e to locali,e fault
 Simulated o&ser%ed wa%eforms
to identify root:cause
– Eood de%ice to &ad de%ice
com$arison aided analysis
@?

!+
1esistive .ia -ocali$ation
 Information related to failure7s8 was used in fault diagnosis #rocess
: Syno#sys TetraM+G and Cadence 0ncounter Test "iagnostics were used
to locali$e fault
Failing
Fli#%Flo#s
The schematic a&o%e highlights the fli$:flo$s where the failure is
occurring.
The failing flo$ information was fed into &oth Syno$sys Tetra!AH and
5adence Test&ench *now called #ncounter Test Design #dition+ for
fault modeling and diagnosis.
@<

!,
1esistive .ia -ocali$ation 7contHd8
 Failure was li'ely related to the = ;O1 Fates
U The ) ;C- gates were then $ro&ed. An a&normal emission
wa%eform was ca$tured from &oth gates. The signals were slow
$ersistent emission wa%eforms suggesting a %ery slow in$ut signal to
&oth of the ;C- gates.
U From e"$erience the $ro&lem looked to &e resisti%e in nature.
@7

!-
1esistive .ia -ocali$ation 7contHd8
 Pro&e results clearly identified failing net
 0ased on results one of two %ias was $oint of failure
U Cn in%estigation of the layout we found that the ) ;C- gates were
fed &y a common metal segment. Cne of two 1AAs on this segment
was e"hi&iting a&normal resisti%ity.
43

)/
-ogic "eug
– Test results indicate the &+" is high while e)#ected value is low
– 9se logic state tracing to identify source of failure
F
F 7C-*8
F-I&%F-O&
0 "
C
, +
&+"
The e"am$le descri&es how to trace a ty$ical signal
through a logic $ath to $in$oint the root cause of a $ro&lem.
The sym$tom of the failure is that the tester re$orts that
PAD is high while the e"$ected %alue is /CW.
The failure analysis starts at PAD and $ro&es &ackwards
through the logic. He com$ares the e"$ected *simulated+
wa%eforms to the data measured &y the #miSco$e. Af no
simulation information is a%aila&le he could $ro&e the same
signals on a good $art and on a &ad $art. An this case
simulation data is a%aila&le to which he com$ares the
#miSco$e data. He is looking for a gate with the correct
in$uts &ut the wrong out$uts indicating that there is
something wrong with that circuit.
The #miSco$e $roduces current emission $ulses. The
n!CS $roduces an emission s$ike when the out$ut $asses
from high to low while the $!CS $roduces a $hoton
emission s$ike when the out$ut $asses from low to high.
The strength of emission of the $!CS is lower than the
n!CS &ecause holes *the maLority carrier for $:do$ed
silicon+ ha%e lower mo&ility than electrons *the maLority
carrier for n:do$ed silicon+.
41

).
-ogic "eug 7contHd8
F
E *5/6+
F/AP:F/CP
# D
5
0 A
PAD
EmiScope Data Reconstructed Logic Simulated Logic
A

B

C

D

E

F

G


"iscussion
The #miSco$e $ro&es signals from switching transistors. An this
e"am$le we are $ro&ing transistors *&oth n!CS and $!CS+
which are dri%ing the lines associated with the signal.
The $ro&e locations and results are discussed &elow2
A. The reconstructed wa%eform doesnDt match the simulated data.
The error must &e u$stream from the $ro&ed signal
0. The reconstructed wa%eform still doesnDt match the simulated
wa%eform. The error is further u$stream.
5. The wa%eform matches the simulated signal. The error is not in the
$ath &efore 5 so we sto$ $ro&ing this $ath.
D. The wa%eform does not match simulation.
#. The wa%eform still doesnDt match simulation.
F. The wa%eform does match simulation suggesting that something
is going wrong at the fli$:flo$.
E. The reconstructed wa%eform shows that 5/6 edge is too early so
the wrong data from F is &eing $assed through the latch.
4)

)2
Ty#ical &ost%Silicon &rolems
 Mield is lower than re'uired on new technology
– Ana&ility to fully model circuit &eha%ior
– Anaccurate design models es$ecially for timing and Litter
 -esisti%e failures
– Ancom$lete %ias electromigration metal &ridges etc.
 Design errors
– C%er 43P of design time is s$ent in %erification
– Met – desi1n errors "re still common
 Ancom$lete success with ATPE methodologies
– Ancom$lete test co%erage
– Ancom$lete fault co%erage
– Scan chain failures
They are e)#ected to get worse elow E> nm


)
:
st
Si Failures %"esign "eug Issues
AI
:@I
:CI
:CI
=>I
=:I
=@I
=BI
=DI
=EI
@BI
?CI
Other
Firmware
&ower
1ace Condition
I1 "ro#s
Mi)ed%Signal Interface
<ield
Cloc'ing
Slow &ath
;oise
+nalog Circuit
-ogic or Functional
HCollett International ;$B2
:st Si 0rror/Flaw "istriution
Sam$le of )41 designs from
;orth America com$leted in )33)
@
or more
>
)
1
13P )3P >3P
;
u
m

e
r

o
f

S
i
l
i
c
o
n

S
#
i
n
s
@3P
HCollett International +esearc! Inc7 from Electronic
,usiness Iun$BD
+t least ?:I of new designs
7or shrin's8 re2uired a res#in
TodayDs A5 $erformance re'uirements and leading:edge $rocesses
make it %ery difficult to se$arate design errors from $rocess margins


)!
design
definition
design
-artitioning
structural
im-lementation
-!ysical
im-lementation
design
-rototy-e
de%ice
%alidation
design
%erification
Firmware 7:@I8
&ower 7:CI8
1ace Condition 7:CI8
I1 "ro#s 7=>I8
Mi)ed%Signal Interface 7=:I8
<ield 7=@I8
Cloc'ing 7=BI8
Slow &ath 7=DI8
-ogic or Functional 7?CI8
;oise 7=EI8
+nalog Circuit 7@BI8
CF*LD D7V7 EAVE
CA*GET TEEM ALL //
Collett Intern"tion"l :ese"rch, A(ril 2//2
"esigns 6aving One or More 1e%s#ins y Ty#e of Flaw
Why didnHt it wor' ??
EFFECTIVE TFFLS A+E
STILL )FT AVAILA,LE JJ


))
The "eug Challenge
 Huge 'uantities of circuitry
 !assi%e %olumes of data to manageIanaly,e
 Parametric de%iations causing more de%ice failures
 Data access limited &y AC &andwidth
– faster data access R shorter de&ug time
 Desired data flow for de&ug
– *may&e+ scan in to esta&lish starting state of entire de%ice
– $attern e"ecution with AC esta&lished &y $attern
– *may&e+ scan dum$ together with standard AC for analysis
 !ulti E0PS data rate RS non:deterministic $atterns
– data collection must co$e with %arying data
– cannot acce$t fi"ed:$rotocol solutions
– reconfigure AT# for s$ecific $rotocols
– dum$ &it $atterns for later software $rotocol analysis


)*
"iffering "eug .iew#oints
 TesterDs:eye 1iew
– dataflow – &oth in and out
– in$ut wa%eforms
– out$ut wa%eforms
 D(TDs:eye 1iew
– high:le%el structure
– -T/
– logical circuit detail
– to$ology
– $hysical im$lementation


)+
"9THs%eye .iew: 6igh%-evel Structure 7:8


),
"9THs%eye .iew: 6igh%-evel Structure 7=8
#include "systemc.h"
void fft::entry()
{ float sample[16][2]
unsi!ned int inde"
#hile(true)
{ data$re%.#rite(false)
#hile( inde" & 16 )
{
data$re%.#rite(true)
#ait$until(data$valid.delayed() '' true)
sample[inde"][(] ' in$real.read()
sample[inde"][1] ' in$ima!.read()
inde"))
data$re%.#rite(false)
#ait()
*
inde" ' (
++,alculate the -.values recursively
#$real ' cos(theta)
#$ima! ' .sin(theta)
#hile(inde" & len.1)
{
#$temp ' #$rec$real/#$real . #$rec$ima!/#$ima!
#$rec$ima! ' #$rec$real/#$ima! ) #$rec$ima!/#$real
#$rec$real ' #$temp
-[inde"][(] ' #$rec$real
-[inde"][1] ' #$rec$ima!
inde"))
*
++0e!in ,omputation
sta!e ' (
len ' 1 incr ' 1
#hile (sta!e & 2)
{
len ' len+2
#hile(i & 1)
{
sample[inde"][(] ' tmp$real
sample[inde"][1] ' tmp$ima!
i ' i ) 2/len
*
sta!e))
*
*


)-
"9THs%eye .iew: 1T-
#include "systemc.h"
void fft::entry()
{ float sample[16][2]
unsi!ned int inde"
#hile(true)
{ data$re%.#rite(false)
#hile( inde" & 16 )
{
data$re%.#rite(true)
#ait$until(data$valid.delayed() '' true)
sample[inde"][(] ' in$real.read()
sample[inde"][1] ' in$ima!.read()
inde"))
data$re%.#rite(false)
#ait()
*
inde" ' (
++,alculate the -.values recursively
#$real ' cos(theta)
#$ima! ' .sin(theta)
#hile(inde" & len.1)
{
#$temp ' #$rec$real/#$real . #$rec$ima!/#$ima!
#$rec$ima! ' #$rec$real/#$ima! ) #$rec$ima!/#$real
#$rec$real ' #$temp
-[inde"][(] ' #$rec$real
-[inde"][1] ' #$rec$ima!
inde"))
*
++0e!in ,omputation
sta!e ' (
len ' 1 incr ' 1
#hile (sta!e & 2)
{
len ' len+2
#hile(i & 1)
{
sample[inde"][(] ' tmp$real
sample[inde"][1] ' tmp$ima!
i ' i ) 2/len
*
sta!e))
*
*
#include "systemc.h"
void fft::entry()
{ float sample[16][2]
unsi!ned int inde"
#hile(true)
{ data$re%.#rite(false)
#hile( inde" & 16 )
{
data$re%.#rite(true)
#ait$until(data$valid.delayed() '' true)
sample[inde"][(] ' in$real.read()
sample[inde"][1] ' in$ima!.read()
inde"))
data$re%.#rite(false)
#ait()
*
inde" ' (
++,alculate the -.values recursively
#$real ' cos(theta)
#$ima! ' .sin(theta)
#hile(inde" & len.1)
{
#$temp ' #$rec$real/#$real . #$rec$ima!/#$ima!
#$rec$ima! ' #$rec$real/#$ima! ) #$rec$ima!/#$real
#$rec$real ' #$temp
-[inde"][(] ' #$rec$real
-[inde"][1] ' #$rec$ima!
inde"))
*
++0e!in ,omputation
sta!e ' (
len ' 1 incr ' 1
#hile (sta!e & 2)
{
len ' len+2
#hile(i & 1)
{
sample[inde"][(] ' tmp$real
sample[inde"][1] ' tmp$ima!
i ' i ) 2/len
*
sta!e))
*
*
void fft::entry()
{ float sample[16][2]
unsi!ned int inde"
#hile(true)
{ data$re%.#rite(false)
#hile( inde" & 16 )
{
data$re%.#rite(true)
#ait$until(data$valid.delayed() '' true)
sample[inde"][(] ' in$real.read()
sample[inde"][1] ' in$ima!.read()
inde"))
data$re%.#rite(false)
#ait()
*
inde" ' (
++,alculate the -.values recursively
#$real ' cos(theta)
#$ima! ' .sin(theta)
#hile(inde" & len.1)
{
#$temp ' #$rec$real/#$real . #$rec$ima!/#$ima!
#$rec$ima! ' #$rec$real/#$ima! ) #$rec$ima!/#$real
#$rec$real ' #$temp
-[inde"][(] ' #$rec$real
-[inde"][1] ' #$rec$ima!
inde"))
*
++0e!in ,omputation
sta!e ' (
len ' 1 incr ' 1
#hile (sta!e & 2)
{
len ' len+2
#hile(i & 1)
{
sample[inde"][(] ' tmp$real
sample[inde"][1] ' tmp$ima!
i ' i ) 2/len
*
sta!e))
*
*
void fft::entry()
{ float sample[16][2]
unsi!ned int inde"
#hile(true)
{ data$re%.#rite(false)
#hile( inde" & 16 )
{
data$re%.#rite(true)
#ait$until(data$valid.delayed() '' true)
sample[inde"][(] ' in$real.read()
sample[inde"][1] ' in$ima!.read()
inde"))
data$re%.#rite(false)
#ait()
*
inde" ' (
++,alculate the -.values recursively
#$real ' cos(theta)
#$ima! ' .sin(theta)
#hile(inde" & len.1)
{
#$temp ' #$rec$real/#$real . #$rec$ima!/#$ima!
#$rec$ima! ' #$rec$real/#$ima! ) #$rec$ima!/#$real
#$rec$real ' #$temp
-[inde"][(] ' #$rec$real
-[inde"][1] ' #$rec$ima!
inde"))
*
++0e!in ,omputation
sta!e ' (
len ' 1 incr ' 1
#hile (sta!e & 2)
{
len ' len+2
#hile(i & 1)
{
sample[inde"][(] ' tmp$real
sample[inde"][1] ' tmp$ima!
i ' i ) 2/len
*
sta!e))
*
*
void fft::entry()
{ float sample[16][2]
unsi!ned int inde"
#hile(true)
{ data$re%.#rite(false)
#hile( inde" & 16 )
{
data$re%.#rite(true)
#ait$until(data$valid.delayed() '' true)
sample[inde"][(] ' in$real.read()
sample[inde"][1] ' in$ima!.read()
inde"))
data$re%.#rite(false)
#ait()
*
inde" ' (
++,alculate the -.values recursively
#$real ' cos(theta)
#$ima! ' .sin(theta)
#hile(inde" & len.1)
{
#$temp ' #$rec$real/#$real . #$rec$ima!/#$ima!
#$rec$ima! ' #$rec$real/#$ima! ) #$rec$ima!/#$real
#$rec$real ' #$temp
-[inde"][(] ' #$rec$real
-[inde"][1] ' #$rec$ima!
inde"))
*
++0e!in ,omputation
sta!e ' (
len ' 1 incr ' 1
#hile (sta!e & 2)
{
len ' len+2
#hile(i & 1)
{
sample[inde"][(] ' tmp$real
sample[inde"][1] ' tmp$ima!
i ' i ) 2/len
*
sta!e))
*
*
#include "systemc.h"
void fft::entry()
{ float sample[16][2]
unsi!ned int inde"
#hile(true)
{ data$re%.#rite(false)
#hile( inde" & 16 )
{
data$re%.#rite(true)
#ait$until(data$valid.delayed() '' true)
sample[inde"][(] ' in$real.read()
sample[inde"][1] ' in$ima!.read()
inde"))
data$re%.#rite(false)
#ait()
*
inde" ' (
++,alculate the -.values recursively
#$real ' cos(theta)
#$ima! ' .sin(theta)
#hile(inde" & len.1)
{
#$temp ' #$rec$real/#$real . #$rec$ima!/#$ima!
#$rec$ima! ' #$rec$real/#$ima! ) #$rec$ima!/#$real
#$rec$real ' #$temp
-[inde"][(] ' #$rec$real
-[inde"][1] ' #$rec$ima!
inde"))
*
++0e!in ,omputation
sta!e ' (
len ' 1 incr ' 1
#hile (sta!e & 2)
{
len ' len+2
#hile(i & 1)
{
sample[inde"][(] ' tmp$real
sample[inde"][1] ' tmp$ima!
i ' i ) 2/len
*
sta!e))
*
*
void fft::entry()
{ float sample[16][2]
unsi!ned int inde"
#hile(true)
{ data$re%.#rite(false)
#hile( inde" & 16 )
{
data$re%.#rite(true)
#ait$until(data$valid.delayed() '' true)
sample[inde"][(] ' in$real.read()
sample[inde"][1] ' in$ima!.read()
inde"))
data$re%.#rite(false)
#ait()
*
inde" ' (
++,alculate the -.values recursively
#$real ' cos(theta)
#$ima! ' .sin(theta)
#hile(inde" & len.1)
{
#$temp ' #$rec$real/#$real . #$rec$ima!/#$ima!
#$rec$ima! ' #$rec$real/#$ima! ) #$rec$ima!/#$real
#$rec$real ' #$temp
-[inde"][(] ' #$rec$real
-[inde"][1] ' #$rec$ima!
inde"))
*
++0e!in ,omputation
sta!e ' (
len ' 1 incr ' 1
#hile (sta!e & 2)
{
len ' len+2
#hile(i & 1)
{
sample[inde"][(] ' tmp$real
sample[inde"][1] ' tmp$ima!
i ' i ) 2/len
*
sta!e))
*
*
void fft::entry()
{ float sample[16][2]
unsi!ned int inde"
#hile(true)
{ data$re%.#rite(false)
#hile( inde" & 16 )
{
data$re%.#rite(true)
#ait$until(data$valid.delayed() '' true)
sample[inde"][(] ' in$real.read()
sample[inde"][1] ' in$ima!.read()
inde"))
data$re%.#rite(false)
#ait()
*
inde" ' (
++,alculate the -.values recursively
#$real ' cos(theta)
#$ima! ' .sin(theta)
#hile(inde" & len.1)
{
#$temp ' #$rec$real/#$real . #$rec$ima!/#$ima!
#$rec$ima! ' #$rec$real/#$ima! ) #$rec$ima!/#$real
#$rec$real ' #$temp
-[inde"][(] ' #$rec$real
-[inde"][1] ' #$rec$ima!
inde"))
*
++0e!in ,omputation
sta!e ' (
len ' 1 incr ' 1
#hile (sta!e & 2)
{
len ' len+2
#hile(i & 1)
{
sample[inde"][(] ' tmp$real
sample[inde"][1] ' tmp$ima!
i ' i ) 2/len
*
sta!e))
*
*
void fft::entry()
{ float sample[16][2]
unsi!ned int inde"
#hile(true)
{ data$re%.#rite(false)
#hile( inde" & 16 )
{
data$re%.#rite(true)
#ait$until(data$valid.delayed() '' true)
sample[inde"][(] ' in$real.read()
sample[inde"][1] ' in$ima!.read()
inde"))
data$re%.#rite(false)
#ait()
*
inde" ' (
++,alculate the -.values recursively
#$real ' cos(theta)
#$ima! ' .sin(theta)
#hile(inde" & len.1)
{
#$temp ' #$rec$real/#$real . #$rec$ima!/#$ima!
#$rec$ima! ' #$rec$real/#$ima! ) #$rec$ima!/#$real
#$rec$real ' #$temp
-[inde"][(] ' #$rec$real
-[inde"][1] ' #$rec$ima!
inde"))
*
++0e!in ,omputation
sta!e ' (
len ' 1 incr ' 1
#hile (sta!e & 2)
{
len ' len+2
#hile(i & 1)
{
sample[inde"][(] ' tmp$real
sample[inde"][1] ' tmp$ima!
i ' i ) 2/len
*
sta!e))
*
*
#include "systemc.h"
void fft::entry()
{ float sample[16][2]
unsi!ned int inde"
#hile(true)
{ data$re%.#rite(false)
#hile( inde" & 16 )
{
data$re%.#rite(true)
#ait$until(data$valid.delayed() '' true)
sample[inde"][(] ' in$real.read()
sample[inde"][1] ' in$ima!.read()
inde"))
data$re%.#rite(false)
#ait()
*
inde" ' (
++,alculate the -.values recursively
#$real ' cos(theta)
#$ima! ' .sin(theta)
#hile(inde" & len.1)
{
#$temp ' #$rec$real/#$real . #$rec$ima!/#$ima!
#$rec$ima! ' #$rec$real/#$ima! ) #$rec$ima!/#$real
#$rec$real ' #$temp
-[inde"][(] ' #$rec$real
-[inde"][1] ' #$rec$ima!
inde"))
*
++0e!in ,omputation
sta!e ' (
len ' 1 incr ' 1
#hile (sta!e & 2)
{
len ' len+2
#hile(i & 1)
{
sample[inde"][(] ' tmp$real
sample[inde"][1] ' tmp$ima!
i ' i ) 2/len
*
sta!e))
*
*
void fft::entry()
{ float sample[16][2]
unsi!ned int inde"
#hile(true)
{ data$re%.#rite(false)
#hile( inde" & 16 )
{
data$re%.#rite(true)
#ait$until(data$valid.delayed() '' true)
sample[inde"][(] ' in$real.read()
sample[inde"][1] ' in$ima!.read()
inde"))
data$re%.#rite(false)
#ait()
*
inde" ' (
++,alculate the -.values recursively
#$real ' cos(theta)
#$ima! ' .sin(theta)
#hile(inde" & len.1)
{
#$temp ' #$rec$real/#$real . #$rec$ima!/#$ima!
#$rec$ima! ' #$rec$real/#$ima! ) #$rec$ima!/#$real
#$rec$real ' #$temp
-[inde"][(] ' #$rec$real
-[inde"][1] ' #$rec$ima!
inde"))
*
++0e!in ,omputation
sta!e ' (
len ' 1 incr ' 1
#hile (sta!e & 2)
{
len ' len+2
#hile(i & 1)
{
sample[inde"][(] ' tmp$real
sample[inde"][1] ' tmp$ima!
i ' i ) 2/len
*
sta!e))
*
*
void fft::entry()
{ float sample[16][2]
unsi!ned int inde"
#hile(true)
{ data$re%.#rite(false)
#hile( inde" & 16 )
{
data$re%.#rite(true)
#ait$until(data$valid.delayed() '' true)
sample[inde"][(] ' in$real.read()
sample[inde"][1] ' in$ima!.read()
inde"))
data$re%.#rite(false)
#ait()
*
inde" ' (
++,alculate the -.values recursively
#$real ' cos(theta)
#$ima! ' .sin(theta)
#hile(inde" & len.1)
{
#$temp ' #$rec$real/#$real . #$rec$ima!/#$ima!
#$rec$ima! ' #$rec$real/#$ima! ) #$rec$ima!/#$real
#$rec$real ' #$temp
-[inde"][(] ' #$rec$real
-[inde"][1] ' #$rec$ima!
inde"))
*
++0e!in ,omputation
sta!e ' (
len ' 1 incr ' 1
#hile (sta!e & 2)
{
len ' len+2
#hile(i & 1)
{
sample[inde"][(] ' tmp$real
sample[inde"][1] ' tmp$ima!
i ' i ) 2/len
*
sta!e))
*
*
void fft::entry()


*/
"9THs%eye .iew: -ogic Circuit "etail
#include "systemc.h"
void fft::entry()
{ float sample[16][2]
unsi!ned int inde"
#hile(true)
{ data$re%.#rite(false)
#hile( inde" & 16 )
{
data$re%.#rite(true)
#ait$until(data$valid.delayed() '' true)
sample[inde"][(] ' in$real.read()
sample[inde"][1] ' in$ima!.read()
inde"))
data$re%.#rite(false)
#ait()
*
inde" ' (
++,alculate the -.values recursively
#$real ' cos(theta)
#$ima! ' .sin(theta)
#hile(inde" & len.1)
{
#$temp ' #$rec$real/#$real . #$rec$ima!/#$ima!
#$rec$ima! ' #$rec$real/#$ima! ) #$rec$ima!/#$real
#$rec$real ' #$temp
-[inde"][(] ' #$rec$real
-[inde"][1] ' #$rec$ima!
inde"))
*
++0e!in ,omputation
sta!e ' (
len ' 1 incr ' 1
#hile (sta!e & 2)
{
len ' len+2
#hile(i & 1)
{
sample[inde"][(] ' tmp$real
sample[inde"][1] ' tmp$ima!
i ' i ) 2/len
*
sta!e))
*
*
void fft::entry()
{ float sample[16][2]
unsi!ned int inde"
#hile(true)
{ data$re%.#rite(false)
#hile( inde" & 16 )
{
data$re%.#rite(true)
#ait$until(data$valid.delayed() '' true)
sample[inde"][(] ' in$real.read()
sample[inde"][1] ' in$ima!.read()
inde"))
data$re%.#rite(false)
#ait()
*
inde" ' (
++,alculate the -.values recursively
#$real ' cos(theta)
#$ima! ' .sin(theta)
#hile(inde" & len.1)
{
#$temp ' #$rec$real/#$real . #$rec$ima!/#$ima!
#$rec$ima! ' #$rec$real/#$ima! ) #$rec$ima!/#$real
#$rec$real ' #$temp
-[inde"][(] ' #$rec$real
-[inde"][1] ' #$rec$ima!
inde"))
*
++0e!in ,omputation
sta!e ' (
len ' 1 incr ' 1
#hile (sta!e & 2)
{
len ' len+2
#hile(i & 1)
{
sample[inde"][(] ' tmp$real
sample[inde"][1] ' tmp$ima!
i ' i ) 2/len
*
sta!e))
*


*.
"9THs%eye .iew: The Circuit "eug &rocess
#include "systemc.h"
void fft::entry()
{ float sample[16][2]
unsi!ned int inde"
#hile(true)
{ data$re%.#rite(false)
#hile( inde" & 16 )
{
data$re%.#rite(true)
#ait$until(data$valid.delayed() '' true)
sample[inde"][(] ' in$real.read()
sample[inde"][1] ' in$ima!.read()
inde"))
data$re%.#rite(false)
#ait()
*
inde" ' (
++,alculate the -.values recursively
#$real ' cos(theta)
#$ima! ' .sin(theta)
#hile(inde" & len.1)
{
#$temp ' #$rec$real/#$real . #$rec$ima!/#$ima!
#$rec$ima! ' #$rec$real/#$ima! ) #$rec$ima!/#$real
#$rec$real ' #$temp
-[inde"][(] ' #$rec$real
-[inde"][1] ' #$rec$ima!
inde"))
*
++0e!in ,omputation
sta!e ' (
len ' 1 incr ' 1
#hile (sta!e & 2)
{
len ' len+2
#hile(i & 1)
{
sample[inde"][(] ' tmp$real
sample[inde"][1] ' tmp$ima!
i ' i ) 2/len
*
sta!e))
*
*
void fft::entry()
{ float sample[16][2]
unsi!ned int inde"
#hile(true)
{ data$re%.#rite(false)
#hile( inde" & 16 )
{
data$re%.#rite(true)
#ait$until(data$valid.delayed() '' true)
sample[inde"][(] ' in$real.read()
sample[inde"][1] ' in$ima!.read()
inde"))
data$re%.#rite(false)
#ait()
*
inde" ' (
++,alculate the -.values recursively
#$real ' cos(theta)
#$ima! ' .sin(theta)
#hile(inde" & len.1)
{
#$temp ' #$rec$real/#$real . #$rec$ima!/#$ima!
#$rec$ima! ' #$rec$real/#$ima! ) #$rec$ima!/#$real
#$rec$real ' #$temp
-[inde"][(] ' #$rec$real
-[inde"][1] ' #$rec$ima!
inde"))
*
++0e!in ,omputation
sta!e ' (
len ' 1 incr ' 1
#hile (sta!e & 2)
{
len ' len+2
#hile(i & 1)
{
sample[inde"][(] ' tmp$real
sample[inde"][1] ' tmp$ima!
i ' i ) 2/len
*
sta!e))
*
=)

*2
 Short channel – 73 nm and =4 nm design rules
– Amage and s$atial resolution
– Short channel modeling is difficult
 Dro$$ing o$erating %oltage le%els
– #mission signals are weaker
– /ower $roducti%ity and effecti%eness of solutions
 !aterials and $rocess challenges
– -esisti%e shorts I &ridges
– Higher leakage $ro&lems
 !ulti$le metal interconnect
– S = metal layers – 8front side o&struction9
– 5a$aciti%e effects and cross talkF difficult modeling
 Physical node le%el de&ug and FA is essential
 #%er increasing $erformance I sensiti%ity is most im$ortant
Challenges of +dvanced &roduct F+ / "eug
;eed for &etter
resolution N
node le%el $ro&ing
;eed for &etter
sensiti%ity
;eed for &etter
sensiti%ity
;eed for &ackside
image resolution N
node le%el $ro&ing
=>

22
*
0
r
i
d
g
e

D
e
f
e
c
t
s

P
o
$
u
l
a
t
i
o
n
4Test Challenges for "ee# Su%Micron Technologies5J MJ 1odgers, etJ alJ "+C =>>>
Fault Free
S-eed Failure
Soft Fail
Logic Failure
Hard Fail *SIA fault+
Increasing ,ridge
+esistance
D !allett, et al, "#$
Smaller $rocess nodes *1>3 nm N &elow+ are
&ecoming more sensiti%e to higher - &ridges.
Ancreasing num&er of resisti%e defects causing more
1dd tem$ N fre' sensiti%e fails *soft failures+.
/ocali,ing resisti%e defects is %ery difficult using
con%entional techni'ues *mech $ro&es+.
0ffects of 1esistive ,ridges vs &rocess ;ode


*!
0ffective 1esistive "efect -ocali$ation Techni2ues
-aser λ
( 0ffect8
Static -aser Stimulation 7S-S8 "ynamic -aser Simulation
7"-S8
,ias: C. Measure: ∆I
,ias: CI Measure: ∆.
,ias: ;one Measure:
∆. or ∆I
Monitor &ass/Fail
K ::>> nm
7Carrier
In!ection8
-I.+/GI.+, L
"iffusions
GI.+/O,IC, LJ
"iffusions
-+"+/C&+
Marginality isolation y
carrier in!ection
:@>> nm
7Thermal8
TI.+/O,I1C6/GI.+
1esistive vias
Metal shorts
1esistive o#ens
0lectromigration
S00,0C*
Contact o#ens
S"-/C&+
Marginality isolation y
local heating 7soft defects8
1esistive interconnects
1esistive ridges
Elo&alScan /aser Stimulation A$$lications


*)
0ffective 1esistive "efect -ocali$ation Techni2ues
-esisti%e single node
interconnect defect
O,I1C6:
Aneffecti%e
"-S:
High success P
Most difficult to isolate
.dd
F;"
-esisti%e defect to
1dd NIor E;D
O,I1C6:
High success P
"-S:
!edium success P
Classic static use case
-esisti%e defect *&ridges+
&etween internal nodes
O,I1C6:
!edium success P
"-S:
High success P
Challenging to isolate


**
"-S Case Study M: % SI- on E> nm IC

Design meets design rules *73nm $rocess+

Mield T13P

Part sensiti%e to2
U 1oltage
U Tem$erature *would tend to Pass if heated a few degrees+
U Fre'uency

Simulations una&le to isolate
 Sus$ect logic &lock was identified &ut could not &e %erified or
locali,ed to the transistors
#miSco$e and Elo&alScan used to effecti%ely locali,e the
defect area
System &oard was used as stimulus N PassIFail
generation


*+
"-S Case Study M: %SI- on E> nm IC "ata
==>) SI- lens
Thresholding used to
highlight strongest signal
region
==>) SI- lens
SA/ D/S image showing
resolution T)33 nm
433nm
Elo&alScan Thermal D/S !ode *SA/ /ens+
433nm
 Freen indicates &ass
7#asses when heated8
 9sing SI- N "-S, the data
clearly identifies !ust a few
4minimum dimension5
transistors in the sus#ect
areaJ
 4Freen stringers5 follow
the #oly structure
 Standard air ga# lens can
not #rovide this detail
 "ata shows a shar# thermal
sensitivity inside the circuit
area
 "ata collected in minutes


*,
"-S Case Study M= %n.I"I+ +SIC Elo&alScan Thermal D/S !ode :Soft Failure in AP !emory 0lock
 Mield $ro&lem intermittent
read failures from an AP &lock
 Failure at high T high 1
low fre'. *leakage sus$ected+
 Schematics N S&IC0
unavailale from I& vendor
 -esults o&tained in a few hours
of $ro&ing time
D/S 8Fail9 signals *red circles+ highlighting
transistor ;> as defect site o%erlaid with
5AD *green $oly+ N /S! image


*-
"-S Case Study M@ 3 +naly$ing a <ield &rolem
 Mield $ro&lem failure identified on
a frame &uffer using 0AST
 ;o fault found using #miSco$e
 D/S *1>@3+ used to locali,ed fault
 Failure locali,ed to a P// circuit
– Ereen circles identify the section of
the Failing P//
– -ed &o"es are 5AD o%erlay
– &-- was never sus#ected as a
#otential #rolem
– -esults o&tained V1 hour
 Allustrates com$limentary %alue of
Elo&alScan *D/S+ N #miSco$e
*timing+ for efficient defect
locali,ation


+/
"-S Case MA 3 Flash Memory 1esistive Interconnect
"efect
Flash de%ice with failing
-ead o$eration.
De%ice $ass sometimes
when o$erated at
higher 1dd.
(sed D/S to locali,e
what was likely to &e a
resisti%e %ia *green dot+.
?1

+.
Common Causes of Soft "efects
!etalli,ation or interconnect
defects

1ia $ush u$ or %oids

#lectro migration

Stress %oids

!etal 8mouse &ites9

EranularityIErain &oundaries

-esisti%e &ridging
Anter:le%el Dielectric *A/D+

1oids

!etal 8sli%ers9

5ontamination
C"ide Defects

Soft gate o"ide shorts

Hot carrier inLection
Process %ariations

Transistor effects2
–1t shifts WW
–/eff shift Weff shift
–;!CS to P!CS length ratio
–Diffusion resistance WW

Anterconnect
–!etal thickness %ariations
–S$acing or $itch %ariations

Eate C"ide and A/D
–Thickness %ariation
Anaccurate li&rary models
;oise -elated effects
–E;DI1dd ;oise 1dd sag
–5ross talk
–5/6IP// Litter
Soft Defect Localization (SDL) on ICs ! "ruce# $ "ruce# %ppes# &ilco'# % Cole#
(an)*un*on)# C +aw,ins IS(FA 2002
Design N $rocess margins are &eing $ushed to the limit N
no longer ha%e distinct 8&oundaries9
OO;on%visile
defects


+2
,are "ie 0lectrical Fi)turing Solution
 D(T 5ard :&ackside %iew
 Form factor of a 8uni%ersal9 41):$in
D(T card
 /ow $rofile JAF socket for 14 " 14 PEA
 /ow cost &oard – only one needed
 D(T 5arrier
 14"14 PEA foot$rint *1.44
inch s'uare+ )@ contacts
 1:inch s'uare clear ,one for
loose die or small fragment
 /ow cost consuma&le
 Wire &ond loose die onto die carrier
 #liminates need for multi$le
mechanical $ro&es
 Sim$ler solution for $ro&ing un$ackaged die
!ount Die
Wire 0ond


+
Fundamentals of IC Test: Summary of Session =
 A5 Test dri%es $hysical failure analysis
– 5ollected test data identify $otential failure locations
– Additional locali,ation re'uired to correct circuit $ro&lems
– 5ircuit edit to %alidate design error hy$othesis and continue de&ug
– Defect site locali,ation to reduce I eliminate wasted milling
– Fi"turing signal management test $rogram mani$ulation are critical
 1ariety of $henomena to dis$lay circuit &eha%ior
– !ost are weak re'uiring millions of test $attern cycles
– !ust kee$ circuit sta&ili,ed during data ac'uisition
– AT# su$$ort for $hysical failure analysis needs synchroni,ation
 ;anoscale $rocesses continue the challenge
– (nending room for inno%ation in PFA tools and techni'ues