Table of Contents

S.No Assignment
1 Design of combinational circuit, 2-4 Decoder, 4-2 encoder,
Binary to gray code converter using VHDL.
2 Model fli-flo, register and latc! in VHDL. "mlement
#sync!ronous and sync!ronous reset

$ Design of a state mac!ine% &ircuit to detect if an incoming
'erial number is divisible by (. 'imulate t!e incoming serial
)umber *it! a cloc+ and Data in *!ic! is set to !ig! or lo*.
,!e incoming data is entering from t!e rig!t. -se VHDL.
4 Design traffic lig!t controller using VHDL.
( Binary and B&D counter using VHDL.
. Data demultile/er. Data is re0uired on a !ig! seed
4-bit inut bus, outut to one of t!e t!ree 4-bit outut bus.
1 'erial in arallel out register using VHDL.
2 #L- using VHDL.
#ssignment 3 1
Design of 2/4 Decoder
--code for 2x4 decoder
library ieee4
use ieee.std5logic511.4.all4
entity Decoder2/4 is
ort6i %in std5logic5vector61 do*nto 784e %in
std5logic4o std5logic5vector6$ do*n to 7884
end Decoder2/44
arc!itecture Be!v of Decoder2/4 is
begin
rocess6i,e8
begin
if6e9:1:8 t!en
o678;9 6not i6788 and 6not i61884
o618;9 i678 and 6not i61884
o628;9 6not i6788 and i6184
o6$8;9 i678 and i6184
else
o;-<====>4
end if4
end rocess4
end arc!itecture4
Test Bench
--test benc!
entity ,B is
end ,B4
arc!itecture ,B5arc! of ,B is
comonent Decoder2/4 is
ort6i %in std5logic5vector61 do*nto 784e %in
std5logic4o std5logic5vector6$ do*n to 7884
end comonent4
signal i%std5logic5vector61 do*nto 784
signal e%std5logic4
signal o%std5logic5vector6$ do*nto 784
begin
inst%Decoder2/4 ort ma6i,e,o84
rocess
begin
e;9 not e after 27 ns4
i;9 transort <77>4
*ait for 27ns4
i;9 transort <71>4
*ait for 27ns4
i;9 transort <17>4
*ait for 27 ns4
i;9 transort <11>4
*ait for 27 ns4
end rocess4
end arc!itecture4
Design of 4/2 ?ncoder
--code for 4x2 encoder
library ieee4
use ieee.std5logic511.4.all4
entity encoder4/2 is
ort6i%in std5logic5vector6$ do*nto 784o%out
std5logic5vector61 do*nto 784e%in std5logic84
end encoder4@24
arc!itecture be!v of encoder4/2 is
begin
rocess6i,e8
begin
if e9:1: t!en
case i is
*!en <7771>9A o;9>77>4
*!en <7717>9A o;9>71>4
*!en <7177>9A o;9>17>4
*!en <1777>9A o;9>11>4
*!en ot!ers9A o;9>==>4
else
o;9>==>4
end if4
end rocess4
end arc!itecture4
Test Bench
-- test benc!
entity tb is
end tb4
arc!itecture tb5arc! of tb is
comonent encoder4/2 is
ort6i%in std5logic5vector6$ do*nto 784o%out
std5logic5vector61 do*nto 784e%in std5logic84
end comonent4
signal i%std5logic5vector6$ do*nto 784
signal o%std5logic5vector61 do*nto 784
signal e%std5logic4
begin
inst%encoder4/2 ort ma6i,o,e84
rocess
begin
e;9 not e after 47 ns4
i;9>7771>4
*ait 17 ns4
i;9>7717>4
*ait 17 ns4
i;9>7177>4
*ait 17 ns4
i;9>1777>4
*ait 17 ns4
end rocess4
end arc!itecture4
Design of Binary to Bray &ode &onverter
-- code for binary to gray converter
library ieee4
use ieee.std5logic511.4.all4
entity b2g is
ort6i%in std5logic5vector6$ do*nto 784
o%out std5logic5vector6$ do*nto 784e%in std5logic84
end b2g4
arc!itecture be!v of b2g is
begin
rocess6i,e8
begin
if e9:1: t!en
o678;9 i678 /or i6184
o618;9 i618 /or i6284
o628;9 i628 /or i6$84
o6$8;9 i6$84
else
o;9>====>4
end if4
end rocess4
end arc!itecture4
Test Bench
-- test benc!
entity tb is
end tb4
arc!itecture tb5arc! of tb is
comonent b2g is
ort6i%in std5logic5vector6$ do*nto 784
o%out std5logic5vector6$ do*nto 784e%in std5logic84
end comonent4
signal i%std5logic5vector6$ do*nto 784
signal o%std5logic5vector6$ do*nto 784
signal e%std5logic4
begin
inst%b2g ort ma6i,o,e84
rocess
begin
e;9not e after $7 ns4
i;9>7777>4
*ait for 17 ns4
i;9>7711>:
*ait for 17 ns4
i;9>1717>4
*ait for 17 ns4
end rocess4
end arc!itecture4
#ssignment 3 2
Design of 'ync!ronous and #sync!ronous Cegister
--synchronous register
library ieee4
use ieee.std5logic511.4.all4
entity syn525reg is
ort6d%in std5logic5vector61 do*nto 784
0%out std5logic5vector61 do*nto 784
cl+%in std5logic4rst%in std5logic84
end syn525reg4
arc!itecture be!v5syn of syn525reg is
begin
rocess6cl+8
begin
if cl+9:1: t!en
if rst9:1: t!en
0;9>77777777>4
else
0;9d4
end if4
end if4
end rocess4
end arc!itecture4
--async!ronous register
library ieee4
use ieee.std5logic511.4.all4
entity asyn525reg is
ort6d%in std5logic5vector61 do*nto 784
0%out std5logic5vector61 do*nto 784
cl+%in std5logic4rst%in std5logic84
end asyn525reg4
arc!itecture be!v5asyn of asyn525reg is
begin
rocess6cl+,rst8
begin
if rst9:1: t!en
0;9>77777777>4
elsif cl+9:1: t!en
0;9d4
end if4
end rocess4
end arc!itecture4
Test Bench
--test benc!
entity tb is
end tb4
arc!itecture tb5arc! of tb is
comonent syn525reg is
ort6d%in std5logic5vector61 do*nto 784
0%out std5logic5vector61 do*nto 784
cl+%in std5logic4rst%in std5logic84
end comonent4
comonent asyn525reg is
ort6d%in std5logic5vector61 do*nto 784
0%out std5logic5vector61 do*nto 784
cl+%in std5logic4rst%in std5logic84
end comonent4
signal d%std5logic5vector61 do*nto 784
signal 0syn,0asyn%std5logic5vector61 do*nto 784
signal cl+%std5logic4
signal rst%std5logic4
begin
inst1%syn525reg ort ma6d,0syn,cl+,rst84
inst2%asyn525reg ort ma6d,0asyn,cl+,rst84
cl+;9not cl+ after 1( ns4
rst;9not rst after 17 ns4
rocess
begin
d;9>77777777>4
*ait for $7 ns4
d;9>77711177>4
*ait for $7 ns4
end rocess4
end arc!itecture4
Design of 'ync!ronous and #sync!ronous D Dli-flo
--synchronous fli!-flo!
library ieee4
use ieee.std5logic511.4.all4
entity syn5d5ff is
ort6d%in std5logic40%out std5logic4cl+%in std5logic4
rst%in std5logic84
end syn5d5ff4
arc!itecture be!v5syn of syn5d5ff is
begin
rocess6cl+8
begin
if cl+9:1: t!en
if rst9:1: t!en
0;9:7:4
else
0;9d4
end if4
end if4
end rocess4
end arc!itecture4
--async!ronous D fli-flo
library ieee4
use ieee.std5logic511.4.all4
entity asyn5d5ff is
ort6d%in std5logic40%out std5logic4cl+%in std5logic4
rst%in std5logic84
end asyn5d5ff4
arc!itecture be!v5asyn of asyn5d5ff is
begin
rocess6cl+,rst8
begin
if rst9:1: t!en
0;9:7:4
elsif cl+9:1: t!en
0;9d4
end if4
end rocess4
end arc!itecture4
Test Bench
--test benc!
entity tb is
end tb4
arc!itecture tb5arc! of tb is
comonent syn5d5ff is
ort6d%in std5logic40%out std5logic4cl+%in std5logic4
rst%in std5logic84
end comonent4
comonent asyn5d5ff is
ort6d%in std5logic40%out std5logic4cl+%in std5logic4
rst%in std5logic84
end comonent4
signal d,0syn,0asyn,rst,cl+% std5logic4
begin
inst1% syn5d5ff ort ma6d,0syn,cl+,rst84
inst2% asyn5d5ff ort ma6d,0asyn,cl+,rst84
rocess
begin
d;9:1:4
*ait for $7 ns4
d;9:7:4
*ait for $7 ns4
end rocess4
cl+;9not cl+ after 1( ns4
rst;9not rst after 17 ns4
end arc!itecture4
Design of Latc!
-- "atch
library ieee4
use ieee.std5logic511.4.all4
entity dlatc! is
ort6d%in std5logic40%out std5logic4cl+%in std5logic4
rst%in std5logic84
end dlatc!4
arc!itecture be!v5latc! of dlatc! is
begin
rocess6d,rst8
begin
if rst9:1: t!en
0;9:7:4
elsif cl+9:1: t!en
0;9d4
end if4
end rocess4
end arc!itecture4
Test Bench
entity tb is
end tb4
arc!itecture tb5arc! of tb is
comonent dlatc! is
ort6d%in std5logic40%out std5logic4cl+%in std5logic4
rst%in std5logic84
end comonent4
signal d,0,rst,cl+% std5logic4
begin
inst% dlatc! ort ma6d,0,cl+,rst84
rocess
begin
d;9:1:4
*ait for $7 ns4
d;9:7:4
*ait for $7 ns4
end rocess4
cl+;9not cl+ after 1( ns4
rst;9not rst after 17 ns4
end arc!itecture4
#ssignment 3 $
Detection of divisibility by (
library ieee4
use ieee.std5logic511.4.all4
entity D'M( is
ort 6i%in std5logic4 re%out std5logic5vector6$ do*nto 784o%out std5logic4 cl+%in
std5logic84
end D'M(4
arc!itecture c!ec+div( of D'M( is
tye states is 6'1, '2, '$, '4, '(84
signal state%states4
signal count%integer range 7 to $14
begin
1%rocess6cl+8
begin
if cl+Eevent and cl+9E1E t!en
case state is
*!en '1 9A
if i 9 E7E t!en
state ;9 '14
else state ;9 '24
end if4
*!en '2 9A
if i 9 E7E t!en
state ;9 '$4
else state ;9 '44
end if4
*!en '$ 9A
if i 9 E7E t!en
state ;9 '(4
else state ;9 '14
end if4
*!en '4 9A
if i 9 E7E t!en
state ;9 '24
else state ;9 '$4
end if4
*!en '( 9A
if i 9 E7E t!en
state ;9 '44
else state ;9 '(4
end if4
end case4
count ;9 count F 14
end if4
if6state9'18 t!en
re;9G7777G4
o;9E1E4
end if4
if6state9'28 t!en
re;9G7771G4
o;9E7E4
end if4
if6state9'$8 t!en
re;9G7717G4
o;9E7E4
end if4
if6state9'48 t!en
re;9G7711G4
o;9E7E4
end if4
if6state9'(8 t!en
re;9G7177G4
o;9E7E4
end if4

end rocess4
end c!ec+div(4
#ssignment 3 4
Design of ,raffic Lig!t &ontroller
--traffic lig!t controller
library ieee4
use ieee.std5logic511.4.all4
entity tlc is
ort6cl+%in std5logic4red%out std5logic4yello*%out
std5logic4green%out std5logic84
end tlc4
arc!itecture tlc5arc! of tlc is
tye state is 6'C?D,'H?LLIJ,'BC??)84
variable tlcstate %state%9'C?D4
variable count%integer%974
begin
rocess6cl+8
begin
if cl+9:1: t!en
case tlcstate is
*!en 'C?D9A
if count917 t!en
tlcstate%9'BC??)4
count%974
else
count%9countF14
red;9:1:4
yello*;9:7:4
green;9>7:4
end if4
*!en 'H?LLIJ9A
if count92 t!en
tlcstate%9'C?D4
count%974
else
count%9countF14
red;9:7:4
yello*;9:1:4
green;9:7:4
end if4
*!en 'BC??)9A
if count917 t!en
tlcstate%9'H?LLIJ4
count%974
else
count%9countF14
red;9:7:4
yello*;9:7:4
greem;9:1:4
*!en ot!ers9A tlcstate%9'C?D4
count%974
end case4
end if4
end rocess4
end arc!itecture4
Test Bench
--test benc!
entity tb is
end tb4
arc!itecture tb5arc! of tb is
comonent tlc is
ort6cl+%in std5logic4red%out std5logic4yello*%out
std5logic4green%out std5logic84
end comonent4
signal cl+%std5logic%9:7:4
signal red, yello*, green % std5logic4
begin
cl+;9not cl+ after 17 ns4
inst%tlc ort ma6cl+,red,yello*,green84
end arc!itecture4
#ssignment 3 (
Design of Binary &ounter and B&D &ounter
--binary counter
library ieee4
use ieee.std5logic511.4.all4
entity bincnt is
ort6count%out std5logic5vector6$ do*nto 784cl+%in
std5logic4rst%in std5logic84
end bincnt4
arc!itecture bincnt5arc! of bincnt is
begin
rocess6cl+,rst8
begin
if rst9:1: t!en
count;9>7777>4
elsif cl+:event and cl+9:1: t!en
count;9countF14
end if4
end rocess4
end arc!itecture4
--bcd counter
library ieee4
use ieee.std5logic511.4.all4
entity bcdcnt is
ort6count%out std5logic5vector6$ do*nto 784cl+%in
std5logic4rst%in std5logic84
end bcdcnt4
arc!itecture bcdcnt5arc! of bcdcnt is
begin
rocess6cl+,rst8
begin
if rst9:1: t!en
count;9>7777>4
elsif cl+:event and cl+9:1: t!en
if count9>1771> t!en
count;9>7777>4
else
count;9countF14
end if4
end if4
end rocess4
end arc!itecture4
Test Bench
--testbenc!
entity tb is
end tb4
arc!itecture tb5arc! of tb is
comonent bincnt is
ort6count%out std5logic5vector6$ do*nto 784cl+%in
std5logic4rst%in std5logic84
end comonent4
comonent bcdcnt is
ort6count%out std5logic5vector6$ do*nto 784cl+%in
std5logic4rst%in std5logic84
end comonent4
signal cl+,rst%std5logic%9:7:4
signal bcdcount,bincount%std5logic5vector6$ do*nto 784
begin
cl+;9not cl+ after 27 ns4
rst;9not rst after 477 ns4
inst1% bincnt ort ma6bincount,cl+,rst84
inst2% bcdcnt ort ma6bcdcount,cl+,rst84
end arc!itecture4
#ssignment 3 .
Design of 4 Bit Data Demultile/er
--emulti!lexer 4 bit data on three 4 bit out!ut bus
library ieee4
use ieee.std5logic511.4.all4
entity demu/ is
ort6din%in std5logic5vector6$ do*nto 784sel%in
std5logic5vector61 do*nto 784dout1, dout2,dout$%out
std5logic5vector6$ do*nto 7884
end demu/4
arc!itecture demu/5arc! of demu/ is
begin
rocess6din,sel8
begin
case sel is
*!en <77>9A dout1;9din4
dout2;9>KKKK>4
dout$;9>KKKK>4
*!en <71>9A dout1;9>KKKK>4
dout2;9din4
dout$;9>KKKK>4
*!en ot!ers9Adout1;9>KKKK>4
dout2;9>KKKK>4
dout$;9din4
end case4
end rocess4
end arc!itecture4
Test Bench
-- testbenc!
entity tb is
end tb4
arc!itecture tb5arc! of tb is
comonent demu/ is
ort6din%in std5logic5vector6$ do*nto 784sel%in
std5logic5vector61 do*nto 784dout1, dout2,dout$%out
std5logic5vector6$ do*nto 7884
end comonent4
signal din,dout1,dout2,dout$%std5logic5vector6$ do*nto 784
signal sel%std5logic5vector61 do*nto 784
begin
inst%demu/ ort ma6din,sel,dout1,dout2,dout$84
1%rocess
begin
din;9>7717>4
*ait for 27 ns4
din;9>1771>4
*ait for 27 ns4
end rocess4
2%rocess
begin
sel;9>77>4
*ait for 2( ns4
sel;9>71>4
*ait for 2( ns4
sel;9>17>4
*ait for 2( ns4
sel;9>71>4
*ait for 2( ns4
sel;9>11>4
*ait for 2( ns4
end rocess4
end arc!itecture4
#ssignment 3 1
'erial in Larallel Iut
library ieee4
use ieee.std5logic511.4.all4
entity sio is
ort6sin,cl+,rst,enable%in std5logic4 o%out
std5logic5vector6$ do*nto 7884
end sio4
arc!itecture sio5arc! of sio is
signal tem%std5logic5vector6$ do*nto 784
begin
rocess6cl+8
begin
if rst9:1: t!en
tem9>7777>4
else
if cl+9:1: and enable9:1: t!en
tem6$8;9tem6284
tem628;9tem6184
tem618;9tem6784
tem678;9sin4
end if4
end if4
end rocess4
o;9tem4
end arc!itecture4
--testbenc!
entity tb is
end tb4
arc!itecture tb5arc! of tb is
comonent sio is
ort6sin,cl+,rst,enable%in std5logic4 o%out
std5logic5vector6$ do*nto 7884
end comonent4
signal sin,cl+,rst,enable%std5logic4
signal o%std5logic5vector6$ do*nto 784
begin
inst% sio6sin,cl+,rst,enable,o84
cl+;9not cl+ after 17 ns4
rocess
enable;9:1:4
rst;9:7:4
sin;9:1:4
*ait for 17 ns4
sin;9:1:4
*ait for 17 ns4
sin;9:7:4
*ait for 17 ns4
sin;9:1:4
*ait for 17 ns4
end rocess4
end arc!itecture4
#ssignment 3 2
#L-
entity art!m5com is
ort 6/,y% in bit5vector6$ do*nto 784 cin,o1,o2% in bit4f1% out bit5vector6$
do*nto 7884
end entity4
arc!itecture art!m5com5arc! of art!m5com is
comonent fa54bit is
ort 6 / , y % in bit5vector6 $ do*nto 784carryin,o1,o2 % in bit4K % out
bit5vector6 $ do*nto 784
carryout % out bit84
end comonent4
begin
adder54bit% fa54bit ort ma6/,y,cin,o1,o2,f184
end art!m5com5arc!4
"#$%CA" C#&'#N(NT
entity logical is
ort6/% in bit5vector6$ do*nto 784y% in bit5vector6$ do*nto 784 o1,o2% in
bit4
f2% out bit5vector6$ do*nto 7884
end entity4
arc!itecture logical5arc! of logical is
begin
f2 ;9 / and y *!en o19E7E and o29E7E else
/ or y *!en o19E7E and o29E1E else
/ /or y *!en o19E1E and o29E7E else
not /4
end logical5arc!4
) B%T *+"" A(,
entity fa51bit is
ort 6 a , b, cin % in bit 4f, cout % out bit84
end entity4
arc!itecture fa51bit5arc! of fa51bit is
begin
f ;9 a /or 6b /or cin8 4
cout ;9 6a and b 8 or 6 a and cin8 or 6b and cin8 4
end fa51bit5arc! 4
4 B%T *+"" A(,
entity fa54bit is
ort 6/,y% in bit5vector6$ do*nto 784 carryin,o1,o2% in bit4 K% out
bit5vector6$ do*nto 784 carryout%out bit84
end entity 4
arc!itecture fa54bit5arc! of fa54bit is
comonent fa51bit is
ort 6 a , b, cin % in bit 4f, cout % out bit84
end comonent 4
comonent mu/4/1 is
ort 6a,b,c,d% in bit4 s1,s2% in bit4 e% out bit84
end comonent4
signal tm5carry % bit5vector 62 do*nto 784
signal mu/o%bit5vector6$ do*nto 784
signal tem%bit5vector6$ do*nto 784
begin
tem;9not y4
inst1% mu/4/1 ort ma6y678,tem678,E7E,E1E,o1,o2,mu/o67884
inst2% mu/4/1 ort ma6y618,tem618,E7E,E1E,o1,o2,mu/o61884
inst$% mu/4/1 ort ma6y628,tem628,E7E,E1E,o1,o2,mu/o62884
inst4% mu/4/1 ort ma6y6$8,tem6$8,E7E,E1E,o1,o2,mu/o6$884
inst(% fa51bit ort ma6/678, mu/o678, carryin, K678, tm5carry678 84
inst.% fa51bit ort ma6/618, mu/o618, tm5carry678, K618, tm5carry618 84
inst1% fa51bit ort ma6/628, mu/o628, tm5carry618, K628, tm5carry628 84
inst2% fa51bit ort ma6/6$8, mu/o6$8, tm5carry628, K6$8, carryout 84
end fa54bit5arc! 4
4-) &+"T%'"(-(,
entity mu/4/1 is
ort 6a,b,c,d% in bit4 s1,s2% in bit4 e% out bit84
end entity4
arc!itecture mu/4/15arc! of mu/4/1 is
begin
e ;9 a *!en s19E7E and s29E7E
else b *!en s19E7E and s29E1E
else c *!en s19E1E and s29E7E else d 4
end mu/4/15arc!4
A"+ A,C.%T(CT+,(
entity alu is
ort 6L,M%in bit5vector6$ do*nto 784&"),'?L1,'?L2,'?L$,'?L4% in bit4
DI-,% out bit5vector6$ do*nto 7884
end entity4
arc!itecture alu5arc! of alu is
comonent art!m5com is
ort 6/,y% in bit5vector6$ do*nto 784cin,o1,o2% in bit4
f1% out bit5vector6$ do*nto 7884
end comonent4
comonent logical is
ort6/% in bit5vector6$ do*nto 784y% in bit5vector6$ do*nto 784 o1,o2% in
bit4f2% out bit5vector6$ do*nto 7884
end comonent4
comonent mu/4/1 is
ort 6a,b,c,d% in bit4 s1,s2% in bit4 e% out bit84
end comonent4
signal val1,val2% bit5vector6$ do*nto 784
begin
#&% art!m5com ort ma6L,M,&"),'?L1,'?L2,val184
L&% logical ort ma6L,M,'?L1,'?L2,val284
M-@1% mu/4/1 ort ma6val1678,val2678,E7E,L618,'?L$,'?L4,DI-,67884
M-@2% mu/4/1 ort ma6val1618,val2618,L678,L628,'?L$,'?L4,DI-,61884
M-@$% mu/4/1 ort ma6val1628,val2628,L618,L6$8,'?L$,'?L4,DI-,62884
M-@4% mu/4/1 ort ma6val16$8,val26$8,L628,E7E,'?L$,'?L4,DI-,6$884
end alu5arc!4
A"+ T(STB(NC.
entity alu5testbenc! is
end entity4
arc!itecture alu5test5arc! of alu5testbenc! is
comonent alu is
ort 6L,M%in bit5vector6$ do*nto 784&"),'?L1,'?L2,'?L$,'?L4% in bit4
DI-,% out bit5vector6$ do*nto 7884
end comonent4
signal in1,in2,out1%bit5vector6$ do*nto 784
signal cin,s1,s2,s$,s4 %bit4
begin
inst1% alu ort ma6in1,in2,cin,s1,s2,s$,s4,out184
rocess
begin
in1 ;9 G7771G4in2 ;9 G7171G4cin ;9E7E4s1 ;9 E7E4
s2 ;9 E7E4s$ ;9 E7E4s4;9E7E4
*ait for 27 ns4
s1 ;9 E7E4s2 ;9 E1E4cin;9E1E4
*ait for 27 ns4
s1 ;9 E1E4s2 ;9 E7E4
*ait for 27 ns4
s1 ;9 E1E4s2 ;9 E1E4cin;9E7E4
*ait for 27 ns4
s1 ;9 E7E4s2 ;9 E7E4s$ ;9 E1E4
*ait for 27 ns4
s1 ;9 E7E4s2 ;9 E1E4
*ait for 27 ns4
s1 ;9 E1E4s2 ;9 E7E4
*ait for 27 ns4
s1 ;9 E1E4s2 ;9 E1E4
*ait for 27 ns4
in1 ;9 G1771G4in2 ;9 G7111G4cin ;9E7E4s1 ;9 E7E4
s2 ;9 E7E4s$ ;9 E7E4
*ait for 27 ns4
s1 ;9 E7E4s2 ;9 E1E4cin;9E1E4
*ait for 27 ns4
s1 ;9 E1E4s2 ;9 E7E4
*ait for 27 ns4
s1 ;9 E1E4s2 ;9 E1E4cin;9E7E4
*ait for 27 ns4
s1 ;9 E7E4s2 ;9 E7E4s$ ;9 E1E4
*ait for 27 ns4
s1 ;9 E7E4s2 ;9 E1E4
*ait for 27 ns4
s1 ;9 E1E4s2 ;9 E7E4
*ait for 27 ns4
s1 ;9 E1E4s2 ;9 E1E4
*ait for 27 ns4
in1 ;9 G7771G4in2 ;9 G7171G4cin ;9E7E4s1 ;9 E7E4
s2 ;9 E7E4s$ ;9 E7E4s4;9E1E4
*ait for 27 ns4
s1 ;9 E7E4s2 ;9 E1E4cin;9E1E4
*ait for 27 ns4
s1 ;9 E1E4s2 ;9 E7E4
*ait for 27 ns4
s1 ;9 E1E4s2 ;9 E1E4cin;9E7E4
*ait for 27 ns4
s1 ;9 E7E4s2 ;9 E7E4s$ ;9 E1E4
*ait for 27 ns4
s1 ;9 E7E4s2 ;9 E1E4
*ait for 27 ns4
s1 ;9 E1E4s2 ;9 E7E4
*ait for 27 ns4
s1 ;9 E1E4s2 ;9 E1E4
*ait for 27 ns4
in1 ;9 G1771G4in2 ;9 G7111G4cin ;9E7E4s1 ;9 E7E4
s2 ;9 E7E4s$ ;9 E7E4
*ait for 27 ns4
s1 ;9 E7E4s2 ;9 E1E4cin;9E1E4
*ait for 27 ns4
s1 ;9 E1E4s2 ;9 E7E4
*ait for 27 ns4
s1 ;9 E1E4s2 ;9 E1E4cin;9E7E4
*ait for 27 ns4
s1 ;9 E7E4s2 ;9 E7E4s$ ;9 E1E4
*ait for 27 ns4
s1 ;9 E7E4s2 ;9 E1E4
*ait for 27 ns4
s1 ;9 E1E4s2 ;9 E7E4
*ait for 27 ns4
s1 ;9 E1E4s2 ;9 E1E4
*ait for 27 ns4
in1 ;9 G7771G4in2 ;9 G7171G4cin ;9E7E4s1 ;9 E7E4
s2 ;9 E7E4s$ ;9 E1E4s4;9E7E4
*ait for 27 ns4
s1 ;9 E7E4s2 ;9 E1E4cin;9E1E4
*ait for 27 ns4
s1 ;9 E1E4s2 ;9 E7E4
*ait for 27 ns4
s1 ;9 E1E4s2 ;9 E1E4cin;9E7E4
*ait for 27 ns4
s1 ;9 E7E4s2 ;9 E7E4s$ ;9 E1E4
*ait for 27 ns4
s1 ;9 E7E4s2 ;9 E1E4
*ait for 27 ns4
s1 ;9 E1E4s2 ;9 E7E4
*ait for 27 ns4
s1 ;9 E1E4s2 ;9 E1E4
*ait for 27 ns4
in1 ;9 G1771G4in2 ;9 G7111G4cin ;9E7E4s1 ;9 E7E4
s2 ;9 E7E4s$ ;9 E7E4
*ait for 27 ns4
s1 ;9 E7E4s2 ;9 E1E4cin;9E1E4
*ait for 27 ns4
s1 ;9 E1E4s2 ;9 E7E4
*ait for 27 ns4
s1 ;9 E1E4s2 ;9 E1E4cin;9E7E4
*ait for 27 ns4
s1 ;9 E7E4s2 ;9 E7E4s$ ;9 E1E4
*ait for 27 ns4
s1 ;9 E7E4s2 ;9 E1E4
*ait for 27 ns4
s1 ;9 E1E4s2 ;9 E7E4
*ait for 27 ns4
s1 ;9 E1E4s2 ;9 E1E4
*ait for 27 ns4
in1 ;9 G7771G4in2 ;9 G7171G4cin ;9E7E4s1 ;9 E7E4
s2 ;9 E7E4s$ ;9 E1E4s4;9E1E4
*ait for 27 ns4
s1 ;9 E7E4s2 ;9 E1E4cin;9E1E4
*ait for 27 ns4
s1 ;9 E1E4s2 ;9 E7E4
*ait for 27 ns4
s1 ;9 E1E4s2 ;9 E1E4cin;9E7E4
*ait for 27 ns4
s1 ;9 E7E4s2 ;9 E7E4s$ ;9 E1E4
*ait for 27 ns4
s1 ;9 E7E4s2 ;9 E1E4
*ait for 27 ns4
s1 ;9 E1E4s2 ;9 E7E4
*ait for 27 ns4
s1 ;9 E1E4s2 ;9 E1E4
*ait for 27 ns4
in1 ;9 G1771G4in2 ;9 G7111G4cin ;9E7E4s1 ;9 E7E4
s2 ;9 E7E4s$ ;9 E7E4
*ait for 27 ns4
s1 ;9 E7E4s2 ;9 E1E4cin;9E1E4
*ait for 27 ns4
s1 ;9 E1E4s2 ;9 E7E4
*ait for 27 ns4
s1 ;9 E1E4s2 ;9 E1E4cin;9E7E4
*ait for 27 ns4
s1 ;9 E7E4s2 ;9 E7E4s$ ;9 E1E4
*ait for 27 ns4
s1 ;9 E7E4s2 ;9 E1E4
*ait for 27 ns4
s1 ;9 E1E4s2 ;9 E7E4
*ait for 27 ns4
s1 ;9 E1E4s2 ;9 E1E4
*ait for 27 ns4
end rocess4
end alu5test5arc!4