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[3] P. Babighian, L. Benini, A. Macii, and E. Macii, “Post-layout leakage power minimization based on distributed sleep transistor insertion,” in Proc. Int. Symp. Low Power Electron. Design, 2004, pp. 138–143. [4] E. Pakbaznia and M. Pedram, “Coarse-grain MTCMOS sleep transistor sizing using delay budgeting,” in Proc. Design Autom. Test Eur., 2008, pp. 224–229. [5] M. Keating, D. Flynn, R. Aitken, A. Gibbons, and K. Shi, Low Power Methodology Manual: For System-on-Chip Design. New York: Springer-Verlag, 2007. [6] F. Najm, “A survey of power estimation techniques in VLSI circuits,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 2, no. 4, pp. 446–455, Dec. 1994. [7] Y. Jiang and K. Cheng, “Vector generation for power supply noise estimation and verification of deep submicron designs,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 9, no. 2, pp. 329–339, Apr. 2001. [8] M. Anis, S. Areibi, and M. Elmasry, “Design and optimization of multithreshold CMOS (MTCMOS) circuits,” IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 22, no. 10, pp. 1324–1342, Oct. 2003. [9] N. Evmorfopoulos, G. I. Stamoulis, and J. N. Avaritsiotis, “A Monte Carlo approach for maximum power estimation based on extreme value theory,” IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 21, no. 4, pp. 415–432, Apr. 2002. [10] K. Ganeshpure, A. Sanyal, and S. Kundu, “A pattern generation technique for maximizing power supply currents,” in Proc. Int. Conf. Comput. Design, 2006, pp. 338–343. [11] C.-T. Hsieh, J.-C. Lin, and S.-C. Chang, “Efficient transition-mode Boolean characteristic function with its application to maximum instantaneous current analysis,” in Proc. Int. Symp. Quality Electron. Design, 2007, pp. 602–606. [12] Y.-M. Kuo, Y.-L. Chang, and S.-C. Chang, “Efficient Boolean characteristic function for fast timed ATPG,” in Proc. Int. Conf. Comput.Aided Design, 2006, pp. 96–99. [13] C. Long and L. He, “Distributed sleep transistor network for power reduction,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 12, no. 9, pp. 937–946, Sep. 2004. [14] C.-T. Hsieh, J.-C. Lin, and S.-C. Chang, “A vector less estimation of maximum instantaneous current for sequential circuits,” IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 25, no. 11, pp. 2341–2352, Nov. 2006. [15] H. Kriplani, F. N. Najm, and I. N. Hajj, “Pattern independent maximum current estimation in power and ground buses of CMOS VLSI circuits: Algorithms, signal correlations, and their resolution,” IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 14, no. 8, pp. 998–1012, Aug. 1995. [16] F. Brglez and H. Fujiwara, “A neutral netlist of 10 combinational benchmark circuits and a target translator in fortran,” in Proc. Int. Symp. Circuits Syst., 1985, pp. 663–698. [17] F. Brglez, D. Bryan, and K. Kozminski, “Combinational profiles of sequential benchmark circuits,” in Proc. Int. Symp. Circuits Syst., 1989, pp. 1929–1934.

Multi-Threshold Voltage FinFET Sequential Circuits
Sherif A. Tawfik and Volkan Kursun

Abstract—New multi threshold voltage (multi) brute-force FinFET sequential circuits with independent-gate bias, work-function engineering, and gate-drain/source overlap engineering techniques are presented in this paper. The total active mode power consumption, the clock power, and the sequential circuits are reduced by average leakage power of the multiup to 55%, 29%, and 53%, respectively, while maintaining similar speed and data stability as compared to the circuits in a single threshold voltage ) tied-32 nm-gate FinFET technology. Furthermore, the area is (singlereduced by up to 21% with the new sequential circuits as compared to the tied-gate FinFETs. circuits with singleIndex Terms—Gate-drain/source overlap engineering, independent-gate bias, multi-threshold-voltage, work-function engineering.

I. INTRODUCTION Static latches and flip-flops are extensively used in synchronous integrated circuits (ICs). A significant portion (e.g., reported as 33% in [3]) of the total power is consumed by the clock subsystem in typical synchronous systems such as the high performance microprocessors. Brute-force sequential circuits with reduced clock load and simpler circuitry are therefore attractive for the state-of-the-art integrated circuits [3], [4]. In this paper, new compact and light-clock-load FinFET latches and flip-flops that operate based on data forcing are presented. Independentgate bias, work-function engineering, and gate-drain/source overlap engineering are explored to achieve multi threshold voltage (multi-Vth ) compact FinFET sequential circuits with reduced power consumption as compared to the standard single threshold voltage (single-Vth ) tiedgate FinFET circuits. The sequential circuits are characterized using Medici [5] in a FinFET technology with 32 nm gate length. This paper is organized as follows. The FinFET technology is presented in Section II. The new multi-Vth FinFET static brute-force sequential circuits are described in Section III. Simulation results for the FinFET latches and flip-flops are provided in Section IV. Finally, conclusions are provided in Section V. II. FinFET TECHNOLOGY The effects of different gate bias conditions, gate work-function, and gate-drain/source overlaps on the transistor threshold voltage and the drain current are presented in this section. The technology parameters of the low threshold voltage FinFETs considered in this paper are as given in [6]. An independent-gate FinFET has two modes of operation: singlegate mode and dual-gate mode [6], [8]. Disabling one of the gates in the single gate mode increases the absolute value of the threshold voltage as compared to the dual-gate mode. It is therefore possible to modulate the threshold voltage of a FinFET by independent gate-bias. The independent gate bias technique is explored in [6] and [11] to enhance
Manuscript received September 27, 2008; revised February 23, 2009 and June 25, 2009. First published September 29, 2009; current version published December 27, 2010. S. A. Tawfik is with the Department of Electrical and Computer Engineering, University of Wisconsin-Madison, Madison, WI 53706-1691 USA (e-mail: sa.tawfik@gmail.com). V. Kursun is with the Department of Electronic and Computer Engineering, The Hong Kong University of Science and Technology, Clear Water Bay, Kowloon, Hong Kong (e-mail: eekursun@ust.hk). Digital Object Identifier 10.1109/TVLSI.2009.2028028

1063-8210/$26.00 © 2009 IEEE

The off-current and the on-current are thereby reduced with the increased gate-drain/source underlaps. a minimum sized transmission gate is composed of single fin n-type and single fin p-type FETs. In this paper. Similarly. Gate oxide thickness 1. AND OFF-CURRENTS OF TIED-GATE FINFETS Single fin tied-gate FinFETs. ON-CURRENTS. FinFETs with gate-drain/source underlaps are utilized in [10] for enhancing the data stability and write ability of SRAM circuits while reducing the leakage power consumption. 2. The work-function engineering technique is explored in [7] and [11] to enhance the data stability and reduce the power consumption in static random access memory (SRAM) and sequential circuits. [10]. Gate length = 32 nm. AND OFF-CURRENTS OF TIED-GATE FINFETS Fig. The on-current and off-current of FinFETs versus the gate-drain/source overlap are illustrated in Gate-drain/source underlap is represented with a negative overlap. Single-Vth Tied-Gate FinFET Latches The standard implementations of a brute-force latch with a single-Vth tied-gate FinFET technology are shown in Fig. the feedback inverter (I2 ) should provide sufficient driving strength to maintain the voltage on Node1 when the latch is opaque in the presence of leakage currents and coupling noise [11]. Two standard implementations of a brute-force latch with single-Vth tied-gate FinFETs are described in Section III-A.8 V). and increased source and drain series resistances. The threshold voltage is the gate-to-source voltage at which the drain current per fin height is 1004 A=m for jVDS j = VDD (VDD = 0. FinFETs with gate-drain/source overlaps and gate-drain/source underlaps can be cointegrated by skipping the extension doping for the high-Vth transistors only. Alternatively.8 V. 1) [9]. = = = Fig.152 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS.2 nm. Off-current is the drain current when VGS = 0 V and jVDS j = 0. as shown in Fig. With the first single-Vth tied-gate implementation (LATCH-TG1). 2. minimum sized (single fin) low-Vth FinFETs are employed in the feedback inverter. the performance and reduce the area of FinFET brute-force sequential circuits. Increasing the threshold voltage with work-function engineering leads to a lower on current and a significantly suppressed off current. suppressed short-channel effect. In this paper. NO. Gate-drain/source overlap engineering is easier to implement with fewer processing steps as compared to the independent-gate bias and work-function engineering techniques. 3 [6].6 nm. 1. The multi-Vth FinFET latches based on independent-gate-bias. FinFETs with gate-drain/source overlaps and gatedrain/source underlaps are simultaneously used to design low-power and compact multi-Vth sequential circuits. . (a) With gate to drain/source overlap. ON-CURRENTS. [2].8 V. JANUARY 2011 TABLE I GATE WORK-FUNCTIONS AND THE CORRESPONDING THRESHOLD VOLTAGES. The threshold voltages achieved with gate-drain/source overlap engineering are listed in Table II. The on-current is the drain current when jVGS j = jVDS j = 0. The threshold voltage of a FinFET can also be tuned by adjusting the work function of the gate material [1]. Alternatively. Designing transistors with gate-drain/source underlap rather than gate-drain/source overlap results in increased effective channel length. FinFET LATCHES Static FinFET latches that operate with brute force in the transparent mode are presented in this section. On current and off current of FinFETs versus gate-drain/source overlap. High threshold voltage underlap-engineered FinFETs are implemented with 8 nm gate-drain/source underlaps in this study. The effective gate-to-source and drain-to-source voltage differences are reduced due to the additional voltage drops across the series resistances of the drain and source underlap areas. 19. 2. The off-current is reduced by 76% when the gate-drain/source overlap is reduced from 3. and gate-drain/source overlap engineering are described in Section III-B. The resistances of the pull-up and the pull-down networks of the feedback inverter are enhanced by employing transistor stacks. III. = TABLE II GATE-DRAIN/SOURCE OVERLAPS AND THE CORRESPONDING THRESHOLD VOLTAGES. Cross sectional top view of a FinFET. (b) With gate to drain/source underlap.2 nm to 08 nm. 3(a). T 110 C. T vice parameters are the same as the low-V FinFETs. VOL. Fig. A. [11]. 1. FinFETs with gate-drain/source underlaps are fabricated by skipping the implantation of the source and drain extension regions before the formation of the spacers [9]. Gate-drain/source underlaps are represented as negative overlaps in Fig. a minimum sized inverter is composed of a single fin nMOS and a two-fin pMOS transistor. The feedback inverter (I2 ) must be weaker than the input stage composed of the driver inverter (I1 ) and the transmission gate (T1 ) in order to be able to change the stored data when the latch is transparent (clock signal is high). 110 C. An alternative approach for adjusting the threshold voltage of FinFETs is the gate-drain/source overlap engineering (see Fig. work-function engineering. The other deUnderlaps are represented with negative overlaps. Gate-drain/source overlap 3. The work-functions of the low-Vth and the high-Vth FinFETs considered in this paper are listed in Table I with the corresponding drain currents and threshold voltages at 110  C.

and the reduction of output node V V V V V V V . and gate-drain/source underlap engineering are presented in this section. The setup times of the latches and the flip-flops are measured as described in [6] and [11].th FinFETs operating in the single-gate mode. LATCH-Underlap-IG is based on gate-drain/source Fig. 4(c). With LATCH-WF. (e) LATCH-Underlap-IG. T . FF-TG1.2 fF (0. The contention between the input stage and the feedback inverter is therefore reduced. FF-WF-IG. The size of a FinFET is quantized due to the constant fin height in a FinFET technology [7]. the lower contention at Node1 . respectively). The clock power is measured when the clock is the only switching signal with the input and the output nodes steady at 0 V.th minimum sized gates (with positive gate-drain/source overlaps). (c) LATCH-WF-IG. The third compact multi. The contention at Node1 is thereby further reduced as compared LATCH-IG. is based on an independent-gate FinFET technology. 19. With the second single-Vth tied-gate implementation (LATCHTG2). 4(d).th latch (LATCH-Underlap) is shown in Fig.th FinFETs. 3.th FinFETs implemented with gate-drain/source underlap engineering (see Table II).IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS. shown in Fig.2 fF capacitance is approximately equivalent to the gate capacitance of an inverter sized twice the minimum size. FF-TG2. The total power consumption includes the power consumed during data transfer and the power consumed by the clock driver. (d) LATCH-Underlap. NO. 4(b). (b) LATCH-WF. Seven master-slave FinFET flip-flops (FF) are also characterized. LATCH-Underlap. and the single. V V V V V IV. the feedback inverter is composed of minimum sized high. I is minimum sized for both circuits. The fifth compact multi. Short thick lines indicate high-V FinFETs with gate-drain/source overlaps based on work-function engineering (see Table I). respectively. LATCH-TG1: minimum-sized I . and FF-Underlap-IG are based on the LATCH-TG1. This technique leads to higher input and clock load capacitances due to the larger input stage [6]. as shown in Fig.th . 4(e). Alternatively. Proposed multi-V brute-force latches.th tied-gate FinFET latches. 4. (b) LATCH-TG2.th latch (LATCH-Underlap-IG) is shown in Fig.3% as compared to LATCH-TG2) due to the minimum sized gates. M M V overlap engineering and independent gate FinFET technology. Alternatively. The contention at Node1 and the capacitance at the output node are therefore simultaneously reduced. Long thick lines indicate high-V FinFETs based on gate-drain/source underlaps (see Table II).th latch (LATCH-WF) is shown in Fig. With LATCH-IG. FF-IG. The contention at Node1 is therefore reduced. 3(b). LATCH-Underlap.th . and I are sized twice the minimum size. T . and I are minimum sized in all of the proposed multi-V latches. and I3 have low. T1 . the feedback inverter is composed of minimum sized high. and I3 have low. JANUARY 2011 153 Fig. LATCH-IG-WF consumes the lowest total power (reduced by 50.th FinFETs with gate-drain/source underlaps operating in the single-gate mode. The feedback inverter is composed of minimum sized work-function engineered high. I . All the gates of the multi-Vth latches are minimum sized. 4(a). I . LATCH-WF-IG is based on a work-function engineered independent-gate FinFET technology. B. The first multi-Vth latch (LATCH-IG) [6]. work-function engineering. Brute-force latch implementations with single-V tied-gate FinFETs [11]. LATCH-WF. and LATCH-Underlap-IG. Alternatively. LATCH-TG2: I . LATCH-IG.4 fF). (a) LATCH-IG. and I . The fourth compact multi. The contention at Node1 is thereby further reduced as compared LATCH-IG and LATCH-WF. FF-WF. VOL. T . New Brute-Force Multi-Vth FinFET Latches Five compact multi-Vth FinFET latches based on independent-gate-bias. The driver inverter (I1 ) and the transmission gate (T1 ) are low. the feedback inverter is composed of minimum sized work-function engineered high. 1. The temperature is 110  C. the minimum sized transistors in the feedback path are weakened by operating in the single-gate mode (one of the gates of 2 and 1 are connected to DD and GND. the transistors of I1 . T1 . Each latch (flip-flop) drives a capacitive load of 0. FF-Underlap.th latch (LATCH-WF-IG) is shown in Fig. (a) LATCH-TG1. SIMULATIONS RESULTS Simulation results are provided in this section for the FinFET brute-force latches. 0. LATCH-WF-IG. The second compact multi. The functionality of LATCH-TG2 is achieved by utilizing input drivers (I1 and T1 ) sized twice the minimum size. LATCHTG2. minimum sized low-Vth tied-gate FinFETs are employed in the feedback inverter (I2 ). The transistors of I1 .

The propagation delays of LATCH-WF-IG and the LATCH-Underlap-IG latches are up to 60% shorter as compared to LATCH-WF across the different process corners. Clock is gated low. Similar conclusions are valid for the characteristics of the flip-flops as well. Fig. LATCH-WF-IG and LATCH-Underlap-IG reduce the power consumption by up to 56% as compared to the LATCH-WF latch across the different process corners. LATCH-WF-IG. 10. Furthermore. parasitic capacitance. as shown in Figs. LATCH-Underlap. 15. 8. 5. The FinFET device parameters that produce the 3 points of the on-current distribution curves given in [11] are used to characterize the strong and the weak transistors. The propagation delay and the setup time are minimized with LATCH-WF-IG (49% shorter delay and 71% shorter setup time as compared to LATCH-TG1) due to the reduced output node parasitic capacitance and the weaker contention at Node1 as compared to the other latches. Static noise margin of the cross-coupled inverters in the FinFET latches and flip-flops. 5–10. LATCH-WF and LATCH-WF-IG consume the lowest leakage power (47% lower as compared to LATCH-TG2) due to the smaller gates and the utilization of multi-Vth transistors. Setup time of the FinFET latches and flip-flops. Fig. 6. JANUARY 2011 Fig.154 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS. The latches are characterized at TABLE III PROCESS CORNERS UNDER PARAMETER VARIATIONS each process corner (including the nominal design). Alternatively. LATCH-WF provides the highest SNM among the latches evaluated in this paper as shown in Fig. Total active-mode power consumption of the FinFET latches and flipflops. LATCH-WF latch provides up to 23. Fig. as shown in Figs. NO. the layout area is reduced by up to 21% with the multi-Vth circuits as compared to the single-Vth tied-gate circuits [6]. Average propagation delay of the FinFET latches and flip-flops. 9. These devices are used for a variation corner analysis to assess the impact of process fluctuations on the LATCH-WF. Fig. 19. LATCH-TG2 consumes the highest clock power (up to 29% higher clock power as compared to the proposed multi-Vth FinFET latches) due to the larger clocked transistors. Clock power of the FinFET latches and flip-flops. and LATCH-Underlap-IG circuits.5% enhancement in SNM as compared to LATCH-Underlap across the different process corners. 1. 7. A fifth process corner (C5) is used for characterizing the worst-case static noise margin. Fig. Flip-flops: propagation delay is measured from clock to output. LATCH-WF-IG and LATCH-Underlap-IG consume the lowest power and have the shortest propagation delay among the latches considered in this paper across the different process corners as shown in Figs. 11–15. The four . Latches: propagation delay is measured from input to output. VOL. Four process corners that represent the worst and the best cases of delay and power consumption are identified as listed in Table III. Leakage power (averaged for four different input-output combinations in the standby mode) of the FinFET latches and flip-flops. 11 and 14. LATCH-WF provides the highest static noise margin (18% higher as compared to LATCH-TG1) due to the more symmetric voltage transfer characteristics of the cross-coupled inverters as compared to the other latches. [11].

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h . and R. A single-carrier frequency-domain equalizer (SC-FDE). 54. SISO OFDM and MIMO OFDM. most single-carrier (SC) transmissions can not adopt frequency-domain equalizer (FDE) directly. Syst. [10] S. preambles. Block diagram of the proposed single-FFT SC-FDE for sharing with an MIMO-OFDM modem. catsai@csie.156 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS. Taiwan (e-mail: tyhsu@cs. multimode. is assumed to roughly span two symbols of -sample preambles and -bit block codes.15. 2009. vol. 1. Sassman. In addition. Yet. Reconfigurable and scalable architectures [1]. 8. 2008. and additive white Gaussian noise (AWGN) vector with variance n Sj is the th 2 1 transmitted symbol. Channel Estimator and Aliasing Canceller for Equalizing and Decoding Non-Cyclic Prefixed Single-Carrier Block Transmission via MIMO-OFDM Modem Shau-Yu Cheng.edu.11 very high throughput (VHT). [4]. IEEE [14] and JTC [15]. Tawfik and V. System Descriptions Indoor frequency-selective fading.. Manuscript received July 23. Finally. Kim and J.” IEEE Trans. IEEE Asia Symp. Jul. The authors are with the Department of Computer Science.. UWB and WRAN. IEEE Symp.. e.e. NO. H2L22L is the circulant Toeplitz matrix with the first column being h and h = [ 0 1 . Section VI presents our conclusions.. single-carrier (SC) block codes. overlap-and-save and overlap-and-add methods. 1 displays the block diagram of this work. single-input single-output orthogonal frequency-division multiplexing (SISO-OFDM) and multiple-input multiple-output orthogonal frequency-division multiplexing (MIMO-OFDM) systems can be easily integrated. SYSTEM ASSUMPTIONS A. INTRODUCTION In most of the wireless broadband applications like WiMax.3a with an impulse option [9] were developed to demodulate SCBT with CP over time domains.g. 2008. 1–8. .00 © 2009 IEEE . Kursun. single-carrier frequencydomain equalization (SC-FDE). 2L01 ] denotes a channel impulse response (CIR).tw. inserting CP into single-carrier datum against the multipath propagation. modulated by QPSK and synchronized via -sample tain preambles (  ). this can help estimate channels and equalize packets over frequency domains directly. -bit block codes ( ) are decodable over frequency domains with DF-AC’s help. where the sphere decoder (SD) [11]–[13] is widely adopted in MIMO-OFDM modems. 1934–1942. First published October 06. and it was also demodulated in the time domain. H. [11] S. a block-based SC-FDE with both DFT and IDFT for HIPERLAN-2 [10] was utilized to yield an additional 3-dB gain. Both L L j L  N L h .tw). shauyu.g. 19.-W.2031137 consolidation of non-CP SCBT.11 very high throughput (VHT). All equalizations and decoding are performed over the frequency domain. Quality Electron. 2010. The user defined formats [5]–[7]. M. Performance evaluations are presented in Section IV. no. revised December 29. An -point FFT is sufficient to measure channel frequency responses (CFR) from -sample preambles ( 2). multiple equalizers are built in designs. And then.nctu. M.” in Proc. A. additional DFT units were included. 2009. Thus. [2] with heterogeneous units are good solutions to support such operations. N= L M N M L II. non-CP single-carrier block transmission (SCBT) can be decoded using sphere decoder of MIMO-OFDM modems to support multimode and backward compatibility under an acceptable complexity in IEEE 802. even if there is no CP existed against the distortions of multipath propagation. This work was conducted under “A plan to actively participate in international standard organizations for wireless communications” of the Institute for Information Industry.1109/TVLSI.-H. In this way. G. Appl. channel estimator. e. Although single-carrier block transmission (SCBT) without any CP gains throughput. were created to improve performance. with a non-CP SCBT. I. The remainder of this paper is organized as follows. under Grant NSC 98-2220-E-009-004. An -point FFT is sufficient   to process -sample preambles and -bit block codes ( 2). current version published December 27. “Enhanced performance and SRAM stability in FinFET with reduced process steps for source/drain doping. This work utilizes frequency-domain channel estimator (FD-CE) and decision-feedback aliasing canceller (DF-AC) to produce single-FFT SC-FDE. Electron Devices. 2007..g. is developed to eliminate FFT aliasing without a circular property in some approaches [3]. pp.This work was supported in part by the National Science Council of Taiwan. it causes fast Fourier transformation (FFT) aliasing in frequency-domain equalizer (FDE)—FDE can not assure sufficient performance directly.net. 20–21. SC-FDEs with a pair of FFT and IFFT for IEEE 802.edu. pp. R.hinet. The th received signal can be expressed as M L M K L M j j L rj = HL sj + HU sj 01 + n0 (1) where rj is the th 2 2 1 received vector. single-carrier block transmission (SCBT).. Des. 2008. VLSI Technol.16 [8] and IEEE 802.2009. Index Terms—Aliasing canceller. National Chiao Tung University. Jammy. In the case of single-carrier transmissions with pseudo noise (PN) spreading. Implementations and complexity are discussed in Section V. . “Design optimization and performance projections of double-gate FinFETs with gate-source/drain underlap for SRAM application. JANUARY 2011 [9] J. e. n0 is 2 2 1 complex 2 . Hussain. such as IEEE 802. 1. Digital Object Identifier 10.. and Terng-Yin Hsu Abstract—Without a cyclic prefix (CP). Fig. Apr. .” in Proc. being an attractive solution. MOEA. Fossum.. Chueh-An Tsai. compatibility. “Mutual exploration of FinFET technology and circuit design options for implementing compact bruteforce latches. The proposed packet format of non-CP SCBT is that datum without FEC are encoded by block code ( code sets conbits). The proposed single-FFT processes are described in Section III.h 1063-8210/$26. However. one of the major challenge for multimode integrations is to make equalizers as compact as possible. compensation for multipath fading is highly pointed in order to make systems work properly. Aug. VOL.-H.nctu. or multicarrier datum with 0 zeros. Harris. cheng@msa. H. Hsinchu 300. With the help of a cyclic prefix (CP). Yang. Tseng. B. The objective of this study is to derive single-FFT processes for supporting multimode and backward compatibility under an acceptable complexity in MIMO-OFDM modems. The system assumptions with problem statements are addressed in Section II. Wifi. Simulations and measurements imply that this work can ensure adequate performance. pp. Fig. i.