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Lecture plan
Code & name of subject: 141403 computer organization and architecture
Unit no: 3
Hazard (computer architecture)
In computer architecture, a hazard is a potential problem that can
happen in a pipelined processor. It refers to the possibility of erroneous
computation when a CPU tries to simultaneously execute multiple
instructions which exhibit data dependence. There are typically three types
of hazards: data hazards, structural hazards, and branching hazards (control
hazards).
Instructions in a pipelined processor are performed in several stages, so that
at any given time several instructions are being executed, and instructions
may not be completed in the desired order.
All the data hazards discussed here involve registers within the CPU.
By convention, the hazards are named by the ordering in the program that
must be preserved by the pipeline.
RAW (read after write) WAW (write after write) WAR (write after
read)
Consider two instructions i and j, with i occurring before j. The
possible data hazards are:
RAW (read after write) - j tries to read a source before i writes it, so j
incorrectly gets the old value.
This is the most common type of hazard and the kind that we use forwarding
to overcome.
WAW (write after write) - j tries to write an operand before it is
written by i. The writes end up being performed in the wrong order, leaving
the value written by i rather than the value written by j in the destination.
This hazard is present only in pipelines that write in more than one pipe
stage or allow an instruction to proceed even when a previous instruction is
stalled. The DLX integer pipeline writes a register only in WB and avoids
this class of hazards.
WAW hazards would be possible if we made the following two
changes to the DLX pipeline:
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Lecture plan
Code & name of subject: 141403 computer organization and architecture
Unit no: 3
Data Hazards
We must ensure that the results obtained when instructions are
executed in a pipelined processor are identical to those obtained when
the same instructions are executed sequentially.
Hazard occurs
A 3 + A
B 4 A
No hazard
A 5 C
B 20 + C
When two operations depend on each other, they must be executed
sequentially in the correct order.
Another example:
Mul R2, R3, R4
Add R5, R4, R6
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Lecture plan
Code & name of subject: 141403 computer organization and architecture
Unit no: 3
Operand Forwarding
Instead of from the register file, the second instruction can get data
directly from the output of ALU after the previous instruction is
completed.
A special arrangement needs to be made to forward the output of
ALU to the input of ALU.
Register
file
SRC1 SRC2
RSLT
Destination
Source 1
Source 2
(a) Datapath
ALU
E: Ex ecute
(ALU)
W: Write
(Register file)
SRC1,SRC2 RSLT
(b) P osition of the source and result registers in the processor pipeline
Figure 8.7. Operand forw arding in a pipelined processor .
Forw arding path
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Lecture plan
Code & name of subject: 141403 computer organization and architecture
Unit no: 3
Handling Data Hazards in Software
Let the compiler detect and handle the hazard:
I1: Mul R2, R3, R4
NOP
NOP
I2: Add R5, R4, R6
The compiler can reorder the instructions to perform some useful
work during the NOP slots.
Side Effects:
The previous example is explicit and easily detected.
Sometimes an instruction changes the contents of a register other than
the one named as the destination.
When a location other than one explicitly named in an instruction as a
destination operand is affected, the instruction is said to have a side
effect. (Example?)
Example: conditional code flags:
Add R1, R3
AddWithCarry R2, R4
Instructions designed for execution on pipelined hardware should
have few side effects.
Instruction Hazards
-> Whenever the stream of instructions supplied by the instruction fetch
unit is interrupted, the pipeline stalls.
->Cache miss
->Branch
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Lecture plan
Code & name of subject: 141403 computer organization and architecture
Unit no: 3
Unconditional Branches
F
2
I
2
(Branch)
I
3
I
k
E
2
F
3
F
k
E
k
F
k+1
E
k+1
I
k+1
Instruction
Figure 8.8. An idle cycle caused by a branch instruction.
Execution unit idle
1 2 3 4 5 Clock cycle
Time
F
1
I
1
E
1
6
X
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Lecture plan
Code & name of subject: 141403 computer organization and architecture
Unit no: 3
Branch Timing
--Branch penalty
- Reducing the penalty
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Lecture plan
Code & name of subject: 141403 computer organization and architecture
Unit no: 3
Instruction Queue and Prefetching
Conditional Branches
A conditional branch instruction introduces the added hazard caused
by the dependency of the branch condition on the result of a preceding
instruction.
The decision to branch cannot be made until the execution of that
instruction has been completed.
Branch instructions represent about 20% of the dynamic instruction
count of most programs.
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Lecture plan
Code & name of subject: 141403 computer organization and architecture
Unit no: 3
Datapath and Control Considerations
Datapath: portion of the processor which contains hardware necessary to
perform all operations required by the computer (the brawn).
Control: portion of the processor (also in hardware) which tells the datapath
what needs to be done (the brain).
Following operations can be performed independently
in the processor :
Reading an instruction from instruction cache
Incrementing the PC
Decoding an instruction
Reading from or writing into data cache
Reading the contents of up to two registers from the register
file
Writing into one register in register file
Performing an ALU operation
Performance Considerations
Performance = (accuracy, cost of misprediction)
Branch History Table (BHT):
Lower bits of PC used to index table of 1-bit
values
Says whether or not branch taken last time
No address check (unlike caches)
Problem: in loop, 1-bit BHT causes double
misprediction
End-of-loop case, when it exits instead of
looping
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Lecture plan
Code & name of subject: 141403 computer organization and architecture
Unit no: 3
First loop pass next time: predicts exit instead of
looping(Average loop does about 9 iterations
before exit)
Exception Handling
Exception Types
I/O device request
Breakpoint
Integer arithmetic overflow
FP arithmetic anomaly
Page fault
Misaligned memory accesses
Memory-protection violation
Undefined instruction
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Lecture plan
Code & name of subject: 141403 computer organization and architecture
Unit no: 3
Privilege violation
Hardware and power failure
Exception Requirements
Synchronous vs. asynchronous
I/O exceptions: Asyncronous
Allow completion of current instruction
Exceptions within instruction: Synchronous
Harder to deal with
User requested vs. coerced
Requested predictable and easier to handle
User maskable vs. unmaskable
Resume vs. terminate
Easier to implement exceptions that terminate program
execution
Stopping & Restarting Execution
Some exceptions require restart of instruction
e.g. Page fault in MEM stage
When exception occurs, pipeline control can:
Force a trap instruction into next IF stage
Until the trap is taken, turn off all writes for the faulting (and later)
instructions
OS exception-handling routine saves faulting instruction PC
Precise exceptions
Instructions before the faulting one complete
Instructions after it restart
As if execution were serial
Exception handling complex if faulting
instruction can change state before exception occurs
Precise exceptions simplifies OS
Required for demand paging
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