A four-quadrant analog multiplier under a single power supply

voltage
Xiaobing Tao

Chao Liu

Tao Zhao
Received: 21 August 2008 / Accepted: 7 July 2011 / Published online: 20 July 2011
Ó Springer Science+Business Media, LLC 2011
Abstract An analog multiplier driven by a single supply
voltage is proposed. Some improvements are introduced so
as to get a higher performance. The proposed analog mul-
tiplier can work precisely in four quadrants with a very small
THD. An added OTA keeps the linearity error of the circuit
smaller than 1%. The presented multiplier is designed on the
0.6 lm BCD process and the simulation results by HSPICE
shows a perfect performance. It can be used in any system
that requires a high performance analog multiplier.
Keywords Analog multiplier Á Single supply voltage Á
Four quadrants Á Small linearity error
1 Introduction
Analog multipliers have been widely applied in many fields
such as adaptive filtering, modulation, detection and auto-
matic gain control, and it is an indispensable part especially
in the active power factor correct (APFC) controllers.
There are many approaches to design analog multipliers.
Some multipliers use the quadratic relationship between
drain current and gate-source voltage of the MOS transis-
tors in the saturation region [1], some use the linearity of
drain current of MOS transistors in the ohmic region [2],
some are implemented in current mode [3–5]. But the
common shortcomings are small linear input range, large
linearity error and high distortion. In this paper, a four-
quadrant analog multiplier with high-linearity based on an
improved Gilbert Cell is presented. By adding a level
shifter to the input, the linear input range is extended. The
linearity is improved by adopting an OTA to supply tail
currents for Gilbert Cell, which also decreases the THD.
Driven by a single supply voltage of ?7 V, the proposed
circuit is characterized by large linear input range, small
linearity error and low THD.
2 Principles
2.1 Analog multiplier
Figure 1 shows a simplified differential amplifier [6]. With
Q
1
and Q
2
biased in the active region, the relationship
between emitter current and base-emitter voltage is given
below
I
e1
¼ I
s
ðe
V
BE1
=V
T
À 1Þ I
s
e
V
BE1
=V
T
ð1Þ
I
e2
¼ I
s
ðe
V
BE2
=V
T
À 1Þ I
s
e
V
BE2
=V
T
ð2Þ
where I
s
is the saturation current and V
T
= kT/q is the
thermal voltage.
As is known from Fig. 1 that I = I
e1
? I
e2
and
V
x
= V
BE1
- V
BE2
, so
I ¼ I
e1
1 þ
I
e2
I
e1

I
c1
ð1 þ e
ÀV
x
=V
T
Þ ð3Þ
I ¼ I
e2
1 þ
I
e1
I
e2

I
c2
ð1 þ e
V
x
=V
T
Þ ð4Þ
Then the collector currents are obtained as follows:
X. Tao (&) Á C. Liu Á T. Zhao
Xidian University, No. 2 TaiBai South Road, Xi’an,
Shannxi, China
e-mail: taoxiaobing4213@126.com
C. Liu
e-mail: liuchao4213@126.com
T. Zhao
e-mail: zhaotao4213@126.com
1 3
Analog Integr Circ Sig Process (2012) 71:525–530
DOI 10.1007/s10470-011-9692-8
I
c1

I
1 þ e
ÀV
x
=V
T
¼
I
2
þ
I
2
e
V
x
=2V
T
À e
ÀV
x
=2V
T
e
V
x
=2V
T
þ e
ÀV
x
=2V
T
¼
I
2
þ
I
2
tan
V
x
2V
T

ð5Þ
I
c2

I
1 þ e
V
x
=V
T
¼
I
2
À
I
2
tan
V
x
2V
T

ð6Þ
Therefore
V
out
¼ ÀI
c1
R
c
þ I
c2
R
c
¼ ÀðI
c1
À I
c2
ÞR
c
¼ ÀR
c
I tan
V
x
2V
T

ð7Þ
g
m
¼
2oI
c1
oV
x
¼
I
2V
T
ð8Þ
A
v
¼
oV
out
oV
x
¼ À
R
c
2V
T
I ð9Þ
Equations 8 and 9 give the result that the transconductance
g
m
and differential gain A
v
are proportional to the tail
current I, so automatic gain control can be implemented by
changing I. Furthermore, if I is proportional to a certain
input V
y
, that is I = bV
y
, then the output can be expressed as
V
out
¼ A
v
V
x
¼ À
R
c
2V
T
bV
y
V
x
¼ aV
x
V
y
ð10Þ
where a ¼ À
R
c
2V
T
b is a constant. In this case the differential
amplifier operates the multiplication of two analog
voltages.
2.2 Gilbert Cell
For the multiplier in Fig. 1, V
y
must be positive, leading the
multiplier only to work in two quadrants, which is not
suitable for the system that requires large swing and a
bidirectional variation in the gain. In this case, it is con-
siderable to adopt Gilbert Cell [7].
As shown in Fig. 2, Gilbert Cell contains a combination
of two differential pairs, which enables the gain to vary
continuously from negative to positive. The principle is as
follows: Suppose that Q
1
–Q
4
are absolutely identical (The
transconductance of each transistor is g
m
) and neglect the
base current of the transistors. Consider the pair of Q
1
–Q
2
only, then
A
v1
¼
V
out
V
x
due to Q1;Q2

¼ Àg
m
R
D
ð11Þ
Similarly, consider the pair of Q
3
–Q
4
only, then
A
v2
¼
V
out
V
x
due to Q3;Q4

¼ þg
m
R
D
ð12Þ
Thus, the output can be written as
Fig. 1 A simplified differential amplifier
Fig. 2 Gilbert Cell
Fig. 3 Improved Gilbert Cell
526 Analog Integr Circ Sig Process (2012) 71:525–530
1 3
V
out
¼ V
out due to Q1;Q2

þ V
out due to Q3;Q4

¼ A
v1
V
x
þ A
v2
V
x
ð13Þ
By Eqs. 8 and 9, |A
v1
| and |A
v2
| vary inversely as I
c5
and I
c6
change in the same manner, which leads to a continuous
variation of the gain from negative to positive, and then
the four-quadrant multiplication of analog signals is
implemented.
The inverse variations in I
c5
and I
c6
are implemented by
the differential pair of Q
5
and Q
6
. Because I
c5
plus I
c6
always equals I
ss
, they change in the opposite directions.
In actual applications, as a result of the nonlinearity
between the emitter current and V
BE
of a transistor, non-
linearity compensation should be added to the inputs of Q5
an Q6, or Q5 and Q6 are replaced by a MOSFET in triode
region.
2.3 Improved Gilbert Cell
Figure 3 shows an improved Gilbert Cell. Firstly, the input
V
x
is sent to Gilbert Cell after being pulled up by a level
shifter with a differential output, which extends the linear
input range of V
x
. Secondly, the input V
y
supplies tail
currents to the pairs of Q
1
–Q
2
and Q
3
–Q
4
through an OTA
with a differential output, which not only extends the linear
input range of V
y
but also improves the linearity of the
multiplier.
3 Circuit
The proposed multiplier is shown in Fig. 4. Q
1
–Q
6
con-
stitute a level shifter, which extends the input range of V
x
.
R
1
and R
2
are used to modulate the linearity of the input V
x
.
The gain of the multiplier can be improved by decreasing
R3–R4 or increasing R5–R6. Q13 and Q14 are introduced
to improve the precision of current mirrors.
From Fig. 4, the voltages and currents in the multiplier
can be expressed as
V
1
À V
2
V
x
g
m5;6
1
g
m5;6
g
m3;4
1
g
m1;2
jj R
1
þ
1
g
m3;4

¼
1 þ g
m3;4
R
1
1 þ
g
m1;2
g
m3;4
1 þ g
m3;4
R
1
À Á V
x
ð14Þ
Fig. 4 The high-linearity
analog multiplier with low THD
Fig. 5 The DC-characteristic of proposed multiplier
Analog Integr Circ Sig Process (2012) 71:525–530 527
1 3
I
c10
¼ kI
c9
¼ k
V
y
2
g
m2
¼
k
2
g
m
V
y
ð15Þ
I
c12
¼ kI
c11
¼ Àk
V
y
2
g
m1
¼ À
k
2
g
m
V
y
ð16Þ
where k is the aspect ratio of the current mirrors Q9–Q10
and Q11–Q12. Therefore, the output can be written as
V
out
¼ À
I
c10
2V
T
R
7
ðV
1
À V
2
Þ þ
I
c12
2V
T
R
8
ðV
1
À V
2
Þ
¼
ðI
c12
À I
c10
ÞR
2V
T
ðV
1
À V
2
Þ
¼ À
kg
m1;2
2V
T
1 þ g
m3;4
R
1;2
1 þ
g
m1;2
g
m3;4
ð1 þ g
m3;4
R
1;2
Þ
R
7;8
V
x
V
y
¼ aV
x
V
y
ð17Þ
where a ¼ À
kg
m1;2
2V
T
1þg
m3;4
R
1;2

g
m1;2
g
m3;4
ð1þg
m3;4
R
1;2
Þ
R
7;8
is a constant.
Equation 17 shows that the output V
out
is a multiplica-
tion of the inputs V
x
and V
y
.
4 Performances
The performances of the proposed multiplier in Fig. 4 can
be confirmed by HSpice on the basis of UMC 0.6 lm BCD
technology with V
TN
= 0.83 V and V
TP
= 0.87 V.
The DC characteristic is shown in Fig. 5(a) and (b). It
can be shown the linearity and a dynamic range of ±2 V.
Figure 6(a) and (b) show the linearity error of the pro-
posed multiplier while V
x
and V
y
input, respectively. From
Fig. 6, the linearity error is smaller than 1% in all the input
range, especially smaller than 0.1% in [-1,1].
One of the realistic application of the proposed multi-
plier is amplitude modulation (AM). The frequency of
carrier and modulate waves are 500 kHz and 20 kHz,
respectively. The amplitude of both inputs are 2Vp-p. The
input signals and AM output are shown in Fig. 7.
Fig. 6 The linearity error of proposed multiplier
Fig. 7 a Input signals. b Output
signal
528 Analog Integr Circ Sig Process (2012) 71:525–530
1 3
Figure 8 shows the THD of the proposed multiplier. By
making V
x
at 20 kHz with varied amplitude between 0.2
and 2Vp-p, The THD is smaller than 0.3% for different V
y
.
The bandwidth of the proposed multiplier is shown in
Fig. 9, which is larger than 10 MHz.
The comparison of the proposed multiplier with the
circuits proposed in the reference is presented in Table 1.
5 Conclusion
In the paper, a four-quadrant analog multiplier with high-
linearity is proposed with linearity error and THD smaller
than 1 and 0.3%, respectively. The achieved linear input
range is ±2 V and the bandwidth is 10 MHz, so the pro-
posed multiplier is suitable for the system that is under high
voltage and requires large linear input range, low THD and
low linearity error.
References
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multiplier. In ISCAS ‘97. Proceedings of 1997 IEEE international
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June 1997.
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Dejhan, K. (2005). Single low-supply and low-distortion CMOS
analog multiplier. In ISCIT 2005. IEEE international symposium on
communications and information technology (Vol. 1, pp. 251–254),
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current-mode multiplier for low power artificial neural networks
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A novel current-mode very low power analog CMOS four
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Sept 2005.
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quadrant multiplier. Electronics Letters, 33(3), 207–208.
6. Gray, P. R., Hurst, P. J., Lewis, S. H., & Meyer, R. G. (2001).
Analysis and design of analog integrated circuits (4th ed.,
pp. 708–716). New York: Wiley.
7. Razavi, B. (2003). Design of analog CMOS integrated circuits
(McGraw-Hill International Edition, pp. 126–129).
Xiaobing Tao got his MD in
XidianUniversity, Shanxi, China.
He has been studying design of
analog integrated circuits in
Institute of Electronic CAD,
Xidian University for 2 years and
specialize in design of Switch
Mode Power Supply (SMPS)
chips.
Fig. 8 The THD of proposed circuit
Fig. 9 The bandwidth of proposed circuit
Table 1 The comparison of proposed circuit with previous works
[2] [3] [5] Proposed
Supply (V) ±1.5 ±1.25 ±1.5 ?7
THD 0.22%
@1 MHz
6%
@100 kHz
2%
@3 kHz
0.3%
@20 kHz
Linearity
error (%)
0.5 – 2 1
Input range
(V)
±0.4 ±1 ±0.8 ±2
Freq -3 dB
(MHz)
34 1 5 10
Technology
(lm)
0.2 0.8 0.8 0.6
Analog Integr Circ Sig Process (2012) 71:525–530 529
1 3
Chao Liu is a member of Insti-
tute of Electronic CAD, Xidian
University. She has participated
in the design of several SMPS
chips. Now she is researching the
design of active power factor
correct (APFC) chips.
Tao Zhao is a graduate student
of the Xidian University and is
specialized in high speed
CMOS integrated circuit.
530 Analog Integr Circ Sig Process (2012) 71:525–530
1 3