IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: ANALOG AND DIGITAL SIGNAL PROCESSING, VOL. 50, NO.

8, AUGUST 2003

481

Transactions Brief___________________________________________________________________
Absolute-Value Circuit Using Junction Field-Effect Transistors
Alexandru A. Ciubotaru

Abstract—A novel configuration for an absolute-value circuit (full-wave rectifier with zero threshold) using two matched junction field-effect transistors is proposed and experimentally demonstrated. The zero-threshold rectification is accompanied by a scaling of the input signal by a theoret2, and is achieved by mathematically exploiting the nonical factor of 1 linear characteristics of the transistors. The circuit operates with complementary input signals and requires a dc bias voltage for the transistor gates. Negative or positive output voltages can be obtained by using either - or p-channel devices. Index Terms—Circuit functions, JFET analog integrated circuits, JFETs, nonlinear circuits, rectifiers.

Fig. 1.

Proposed absolute-value circuit.

I. INTRODUCTION Absolute-value circuits (sometimes known as full-wave rectifiers) are widely used in analog electronics in applications such as ac measurements, function fitting, providing inputs to single-quadrant devices, triangular-wave frequency doubling, error measurements, average envelope detection, and clock recovery [1]–[3]. For these and other analog signal processing circuits there is a continuous reduction in supply voltage and power consumption, driven primarily by portability requirements. The ever-shrinking headroom available to the active devices causes important mutations in the circuit topology, such as the absence of Darlington pairs, cascodes, and even emitter followers [4]. Thus, it becomes increasingly difficult to avoid the degradation of performance due to these topological changes, and new circuit configurations capable of high performance with low supply voltages must be invented. Although there exists a wide variety of absolute-value circuits, most of the proposed topologies to date are either not suitable for operation in low supply voltage environments (on the order of 1 V), or are not very accurate. Examples of circuits in the former category can be found in [5]–[14], where relatively large supply voltages are required typically because of complementary devices, current mirrors, or the need to accommodate logic signals for switches; an example in the latter category is [15], where relatively inaccurate transfer characteristics are accepted as approximations for the absolute-value function. There are also other implementations of the absolute-value function using current-mode circuits [16]–[19]. Although one of the circuits proposed in [16] does have the potential of operating with low supply voltages, the schematic is relatively complicated and requires three operational amplifiers. The CMOS circuits described in [17]–[19] are comparatively simple but require a current input, and a transconductor must be used in case the input is a voltage; moreover, a current mirror (which further limits the minimum acceptable supply voltage) must be used for true absolute-value operation.

This brief presents a simple and novel absolute-value circuit which uses two matched symmetrical junction field-effect transistors (JFETs) to eliminate the disadvantages associated with low supply voltages. The zero-threshold rectification takes place indirectly at the transistor level, as a mathematical consequence of the JFET nonlinearities. In this way, the circuit works with low supply voltages that accommodate only two complementary input voltages without any headroom for additional circuitry, being very attractive for use in portable systems. The present circuit also uses a dc bias voltage for the gates of the JFETs, which is very easy to generate and requires only a small bias current. If n-channel devices are used, the output of the circuit is a negative voltage; a positive output is generated for p-channel devices. p The theoretical scaling factor between input and output is 1= 2, and is not a function of the JFET parameters (notably the drain saturation current and the pinch-off voltage). The circuit is somewhat related to several other nonlinear JFET circuits that use complementary input voltages [20]–[24], and can easily be realized in monolithic form or be integrated in more complex systems. II. PRINCIPLE OF OPERATION The proposed circuit is shown in Fig. 1, where Q1 and Q2 are identical and symmetrical n-channel JFETs (the drain and source of a symmetrical JFET can be interchanged without affecting the characteristics of the transistor). For an input voltage vIN > 0 and assuming a sufficiently large load resistance RL such that iL  iD1 ; iD2 (i.e., iD 1  = iD2 ); Q1 operates in saturation and Q2 operates in the triode region (vice versa for vIN negative). These operating conditions are not evident at this point, but will be confirmed by computing vOUT and the transistor voltages using the appropriate saturation- and triode-region expressions for the drain currents. Thus, if the dc bias voltage is set equal to the JFET pinch-off voltage VP , currents iD1 and iD2 can be written as [25]

i

D1 = IDSS D2 = IDSS

i

0 GS1 P GS2 DS2 2 10 0P0 P
1
v V v v V V

2

(1)
vDS2 V

2

P

(2)

Manuscript received May 7, 2002. This paper was recommended by Associate Editor L. Trajkovic The author is with the Maxim Integrated Products, Melbourne Design Center, Melbourne, FL 32934 USA (e-mail: alexc@mxim.com). Digital Object Identifier 10.1109/TCSII.2003.813587

where vGS1 = VP 0vOUT ; vGS2 = VP +vIN and vDS2 = vOUT +vIN . After a few manipulations that are not shown, from iD1  = iD2 and using (1) and (2), it follows that
vIN

2

02

vOUT

2 

=0

(3)

1057-7130/03$17.00 © 2003 IEEE

whose gain is independent of the transistor parameters. The circuit operates correctly as long as the JFET breakdown voltages are not exceeded and the transistor junctions (gate–source and gate–drain) are not in strong forward bias. AUGUST 2003 Fig. which is the necessary and sufficient condition for the operation of Q1 in saturation. the circuit of Fig. 2. in the same way. which yields vOUT  = 6 1= 2 jvIN j.707 (or 01= 2) predicted by (4). RL = 10 k ) is shown in Fig. Circuit for simulating the high-frequency response of absolute-value circuit. 2= 2 + 1 VBR . which is true. It is easy to show that if p-channel JFETs are used in Fig. The fitting rms error was 1. If vIN < 0. and a low-power operational amplifier can be used in portable applications for low-power dissipation. the circuit works well even with very small signals. line was obtained by nonlinear fitting. the circuit of Fig. Circuit for accurately generating the dc bias voltage in Fig.. the same expression (4) is obtained for vOUT . the same input voltage range. Measured dc transfer characteristic (v against v ) of circuit of Fig. Thus. Due to a combination of high frequency and nonlinear effects. then the operational amplifier output voltage is practically equal to the pinch-off voltage VP of the JFETs in Fig. 1 jv j:  =p IN 2 (5) One approach for generating the dc bias voltage in Fig. but must have low input offset voltage and drift. a very small number which indicates that the characteristic of the circuit is well approximated by an ideal absolute-value function. The operational amplifier can be relatively rudimentary because it does not have to drive any load and needs to provide only a dc voltage for the JFET gates. 1 was constructed using an NPDS402 n-channel dual JFET [28]. Using the nonlinear fitting feature available in a software package [29]. where the JFET matches Q1 and Q2 . in good agreement with 00. which will still be given by (4). the temperature drift of the JFET pinch-off voltage (which can be as large as 2 mV/ C [27]) or of the JFET drain saturation current IDSS will have no effect on the circuit’s output voltage. VOL. Also explicitly shown in Fig. and was obtained using 121 equally spaced vIN values in the range [01:2 V. The gate bias of the circuit was externally generated and set to 0. 3. 1 instead of n-channel devices. and will track this value over temperature and fabrication process. The positive solution is not valid because it turns off Q1 (vGS1 < VP .6 V for silicon devices) and VBR is the JFET breakdown voltage.482 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: ANALOG AND DIGITAL SIGNAL PROCESSING. due to the symmetry of the transistors and the complementary input signals which revert polarity. iDS1 = 0). 4. condition vDS2 < (vGS2 0 VP ) ensures the operation of Q2 in the triode region and is true because it also reduces to vIN > 0. Thus. and the output voltage of the circuit is accurately predicted by (4). The measured dc transfer characteristic of the absolute-value circuit (vOUT against vIN . where the JFET capacitive parasitics are shown explicitly (CGS = CGD for symmetrical JFETs). I0 = 0:001IDSS [26]). If the bias current I0 is sufficiently small (e. these pconditions p can be expressed as jvIN j < min VGSon + jVP j. 1. reduces to vIN > 0. respectively. v With the output voltage given by (4) it is easy to verify the initial assumption that Q1 and Q2 operate in saturation and in the triode region. a function of the form K jvIN j with K as a variable was fitted to the curve of Fig. 1 is illustrated in Fig. 8. using a high-speed setup such as the one shown in Fig. then the absolute-value circuit has positive output. III. In this way.2 V]. In mathematical form. EXPERIMENTAL RESULTS AND DISCUSSION In order to validate the proposed technique for obtaining the absolute value of a signal.g. where VGSon is the threshold voltage of the gate-source or gate-drain junction (typically 0. 4 . 2. 4. It is also of interest to investigate the operation of the proposed absolute-value circuit at high frequencies. the dynamic operation is best illustrated by simulation. The measured parameters of the JFETs were IDSS = 2 mA and VP = 00:94 V. = 0:643 v . 3. and vOUT is vOUT 0 = j j Fig. 50. 1. 1. inequality vDS1 > (vGS1 0 VP ). 1. the correct solution is then vOUT p 1 jv j:  = 0p IN 2 (4) Fig. NO. has virtually no threshold. 1 is an absolute-value circuit with negative output. 3.94 V (VP ). the rms error being calculated as "rms = 121 i=1 [K jvINi j 0 vOUTi ]2 = 121 1 2 vOUT i 2 100% (6) where vINi are the input voltages and vOUTi are the measured output voltages. for R 10 k (symbols). The value returned by the fitting package was p K = 00:643.29%. thus.

pp. [14] W. E. “Absolute value circuit. Patent 4 906 915. 5 (without an external capacitance CL ) is expected to extend to much higher frequencies in a monolithic circuit. Fig. p. 5 also shows the response of the circuit for an intentional CL = 220 pF. Walker and M. “Absolute value circuit capable of providing full-wave rectification with less distortion. [9] Z. The transfer characteristic of the circuit is a good approximation of the p absolute-value function and has an embedded scaling factor of 1= 2. 1989. Aug. 1990. Communication Circuits: Analysis and Design. Hearn and D. MA. 1994. Brazil.” U. comes at the price of reducing the low-frequency accuracy. vol. 38th Midwest Symp. An interesting effect. 470–480.S. 771–777. and it is this capacitance that is primarily responsible for the degradation of the high-frequency response. Lett. Sept.” U. 2. “Low-voltage and low-power circuit design for mixed analog/digital systems in portable equipment. 6. Keate. 832–841. Oct. Using sinusoidal complementary inputs 6vIN of amplitude 0. Hess.” U. where. p however. [10] G. Patent 4 899 064. Mar. and V. June 1998.7 V. “Full-wave precision rectification that is performed in current domain and very suitable for CMOS implementation. 1995. 1995. Huang. “A fully integrated self-calibrating transmitter/receiver IC for an ultrasound presence detector microsystem. R. Shou. and becomes clearly distorted at 10 MHz. Apr. vol. Patent 5 703 518.” IEEE Trans. FL: Krieger. however. Kimura. Neidorff. “CMOS half-wave and full-wave precision voltage rectification circuits. vol. Solid-State Circuits.S. K. The output resistance RL (allowed to assume the negligibly large value of 10 k in the simulation shown in Fig. RS = 25 in this case). vol. K. Green. Yamamoto. 28. With no intentional output capacitance CL . pp. [7] R. D. Kuratli and Q. 5. pp. is that the average value of the output (VAVG  = 0VIN 2=) is not affected by the input frequency or the transistor capacitances. Principles of Digital and Analog Communications. May 23. CDS = 6 pF [28]). S. 478. the parasitic device capacitances can be reduced to a fraction of a pF. 39.S. June 1992. Matsuzawa. “Voltage to Absolute value current converter. the high-frequency response of the circuit starts degrading at input frequencies around 1 MHz. 5) also plays a role in the high-frequency operation of the circuit. 50. [6] C. Takatori. “Sinusoidal frequency doubler and full-wave rectifier using translinear current conveyor. Abdi. vol. 8. 23. [15] K. Clarke and D.. D. Solid-State Circuits.” U. May 21.” in Proc. this improvement. 1994. Rio de Janeiro. pp. and produces negative or positive output voltages according to the type (n.” U. Wang. Ed. 13–16. Patent 4 518 877.. ACKNOWLEDGMENT The contribution of two anonymous reviewers toward improving the quality of the original manuscript is gratefully acknowledged. Analog Devices. Rondeau.S. “Absolute value differential amplifier. Feb. . and the load capacitance CL . 456–462. pp. Sheingold. VOL. depending on the process technology. A. 33. 1998. REFERENCES [1] Nonlinear Circuits Handbook. Circuits Syst. [8] B. are series resistances RS (primarily accounting for the signal sources.” IEEE J. High-frequency response of absolute-value circuit. CONCLUSION A simple and novel absolute-value circuit has been presented and experimentally demonstrated. 2077–2079. J. 199. Riewruja. 1989.S. 30.” U. and computer simulation and optimization must be used for determining the best tradeoff. 1985.or p-channel) of the transistors. and M. It is interesting to note that. Patent 4 833 639. 29..” IEEE Trans. NO.. 1976. Inc. “Precision Absolute Value Amplifier for a Precision Voltmeter. 6. Yamamoto. 5. 39. 1990. [13] C. Dec.” Electron. Gibson. Melbourne. New York: Macmillan. T. IV. p. the total capacitance seen by the output node is approximately (CL + 2CDS + CGS + CGD). Patent 5 394 107. “High-speed analog multiplier-aAbsolute value detector. D. 1997. vol. M. [4] A. AUGUST 2003 483 Fig. Norwood. the output voltage of the circuit at different frequencies is shown in Fig. [5] W.. [3] J. 901–904. p. “Some circuit design techniques for bipolar and MOS pseudologarithmic rectifiers operable on low supply voltage.” IEEE J. Circuits Syst. Feb.IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: ANALOG AND DIGITAL SIGNAL PROCESSING. pp. Surakampontorn. Anuntahirunrat. for VP ideally decoupled (short to ground at ac frequencies). The circuit uses two matched junction field-effect transistors. H. . The dynamic response illustrated in Fig. [2] K. which suggests its potential use as an average-value detector at high frequencies.S. 34. 29. and catalog values for the capacitances of the NPDS402 devices (CGS = CGD = 11 pF. Circuits Syst. [11] P. and can be reduced to moderate values for improving the dynamic response. [12] S. 1992.

transmission multipath and fading) [3]. . a special neural network is introduced. Toumazou.” in Proc. J. Mar. Lett. 28. 34. “Cube-law circuit using junction field-effect transistors. pp. 3. pp. [20] A. “Fifth power-law circuits using junction field-effect transistors. Also. 1904–1905. the optimization problem at hand involves both inequality and equality constraints. Marini. and their references. New York: Holt. J. without the risk of spurious responses. this would require the use of two inverted diodes. vol. June 1998. it is expected that those algorithms are too complex to implement on mobile user terminals. Version 2. S. A. Circuits Syst..” in Proc. for other applications in the telecommunications field where the use of neural networks has already proven effective. [3]. The goal is to exploit the real time optimization capabilities of neural networks in order to significantly improve the optimization speed with respect to existing sequential algorithms. This in turn impairs their practical applicability to actual wireless CDMA communication systems. “Current-mode full-wave rectifier and vector summation circuit. [26] “Field Effect Transistors in Theory and Practice. 17. 268–269. One could also apply other methods [5] for solving convex optimization problems. Sec.814805 L01 j =0 E (x) = h[0 y i j ]. Such an optimization problem is convex (see [2. . New York: McGraw-Hill. This leads to the definition of a new class of neural dynamical systems which has potential applications also to solve other optimization problems.” Electron. 469–471. the main drawback of these sequential algorithms is that their convergence is too slow with respect to the time variations of MAI. 1322–1325. Lett. Aug. Lett.484 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: ANALOG AND DIGITAL SIGNAL PROCESSING. May 28–31. [25] A. 8. 544–545. Computer simulations are presented to verify the neural network optimization capabilities and speed.2003. [18] J. M. vol.1109/TCSII. 2002.. the adaptive filter proposed in [2] is designed via the optimization of the mean energy at the filter output.. Bipolar Transistor. 2. and G. there are technical problems for the implementation. However. Inc. Though an equality constraint can be mathematically brought back to a pair of simultaneous inequalities. due to the time variation of both the number of transmitting users and channel propagation conditions (i. which is derived via a nonobvious modification of the circuit for nonlinear programming introduced by Kennedy and Chua. Field-Effect Transistors. IL. 1999. which could not work properly in practice [7]. “New current-mode precision rectifiers. 36. Champaign.00 © 2003 IEEE . Wolfram Research.e. Sevin Jr. 50. Microelectronic Circuits. Rinehart. 36. Lett. vol. [4]. Marini. and C. Application Note AN211A. R. IL. Ciubotaru.” in Electron. in the generic ith bit it is required to minimize the function [2] 1 L I. If the mean is evaluated over a window of bits of length L. [17] C. II]). M. Sedra and K. pp. revised September 19. A basic approach to mitigate MAI effects in CDMA systems is blind adaptive interference suppression [2]. 53100 Siena. Winston. constrained optimization problems. The network. Forti is with the Dipartimento di Ingegneria dell’Informazione. IEEE Int. 2001. 5–8. Università di Siena.-I. 1996. May 3–6. and can be implemented in principle on mobile user terminals in CDMA systems. vol. essentially degraded by the multiple-access interference (MAI) caused by the presence of simultaneous users. the optimal adaptive filter coefficients in a blind CDMA receiver are obtained via the minimization of the mean energy at the filter output... and G.” [21] Electron. and JFET Products Databook. C. Forti.. More specifically. see also [1]. Inc. Lidgey. which relies on the use within the receiver of an adaptive filter for MAI attenuation. Ramírez-Angulo et al.” Motorola. From a mathematical viewpoint. The performance of a CDMA system is Manuscript received June 6. OPTIMIZATION PROBLEM FORMULATION The theory of blind interference suppression has been developed in [2]. M. 1599–1600. AZ. Lett. Fantacci. Vannuccini are with the Dipartimento di Elettronica e Telecomunicazioni. Liu. Hence. “Four-quadrant multiplier using junction field-effect transistors. Phoenix. pp. Digital Object Identifier 10. Università di Firenze. We refer the reader to [8] and [9]. 1993. 33. INTRODUCTION One of the most promising techniques for simultaneous transmission of multiple users in wireless communication systems. “Very low-voltage class AB CMOS precision voltage and cur[19] rent rectifiers. Hayatleh. An original technique is thus proposed in this paper to exactly satisfy the required equality constraints.-C. II. In fact. such as interior point algorithms.. Chicago. VOL. Symp. is code-division multiple access (CDMA) [1]. only. 14. Lett. 2000. 2000. Chang and S..” Wolfram Research. M. Switzerland. [28] “Discrete Semiconductor Products—Diode. K. However. Geneva. and the performance in the application to CDMA communication systems. Circuits Syst.. vol.” National Semiconductor Corp. p. Tarchi. Mar.. neural networks. x +s i2 (1) 1057-7130/03$17. is shown to be globally asymptotically stable. We recall that the neural network in [6] was conceived for optimization in the presence of inequality constraints. pp..2. . “4th power-law circuits using junction field-effect transistors. as it was pointed out in [3]. IEEE Int. vol. and the commonly employed algorithms for solving the problem are those based on the stochastic gradient descendent rule [1]. 1999. AUGUST 2003 [16] F. vol. 35. CA.” Elec[22] tron. 1442–1443. Firenze 50139 Italy. . In this brief. 1175–1176. subject to suitable constraints. Kennedy. 1997. Fantacci. MAI is rapidly time varying. National Semiconductor Corp.” [23] Electron. [29] “Mathematica.. 2000. pp. 1993. Oct. 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D. which derives from a nonobvious modification of the neural network for nonlinear programming proposed by Kennedy and Chua in [6]. 1997. From a mathematical point of view. pp. To achieve the previous goal. “Square-law circuit using junction field-effect transistors. Symp. . NO.” Electron. we theoretically investigate the possible use of a neural network approach to solve the constrained optimization problem arising in blind adaptive interference suppression. Italy. D. Tarchi. Index Terms—Code-division multiple access (CDMA) communication systems. 35. pp. due to the stringent limitations on the hardware.