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CHANDIGARH GROUP OF COLLEGES

JHANJERI, MOHALI

DEPARTMENT OF ELECTRONICS & COMM. ENGG


List of Microprocessor and assembly language programming
experiments

1. Introduction to 8085 kit.
2. Addition of two 8 bit numbers, sum 8 bit.
3. Subtraction of two 8 bit numbers.
4. Find 1s complement of 8 bit number.
5. Find 2s complement of 8 bit number.
6. Shift an 8 bit no. by one bit.
7. Find Largest of two 8 bit numbers.
8. Find Largest among an array of 8 bit numbers.
9. Sum of series of 8 bit numbers.
10. Introduction to 8086 kit.
11. Addition of two 16 bit numbers, sum 16 bit.
12. Subtraction of two 16 bit numbers.
13. Find 1s complement of 16 bit number.
14. Find 2s complement of 16 bit number.



CHANDIGARH GROUP OF COLLEGES
JHANJERI, MOHALI

DEPARTMENT OF ELECTRONICS & COMM. ENGG


Practical No. 1
AIM: Introduction to 8085 Kit.
A Microprocessor is a multipurpose, programmable, clock driven, register-based electronic device that
reads binary instructions from a storage device called memory, accepts binary data as input and processes
data according to those instructions, and provides results as output.
ESA85-2 is an extremely powerful microprocessor trainer based on the popular 8085 CPU. It can be
used as a Flexible instructional aid in academic institutions. Sophisticated features like powerful 2-pass
Assembler and Text Editor allow the use of ESA85-2 for serious microcomputer development work in
research institutions and R&D laboratories.
On-board facilities like EPROM programmer, Audio Tape Interface and Centronics compatible Parallel
Printer Interface enhance the power and utility of ESA85-2 system.

Following are the main features of ESA85-2:
ESA85-2 can be operated either from on-board or from a CRT terminal through its RS 232 C
interface.
Keyboard and serial monitor programs support the entry of user programs, editing and relocation,
debug facilities like breakpoints and single-stepping, direct port input/ output and full speed
execution of user programs.
Text editor permits line-oriented editing facilities for ASCII files and saving and restoring of files
from audiocassette.
2-pass Assembler can assemble any memory-resident assembly language program. Supports all
the standard INTEL mnemonics, useful directives like ORG, DB, DW, DS, EQU, SET etc.
Supports labels of upto six characters.
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DEPARTMENT OF ELECTRONICS & COMM. ENGG


2-Pass Disassembler disassembles the object code into standard INTEL mnemonics, converts all
branch and subroutine into lablels for easy reference.
On-board PROM Programmer features a 28-pin ZIF socket to program all standard PROMs 2716
through 27512. Intelligent Programming Algorithm is used wherever possible resulting in
significant reduction in programming time (for e.g. less than 2 minutes for programming a
27128!).
On-board Audio Tape Interface provides MIC and EAR sockets for operation with an Audio Tape
recorder. Reliable storing/ loading of assembly language source programs, object codes, data etc.
is possible.
On-board interrupt controller 8259A to service upto 8 interrupts.
32 K Bytes of CMOS static RAM is provided with battery back-up option. Total on-board
memory can be upto 64K Bytes.
Allows multi-processor system design by supporting the HOLD and HLDA signals.
STD bus compatible signals available on the bus connector for easy expansion.

Option Available
a. Interface Modules for training purpose (Calculator Keyboard, Elevator, Display, ADC with
DAC, Dual Slope ADC, Dual DAC, Logic Controller, Traffic Lights, 8253 Demo, RTC, Tone
Generator, Stepper Motor, Numerical Printer, etc.)
b. 8-bit, 16 Channel ADC
c. 5 Floppy Disk Drive Interface
d. 26 Core Ribbon Cable Connector Set.
e. RS-232C Interface Cable for terminal (25 pin D type male connector on both sides of the cable)
f. XT852: A communication package that can be used with a PC/ XT/ AT or compatible systems
with connecting cable (25 pin D type male on one end and 25 pin D type female on the other
end)
g. Ni-Cd battery
CHANDIGARH GROUP OF COLLEGES
JHANJERI, MOHALI

DEPARTMENT OF ELECTRONICS & COMM. ENGG



SPECIFICATIONS:
CPU :8085 Operated at 3.072 MHz
Memory :Three 28-pin JEDEC sockets offer 64K Bytes of memory as follows:
16K Bytes of firmware in one 27128
32K Bytes of static RAM Using one 62256 with optional battery backup
16K Bytes of PROM/ RAM (Optional) through Jumper selections allow this socket to
accommodate 2764/ 27128/ 6264/ 62256
Firmware :
Serial and Keyboard Monitors.
Text Editor, Assembler (2 pass), Disassembler package (can be used in serial mode only)
Audio tape interface driver software.
Centronics printer interface driver software.
PROM Programming software.

Peripherals :
8279-5 :To control 32 keys keyboard and 6-digit, 0.5 seven segment LED display.
8253-5 :3 Programmable interval timers
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DEPARTMENT OF ELECTRONICS & COMM. ENGG


Timer 0 is used for implementing single-step facility. Timer 1 is used for generating
baud clock, Timer 2 is available to the user (Through jumper option, user can use Timer 1
also, if he does not use it for baud clock).
8251 A :For serial communication supporting all standard bauds from 110 to 19.200. (Baud is
selected through on-board DIP switch)
8259 A : Programmable Interrupt Controller accepts 8 Interrupt signals from the auxiliary system
connector.
8255-5 : (4 numbers) Two are used by the system to implement PROM Programmer, Audio
Cassette Interface and Parallel Printer interface. The other two are available to user
giving 48 programmable I/O Lines.

Bus Expansion
STD bus Compatibles signals are available on a strip connector.

Interface Signals
Parallel I/O: 48 lines (2 X 8255-5) of TTL compatible bus brought out to two Spectra-strip type
ribbon cable connectors.
Serial I/O : RS-232C with standard MODEM control signals through on-board 25 pin D-
type female connector.
Cassette Interface Signals: Available on MIC and EAR sockets.
Parallel Printer Signals:
Centronics compatible Parallel Printer Interface signals available on a 25-pin D type female
connector in IBM PC/ XT Compatible pin configuration.
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JHANJERI, MOHALI

DEPARTMENT OF ELECTRONICS & COMM. ENGG



Interrupts
All interrupts except TRAP (used for single-step implementation) are available to user.

Power Supply (Optional)
5V, ( 0.1V), 3.0A
+ 12V, ( 1.)V), 250 mA
- 12V, ( 1.0V), 250 mA
30V ( 2.0V), 100mA


Introduction to INTEL 8085

INTEL 8085 is an 8-bit, NMOS microprocessor. It is a 40 pin I.C. package fabricated on a single LSI
chip. The INTEL 8085 uses a single +5V
d.c.
supply for its operation. Its clock speed is about 3MHz. The
clock cycle is of 320 ns. The time for the clock cycle of the INTEL 8085AH-2, version is 200 ns. It has
80 basic instructions and 246 opcodes.

Memory
Program, data and stack memories occupy the same memory space. The total addressable memory size
is 64 KB.
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DEPARTMENT OF ELECTRONICS & COMM. ENGG


Program memory - program can be located anywhere in memory. Jump, branch and call instructions
use 16-bit addresses, i.e. they can be used to jump/branch anywhere within 64 KB. All jump/branch
instructions use absolute addressing.
Data memory - the processor always uses 16-bit addresses so that data can be placed anywhere.
Stack memory is limited only by the size of memory. Stack grows downward.
First 64 bytes in a zero memory page should be reserved for vectors used by RST instructions.

Interrupts
The processor has 5 interrupts. They are presented below in the order of their priority (from lowest to
highest):
INTR is maskable 8080A compatible interrupt. When the interrupt occurs the processor fetches from the
bus one instruction, usually one of these instructions:
- One of the 8 RST instructions (RST0 - RST7). The processor saves current program counter into
stack and branches to memory location N * 8 (where N is a 3-bit number from 0 to 7 supplied
with the RST instruction).
- CALL instruction (3 byte instruction). The processor calls the subroutine, address of which is
specified in the second and third bytes of the instruction.
RST5.5 is a maskable interrupt. When this interrupt is received the processor saves the contents of the
PC register into stack and branches to 2Ch (hexadecimal) address.
RST6.5 is a maskable interrupt. When this interrupt is received the processor saves the contents of the
PC register into stack and branches to 34h (hexadecimal) address.
RST7.5 is a maskable interrupt. When this interrupt is received the processor saves the contents of the
PC register into stack and branches to 3Ch (hexadecimal) address.
CHANDIGARH GROUP OF COLLEGES
JHANJERI, MOHALI

DEPARTMENT OF ELECTRONICS & COMM. ENGG


Trap is a non-maskable interrupt. When this interrupt is received the processor saves the contents of the
PC register into stack and branches to 24h (hexadecimal) address.
All maskable interrupts can be enabled or disabled using EI and DI instructions. RST 5.5, RST6.5 and
RST7.5 interrupts can be enabled or disabled individually using SIM instruction.

I/O ports
256 Input ports
256 Output ports

Registers
Accumulator or A register is an 8-bit register used for arithmetic, logic, I/O and load/store operations.
Flag is an 8-bit register containing 5 1-bit flags:
- Sign - set if the most significant bit of the result is set.
- Zero - set if the result is zero.
- Auxiliary carry - set if there was a carry out from bit 3 to bit 4 of the result.
- Parity - set if the parity (the number of set bits in the result) is even.
- Carry - set if there was a carry during addition, or borrow during subtraction/comparison.

General registers:
- 8-bit B and 8-bit C registers can be used as one 16-bit BC register pair. When used as a pair the C
register contains low-order byte. Some instructions may use BC register as a data pointer.
- 8-bit D and 8-bit E registers can be used as one 16-bit DE register pair. When used as a pair the E
register contains low-order byte. Some instructions may use DE register as a data pointer.
CHANDIGARH GROUP OF COLLEGES
JHANJERI, MOHALI

DEPARTMENT OF ELECTRONICS & COMM. ENGG


- 8-bit H and 8-bit L registers can be used as one 16-bit HL register pair. When used as a pair the L
register contains low-order byte. HL register usually contains a data pointer used to reference
memory addresses.
Stack pointer is a 16 bit register. This register is always incremented/decremented by 2.
Program counter is a 16-bit register.

Instruction Set
8085 instruction set consists of the following instructions:
- Data moving instructions.
- Arithmetic - add, subtract, increment and decrement.
- Logic - AND, OR, XOR and rotate.
- Control transfer - conditional, unconditional, call subroutine, return from subroutine and restarts.
- Input/Output instructions.
- Other - setting/clearing flag bits, enabling/disabling interrupts, stack operations, etc.
Addressing modes
Register - references the data in a register or in a register pair.
Register indirect - instruction specifies register pair containing address, where the data is located.
Direct.
Immediate - 8 or 16-bit data.



CHANDIGARH GROUP OF COLLEGES
JHANJERI, MOHALI

DEPARTMENT OF ELECTRONICS & COMM. ENGG


Practical No. 2

AIM: Addition of two 8 bit numbers, sum 8 bit.
APPARATUS: Battery, 8085 kit, power supply 220V.
ALGORITHM:
1: LXI H (LOAD REGISTER PAIR IMMEDIATELY) loads 16 bit data in register pair designated by
operand.
2: MOV A, M copies the data byte into accumulator from the memory specified by the address in H-L
pair
3: INX H (INCREMENT REGISTER PAIR) increments the contents of the register pair by one.
4: ADD adds the contents of memory to accumulator.
5: STA address (STORE ACCUMULATOR DIRECT) copies the contents of the accumulator to the
memory location specified in the instruction
6: HLT (HALT) finishes the execution of the current instruction and stops any further execution.

PROGRAM:
MEMORY
ADDRESS
MACHINE
CODES
MNEMONICS OPERANDS COMMENTS
2000 05 FIRST DATA
2001 06 SECOND DATA
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DEPARTMENT OF ELECTRONICS & COMM. ENGG


2002 0b RESULT
2003
2004
2005
21
00
20
LXI H, 2000 H LOADS THE ADDRESS
OF 1
ST
NO. IN HL PAIR.
2006 7E MOV A,M MOVES THE 1
ST
NO. IN
ACCUMULATOR.

2007 23 INX H INCREMENTS THE
CONTENTS OF HL PAIR
2008 86 ADD M ADDS THE CONTENTS
STORED IN MEMORY
TO THE ACC.
2009 23

INX H STORES THE RESULT
AT 2002 H.
200A 77 MOV M,A MOVE RESULT TO
ACCUMULATOR
200B 76 HLT STOP.



CHANDIGARH GROUP OF COLLEGES
JHANJERI, MOHALI

DEPARTMENT OF ELECTRONICS & COMM. ENGG


Practical No. 3

AIM: Subtraction of two 8 bit numbers.
APPARATUS: Battery, 8085 kit, power supply 220V.
ALGORITHM:
1: LXI H (LOAD REGISTER PAIR IMMEDIATELY) loads 16 bit data in register pair designated by
operand.
2: MOV A, M copies the data byte into accumulator from the memory specified by the address in H-L
pair
3: INX H (INCREMENT REGISTER PAIR) increments the contents of the register pair by one.
4: SUBTRACT the contents of memory to accumulator.
5: STA address (STORE ACCUMULATOR DIRECT) copies the contents of the accumulator to the
memory location specified in the instruction
6: HLT (HALT) finishes the execution of the current instruction and stops any further execution.
PROGRAM:
MEMORY
ADDRESS
MACHINE
CODES
MNEMONICS OPERANDS COMMENTS
2000 05 FIRST DATA
2001 06 SECOND DATA
CHANDIGARH GROUP OF COLLEGES
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DEPARTMENT OF ELECTRONICS & COMM. ENGG


2002 01 RESULT
2003
2004
2005
21
00
20
LXI H, 2000 H LOADS THE ADDRESS
OF 1
ST
NO. IN HL PAIR.
2006 7E MOV A,M MOVES THE 1
ST
NO. IN
ACCUMULATOR.

2007 23 INX H INCREMENTS THE
CONTENTS OF HL PAIR
2008 96 SUB M SUBTRACT THE
CONTENTS STORED IN
MEMORY TO THE ACC.
2009
200A
200B
32
02
20
STA 2002 H STORES THE RESULT
AT 2002 H.
200C 76 HLT STOP.



CHANDIGARH GROUP OF COLLEGES
JHANJERI, MOHALI

DEPARTMENT OF ELECTRONICS & COMM. ENGG


Practical No. 4

AIM: To find one's complement of 8 bit no.
APPARATUS: 8085 kit, 220 V power supply, manual, and battery.
ALGORITHM:
1: The instruction LDA, 2000 H transfers the number from memory location 2000 to the accumulator.
2: Next instruction CMA takes the complement of the no.
3: This instruction ie; STA 2002H stores the result in the memory location.
4: HLT instruction ends the program.
PROGRAM:
MEMORY
ADDRESS
MACHINE
CODES
MNEMONICS COMMENTS
2000
2001
3E
22
MVI A,22H LOADS 8-BIT DATA IN A.

2002 2F CMA COMPLEMENTS THE CONTENTS
IN ACCUMULATOR.
2003
2004
2005
32
02
20
STA 2002H STORES THE CONTENTS OF ACC.
AT 2002H.
2006 76 HLT STOP

CHANDIGARH GROUP OF COLLEGES
JHANJERI, MOHALI

DEPARTMENT OF ELECTRONICS & COMM. ENGG


Practical No. 5

AIM: To find two's complement of 8 bit no.
APPARATUS: 8085 kit, 220 V power supply, manual, and battery.
ALGORITHM:
1: The instruction LDA, 2501 H transfers the number from memory location 2501 to the accumulator.
2: Next instruction CMA takes the complement of the no.
3: INR increments the value of the contents of accumulator to obtain the two's complement.
4: This instruction ie; STA 8502H stores the result in the memory location.
5: HLT instruction ends the program
PROGRAM:
MEMORY
ADDRESS
MACHINE
CODES
MNEMONICS COMMENTS
2000
2001
3E
22
MVI A,22H LOADS 8-BIT DATA IN A.
2002 2F CMA COMPLEMENTS THE CONTENTS
IN ACCUMULATOR.
2003 C6
01
ADI 01H ADDS 01H TO CONTENTS OF ACC.
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DEPARTMENT OF ELECTRONICS & COMM. ENGG


2004
2005
2006
32
02
20
STA 2503 STORES THE CONTENTS OF ACC.
AT 2002H.
2007 76 HLT STOP













CHANDIGARH GROUP OF COLLEGES
JHANJERI, MOHALI

DEPARTMENT OF ELECTRONICS & COMM. ENGG


Practical No. 6

AIM: Write a program to shift an 8 bit no left by 1 bit.
APPARATUS: Battery, 8085 kit, power supply 220V
ALGORITHM:
1: LDA (LOAD ACCUMULATOR DIRECT) load the contents of memory into accumulator.
2: DAD A (ADD REGISTER PAIR TO HL PAIR) shifts the contents of the accumulator to the left by
one bit.
3: STA address (STORE ACCUMULATOR DIRECT) copies the contents of the accumulator to the
memory location specified in the instruction.
4: HLT (HALT) finishes the execution of the current instruction and stops any further execution.
PROGRAM:









MEMORY ADDRESS MNEMONICS HEX-CODE COMMENTS
2000 LDA 2501 3A,01,25 Get data in
accumulator
2003 ADD A 87 Shift in left by 1 bit
2004 STA 2502 32,02,25 Store result in
address 2502
2007 HLT 76 stop
CHANDIGARH GROUP OF COLLEGES
JHANJERI, MOHALI

DEPARTMENT OF ELECTRONICS & COMM. ENGG


Practical No. 7

AIM: Find Largest of two 8 bit numbers.
ALGORITHM:
1. This program compares the two operands to find the largest out of them.

2. After comparison, the largest of two must be in accumulator. If it is already in accumulator, then
it is moved to memory.

3. If it is not in accumulator, then first it is moved to accumulator and then from there, it is moved
to memory.

4. Let us assume that the operands stored at memory location 3000H is 25H and 3001H is 15H.

5. Initially, H-L pair is loaded with the address of first memory location.

6. The first operand is moved to accumulator from memory location 3000H and H-L pair is
incremented to point to next memory location.

7. The second operand is moved to register B from memory location 3001H.

8. The two operands are compared.

9. After comparison, if A > B, then CF = 0, and if A < B, then CF = 1.

10. Carry flag is checked for carry. If there is a carry, it means B is greater than A and it is moved to
accumulator.

11. At last, H-L pair is incremented and the largest number is moved from accumulator to memory
location 3002H.

RESULT:
Thus the largest number from two 8 bit number is found.
CHANDIGARH GROUP OF COLLEGES
JHANJERI, MOHALI

DEPARTMENT OF ELECTRONICS & COMM. ENGG


PROGRAM:
Address Mnemonics Operand Opcode Remarks

2000 LXI H, 3000H 21 Load H-L pair with address 3000H.

2001 00 Lower-order of 3000H.

2002 30 Higher-order of 3000H.

2003 MOV A, M 7E Move the 1
st
operand from memory to reg. A.
2004 INX H 23 Increment H-L pair.

2005 MOV B, M 46 Move the 2
nd
operand from memory to reg. B.
2006 CMP B B8 Compare B with A.

2007 JNC 200BH D2 Jump to address 200BH if there is no carry.

2008 0B Lower-order of 200BH.

2009 20 Higher-order of 200BH.

200A MOV A, B 78 Move largest from reg. B to reg. A.

200B INX H 23 Increment H-L pair.

200C MOV M, A 77 Move the result from reg. A to memory.

200D HLT 76 Halt.

OBSERVATION:
Before Execution:
3000H: 25H
3001H: 15H
After Execution:
3002H: 25H

CHANDIGARH GROUP OF COLLEGES
JHANJERI, MOHALI

DEPARTMENT OF ELECTRONICS & COMM. ENGG


Practical No. 8

AIM: To find the largest among an array (8 bit).
ALGORITHM:
1. Place all the elements of an array in the consecutive memory locations.
2. Fetch the first element from the memory location and load it in the accumulator.
3. Initialize a counter (register) with the total number of elements in an array.
4. Decrement the counter by 1.
5. Increment the memory pointer to point to the next element.
6. Compare the accumulator content with the memory content (next element).
7. If the accumulator content is smaller, then move the memory content (largest element) to the
accumulator. Else continue.
8. Decrement the counter by 1.
9. Repeat steps 5 to 8 until the counter reaches zero
10. Store the result (accumulator content) in the specified memory location.
RESULT:
Thus the largest number in the given array is found out.
PROGRAM:
ADDRE
SS
OPCO
DE
LABEL MNEM
ONICS
OPER
AND
COMMENTS
2001 LXI H,2100 Initialize HL reg. to
2100H 2002
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DEPARTMENT OF ELECTRONICS & COMM. ENGG


2003
2004 MVI B,04 Initialize B reg with no. of
comparisons(n-1)
2005
2006 MOV A,M Transfer first data to acc.
2007 LOOP1 INX H Increment HL reg. to point next
memory location
2008 CMP M Compare M & A
2009 JNC LOOP If A is greater than M then go to
loop
200A
200B
200C MOV A,M Transfer data from M to A reg
200D LOOP DCR B Decrement B reg
200E JNZ LOOP1 If B is not Zero go to loop1
200F
2010
2011 STA 2105 Store the result in a memory
location.
2012
2013
2014 HLT Stop the program


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DEPARTMENT OF ELECTRONICS & COMM. ENGG


OBSERVATION:
INPUT OUTPUT
ADDRESS DATA ADDRESS DATA
2100 2105
2101
2102
2103
2104










CHANDIGARH GROUP OF COLLEGES
JHANJERI, MOHALI

DEPARTMENT OF ELECTRONICS & COMM. ENGG


Practical No. 9

AIM: Write a program to find sum of series of 8 bit numbers.

APPARATUS: Battery, mp kit, power supply 220V.

ALGORITHM:
1: LXI H (LOAD REGISTER PAIR IMMEDIATELY) loads 16 bit data in register pair designated by
operand.
2: MOV C M, copies the contents of the source register to the destination register.
3: MVI A (MOVE IMMEDIATE TO ACCUMULATOR) moves the data specified in the instruction to
accumulator.
4: INX H (INCREMENT REGISTER PAIR) increments the contents of the register pair by one.
5: ADD adds the contents of register with the contents of the memory and stores in the same.
6: DCR C (DECREMENT REGISTER) decrements the counter by one.
7: JNZ loop (CHANGE THE SEQUENCE) changes the sequence of the program to specified 16 bit
address, carry flags.
8: STA address (STORE ACCUMULATOR DIRECT) copies the contents of the accumulator to the
memory location specified in the instruction.
9: HLT (HALT) finishes the execution of the current instruction and stops any further execution.


CHANDIGARH GROUP OF COLLEGES
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DEPARTMENT OF ELECTRONICS & COMM. ENGG



PROGRAM:















MEMORY ADDRESS MNEMONICS HEX-CODE COMMENTS
2400 LXI H,2500 21,00,25 Add for the count in
H-L pair
2403 MOV C,M 4E Move from memory
to register C
2404 MVI A,00H 3E,00 Initial values of sum
is 0
2406 INX H 23 Address of next data
in H-L pair
2407 ADD M 86 Previous sum+ next
no
2408 DCR C 0D Decrement counter
2409 JNZ 2406 C2,06,24 Jump to 2406 if c=! 0
240C STA 2504 32,04,25 Store sum in 2504
240F HLT 76 stop
CHANDIGARH GROUP OF COLLEGES
JHANJERI, MOHALI

DEPARTMENT OF ELECTRONICS & COMM. ENGG


Practical No. 10
AIM: Introduction to 8086 Kit.
OVERVIEWS OF TRAINER
The lNTELs 8086 CPU are very popular and powerful third generation microprocessor. This
processor has 16 bit internal architecture, and can transfer 16 bits at a time. Because of its powerful
architecture and flexibility in operation, this processor is suitable for a wide spectrum of micro
computer applications
SDA trainer is a System Design Aid for the Intel 8086 microprocessors. IT is a highly versatile
and powerful system designed to assist students and engineers in learning about the architecture
and programming of these processors and designing systems& interfacing around them. This
trainer kit is configured for maximum mode only. It is housed in an attractive plastic cabinet; with
the power supply is connected externally.
The salient features of the system are as follow:
* 8086 CPU operating at 5 MHz in MAX mode.
* Provision for on board 8087 coprocessor
* Provision for 256 KB of EPROM and 256 KB of ram onboard
* Battery backup facility for RAM.
* 48 programmable I/) lens using two 8355s
* Three 16 bit timers using 8253A
*. Priority interrupt controller (PIC) for eight input using 8259A
* Computer compatible keyboard* Display is 16X2 line LCD
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DEPARTMENT OF ELECTRONICS & COMM. ENGG


* Designed and engineered to integrate users 8259A
* Computer compatible keyboard
* Display is 16X2 line LCD
* Designed and engineered to integrate users application specific interface conveniently at a
minimum cost.
* Powerful and user friendly keyboard/ serial monitor, support in development of application
programs.
* Software support for development of programs on computer, the RS 232C interface cable
connecting to computer from the kit facilitates transfer of files between the trainee kit& computer
for development and debugging purposes
* High quali9ty reliable PCB with maximum details provided for the user.

SPECIFICATIONS
CPU: Intel 8086 operating at 5MHz in MAX mode; provision for onboard 8087 Co-processor
MEMORY: Total 256KB of memory is provided in the kit
EPROM: 2JEDEC compatible sockets for EPROM;Onboard EPROM capacity is 256KB
(27C010X2)
128KB of EPROM containing keyboard/serial monitor will be supplied.
RAM:
2 JDEC compatible sockets are provided for RAM.
64KB of ram will be 62256X2 will be supplied.
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JHANJERI, MOHALI

DEPARTMENT OF ELECTRONICS & COMM. ENGG


PARALLEL I/O 48 I/O lines using two 8255s
SERIAL I/O: One RS 232C compatible interface using USART 8251A,with hardware
selectable baudrate using one channel of 8253 timer with MAX 232C IC
TIMER:Three 16 bit counter/ timers using 8253A counter 1 is used for serial I/O baudrate
generation
PIC: Programmable interrupt controller using 8259A provides interrupt vectors for 8 jumper
selectable internal/ external sources
KEYBOARD/ DISPLAY :
KEYBOARD: Computer keyboard can be hocked on to the trainer.
DISPLAY: LCD 2 X 16 Display
INTERRUPTS:
NMI: Provision for connecting NMI to a key switch.
INTR: Programmable interrupt controller using 8259A provides interrupt vectors for 8 jumper
selectable/external source. On board interrupt source include: 8251A
TXRDY and RXRDY, 8255 and 8087.

INTERFACE BUS SIGNALS
CPU BUS: All address, data and center lines ate TTL compatible and are terminated in berg
strip header
PARALLER I/O: All signals are TTL compatible and terminated in berg strip headers for PPI
expansion. Its compatible with all of our experimental interface modules.
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DEPARTMENT OF ELECTRONICS & COMM. ENGG


SERIAL I/O: Serial port signals are terminated in standard 9 pin D type connecter.
MONITOR SOFTWARE: 128 KB of serial/ keyboard monitor with powerful commands to
enter verify and debug user programs, including on board assembler &disassemble commands.
COMPUTER INTERFACE This can be interfaced to host computer system through the main
serial port; The driver program or communication between computer and trainer allows the
computer to be used as a simple dumb terminal and also facilitates uploading
POWER REQUIREMENTS: +5V DC, with 2.5 Amps current rating(max).



OPERATING CONFIGURATION: Two different modes of operation of trainer are possible.
They are:
i) serial operation
ii) Keyboard operation

When a Computer system is interfaced to trainer, the driver program must be resident in the computer
system.
The second mode of operation id achieved through onboard KEYBOARD/DISPAY.
In this mode the trainer kit interacts with the user through a computer keyboard and 16x2 LCD
display. This configuration eliminates the need for a computer and offers a convenient way for
using the trainer as a stand alone system.

CHANDIGARH GROUP OF COLLEGES
JHANJERI, MOHALI

DEPARTMENT OF ELECTRONICS & COMM. ENGG


Practical No. 11

AIM: Addition of two 16 bit numbers, sum 16 bit.
ALGORITHM:
1. This program adds two 16-bit operands stored in memory locations 3000H-3001H
and 3002H-3003H, without considering the carry produced (if any).

2. Let us assume that the operands stored at memory locations 3000H-3001H is 02H-04H and
3002H-3003H is 04H-03H.

3. The H-L pair is loaded with the first 16-bit operand 0204H from memory locations 3000H-
3001H.

4. Then, the first 16-bit operand is moved to D-E pair.

5. The second 16-bit operand 0403H is loaded to H-L pair from memory locations 3002H-3003H.

6. The two operands are added and the result is stored in H-L pair.

7. The result is stored from H-L pair to memory locations 3004H-3005H.

RESULT:
Thus the two 16 bit numbers are added and 16 bit sum is produced.
PROGRAM:
Address Mnemonics Operand Opcode Remarks

2000 LHLD 3000H 2A Load H-L pair with 1
st
operand from 3000H.
2001 00 Lower-order of 3000H.

2002 30 Higher-order of 3000H.

CHANDIGARH GROUP OF COLLEGES
JHANJERI, MOHALI

DEPARTMENT OF ELECTRONICS & COMM. ENGG


2003 XCHG EB Exchange H-L pair with D-E pair.

2004 LHLD 3002H 2A Load H-L pair with 2
nd
operand from 3002H.
2005 02 Lower-order of 3002H.

2006 30 Higher-order of 3002H.

2007 DAD D 19 Add D-E pair with H-L pair.

2008 SHLD 3004H 22 Store the result at address 3004H.

2009 04 Lower-order of 3004H.

200A 30 Higher-order of 3004H.

200B HLT 76 Halt.


OBSERVATION:
Before Execution: After Execution:
3000H: 02H 3004H:
3001H: 04H 3005H:
3002H: 04H
3003H: 03H



CHANDIGARH GROUP OF COLLEGES
JHANJERI, MOHALI

DEPARTMENT OF ELECTRONICS & COMM. ENGG


Practical No. 12

AIM: Subtract two 16 bit numbers.
ALGORITHM:
1. This program subtracts two 16-bit operands stored in memory locations 3000H-3001H and
3002H-3003H, without considering the borrow taken (if any).
2. Let us assume that the operands stored at memory locations 3000H-3001H is 08H-06H and
3002H-3003H is 05H-04H.

3. The H-L pair is loaded with the first 16-bit operand 0806H from memory locations 3000H-
3001H.

4. Then, the first 16-bit operand is moved to D-E pair.

5. The second 16-bit operand 0504H is loaded to H-L pair from memory locations 3002H-3003H.

6. The lower-order of first number is moved from register E to accumulator.
7. The lower-order of 2
nd
number in register L is subtracted from lower-order of 1
st
number in
accumulator.

8. The result of subtraction is moved from accumulator to register L.

9. Then, the higher-order of 1
st
number is moved from register D to accumulator.
10. The higher-order of 2
nd
number in register H is subtracted from higher-order of first number in
accumulator, along with the borrow from the previous subtraction.

11. The result of subtraction is moved from accumulator to register H.

12. Now, the final result is in H-L pair.

13. The result is stored from H-L pair to memory locations 3004H-3005H.


CHANDIGARH GROUP OF COLLEGES
JHANJERI, MOHALI

DEPARTMENT OF ELECTRONICS & COMM. ENGG


RESULT:
Thus the two 16 bit numbers are subtracted.
PROGRAM:
Address Mnemonics Operand Opcode Remarks


2000 LHLD 3000H 2A Load H-L pair with 1
st
operand from 3000H.

2001 00 Lower-order of 3000H.


2002 30 Higher-order of 3000H.


2003 XCHG EB Exchange H-L pair with D-E pair.


2004 LHLD 3002H 2A Load H-L pair with 2
nd
operand from 3002H.

2005 02 Lower-order of 3002H.


2006 30 Higher-order of 3002H.


2007 MOV A, E 7B
Move the lower-order of 1
st
number from reg.

E to reg. A.



2008 SUB L 95
Subtract the lower-order of 2
nd
number from

lower-order of 1
st
number.

2009 MOV L, A 6F Move the result from reg. A to register L.


200A MOV A, D 7A
Move the higher-order of 1
st
number from reg.

D to reg. A.



Subtract the higher-order of 2
nd
number from

200B SBB H 9C higher-order of 1
st
number with borrow from

the previous subtraction.


200C MOV H, A 67 Move the result from reg. A to reg. H.


200D SHLD 3004H 22 Store the 16-bit result from H-L pair to

CHANDIGARH GROUP OF COLLEGES
JHANJERI, MOHALI

DEPARTMENT OF ELECTRONICS & COMM. ENGG


memory.



200E 04 Lower-order of 3004H.


200F 30 Higher-order of 3004H.


2010 HLT 76 Halt.


OBSERVATION:
Before Execution: After Execution:
3000H: 08H 3004H: 03H
3001H: 06H 3005H: 02H
3002H: 05H
3003H: 04H








CHANDIGARH GROUP OF COLLEGES
JHANJERI, MOHALI

DEPARTMENT OF ELECTRONICS & COMM. ENGG



Practical No. 13
AIM: To find one's complement of 16 bit no.
APPARATUS: kit, 220 V power supply, manual, and battery.
ALGORITHM:
1: The 8 LSB's are in the memory location 8501 H.
2: The address 8501 is placed in HL pair.
3: The 8 LSB's of the no. are transferred from 8501 to the accumulator.
4: The instruction CMA takes one's complement of the LSB's.
5: The 8 LSB's of the result are stored in the memory location.
6: The address of 8 MSB's to the no. is 8502 and is placed in HL pair.
7: The 8 MSBs of the no. can be transferred from 8502 to the accumulator.
8: The instruction CMA takes one complement of 8 MSBs.
9: The 8MSBs of the result are stored in memory location 8504.
10: HLT ends the program.
PROGRAM:
MEMORY
ADDRESS
MACHINE
CODE
MNEMONICS COMMENTS
2000 21
00
LXI H, 2000 H LOADS 16-BIT DATA
IN THR REG. PAIR.
CHANDIGARH GROUP OF COLLEGES
JHANJERI, MOHALI

DEPARTMENT OF ELECTRONICS & COMM. ENGG


20
2003 7E MOV A,M TRANSFERS DATA
IN ACCUMULATOR.
2004 2F CMA COMPLEMENTS THE
CONTENTS IN
ACCUMULATOR.
2005 32
01
25
STA 2501 H STORES THE
CONTENTS AT THE
GIVEN LOCATION.
2008 21
01
20
LXI H, 2001 H LOADS 16-BIT DATA
IN REG. PAIR.
2011 7E MOV A,M TRANSFERS DATA
IN ACCUMULATOR.
2012 2F CMA COMPLEMENTS
CONTENTS IN
ACCUMULATOR.
2013 32
02
25
STA 2502 H STORES THE
CONTENTS AT THE
GIVEN LOCATION.
2016 76 HLT STOP THE
PROCESSING.

CHANDIGARH GROUP OF COLLEGES
JHANJERI, MOHALI

DEPARTMENT OF ELECTRONICS & COMM. ENGG



Practical No. 14
AIM: To find two's complement of 16 bit no.
APPARATUS: microprocessor kit, 220 V power supply, manual, and battery.
ALGORITHM:
1: The 8 LSB's are in the memory location 8501 H.
2: The address 8501 is placed in HL pair.
3: The 8 LSB's of the no. are transferred from 8501 to the accumulator.
4: The instruction CMA takes one's complement of the LSB's.
5: The 8 LSB's of the result are stored in the memory location.
6: This result is incremented by one and stored at memory location 8503.
7: The carry resulting from the addition of one to 1s compliment is stored in register B.
8: 8 MSBs of the no. are taken and 1s complement is obtained.
9: The carry is added to it.
10: 8 MSBs of the result are stored in 2504.
11: In case of no carry, the program jumps from JNC and go to INXH and the contents of the register B is
not incremented.
12: The addition of zero to ones complement of 8 MSBs does not affect the result.
13: HLT ends the program.


CHANDIGARH GROUP OF COLLEGES
JHANJERI, MOHALI

DEPARTMENT OF ELECTRONICS & COMM. ENGG





PROGRAM:
MEMORY
ADDRESS
MNEMONICS HEXCODE COMMENTS
2000 LXI H,8501 21
01
25
Address of 8
LSBS of no.
2003 MVI B,00H 06
00
Use reg. b to store
carry
2005 MOV A,M 7E 8 LSBS of the
no. in acc.
2006 CMA 2F 1s complement of
8 LSBS of the
no.
2007 ADI 01H C6
01
2s complement of
8 LSBS of the
no.
2009 STA 2503 32
03
25
Store 8 LSBS of
the result
200C JNC GO D2 Jump if carry
CHANDIGARH GROUP OF COLLEGES
JHANJERI, MOHALI

DEPARTMENT OF ELECTRONICS & COMM. ENGG


10
20
200F INR B 04 Store carry
2010 INX H 23 Address of 8
MSBS of no.
2011 MOV A,M 7E 8 MSBS in acc.
2012 CMA 2F 1s complement of
8 MSBS
2013 ADD B 80 Add carry
2014 STA 2504 32
04
25
Store 8 MSBS of
the result
2017 HLT 76 Stop.








CHANDIGARH GROUP OF COLLEGES
JHANJERI, MOHALI

DEPARTMENT OF ELECTRONICS & COMM. ENGG