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Methods Enriching Power and Energy Development (MEPED) 2014 1 | P a g e
Power Generation from the Light Energy Emitted From
the Fluorescent Lamps

N.Lakshmanan
1
, Sumit Kumar
2
, A. Saravanan
3

1,2
Final Year EEE, Dhaanish Ahmed College of Engineering, Chennai, Tamilnadu
3
HOD EEE, Dhaanish Ahmed College of Engineering, Chennai, Tamilnadu

ABSTRACT
The project based on the concept of
conservation of light energy from the House
Hold lamps such as Fluorescent Lamp, CFL,
Incandescent etc .The lamps are the essential
things that we have been using day to day life
.The Solar cells act as the light absorber which
will convert the light energy into the electrical
energy. We have been using more number of
lamps during night .So from that we can
generate more energy by interconnecting n-
number of lamps with the solar cells and store
this in a battery. The overall system design,
Hardware implementation and the performance
have been discussed in this paper.
Keywords: Voltage, Current, Power,
Illumination level, Depreciation Factor,
Utilization Factor
I. INTRODUCTION
This concept have been already worked using the
Infrared leds. The Led will also act as the light
absorber so it is able to generate electricity but the
power generated from this Led arrays on the tube
light are very less it is 12V , 21 A . This paper
has been presented in an International Conference
on Green Computing, Green communication and
Conservation of energy ICGCE 2013 and this is yet
to be published in IEEE Xplore Digital Library [1].
From the proceeding of conference work this paper
has been made. Here we worked on the Fluorescent
lamp with the small solar panel cells and
interconnected with each other in the tube light to
generate the bulk power .
The use of the lamps becomes the essential thing
in our day to day life. In all the places they use the
lamps; the number of lamp used will vary
depending upon the environment. The environment
such as Railway station, Class rooms, saw mills,
Ware house, Food Industry, Companies etc.
So we would be able to install this system in
any of the above applications and power generated
can be stored in the battery and that can be used to
feed to the loads whenever a power shut down
occurs. The overall system design and the work
proceeded have been discussed in this paper.
II. PROPOSED SYSTEM
A. Power Generated from the Single Fluorescent
Lamp using the Solar Cells:
The project work is started with working on the
single tube light. The Block Diagram of the
arrangement of single Tube light with solar panel
has been give below

Fig: 1 Block Diagram of the Single Fluorescent Lamp
with Solar panel
The system contains the Fluorescent lamp, Solar
panel, Voltage Regulator and the Battery unit. The
block diagram depicts the power generation on the
individual lamp. The light energy from the Tube
Light fall on the Solar cells which converts it into
the useful electrical energy. And that will be
regulated by the voltage regulator IC 7805 and then
stored in the battery [4].
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Methods Enriching Power and Energy Development (MEPED) 2014 2 | P a g e
The overall system design has been given below
describes about the placing the solar panels on the
Tube light. The panel support has been made above
the tube light support stand.

Fig 2: Hardware setup of single Fluorescent Lamp with
solar cells with two output terminals
The specification of the system components have
been given below
Table: 1 Technical Specification of Hardware Set up
COMPONENTS
NAME
RATINGS
Solar panel

Fluorescent
Lamp
4V , 100mA , Power = 0.4
W , Size = 64 cm
2

Power = 18 W
Lumens = 1015
Length = 60 cm
Colour Temperature =
6500 K


Fig 3: Voltage and Current Characteristics of the Single
Fluorescent Lamp with Solar cells
From the above graph it shows the variation of the
voltage and current with respect to the time. The
voltage is gradually varying between 3.67 V and
3.69 V. And the current is gradually varying
between 22 mA and 23 mA. The paper is worked
on with Tube light having the length 60 cm
generating 85 milli Watts and that has been used
for the small application but most of the places
people use the Fluorescent Tube light with length
114 cm generally. So we have been mathematically
calculated the power that can be generated from the
114 cm Fluorescent tube light .The power
generated is 170 milli Watts [4].
B.Power Generation from the Multiple Numbers of
Fluorescent Lamps and its Interconnection:
The latter section is dealing about the power
generation from the single Lamp. We can install
this system where multiple numbers of lamps have
been used and it is interconnected to generate more
power and that can be stored in the Battery bank.
From this we can feed to the Loads whenever we
need .The block diagram of multiple Fluorescent
lamp with solar cells is the same process flow in
the power generation from the single lamp
employed with solar cells.
The main factor is the interconnection of these
multiple number of lamps with each other. The
below Figure deals about interconnection of
multiple lamps
3.65 3.68 3.67 3.67 3.69 3.68 3.67 3.67
20.8
22.5 22.8 22.9 23 23.2 22.8 22.9
5.52
PM
5.55
PM
5.57
PM
6.11
PM
6.13
PM
6.17
PM
7.10
PM
8.30
PM
V I
CHARACTERISTICS
VOLTAGE ( Volts) CURRENT ( mA)
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Methods Enriching Power and Energy Development (MEPED) 2014 3 | P a g e

Fig: 4 Multiple Fluorescent Lamp with solar cells
Interconnection Diagram
The fig contains the interconnection diagram which
consists of the Fluorescent lamp with solar cells
symbol, Blocking Diode and the Bypass Diode
.The Role of the Blocking Diode is to prevent the
solar cells which will act as the load for the battery
when the system is at off condition. And the bypass
diode will be used to Bypass the power flow from
one Fluorescent lamp to another because all the
lamps will not be operating continuously. In some
applications depend on the need it will be used and
in some it may be used 247. When it is not
operating continuously at that instant when one of
the Lamps among the network is Off since is at the
series condition , it will make the circuit open this
will reduce the overall output in order to avoid that
the Bypass Diode will bypass the flow of electric
current to the terminals which avoid the circuit
Open . The ratings of the diodes will vary depend
the power ratings of the system such as voltage,
current. This concept is similar to the concept of
interconnection of PV panel in the PV array [2].
III. CALCULATION ON THE POWER CAN
BE GENERATED FROM THE MULTIPLE
LAMPS
The calculations have been made based on the
application of the system where it has been
installed. The various applications are defined in
this paper and also the various parameters are
considered while making these calculations. The
Lux value has been standardized for the various
applications such as School, Library, Ware House,
Company, Show Room etc [5]. Based on this lux
value the calculations have been made on the
amount of power can be generated from these real
time applications.
The table deals with the recommended lux values
in various places and referring the calculations
have been made on the amount power can be
generated in these places and this is purely depends
on the number of lamps used in the particular place
and this count will depend on the lux value
required, Area of the place to be illuminated,
Depreciation Factor of lamps and working
duration. This has been referred from the IES
Standards [5].
The calculation have been made by taking the Data
Sheet of the Philips Fluorescent tube light datasheet
number 36791-2 F17T8/TL835/ALTO [3] [5] .
Example Calculation based on the Philips
Datasheet
Depreciation Factor: 1.05 Utilization Factor:
0.95 Area to be illuminated: 50 m
2

Required Lux value: 200 lux
Lumens required: 50 200 = 10000 lumens
Actual Lumens: 100001.05/0.95 = 11053 lumens
Number Of tube Lights needed = Actual Lumens /
Lumens of Lamp= 11053 / 1400 =7.895 = 8
(approx)
Power can be generated =Number of lamps
power generated in single lamp
Power = 8 170 10
-3
= 1.36 Watts

Table: 2 Recommended Lux Value given by the
IES Standards

S.No

LEVEL

LUX

APPLICATION
1 Very low
illumination
Below
50 lux
Tanks , Entrance ,
Conveyors
2 Low
illumination
100 lux Transformer ,
Switch Gear ,
Bathrooms ,Bed
room , Corridors
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Methods Enriching Power and Energy Development (MEPED) 2014 4 | P a g e
3 Moderate
illumination
150 lux Lecture Hall ,
Hospital ,
Restaurant
4 High
illumination
- I
200 lux Libraries ,Kitchen
sinks , Press
,Machine Works
5 High
illumination
- II
300 lux General Office
work, Cash
Counters
6 Very High
illumination
700 lux Testing Room of
instruments ,
Soldering

In similar way we have been worked out on the
above table recommended lux value by assuming
the depreciation factor, utilization factor and area
to be illuminated.
Table: 3 Calculated Power can be Generated from
Various Applications

APPLICATIO
N

RECO
MMEN
DED
LUX

ILLUMIN
ATED
AREA

CALCUL
ATED
POWER
Transformer ,
Switch Gear

100 lux
370 m
2
4.39
Watts
Hospitals
150 lux
370 m
2
7.44
Watts
Libraries
200 lux
370 m
2
9.93
Watts
General Office
Work

300 lux
370 m
2
14.90
Watts

The graph shown below denotes the variation of
the power generated with respect to the Lux value
.The Graph is Linear and as the Lux value
increases the number of lamp used will also
increase such that the power generated can also
been increased .The Calculation is made by
referring the Illumination Engineering Principles.
The Calculated Power will be varied while
changing Lamp parameters.



Fig: 5 Variation Power generated with respect to Lux
value of various application
The Area of the place is also an important
parameter that will determine amount of power can
be generated in that particular place. The power
generated will increases when area to be
illuminated increases since number of lamps to be
installed increases. More power can be generated
when we place solar cells throughout the lamp. The
place of fluorescent on the solar panel will may
affect the Lux value receiving on the surface to be
illuminated so we designed the system in such a
way in order avoid the effect on the lux level
receiving on the surface. So that we placed solar
cells at the back of the Fluorescent Tube in order to
avoid the affect on the Lux value.
IV. CONCLUSION
The project have been analyzed with the single
Fluorescent Tube light and the result obtained is
discussed and its generating 170 milli Watts , this
is far enough to power the electronic items such as
Electronic motor , Buzzer , Led Array and
Charging the Low rated batteries . Using the
illumination engineering calculation techniques we
calculated the amount of power can be generated
from the various applications such as Substation,
Industries, Colleges and General Office. Future
scope of this project is to find out the power can be
generated from the different kinds of the lamps.
REFERENCES
[1] N.Lakshmanan ,Sumit Kumar, Generating
Electricity from the Tube lights for Charging
Battery Operated Electronics Items using
0
5
10
15
20
25
30
35
40
100 150 200 300
P
O
W
E
R

I
N

W
A
T
T
S
LUX
Power(
Watts)
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Methods Enriching Power and Energy Development (MEPED) 2014 5 | P a g e

Leds 978-1-4673-6126-2 IEEE Digital
Xplore Library( yet to published )
[2] Chetan Singh Solanki, Solar Photovoltaics
book
[3] Philips Advantage T12 Fluorescent Lamp
data sheet on the featuring, ALTO Lamp
Technology
[4] Kulshreshtha, Alok K, Basic Electrical
Engineering: Principles and Applications
India: Tata McGraw-Hill Education.
p. 801. ISBN 0-07-014100-2.
[5] IES standards for the Lightning Design for
the various applications.
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Methods Enriching Power and Energy Development (MEPED) 2014 6 | P a g e
Wind Energy Based Mobile Battery Charging and Battery
Applications
Saikumar.P
1,
Thamaraikannan.D
2
, Yuvaraj.G
3
, Yuvaraj.C
4
1,2,3
Student, B.E.Electrical and Electronics Engineering, Ganadipathy Tulsis Jain Engineering College, Vellore,
India.
4
Assistant Professor, Electrical and Electronics Engineering, Ganadipathy Tulsis Jain Engineering College,
Vellore, India.

ABSTRACT
In recent days power generation using
renewable energy sources gained more
attraction. The most commonly available and
used energy resources are solar and wind. The
objective presented here is charging of low
power electronic gadgets using the wind energy
available during travelling. A DC generator
with a Sepic converter provides voltage required
for charging the gadgets when the vehicle speed
exceeds 40km/hr. Even though the speed fall is
observed, the gadgets will get continuously
charged by the external battery source which is
connected to the proposed circuit. This could be
used as emergency source for charging
electronic gadgets while travelling in a vehicle.

Keywords: Battery, Charging Controller, DC
Motor, Sepic Converter, Voltage Regulator, Wind
Energy
I. INTRODUCTION
With the rapid industrialization development and
exploitation of natural resources. Many times
condition occurs which result in non charging of
our daily use gadgets and mobile. But this problem
can be tackled by using renewable energy
resources[1-5]Technologies like solar charger,
charging pins powered through automobile battery
and gadgets through hand operated dynamo
through a combination of many gears are used for
charging mobile phones .But a problem occurs
when there is no sunlight or the light is not in a
proper amount or when the automobile battery is not
in a condition to charge the other one and also the
use of hand operated gadget is very laborious work
and also not effective for long. In order to
overcome these types of problem, exploration has
been carried out with mobile phone and at present
we have come with a solution of maintaining
sustainability of energy stored in the phone battery
by Wind Driven Mobile Battery Charger [6-7].
This concept utilises wind generated electrical
energy to charge the mobile phones battery.

Figure 1: Block diagram of whole setup

The model consists of four main components that
are propeller, generator, chip integrated on PCB,
and mobile set suitable charging pin.
II. MATERIALS AND METHODS
A. Propeller
A propeller is a t y p e o f fan that
t r a n s m i t s p o we r b y converting rotational
motion into thrust. A pressure difference is
produced between the forward and rear surfaces of
the airfoil -shaped blade, and a fluid (such as air
or water) is accelerated behind the blade.
Propeller dynamics can be modeled b y b o t h
Bernoulli and Newtons t h i r d l a w . A
propeller is often colloquially known as screw.
The number of blades decides the rotational speed
of the propeller and differs with the pitch angle
and the angle between the blades. If the number
of blades is more the speed output is more and
thus give more output voltage and vice versa.
Normally the propeller is chosen according to the
type of application.

B. 12 volt D.C Generator
A simple D.C generator is preferred over the
A.C generator so as to avoid the use of rectifier
circuit and to make the circuit cheap and compact
and also to avoid extra cost. The main difference
in the A.C and D.C generator lies in the manner in
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Methods Enriching Power and Energy Development (MEPED) 2014 7 | P a g e
which the rotating coil is connected to the external
circuit connecting the load. In an A.C generator
both end of the coil is connected to the external
circuit via brushes. In this manner, the e.m.f
E
ext. in the
external circuit is always the same as
the emf E generated around the rotating coil. In a
D.C generator the two ends of the coil are
attached to the different halves of a single split
ring which co-rotates with the coil. The split ring
is connected to the external circuit by means of
metal brushes

The combination of split rings and the stationary
metal brushes is called a commutator. The purpose
of the commutator is to ensure that the emf E
ext.
In t h e external circuit is equal to the emf E
generated around the rotating coil for half the
rotating period, but is equal and opposite of
polarity of this emf for the other half. In the
special case as theoretical, the emf seen in the
external circuit is simply.
E
ext.
= E =E
max.
sin(2ft)
If Eext
.
Plotted as a function of time according to
the Formula. The variation of the voltage with
respect to time is Very similar to that of an A.C
generator, except that when the negative polarity
of an A.C generator is reversed to the positive
one by the commutator. So, as to avoid the use of
diodes in the A.C generator D.C generator is
preferred. So, as a result a bumpy direct emf which
rises and fall but never changes the direction is
achieved at the output terminals.

C. Charging Regulator Circuit
This is a combination of a 6v/22f capacitor.
I.C 7805, charging pin
6V/22f capacitor: The bypass capacitor is
hooked up at the output terminal of the DC
generator .The capacitor is there to filter out any
noise coming from the voltage source (the
generator). The voltage regulator I.C will work
best if a clean D.C is fed to it. To avoid any
A.C noise (ripple) imposed on the D.C line
voltage, the capacitor in essence act as a bypass
capacitor. It shorts the A.C signal of the voltage
signal (which is noise on the voltage signal) to
ground and only the D.C portion of the signal goes
to the regulator.
I.C 7805: I.C. 7805 voltage regulator employ built
in current limiting, thermal shutdown, and safe area
protection which make them virtually immune to
damage from output overload. With adequate heat
sinking it can deliver in excess of 0.5 A of current.
Typical application will include local regulators
which can eliminate the noise and degrade
performance associated with single point
regulation. As the most prominent voltage for
charging the mobile phones is 5 Volts. So, I.C
7805 is used as a regulator.
Battery: In ordinary mobile a 3.7 volts Li
+
battery
is used 3.70 Wh rating the battery when fully
charged shows the voltage of about 3.95 volt and
when discharged it shows 1.75volts.

Table1:Module Parameters


III. DESIGN AND ANALYSIS OF
SEPIC CONVERTER
In a single ended primary inductance converter
(SEPIC) design, the output voltage can be higher or
lower than the input voltage. The SEPIC converter
shown in Figure 2 uses two inductors: L1 and L2.
The two inductors can be wound on the same core
since the same voltages are applied to them
throughout the switching cycle.
S.No Module Specifications
1. Wind Driven Generator
Gen. voltage
(12V max.)
2. Wind Speed Range 40 kmph (min.)
3. Bypass Capacitor 6V/22f
4. Voltage Controller Ic 7805
5. Battery 3.7V,970mAh
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Methods Enriching Power and Energy Development (MEPED) 2014 8 | P a g e

Figure 2:Basic Sepic Topologyy
The basic wave form of the sepic converter has
been shown in the figure3.

Figure 3: Sepic converter switching waveforms (V
Q1
:
Q1 Drain to Source Voltage)
A. Design Parameters:

I. Duty Cycle Consideration:

For a SEPIC converter operating in a
continuous conduction mode (CCM), the
duty cycle is given by:

V V
V V V
1
V
D
is the forward voltage drop of the
diode D1. The maximum duty cycle is

V V
V V V
2
II. Inductor Selection:
A good rule for determining the
inductance is to allow the peak-to-peak ripple
current to be approximately 40% of the maximum
input current at the minimum input voltage. The
ripple current flowing in equal value inductors L1
and L2 is given by:
I I 40% I
V
Vi
40%
3
The inductor value is calculated by:
L1 L2 L
Vinmin
I fsw
D 4
f
sw
is the switching frequency and D
max
is the duty cycle at the minimum V
in
.
The peak current in the inductor, to
ensure the inductor does not saturate, is
given by:

I1 I
V V
V
1
40%
2

5
If L1 and L2 are wound on the same core, the
value of inductance in the equation above is
replaced by 2L due to mutual inductance. The
inductor value is calculated by:

L1

L2


L
2

V
2 I F
D 6

III. Power Mosfet selection:
The parameters governing the selection
of the MOSFET are the minimum threshold
voltage V
th(min)
, the on- resistance R
DS(ON)
,
gate-drain charge Q
GD
, and the maximum drain
to source voltage, V
DS(max)
. Logic level or
sublogic-level threshold MOSFETs should be
used based on the gate drive voltage. The peak
switch voltage is equal to Vin + Vout. The peak
switch current is given by:

I1 I1 I2 7

The RMS current through the switch is given by:
I1
I

Vout V V Vout VD
Vin


8

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Methods Enriching Power and Energy Development (MEPED) 2014 9 | P a g e


The MOSFET power dissipation PQ1 is
approximately:

P1 I1

R
V I1

Q F

9

P
Q1
, the total power dissipation for MOSFETs
includes conduction loss (as shown in the first
term of the above equation) and switching loss
as shown in the second term. I
G
is the gate
drive current. The R
DS(ON)
value should be
selected at maximum operating junction
temperature and is typically given in the
MOSFET data sheet. Ensure that the
conduction losses plus the switching losses do
not exceed the package ratings or exceed the
overall thermal budget.

IV. Output Diode Selection:

The output diode must be selected to
handle the peak current and the reverse voltage.
In a SEPIC, the diode peak current is the same
as the switch peak current I
Q1(peak)
. The
minimum peak reverse voltage the diode must
withstand is:

V1 V V 10

Similar to the boost converter, the average
diode current is equal to the output current.
The power dissipation of the diode is equal to
the output current multiplied by the forward
voltage drop of the diode. Schottky diodes are
recommended in order to minimize the
efficiency loss.

V. Sepic Converter Selection:

The selection of SEPIC capacitor, Cs,
depends on the RMS current, which is given by:

I I
V V
V
11
The SEPIC capacitor must be rated for a large
RMS current relative to the output power. This
property makes the SEPIC much better suited to
lower power applications where the RMS current
through the capacitor is relatively small (relative
to capacitor technology). The voltage rating of
the SEPIC capacitor must be greater than the
maximum input voltage. Tantalum and ceramic
capacitors are the best choice for SMT, having
high RMS current ratings relative to size.
Electrolytic capacitors work well for through-
hole applications where the size is not limited and
they can accommodate the required RMS current
rating.
The peak-to-peak ripple voltage on Cs (assuming
no ESR):
V
I D
C F
12
A capacitor that meets the RMS current
requirement would mostly produce small ripple
voltage on Cs. Hence, the peak voltage is typically
close to the input voltage.
I. Output Capacitor Selection:
In a SEPIC converter, when the power
switch Q1 is turned on, the inductor is charging and
the output current is supplied by the output
capacitor. As a result, the output capacitor sees
large ripple currents. Thus the selected output
capacitor must be capable of handling the
maximum RMS current. The RMS current in the
output capacitor is:

I I
V V
V
13
The ESR, ESL, and the bulk capacitance of
the output capacitor directly control the
output ripple. Assume half of the ripple is
caused by the ESR and the other half is
caused by the amount of capacitance. Hence,

ESR
V 0.5
IL1 IL2
14


Cout
I
V 0.5 F
15


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Methods Enriching Power and Energy Development
The output cap must meet the RMS
ESR and capacitance requirements. In
mount applications, tantalum, polymer
electrolytic, and polymer tantalum, or
layer ceramic capacitors are recommended
the output.

II. Input Capacitor Selection

Similar to a boost converter,
has an inductor at the input. Hence,
current waveform is continuous and
The inductor ensures that the input capacitor
fairly low ripple currents. The RMS current
input capacitor is given by:

IC
I
12
16
The input capacitor should be capable
the RMS current. Although the input
not so critical in a SEPIC application,
higher value, good quality capacitor would
impedance interactions with the input supply.

IV. EXPERIMENTAL RESULTS
Proposed Block Diagram of Wind Energybased
mobile battery charging and battery applications
Figure 4: Block diagram for proposed converter
Proposed Circuit of Sepic Converter is shown in
figure 4. A fixed voltage is boosted to a voltage
level necessary to charge a battery. It is boosted
with the design parameters and simulated using the
matlab. The output voltage and the current
waveforms are shown in the figure 4.1 and 4.2
respectively.
International Journal for Research and Development in Engineering (IJRDE)
ISSN: 2279-0500 Special Iss
Methods Enriching Power and Energy Development (MEPED) 2014
current,
surface
polymer
or multi-
are recommended at
the SEPIC
Hence, the input
triangular.
capacitor sees
current in the

capable of handling
capacitor is
application, a 10 F or
would prevent
supply.
EXPERIMENTAL RESULTS
Proposed Block Diagram of Wind Energybased
mobile battery charging and battery applications
diagram for proposed converter
Proposed Circuit of Sepic Converter is shown in
figure 4. A fixed voltage is boosted to a voltage
level necessary to charge a battery. It is boosted
with the design parameters and simulated using the
voltage and the current
waveforms are shown in the figure 4.1 and 4.2

Figure 4.1 Circuit diagram for proposed converter
Figure 4.2 Input Voltage Waveform
Figure 4.3 Switching Pulse for Mosfet
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10 | P a g e
Circuit diagram for proposed converter
Input Voltage Waveform
Switching Pulse for Mosfet
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Methods Enriching Power and Energy Development (MEPED) 2014 11 | P a g e
Figure 4.4 Output Voltage Waveform
Figure 4.5 Output Current Waveform
V. CONCLUSION
In this a wind battery charger has been investigated
to charge the mobile phone or battery while
travelling .This technology can help to meet the
emergency power requirement when grid electricity
is not available. The wind driven mobile charger is
also portable, cost-effective and energy efficient
.By further suitable modifications, the system could
be used to charge gadgets for daily use. In the
Future work charging of laptop and high power
gadgets will be accomplished.

REFERENCES
[1] S.N. Singh ,Sumit Kumar Jha, Sudhir Kumar
Sinha, 2011, Wind driven mobile charging of
automobile battery International Journal of
Engineering Science and Technology (IJEST) :
(3):1:68-74,
[2] Daniel S. A.and Gaunden,N.A. 2001, A stand
alone integrated array wind turbine gen and
photovoltaic-array in feed-forward controlled
PWM inverter, Proceedings of the
International Conference on energy, automation
and information Technology(EAIT 2001), Indian
Institute of Technology, Kharagpur, India, pp. 667-
670.
[3] Eltamaly, A. M. 2005 Modelling of wind
turbine driving permanent magnet generator with
maximum power point tracking system,
Proceeding of 2nd MInia International conference
for advance Trends in Engg (MICATE2005),
Elminia, Egypt.
[4] Muljadi, E., Piercek, K.and Migliore,P. 1998
Control strategy for variable speed Stall regulated
wind turbines , National Renewable Energy
Laboratory 1617 Cole Boulevard Golden,
Colorado 80401-3393.
[5] Rizk, J. and Nagriak, M.H..2010 Design of
permanent magnet generator for wind energy
application, Power Electronics, Machines and
Drives (PEMD2010) 5th IET International
Conference, Australia.
[6] AN-1484 Designing A SEPIC
Converter(SNVA168EMay 2006-Revised April
2013) by Dongbing Zhang from texas Instruments.
[7] A Novel Design of wind driven mobile battery
charger by K.Sudhakar & Priyanka Saxena,
International Journal of Science, Engineering and
Technology Research (IJSETR),March 2013.


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Methods Enriching Power and Energy Development (MEPED) 2014 12 | P a g e




Design and Implementation of Maximum Power Point Tracking
For Super Lift Converter

Indu V. R
1
; V. Chamundeeswari
2

1,2
Department of EEE, St. Josephs college of engineering, Chennai, India

ABSTRACT
Photovoltaic (PV) is a technical name in which radiant
(photon) energy from the sun is converted to direct
current (dc) Electrical Energy. PV power output is still
low, continuous efforts are taken to develop the PV
converter and controller for maximum power extracting
efficiency and reduced cost factor. The maximum power
point tracking (MPPT) is a process which tracks one
maximum power point from array input, varying the
ratio between the voltage and current delivered to get
the most power it can. A number of algorithms have
been developed for extracting maximum power. This
paper details the study of incremental conductance
MPPT algorithm with the help of a negative output luo
converter.

Keywords- PV Module, MPPT, Incremental
Conductance (IC) Algorithm, luo converter.

I. INTRODUCTION

Solar Energy is the ultimate source of energy, which is
naturally replenished in a short time period of time, for this
reason it is called Renewable Energy or Sustainable
Energy. Due to the severity of the global energy crisis and
environmental pollution, the photovoltaic (PV) system has
become one kind of important renewable energy source.
Solar energy has the advantages of maximum reserve,
inexhaustibleness, and is free from geographical
restrictions, thus making PV technology a popular research
topic. The efficiency of solar cells depends on many factors
such as temperature, insolation, spectral characteristics of
sunlight, dirt, shadow, and so on. Changes in insolation on
panels due to fast climatic changes such as cloudy weather
and increase in ambient temperature can reduce the
photovoltaic (PV) array output power. In
addressing the poor efficiency of PV systems, some
methods is proposed, among which is a new concept called
maximum power point tracking (MPPT). All MPPT
methods follow the same goal which is maximizing the PV
array output power by tracking the maximum power on
every operating condition. In this paper we use incremental
conductance algorithm for precise control under rapidly
changing atmospheric conditions.

II. PV CELL MODELING
A PV module consists of number of solar cells connected in
series and parallel to obtain desired voltage and current.
Each solar cell is basically a p-n diode. As sunlight strikes a
solar cell, the incident energy is converted directly into
electrical energy without any mechanical effort.
Transmitted light is absorbed within the semiconductor by
using its energy to excite free electrons from a low energy
status to an unoccupied higher energy level [6]. When a
solar cell is illuminated, excess electron hole pairs are
generated by light throughout the material, hence the p-n
junction is electrically shorted and current will flow. The
equivalent circuit of a PV cell is as shown in Figure1.



Figure1. PV cell modeled as diode circuit

The current source represents the cell photo current. Rsh
and Rs are the intrinsic shunt and series resistance of the
cell respectively. Usually the value of Rsh is very large and
that of Rs is very small.Equations of PV Module The
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Methods Enriching Power and Energy Development (MEPED) 2014 13 | P a g e




photovoltaic module can be modeled mathematically as
given in equations shown below.
Module photo current:
Iph = [Isc + Ki (Tk - Tref)] * / 1000. (1)
Module reverse saturation current:
Irs = Iscr/[exp( qV / N kAT ) .1] (2)
The module saturation current Io varies with the cell
temperature, which is given by
Io = Irs(T/Tr )^3 exp((qEg/KA)*(1/Tr-1/T)) (3)
The current output of PV module is :
Ipv=Iph- Is*[exp{q(V pv +IpvRs)/Ns AKT}-1] (4)
Where Vpv=Voc. Here we consider 36 series connected Pv
cells

Figure 2 Simulink model

PV system naturally exhibits a nonlinear I-V and P-V
characteristics which vary with the radiant intensity and cell
temperature. The typical I-V and P-V characteristics of
solar cell are shown in figure 3& figure4.


Figure 3 I-V characteristics of PV panel.


Figure 4 P-V characteristic

III. MPPT
MPPT algorithms are necessary in PV applications because
the MPP of a solar panel varies with the irradiation and
temperature, so the use of MPPT algorithms is required in
order to obtain the maximum power from a solar array.
Over the past decades many methods to find the MPP have
been developed and published. These techniques differ in
many aspects such as required sensors, complexity, cost,
range of effectiveness, convergence speed, correct tracking
when irradiation and or temperature change, hardware
needed for the implementation or popularity [1]. Among
these techniques, the P&O and the Incremental
Conductance algorithms are the most common. These
techniques have the advantage of an easy implementation.
Other techniques based on different principles are fuzzy
logic control, neural network, and fractional open circuit
voltage or short circuit current etc .Among different
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Methods Enriching Power and Energy Development (MEPED) 2014 14 | P a g e




algorithms, Incremental Conductance method is used here.
In this method, the array terminal voltage is always adjusted
according to the MPP voltage. It is based on the
incremental and instantaneous conductance of the PV
module figure given below shows that the slope of the PV
array power curve is zero at the MPP, increasing on the left
of the MPP and decreasing on the right-hand side of the
MPPT .The basic equations of this method are as follows
dI/dV= - I/V, at MPP (5)
dI/dV> I/V, left of MPP (6)
dI/dV< I/V, right of MPP (7)
Where, I and V are the PV array output current and voltage
respectively. The left-hand side of the equations represents
the Incremental conductance of the PV module, and the
right-hand side represents the instantaneous conductance.
From (5)(7), it is obvious that when the ratio of change in
the output conductance is equal to the negative output
conductance, the solar array will operate at the MPP. In
other words, by comparing the conductance at each
sampling time, the MPPT will track the maximum power of
the PV module. The accuracy of this method is proven,
where it mentions that the Incremental conductance method
can track the true MPPs independent of PV array
characteristics. The efficiency was observed to be as much
as 98.2%, but it is some modifications and reformations
were proposed on this method so far, but since this method
inherently has a good efficiency, the aforementioned
amendments increase the complexity and cost of the system
and there was no remarkable change in system efficiency.
In this paper, control action is done using a microcontroller.
It generates pulse width modulation (PWM) waveform to
control the duty cycle of the converter switch according to
the Incremental conductance algorithm. Flow chart for the
incremental conductance is given below.


Figure 5. Incremental conductance algorithms

IV. CONVERTER
Luo converters were developed from the prototypes using
VL technique. These converters perform DC-DC voltage
increasing conversion with high power density, high
efficiency, and cheap topology in simple structure. They are
different from any other DC-DC step up converters and
possess many advantages including a high output voltage
with small ripples. Therefore, these converters are widely
used in computer peripheral equipment and industrial
applications, especially for high output voltage projects.
This paper introduces negative output super lift technique
that implements the output voltage increasing in stage by
stage along the geometric progression. Equation (8) shows
the input output relationship of luo converter
Vo = Vin/(1-k) (8)
The NOESLLC provides high voltage transfer gain using
Super-lift technique Its topology differs from the
conventional circuit as it uses additional capacitor in
parallel with the load boosting the output voltage. The
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Methods Enriching Power and Energy Development (MEPED) 2014 15 | P a g e




linkage between input and output is alleviated which
degrades the output voltage. The above figure shows the
circuit diagram of NOESLLC. It consists of a power switch
MOSFET M1, Inductor L1, Resistor R1, Diodes D1, D2,
Capacitor C1, C2 and load resistance.


Figure 6 negative output luo converter
MODE1
When the switch is closed during the duty interval 0 to T,
the supply voltage increases the current through the
inductor L1 and the capacitor C1 gets charged. The load
current is maintained constant by the discharge of the
capacitor C2 during this period



Figure 7 mode 1 representation
MODE 2
During the duty interval T to T the switch is closed where
the stored charges in the inductor supplies the load current
and the capacitor C1 and C2 produces the boosted voltage
across the load


Figure 8 mode 2 representations
V. SIMULATION RESULTS
The simulation system consists of PV module; negative
output luo converter circuit and MPPT control block as
shown in the figure (9).

Figure 9 simulation system

Output power available at the output of the system without
MPPT is given in figure 10. By using incremental
conductance algorithm, PV panels working point is shifted
to the MPP and power output is increased.

Figure 10 PV output power without MPPT
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Methods Enriching Power and Energy Development (MEPED) 2014 16 | P a g e





Figure 11 Output power with MPPT.

VI. CONCLUSION
This paper presents the design and simulation for maximum
power point tracking (MPPT) for photovoltaic system,
which includes a high-efficiency luo converter with
incremental conductance algorithm. The converter can draw
maximum power from the PV panel for a given solar
insolation and temperature by adjusting the duty cycle of
the converter.

REFERENCES
[1] Azadeh Safari And Saadmekhilef, Member, IEEE, (2011)
Simulation And Hardware Implementation Of Incremental
Conductance Mppt With Direct Control Method Using Cuk
Converter IEEE Transactions On Industrial Electronics, Vol. 58,
No. 4, April 2011
[2] S. Nema, R.K.Nema, and G.Agnihotri, Matlab / simulink
based study of photovoltaic cells / modules / array and their
experimental verification, International Journal of Energy and
Environment, pp.487-500, Volume 1, Issue 3, 2010.
[3] N. Femia, D. Granozio, G. Petrone, G. Spagnuolo, andM.
Vitelli, Predictive & adaptive MPPT perturb and observe
method, IEEE Trans. Aerosp.Electron. Syst., vol. 43, no. 3, pp.
934950, Jul. 2007.
[4] E. Koutroulis, K. Kalaitzakis, and N. C. Voulgaris,
Development of a microcontroller-based, photovoltaic maximum
power point tracking controlsystem, IEEE Trans. Power
Electron., vol. 16, no. 1, pp. 4654,Jan. 2001.
[5] S. Jain and V. Agarwal, A new algorithm for rapid tracking of
approximate maximum power point in photovoltaic systems,
IEEE PowerElectron. Lett., vol. 2, no. 1, pp. 1619, Mar. 2004.
[6] S.Chowdhury, S.P.Chowdhury, G.A.Taylor, and Y.H.Song,
Mathematical Modeling and Performance Evaluation of a Stand-
Alone Polycrystalline PV Plant with MPPT Facility, IEEE Power
and Energy Society General Meeting -Conversion and Delivery of
Electrical Energy in the 21st Century, July 20-24, 2008, Pittsburg,
USA.
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Methods Enriching Power and Energy Development (MEPED) 2014 17 | P a g e

Energy Harvesting Using Oscillating Pendulum
S.Nithiya
1
, K.Sadhuna
2
, A. Saravanan
3

1,2
Final Year EEE, Dhaanish Ahmed College of Engineering, Chennai, Tamilnadu

3
HOD EEE, Dhaanish Ahmed College of Engineering, Chennai, Tamilnadu

ABSTRACT
There is abundance of mechanical energy that can be
harvested and recycled from our living environment.
Here we developed a pendulum motion based power
generator that sustains its motion with low
maintenance providing voltage output peaks from a
reciprocating mechanical structure. The reciprocating
effect of our device is enhanced by using gear
mechanism that is composed of shaft with a dynamo.
We demonstrate lighting up a commercial LED light
bulb by harvesting mechanical energy of the
pendulum oscillation. This project is a platform of
developing a sustainable, low maintenance system to
harvest mechanical energy.
I. INTRODUCTION
The more power demand has been occurring now a day
in India. The main reason of the power demand is due to
the lack of improper energy utilization and conservation.
The paper deals with the power generation from the
mechanical energy that has been wasted in many day
today real time applications. The root of paper is the
Soccket ball concept invented in the Chicago in 2010.
The pendulum setup has been made inside the Soccket
ball, that is whenever it has been kicked Off the kinetic
energy of ball makes the pendulum to oscillate which cuts
the electromagnetic field, generates the electrical energy
.Thus the electrical energy obtained will power up t he
LED and stored in the battery for further usage. We can
implement the pendulum based power generation system
in real time application wherever the vibration produced
.The example is vehicles, the vibrations will be produced
due to movement when it passes through the speed
breakers. We can implement a pendulum based power
generation system in such dynamic application we can
generate power from it. The power is used to charge the
batteries .In this paper we have proposed the hardware
setup of the pendulum system, power regulatory circuit
and its battery unit [1].
II. PROPOSED SYSTEM
A. General Block diagram of the proposed system
The Block Diagram of the proposed system given below
deals with the overall system design and process flow
control.
Figure: 1 Proposed System Block Diagram
The pendulum model will be generating power from the
real time dynamic movements. Once when the pendulum
is disturbed from its equilibrium position it swings to and
fro. The oscillation movement is converted into the linear
motion with the help of the Reciprocating system. .The
RPM is coupled with the Dynamo. The Linear Charge
control circuit is the combination of the embedded system
design which will control the flow of power from the
pendulum model to the Battery storage unit and also from
the Battery to the Load.
B.Proposed System Circuit Diagram:
The latter part is dealing about the general block diagram
of the proposed system .The system design , components
and the process flow will be discussed here .The circuit
diagram will contain the following components such as
the given in the table.
Table: 1 Technical specification of the components used
COMPONENT SPECIFICATION
Microcontroller PIC 16F877A
Voltage Regulator IC7805
Inverter SG3525A
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Methods Enriching Power and Energy Development (MEPED) 2014 18 | P a g e

MOSFET RFZ44NTO
Step up Transformer 12/120 Volt
LCD display 4-Bit


Figure: 2 proposed system circuit diagram
The circuit given above will depict the process flow and
the power flow from the pendulum model to the battery
system. The PIC 16F877A microcontroller used in our
paper is basically used in controlling the process flow
among the various devices [4] .And this is cheaper cost
and easily available in market. The Voltage Regulator
IC7805 is used to regulate the voltage and provide the
fixed voltage to the various units in the circuit .The
Inverter SG3525A have been used in this circuit. The
main objective of using this inverter ,that in order to feed
to the AC loads from the battery unit .The inverter will
convert DC to AC and that will feed to the loads. The
inverter will use the PWM technique to provide this
operation with the help of the two MOSFET RFZ44NTO.
The Step Up transformer will act as a voltage doubler
circuit to double the voltage so that it will feed to the AC
Loads. The process flow is quite simple. The pendulum
will be subjected to the motion when it has been placed
on the real time dynamic movements. The power
generated from the pendulum model must be handled
properly to store in the battery unit. The PIC will sense
the battery storage limit once the limit exceeds the PIC
will remove the gate signal from the MOSFET so that
power given to the Inverter SG3525A which will convert
the dc into ac with the help of the PWM Technique[4].
The inverted AC power will feed to the step up
transformer which will step up the voltage to the required
voltage level needed for the load. The load will be such as
the Lamp, Fan and other ac loads depend on the power
stored in the battery.
C. Calculation on the Power Generated from the
Pendulum Model:
The calculation part will consists of the parameter that
have been discussed below
Calculation on Time Period
FORMULAE USED:
T = 2 (L/g)
L Length of Rope (meters)
G Acceleration due to Gravity (m/ s
2
)

Table 2: variation of Time period with length of string

Time period (T) of pendulum is significantly affected
only by its length and the acceleration of gravity.
Depending upon the length of the string the time period
will gets varied
D.Calculation on power generated with respect to the
Angle x (deg):
The power generated from the pendulum system can be
calculated from the formulae given below
Power = 2Mg (1-Cos(x))/ gL
M - Mass of bob
g- Acceleration due to gravity
L- Length of the string
Assuming of the variables:
M = 0.15 kg, G = 9.8 m/s
2
, l = 0.27m, x = 30 Deg
Power = 0.072 Watts
The same calculation has been made on the different
angles that have been made during the oscillation of the

Length
Acceleration due to
gravity
Time Period
(secs)
1.2 m 9.8 m/ s
2
2.2secs
1.5 m 9.8 m/s
2
2.5 secs
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Methods Enriching Power and Energy Development (MEPED) 2014 19 | P a g e

pendulum. And the below table has been made based on
the calculated datas of power generated [2],[3].
Table: 3 variation power with respect to the angle
S.No Angle x ( Deg) Power (Watts)
1. 30 0.072
2. 45 0.157
3. 60 0.268
4. 75 0.398
5. 90 0.5
6. 120 0.805
7. 150 1.02
8. 180 1.074
The calculation has been made and that is described in the
above table and for better understanding the below chart
deals about the variation of power with respect to the
angle x (deg)

Figure: 2 variation power with respect to the angle x (deg)
The graph is exactly defined that when the angle of the
pendulum oscillation increases the power generation also
increases. From this is it clear we can implement this
system in the application where the more dynamic
movements have been available
III. CONCLUSION
Energy harvesting is, in itself, an energy resource. At the
end of a research we have designed a power generator
with a pendulum that employs the concept of
reciprocating system .The ambient vibration can be used
in an effective way by converting them to electrical
energy. It proposes energy conversion system in terms of
generating electricity. The technique of implementing the
pendulum power generator is to reduce global warming.
The compact model not only provides the accurate result
but also gave the computational speed-ups of the
generation. In future, maximize version of our project can
be installed to produce power. Also some techniques need
to be developed to install our setup in the vehicles. A
large amount of vibrations are produced every time when
it passes through the speed breaker. With appropriate
development of technology, the electrical energy
generated from these vibrations can be used to power up
the batteries.
REFERENCES
[1] Weisstein, Eric W. (2007). "Simple Pendulum". Eric
Weisstein's world of science. Wolfram Research. Retrieved
2009-03-09.
[2] E. Roller, Duane, Leo Nedelsky
(2008). "Conservation of energy". Access Science. McGraw-
Hill Companies. Retrieved 2011-08-26.

[3] Tenenbaum (2004). Fundamentals of Applied
Dynamics. Springer. ISBN 0-387-00887-X.
[4] Heath, Steve (2003). Embedded systems design. EDN
series for design engineers, Newnes. pp. 11
12. ISBN 9780750655460
0
0.2
0.4
0.6
0.8
1
1.2
30 45 60 75 90 120 150 180
P
O
W
E
R



(
W
a
t
t
s
)
ANGLE X(Deg)
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Methods Enriching Power and Energy Development (MEPED) 2014 20 | P a g e


Comparison Analysis of PI and Fuzzy Control of LLC
Resonant Converter Incorporating ZVS Boost Converter
N.Madhanakkumar
1
, T. S. Sivakumaran
2
, D.Sujitha
3
1
Research Scholar, Department of Electrical and Electronics Engineering, Anna University, India
madhanakkumar_n@yahoo.co.in
2
Professor, Department of Electrical and Electronics Engineering, Arunai College of Engineering, India
3
PG Scholar in Power Electronics and Drives, Mailam Engineering College, India


ABSTRACT
The closed loop fuzzy control of LLC type of
series parallel resonant converter
configuration of load resonant converter and its
modeling analysis is presented in this paper. The
LLC resonant converter provides high
frequency operation, without affecting its high
efficiency, which leads to their applications
mostly in DC DC converters. The state space
modeling is analyzed to know the internal state
i.e. stability of the converter. The common
closed loop fuzzy controller is used on both the
side of the LLC resonant tank which eliminates
the steady-state error and decrease the rise time
of the output voltage. The input of 40V LLC
resonant converter is built to produce 220V
output with the help of ZVS boost converter
with 140 kHz resonant frequency. The
comparison of simulation result with the closed
loop fuzzy controller and closed loop PI
controller shows the output performance
characteristics and reliability of a fuzzy
controller.
Keywords: Nyquist Plot, LLC Resonant
Converter, Fuzzy controller, State Space
Modelling, Stability Analysis, ZVS Boost
Converter, PI controller.
I. INTRODUCTION
Though there are different categories of resonant
converters and with each having their abundant
benefits such as operating with high frequency
range of the power switches and low switching
losses, among those LLC resonant converter
(LLRC) which merge the merits of the series
resonant converter and parallel resonant converter
are gaining lots of attention in DC DC converter
applications. It is also analyzed that series
parallel resonant converter (SPRC) can operate
over a wide load range and large input range with
excellent efficiency, when compared with half-
bridge series resonant converter (SRC), parallel
resonant converter (PRC) and series parallel
resonant converters (SPRC) [2].
The optimization of LLC resonant converter is
provided with high accuracy and efficiency with
small size [3, 4, and 6] and used for application
such as over current protection [5] with frequency
in an acceptable value. The LLCRC is applicable to
various applications such as SMPS [9],
telecommunication [11] and for an adjustable wide
range regulated current source [9] with the help of
fundamental harmonic approximation method [10].
This FHA analysis with the parasitic components
are included with this converter and analyzed with
traditional FHA method [7]. The steady state
design is done with the help of state space
modeling method [14, 21] and the state plane
trajectories explains about the boundaries of
various operating modes [17] for the resonant tank
circuit.

II. RESONANT CONVERTER

A. LLC Resonant Converter

The LLC resonant converter operates at high
frequency and also the switching losses are
reduced and provide high efficient LLC converter
design [1]. Thus, the LLC resonant converter
provides high power packing density with high
frequency range up to several MHz [12] as it
combines the frequencies of series resonant
converter and parallel resonant converter. The
LLC resonant converter consists of a resonant tank
with a capacitor (C
r
) and an inductor (L
r
) in series
with the inverter side and an inductor (L
m
) in
parallel to the inverter side and rectifier side, to
provide high voltage gain [1]. The LLC resonant
converter is one of the type of series parallel load
resonant converter and it overcomes the
disadvantages of both series resonant
converter and parallel resonant converter, as it
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Methods Enriching Power and Energy Development (MEPED) 2014 21 | P a g e

provides lack in no load regulation and
circulating current independent of load [2]
respectively. The LLC resonant converter in this
work consists of four power MOSFET switches for
construction of single phase full bridge inverter, on
the input side of the converter or primary side of
the transformer which works under the control
operation of ZVS boost converter. The secondary
side of the transformer or the output side of the
converter consists of four IGBT power
semiconductor switches for the construction of 1
full bridge rectifier. The LLC resonant converter
circuit diagram is shown in fig.1.


Fig.1. LLC resonant converter circuit diagram.

B. Zero Voltage Switching Boost Converter

The zero voltage switching (ZVS) eliminates
capacitive turn on loss, but in zero current
switching (ZCS) it leads to capacitive turn on loss
with high current loss when operate in high
frequency so ZVS is more advantageous than ZCS.
Thus, ZVS is mostly suitable for high frequency
operation with constant off time control. So, in
this proposed design to control the input side
inverter circuit and primary side of the transformer,
the ZVS boost converter is applied. The ZVS boost
converter works with the principle operation of DC
DC boost converter under zero voltage switching
condition of MOSFET switches. Thus the input
voltage of 40Volt is boost up to 150Volt at the
output of ZVS boost converter and it acts as input
and control the inverter circuit on primary side of
the transformer.
III. MODELING ANALYSIS
The modeling is done with the help of state space
modeling. The modeling is used to measure the
data for the system model and to predict the system
behavior for different input situations. Though
there are various techniques for modeling of
converter, the state space modeling is more
advantageous than other. Since, they can be
applicable to non linear, time invariant and
MIMO (multiple inputs and multiple outputs)
systems it is preferred mostly for modeling of
resonant converters. But, the transfer function
modeling can be applicable to linear, time invariant
system under zero initial conditions. The state
space modeling is done for the LLC resonant
converter in this proposed work based on different
mode of operation and with the help of equivalent
circuit formation. The state space matrix is
formed only for three modes of operations in this
work. The state vector includes the state variables
which is the voltage or current of capacitor or
inductor element.

A. State space analysis:
Some of the assumptions are made before
forming the state space matrix for above
operating modes. The assumptions are:
a) All the components of ZVS boost converter
and the components before the inverter side are
considered as ideal.
b) The resonant frequency is higher than the
switching frequency.
c) The output capacitor is large enough to
produce constant output voltage Vo.
d) The circuit losses, including the resonant tank,
switch and filter losses are negligible.

1) For PP mode:
In PP mode, the switches M
1
and M
2
on the inverter
side and T
1
and T
2
on the rectifier side is turned on
in positive conduction mode. The state space
input matrix is given as:

di

t
dt
dv

t
dt

0
1
L

1
C

t
v


1
L

0
V



2) For PN mode:
In this mode of operation, there is a positive
conduction of inverter side with the switches M
1

and M
2
turned on and negative conduction on
rectifier side with the switches T
3
and T
4
turned on.
The state space input matrix is given as:
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Methods Enriching Power and Energy Development (MEPED) 2014 22 | P a g e

di

t
dt
dv

t
dt

0
1
L

1
C

t
v


1
L

0
V



3) PO mode:
The positive conduction of inverter side with
switches M
1
and M
2
turned on and turn off of all
the switches on rectifier side defines the PO mode
operation. For this mode the state space input
matrix is:

di

t
dt
dv

t
dt

0
1
L


1
C

t
v


1
L

0
V



B. Stability analysis:

The state space modeling has one major
advantage, as it is used to study about the internal
state of the system. Thus, stability of the system
using the state space matrix is found by plotting
the nyquist plot for the whole operation of resonant
converter. The equivalent circuit of this resonant
converter is shown in Fig.2.



Fig.2. Equivalent circuit of LLC resonant converter

The state space input matrix for this overall
equivalent circuit of LLC resonant converter is
given as :


0 1

0

i


0
1
L



The nyquist plot for this state space
representation is shown in fig.3. The stability of the
system is used to design the closed loop system
under stable operation. The nyquist plot shows the
real and imaginary axes with the poles and zero
plot for the LLC Resonant converter, from the
nyquist plot it is known that the closed loop system
is stable for the chosen LLC values. Since the
nyquist plot curve does not crosses the (-1+j0)
point in any situtaion so it is stated that the closed
loop system is stable.

Fig.3. Stability Analysis of LLC Resonant Converter
Usi
ng Nyquist Plot.


IV. DESIGN OF CLOSED LOOP FUZZY
CONTROL
The identical fuzzy logic controller is used to
control on both the side (i.e. primary and
secondary) of linear transformer to perform better
control action on input and output side. The fuzzy
logic control provides better controller action than
PI controller since it is very robust and can be
easily modified with the use of multiple input and
output sources and also quick and very cheap to
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Methods Enriching Power and Energy Development (MEPED) 2014 23 | P a g e

implement. Fig.1. shows the block diagram
representation of fuzzy control based LLC resonant
converter.

Fig.4. Block diagram of fuzzy control based LLC
Resonant converter
Fuzzy logic system is one of the types of
intelligence based system with work on both
Linguistic language and Boolean logic. The fuzzy
logic control structure is based on four main steps.
The four main steps are:
(a) Fuzzification:
The fuzzification step is used to match
the input variables to fuzzy sets with the
help of membership functions. In other
words, the linguistic/ crisp input variables
are converted into fuzzy sets with the help of
membership functions.
(b) Inference Mechanism:
The inference mechanism is based upon
the rules framed and along with the
membership function fuzzified.
(c) Rules and Database:
The rules are framed as IF THEN rules
with the logic operations either AND/ OR
operation to map the multiple input with
their membership functions.
The database is the membership
functions using the fuzzy rules in the fuzzy
sets
(d) Defuzzification:
The defuzzification is used to obtain
crisp output with the aid of converting fuzzy
output is mapped to a crisp output using the
membership functions.
The general structure of fuzzy controller in block
diagram representation is shown in fig.5




Fig.5.Structure of fuzzy controller

Thus in this proposed system the fuzzification of
seven triangular membership functions is used with
49 rules under AND logic operations. The
defuzzification is used with the centroid output
functions. The crisp output is obtained at the end of
defuzzification and used to generate pulse signal to
the power switches on the ZVS boost converter and
single phase full bridge inverter. The fuzzy rule
base table is shown in TABLE I which is easy to
use and understand the fuzzy logic.

TABLE I
FUZZY RULE BASE


V. SIMULATION RESULTS
The Fig.6.1 shows the closed loop fuzzy response
of LLC resonant converter start - up output voltage
with set point of 40V and nominal load of 100.
The Fig.6.2 shows the response of output voltage
under sudden line disturbance (40V 42V 40V)
at 2.5sec with nominal load of 100 and Fig.6.3
shows the responses of output voltage under

E
CE
NB NM NS Z PB PM PS
NB NB NB NM NM NS NS Z
NM NB NM NM NS NS Z PB
NS NM NM NS NS Z PB PB
Z NM NS NS Z PB PB PM
PB NS NS Z PB PB PM PM
PM NS Z PB PB PM PM PS
PS Z PB PB PM PM PS PS
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Methods Enriching Power and Energy Development (MEPED) 2014 24 | P a g e

sudden load disturbance (100 90 100 ) at
1sec with set point of 40V respectively with fuzzy
controller. Similarly, the closed loop PI control
responses for the performance comparison of
closed loop fuzzy controller with PI controller are
shown in TABLE II. The Fig.6.4 shows the closed
loop PI response of LLC resonant converter start -
up output voltage with set point of 40V and
nominal load of 100. The Fig.6.5 shows the
response of output voltage under sudden line
disturbance (40V 42V 40V) at 2.5sec with
nominal load of 100 and Fig.6.6 shows the
response of output voltage under sudden load
disturbance (100 90 100 ) at 1sec with
set point of 40V respectively. With these
simulation results, the comparison TABLE II is
drawn to clearly predict the performance of the
LLC resonant converter and the controller
importance in the system. The TABLE II shows the
performance of LLC resonant converter under
closed loop fuzzy control and PI control. The table
III shows the parameter specifications for LLC
resonant converter. . The Fig.6.6 shows the
comparison of simulated performances of closed
loop fuzzy control and PI control for LLC Resonant
converter by graphical representation.

Fig.6.1. Simulated start-up voltage of LLCRC
with set - point 40V and nominal load 100 (Fuzzy
Controller)

Fig.6.2. Simulated output voltage of LLCRC with
sudden line disturbances (40V 42V 40V) at t =
2.5sec (Fuzzy Controller)

Fig.6.3. Simulated output voltage of LLCRC with
sudden load disturbances (100 90 100) at
t = 1sec (Fuzzy Controller)

Fig.6.7. Simulated start-up voltage of LLCRC
with set - point 40V and nominal load 100 (PI
Controller)

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Methods Enriching Power and Energy Development (MEPED) 2014 25 | P a g e

Fig.6.9. Simulated output voltage of LLCRC
with sudden line disturbances (40V 42V
40V) at t = 2.5sec (PI Controller)

Fig.6.11. Simulated output voltage of LLCRC with
sudden load disturbances (100 90 100) at t =
1sec (PI Controller)

TABLE II
PERFORMANCE EVALUATION OF CLOSED LOOP FUZZY
CONTROLWITH PI CONTROL OF LLC RESONANT
CONVERTER



TABLE III
PARAMETERS SPECIFICATION FOR LLC
RESONANT CONVERTER

Fig.6.13. Comparison of Simulated Performances of
Closed Loop Fuzzy and PI Controller for LLCRC by
Graphical Representation

VI. CONCLUSION
Thus, the closed loop control of LLC resonant
converter performance was obtained using fuzzy
logic controller. The simulation result with lessen
rise time and elimination of steady state error
was obtained. The system execute better under
sudden line and load disturbance. The stability of
LLCRC was analyzed with the help of nyquist plot
and state space analysis. The closed loop fuzzy
logic controller and closed loop PI controller
characteristic performance was compared and
shows that the closed loop fuzzy control is less
sensitive to the line and load disturbances than
closed loop PI controller system.
REFERENCES

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Somani, Emil Auadisian, John Shen, and Issa
Batarseh, Efficiency oriented optimal design
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[3] T. Liu, Z. Zhou, A. Xiong, J. Zeng, and J. Ying,
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[4] C. Oeder, Analysis and design of a low-profile
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Stone, and C. M. Bingham, Analysis of CLL
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effects of parasitic components, in Proc. IEEE
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[8] G. Ivensky, S. Bronshtein, and A. Abramovitz,
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[9] R. Beiranvand, B. Rashidian, M. R. Zolghadri,
and S. M. H. Alavi, Designing an adjustable
wide range regulated current source, IEEE
PARAMETERS VALUES
Input Voltage, V
dc
40V
Resonant Capacitor, C
r
470nF
Resonant Inductor, L
r
2.75H
Load Resistance, R
L
100
Resonant Inductor, L
m
7.67H
Output Voltage, V
o
220V
1
2
3
4
5
6
7
8
9
10
11
12
13
14
T
i
m
e
F
u
International Journal for Research and Development in Engineering (IJRDE)
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Methods Enriching Power and Energy Development (MEPED) 2014 26 | P a g e


Trans. Power Electron., vol. 25, no. 1, pp. 197
208, Jan. 2010.
[10] T. Duerbaum, First harmonic approximation
including design constraints, in Proc. 20th Int.
Telecommun. Energy Conf.,, 1998, pp. 321328.
[11] W.-Y. Choi, J.-M. Kwon, and B.-H. Kwon,
High-performance front-end rectifier system for
telecommunication power supplies, Proc. Inst.
Elect. Eng., vol. 153, no. 4, pp. 473482, 2006.
[12] H. de Groot, E. Janssen, R. Pagano, and K.
Schetters, Design of a 1-MHz LLC resonant
converter based on a DSP-Driven SOI Half-
Bridge power MOS module, IEEE Trans. Power
Electron., vol. 22, no. 6, pp. 23072320, Nov.
2007.
[13] B. Yang, F. C. Lee, A. J. Zhang, and G. Huang,
LLC resonant converter for front end DC/DC
conversion, in Proc. IEEE Appl. Power
Electron. Conf. Expo., 2002, pp. 11081112.
[14] J. H. Cheng and A. F. Witulski, Analytic
solutions for LLCC parallel resonant converter
simplify use of two-and three-element
converters, IEEE Trans. Power Electron., vol.
13, no. 2, pp. 235243, Mar. 1998.
[15] X. Fang, H. Hu, J. Shen, and I. Batarseh,
Operation mode analysis and peak gain
approximation of the LLC resonant converter,
IEEE Trans. Power Electron., vol. 27, no. 4, pp.
19851995, Apr. 2012.
[16] B. Lu, W. Liu, Y. Liang, F. C. Lee, and J. D. van
Wyk, Optimal design methodology for LLC
resonant converter, in Proc. IEEE Appl. Power
Electron. Conf. Expo., Mar. 2006, vol. 2, p. 6.
[17] N. H. Kutkut, C. Q. Lee, and I. Batarseh, A
generalized program for extracting the control
characteristics of resonant converters via the state
- plane diagram, IEEE Trans. Power Electron.,
vol. 13, no. 1, pp. 5866, Jan. 1998.
[18] I. Batarseh, State-plane approach for the analysis
of half-bridge parallel resonant converters, Proc.
Inst. Elect. Eng., vol. 142, no. 3, pp. 200204,
Jun. 1995.
[19] A. K. S. Bhat, A generalized steady-state
analysis of resonant converters using two-port
model and Fourier-series approach, IEEE Trans.
Power Electron, vol. 13, no. 1, pp. 142151, Jan.
1998.
[20] I. Batarseh, R. Liu, A. Ortiz-Conde, A. Yacoub,
and K. Siri, Steady state analysis and
performance characteristics of the LLC-type
parallel resonant converter, in Proc. Power
Electron. Spec. Conf., 1994, pp. 597606.
[21] J. F. Lazar and R. Martinelli, Steady-state
analysis of the LLC series resonant converter, in
Proc. IEEE Appl. Power Electron. Conf. Expo.,
2001, vol. 2, pp. 728735.
[22] Y. Gu, Z. Lu, L. Hang, Z. Qian, and G. Huang,
Three-level LLC series resonant DC/DC
converter, IEEE Trans. Power Electron., vol. 20,
no. 4, pp. 781789, Jul. 2005.
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Methods Enriching Power and Energy Development (MEPED) 2014 27 | P a g e


Single-Level Single Switch Control for Transformerless Rectifier

Vijay.S
1
,Sudharsan.A.N
2
,Venkatesh Kumar.B
3
, P.Swethamarai
4

1,2,3,4
Electrical & Electronics Dept, R.M.D Engineering College, Kavaraipettai, India


ABSTRACT
This paper presents a high step-down
transformerless single-stage single-switch ac/dc
converter suitable for universal line applications (90
270 V
rms
). The topology integrates a buck-type
power-factor correction (PFC) cell with a buckboost
dc/dc cell and part of the input power is coupled to
the output directly after the first power processing.
With this direct power transfer feature and sharing
capacitor voltages, the converter is able to achieve
efficient power conversion, high power factor, low
voltage stress on intermediate bus (less than 130 V)
and low output voltage without a high step-down
transformer. The absence of transformer reduces the
component counts and cost of the converter. Unlike
most of the boost-type PFC cell, the main switch of
the proposed converter only handles the peak
inductor current of dc/dc cell rather than the
superposition of both inductor currents. Detailed
analysis and design procedures of the proposed
circuit are given and verified by experimental results.

Index TermsDirect power transfer (DPT),
integrated buck buckboost converter (IBuBuBo),
power-factor correction (PFC), single-stage (SS),
transformerless.

I. INTRODUCTION

SINGLE-STAGE (SS) ac/dc converters have received much
attention in the past decades because of its cost effectiveness,
compact size, and simple control mechanism. Among existing
SS converters, most of them are comprised of a boost power-
factor correction (PFC) cell followed by a dc/dc cell for output
voltage regulation [1][7]. Their intermediate bus voltage is
usually greater than the line input voltage and easily goes be-
yond 450 V at high-line application [8]. Although there are a
lot of efforts to limit this bus voltage, it is still near or above
the peak of the line voltage due to the nature of boost-type
PFC cell. For application with low output voltage (e.g.,
48V), this high inter-mediate bus voltage increases
components stresses on the dc/dc cell. With a simple step-
down dc/dc cell (i.e. buck or buckboost converter), extremely
narrow duty cycle is needed for the con-version. This leads to
poor circuit efficiency and limits the input voltage range for
getting better performance [9], [10]. Therefore, a high step-
down transformer is usually employed even when galvanic
isolation is not mandatory. For example, LED drivers without
isolation may satisfy safety requirement [11]. Also, in some
multistage power electronics system (e.g., in data center,
electrochemical and petrochemical industries, and subway
applications [12]), the isolation has been done in the PFC
stage, the second transformer in the dc/dc cell for the sake of
isolation is considered as redundant. Hence, non isolated ac/dc
converter can be employed to reduce unnecessary or
redundant isolation and enhance efficiency of the overall
system. Besides, leakage inductance of the transformer causes
high spike on the switch and lower conversion efficiency. To
protect the switch, snubber circuit is usually added resulting in
more component counts [13]. In addition, the other drawbacks
of the boost-type PFC cell are that it cannot limit the input
inrush current and provide output short-circuit protection [14].
To tackle the aforementioned problems, an effective way is to
reduce the bus voltage much below the line input voltage.
Several topologies have been reported [9], [10], [13], [15]
[18]. Although the recently reported IBoBuBo converter [13]
is able to limit the bus voltage under 400 V, it cannot be
applied to the low-voltage application directly due to the boost
PFC cell. On the other hand, the converters [9], [10], [15]
[18] employ different PFC cells to reduce the intermediate bus
voltage. Among those converters, [9] and [15] use a
transformer to achieve low output voltage either in PFC cell or
dc/dc cell. Therefore, the leakage inductance is unavoidable.
In [10], [17], and [18], the converters employ a buckboost
PFC cell resulting in negative polarity at the output terminal.
In addition, the topologies in [18] and [10] process power at
least twice resulting in low power efficiency. Moreover, the
reported converters, in [16], and [17], consist of two active
switches leading to more complicated gate control.
Apart from reducing the intermediate bus voltage, the
converter in [19] employs resonant technique to further
increase the step-down ratio based on a buck converter to
eliminate the use of intermediate storage capacitor. The
converter features with zero-current switching to reduce the
switching loss. However, without the intermediate storage, the
converter cannot provide hold-up time and presents substantial
low-frequency ripples on its output voltage. Besides, the duty
cycle of the converter for high-line input application is very

Methods Enriching Power and Energy Development (MEPED) 2014 28 | P a g e


narrow, i.e., < 10%. This greatly increases the difficulty in its
implementation due to the minimum on-time of pulse-width-
modulation (PWM) IC and rise/fall time of MOSFET. More
details on comparing different approaches will be given in the
Section V.

In this paper, an intergrated buckbuckboost (IBuBuBo)
converter with low output voltage is proposed. The converter
utilizes a buck converter as a PFC cell. It is able to reduce the
bus voltage below the line input voltage effectively. In
addition, by sharing voltages between the intermediate bus
and output capacitors, further reduction of the bus voltage can
be achieved. Therefore, a transformer is not needed to obtain
the low output voltage. To sum up, the converter is able to
achieve:
1) low intermediate bus and output voltages in the
absence of transformer;
2) simple control structure with a single-switch;
3) positive output voltage;
4) high conversion efficiency due to part of input power
is processed once and
5) input surge current protection because of series
connection of input source and switch.

The paper is organized as follows: operation principle of the
proposed IBuBuBo converter is depicted in Section II and
followed by design consideration with key equations in
Section III. Experimental result and discussion of the
converter are given in Section IV and V, respectively. Finally,
conclusion is stated in Section VI.

II. PROPOSED CIRCUIT AND ITS OPERATING
PRINCIPLE

The proposed IBuBuBo converter, which consists of the
merging of a buck PFC cell (L
1
, S
1
, D
1
, C
o
, and C
B
) and a
buckboost dc/dc cell (L
2
, S
1
, D
2
, D
3
, C
o
, and C
B
) is il-
lustrated in Fig. 1(a). Although L
2
is on the return path of the
buck PFC cell, it will be shown later in Section III-A that it
does not contribute to the cell electrically. Thus, L
2
is not con-
sidered as in the PFC cell. Moreover, both cells are operated
in discontinuous conduction mode (DCM) so there are no
currents in both inductors L
1
and L
2
at the beginning of each
switching cycle t
0
. Due to the characteristic of buck PFC cell,
there are two operating modes in the circuit.
Mode A (v
in
() V
B
+ V
o
): When the input voltage v
in
()
is smaller than the sum of intermediate bus voltage V
B
, and
output voltage V
o
, the buck PFC cell becomes inactive and
does not shape the line current around zero-crossing line
voltage [20], owing to the reverse biased of the bridge
rectifier. Only the buckboost dc/dc cell sustains all the output
power to the load. Therefore, two dead-angle zones are
present in a half-line period and no input current is drawn as
shown in Fig. 1(b). The circuit operation within a switching
period can be divided into three stages and the corresponding
sequence is Fig. 2(a),(b), and (f). Fig. 3(a) shows its key
current waveforms.

1) Stage 1 (period d
1
T
s
in Fig. 3) [see Fig. 2(a)]: When
switch S
1
is turned ON, inductor L
2
is charged linearly
by the bus voltage V
B
while diode D
2
is conducting.
Output capacitor C
o
delivers power to the load.

2) Stage 2 (period d
2
T
s
in Fig. 3) [see Fig. 2(b)]: When
switch S
1
is switched OFF, diode D
3
becomes forward
biased and energy stored in L
2
is released to C
o
and the
load.

3) Stage 3 (period d
3
T
s
- d
4
T
s
in Fig. 3) [see Fig. 2(f)]: The
inductor current i
L

2
is totally discharged and only C
o

sustains the load current.

Mode B (v
in
() > V
B
+ V
o
): This mode occurs when the
input voltage is greater than the sum of the bus voltage and
output voltage. The circuit operation over a switching period
can be divided into four stages and the corresponding
sequence is Fig. 2(c), (d), (e), and (f). The key waveforms are
shown in Fig. 3(b).

1) Stage 1 (period d
1
T
s
in Fig. 3) [see Fig. 2(c)]: When
switch S
1
is turned ON, both inductors L
1
and L
2
are
charged linearly by the input voltage minus the sum of
the bus voltage and output voltage (v
in
() V
B
V
o
),
while diode D
2
is conducting.

2) Stage 2 (period d
2
T
s
in Fig. 3) [see Fig. 2(d)]: When
switch S
1
is switched OFF, inductor current i
L

1

decreases linearly to charge C
B
and C
o
through diode D
1

as well as transferring part of the input power to the load
directly. Meanwhile, the energy stored in L
2
is released
to C
o
and the current is supplied to the load through
diode D
3
. This stage ends once inductor L
2
is fully
discharged.

3) Stage 3 (period d
3
T
s
in Fig. 3) [see Fig. 2(e)]: Inductor
L
1
continues to deliver current to C
o
and the load until its
current reaches zero.

4) Stage 4 (period d
4
T
s
in Fig. 3) [see Fig. 2(f)]: Only C
o

delivers all the output power.



Methods Enriching Power and Energy Development (MEPED) 2014 29 | P a g e


(a)


(b)
Fig. 1. (a) Proposed IBuBuBo SS ac/dc converter. (b) Input voltage
and current waveforms.

III. DESIGN CONSIDERATIONS

To simplify the circuit analysis, some assumptions are made
as follows:
1) all components are ideal;
line input source is pure sinusoidal, i.e. v
in
() = V
pk

sin() where V
pk
and are denoted as its peak voltage and
phase angle, respectively;
2) Both capacitors CB and C0 are sufficiently large such
that they are treated as DC constant voltages
without any ripples ;
3) the switching frequency fs is higher than the line
frequency such that the rectified line voltage
constant with the switching period.

(a)

(b)


(c)

(d)




(e)


Methods Enriching Power and Energy Development (MEPED) 2014 30 | P a g e


(f)
Fig. 2. Circuit operation stages of the proposed ac/dc
converter.

IV. EXPERIMENTAL RESULTS

The performance of the proposed circuit is verified by the
prototype. To ensure the converter working properly with con-
stant output voltage, a simple voltage mode control is
employed. To achieve high performance of the converter for
universal line operation in terms of low bus voltage (< 150V)
and high power factor (> 96%), the inductance ratio has to be
optimized ac-cording to Figs. 4 and 5. The lower the bus
voltage of the converter, the lower voltage rating capacitor
(150 V) can be used.
In addition, the inductance ratio will affect the efficiency of
the converter. More detail will be given in Section V. Taking
the performance of the converter on bus voltage, power factor,
and efficiency into account, the inductance ratio around M =
0.4 is selected. Table II depicts all the components used in the
circuit, and its specification is stated as follows:
1) output power: 100 W;
2) output voltage: 19 V
dc
;
3) power factor: > 96%;
4) intermediate bus voltage: < 150V;
5) line input voltage: 90270 V
rm s
/50 Hz;
6) switching frequency (f
s
): 20 kHz.

TABLE II
CIRCUIT COMPONENTS
Parameters Values

IC Controller TL594

Input filter inductor L
f
2 mH
Input filter capacitor C
f
2 F
Inductor L
1
106 H
Inductor L
2
46 H
Inductance Ratio (M =
L
2
/L
1
) 0.434
MOSFET S
1
SPW47N60CFD
D
1
MUR3040PT
D
2
MUR3040PT
D
3
MUR3040PT
C
B
5 mF
C
o
5 mF


Fig. 7. Measured input characteristic of the converter at (a) 90 V
r m s

and b) 270 V
r m s
under 100-W condition.


Fig. 8. Comparison of IEC61000-3-2 Class D standard with
measured inp

Fig. 9. Measured output voltage (upper trace 10 V/div) and
intermediate bus voltage (bottom trace 40 V/div) at (a) 90 V
r m s
and

Methods Enriching Power and Energy Development (MEPED) 2014 31 | P a g e

(b) 270 V
r m s
under full load condition.

The measured current harmonics met the IEC61000-3-2 class
D standard as shown in Fig. 8. In ad-dition, the measured
output and bus voltages under both low and high line
conditions are shown as in Fig. 9. It can be seen that the bus
voltage was kept at 123 V and well below 150 V at high-line
condition.

Fig. 10. Measured circuit efficiency under load variation.


Fig. 11. Comparison of measured intermediate bus voltage with its
predicted value.

Fig. 10 illustrates the conversion efficiency of the proposed
converter under different line input and out-put power
conditions. The maximum efficiency of the circuit is around
89% at low line application. Furthermore, Fig. 11 shows the
predicted intermediate bus voltage is in good agreement with
the measured value.

V. DISCUSSION

According to [13] and [21], the direct power transfer ratio n
under this type of capacitive coupling is V
o
/V
T
. It can be seen
that the portion of direct power transfer from input to output
decreases when V
B
becomes larger resulting in increase of V
T
.
In other words, the direct power transfer decreases when the
line input voltage increases. It matches with the discussion in
Section III-E. In addition, the increase of V
B
will lower the
conversion efficiency of dc/dc cell due to larger voltage
conversion around ten times at high-line condition, from V
B
=
123 V down to V
o
= 19 V. As a result, it further impairs the
efficiency of the converter at high-line operation. On the other
hand, from (2), decrease of V
B
extends the conduction angle of
the converter leading to higher power factor.
However, lower V
B
requires decrease of inductance ratio
resulting in higher peak inductor currents and causing higher
conduction loss. Thus, trade off has to be made for selecting
the inductance ratio among the peak current of both inductors,
bus voltage, and power factor. Never the less,the converter is
capable to be used under high-line condition with the full load
efficiency around 84% at 240 V
rm s
.

Here Ind. and Trans. are denoted as number of inductors and
number of transformers.

To continue with the comparison from Section I, Table III
shows the performances of recent topologies and the proposed
converter in more detail. In order to achieve low output
voltage and low intermediate bus voltage with high efficiency
for univer-sal line operation, the topologies employ different
approaches.
TABLE III
COMPARISON OF RECENTLY REPORTED
TOPOLOGIES

Di
od
e
Con
trol
Ma
gne
tic Capac
itors
Interme
diate
Bus
Inpu
t
Volt
age
Outpu
t
Maxi
mum
Switc
h
Compon
ents
Voltage
V
B

Vrm
s
Condi
tion
Effici
ency



[1
3] 3 1 2 Ind. 2 400 V
90 ~
270
Vrm
s
100
V/100
W 89.5%
[15] 4 1
1 Ind.
and 1
Trans. 2 220 V
90 ~
270
Vrm
s
48
V/100
W 82%
[9] 2 2
1 Ind.
and 1
Trans. 2 36 V
187
~
265
Vrm
s
56
V/100
W 85.5%
[10] 4 1 2 Ind. 2 86 V
110
Vrm
s
-20
V/50
W 77%
[17] 3 2 3 Ind. 2 209 V
85 ~
265
Vrm
s
-48
V/111
.52 W 83.1%
[18
] 6 1 3 Ind. 3
V
B1
=
70 V
85
Vrm
-5
V/20 80.5%

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V
B2
=
30 V
s W

[19] 2 1 2 Ind. 2 N/A
90 ~
240
Vrm
s
19
V/13.
72 W 90.56%

Propo
sed 3 1 2 Ind. 2 130 V
90 ~
270
Vrm
s
19
V/100
W 88.9%
Furthermore, every converter has their best performance
when working at particular input and output conditions.
Although the input and output conditions for the converters in
the table are not the same, we have two criteria to compare
their performances. First, for a given power level, the lower
the output voltage of the converter, the lower the efficiency it
gets due to more current flowing in the circuit. Second, for
PWM converters, the fewer semiconductor devices used in the
converter, the lesser the con-duction and switching loss of the
converter will be. However, the operational parameters,
selection of switching frequency, and semiconductor will also
impact on the circuit efficiency. Therefore, it is hard to have a
fair efficiency comparison and, hence, circuit efficiencies
shown are just for the information pur-pose. Nevertheless,
apart from the efficiency, the performances on reducing the
bus voltage, the step-down ratio and circuit complexity are
less dependent on the input and output condi-tions, and
operational parameters, but the topology itself and the
inductance ratio. From the table and excluding all the isolated
converters, it can be seen that the proposed converter is able to
achieve the lowest bus voltage at high-line condition with low
output voltage and probably higher efficiency among all trans-
formerless topologies and its structure is simpler. In addition,
comparing with [10], [18] at low-line condition, the proposed
converter is also able to achieve the lowest bus voltage at
around 33.5 V with positive output voltage and probably
higher effi-ciency. Thus, the proposed converter has better
performance for lower output voltage operation.

VI. CONCLUSION

The proposed IBuBuBo single-stage ac/dc converter has
been experimentally verified, and the results have shown good
agree-ments with the predicted values. The intermediate bus
voltage of the circuit is able to keep below 150 V at all input
and output con-ditions, and is lower than that of the most
reported converters. Thus, the lower voltage rating of
capacitor can be used. More-over, the topology is able to
obtain low output voltage without high step-down transformer.
Owing to the absence of trans-former, the demagnetizing
circuit, the associated circuit dealing with leakage inductance,
and the cost of the proposed circuit are reduced compared with
the isolated counterparts. In addition, the proposed converter
can meet IEC 61000-3-2 standard, and provide both input
surge current and output short-circuit protec-tion. Thanks to
the direct power transfer path in the proposed converter, it is
able to achieve high efficiency around 89%.
REFERENCES

[1] Voltage and current stress reduction in single-stage power-
factor correction AC/DC converters with bulk ca-pacitor voltage
feedback, IEEE Trans. Power Electron., vol. 17, no. 4, pp.
477-484,Jul. 2002.
[2] Single phase power factor correction: A survey, IEEE Trans.
Power Electron., vol. 18, no. 3, pp. 749755, May 2003.
[3] Flyboost power factor correction cell and a new family of
single-stage AC/DC converters, IEEE Trans. Power Electron.,
vol. 20, no. 1, pp. 2534, Jan. 2005.
[4] A Single-Stage AC/DC con-verter With high power factor,
regulated bus voltage, and output voltage, IEEE Trans. Power
Electron., vol. 23, no. 1, pp. 218228, Jan. 2008.
[5] Practical design and evaluation of a 1 kW PFC power supply
based on reduced redundant power processing principle, IEEE
Trans. Ind. Electron., vol. 55, no. 2, pp. 665-673, Feb. 2008.

[6] Single-Stage AC/DC Boost: Forward converter with high
power factor and regulated bus and output voltages, IEEE
Trans. Ind. Electron., vol. 56, no. 6, pp. 21282132, Jun. 2009.
[7] Dynamic modelling and controller design for
a single-stage single-switch parallel boost-flybackflyback
converter, IEEE Trans. Power Electron., vol. 27, no. 2, pp.
816827, Feb. 2012.
[8] Design considerations for single-stage isolated power-factor-
corrected power supplies with fast regulation of the output
voltage, in Proc. IEEE Appl. Power Electron. Conf. Expo.,
1995, vol. 1,pp. 454458.
[9] New power factor correction AC-DC converter with reduced
storage capacitor volt-age, IEEE Trans. Ind. Electron., vol. 54,
no. 1, pp. 384397, Feb. 2007.
[10] Buckboost-type unity power factor rectifier with extended
voltage conversion ratio, IEEE Trans. Ind. Electron., vol. 55,
no. 3, pp. 11231132, Mar. 2008.
[11] Electrolytic capacitor-less, nonisolated PFC converter for
high-voltage LEDs driving, in Proc. IEEE Int. Conf. Power
Electron. and ECCE Asia, 2011, pp. 499506.
[12] Unity power factor isolated three-phase rectifier with two
single-phase buck rectifiers based on the scott transformer,
IEEE Trans. Power Electron., vol. 26, no. 9, pp. 26882696,
Sep. 2011.
[13] Implementation of an efficient transformerless single-stage
single-switch ac/dc converter, IEEE Trans. Ind. Electron., vol.
57, no. 12, pp. 40954105, Dec. 2010.
[14] Analysis and design of a tapped-inductor buckboost PFC
rectifier with low bus voltage, IEEE Trans. Power Electron.,
vol. 26, no. 9, pp. 26372649, Sep. 2011.
[15] Integrated buck-flyback converter as a high-power-factor off-
line power supply, IEEE Trans. Ind. Electron., vol. 55, no. 3,
pp. 10901100, Mar. 2008.
[16] Two buck choppers built-in single phase one stage PFC
converter with reduced DC voltage ripple and its specific
control scheme, in Proc. IEEE Appl. Power Electron. Conf.

Methods Enriching Power and Energy Development (MEPED) 2014 33 | P a g e


Expo., 2008, pp. 13781383.
[17] Analysis and design of a single-phase ac/dc step-down
converter for universal input voltage, IET Electr. Power Appl.,
vol. 1, no. 5, pp. 778784, Sep. 2007.
[18] Integrated buckboost quadratic buck PFC rectifier for
universal input applications, IEEE Trans. Power Electron., vol.
24, no. 12, pp. 28862896, Dec. 2009.
[19] Resonance-assisted buck converter for offline driving of
power LED replacement lamps, IEEE Trans. Power Electron.,
vol. 26, no. 2, pp. 532540, Feb. 2011.
[20] Bridgeless high-power-factor buck con-verter, IEEE Trans.
Power Electron., vol. 26, no. 2, pp. 602611, Feb. 2011.
[21] An alternative to supply DC voltages with high power
factor, IEEE Trans. Ind. Electron., vol. 46, no. 4, pp. 703709,
Aug. 19
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An Improved Full Bridge DC-DC Converter for On-
Board Electric Vehicle Battery Charging
Aswathi C P
1
, K.E.Lakshmiprabha
2
P G scholar, EEE Department, Karpaga Vinayaga college of engineering, Chennai, India
1

Associate Professor, EEE Department, Karpaga Vinayaga college of engineering ,Chennai, India
2

ABSTRACT
The battery charger plays the central role in the
development of electric vehicles. This project
focuses on the DC-DC converter for the electric
vehicle battery charger which is the second stage
of a two stage on board charger. The first stage
is a power factor correction rectifier used to
transform the 50Hz electrical quantities into DC
quantities with a good input power factor. The
second stage is a zero voltage switching full
bridge dc-dc converter which adjusts the levels
to the values required by the battery and
moreover provides a galvanic isolation. The
main objective of this project is to process and
deliver power efficiently, to minimize the
charger size, to reduce the switching losses, to
guarantee fast operation and to reduce the cost
of electricity drawn from utility.
Keywords: DC-DC converter, full bridge,
electric vehicle, zero voltage switching(ZVS),
battery charger
I. INTRODUCTION
Fossil fuels have been extensively used in past
several years and if this trend continues we would
end up completely exhausting them and it would
lead to a situation where we would face scarcity of
such fossil fuels. Use of electric energy for vehicles
is one of the alternative as well as ecological
solutions instead of using fossil fuels. Due to the
exhaustible oil reserves and harmful environmental
impacts of burning oil, it is essential to find
alternative energy sources in the field of
transportation. Alternative vehicle technologies to
replace conventional vehicles consist of electric
vehicles, hybrid electric vehicles (HEVs), plug in
hybrid electric vehicles (PHEV) or else commonly
called battery electric vehicles (BEVs), and fuel
cell vehicles (FCVs).
Battery Electric Vehicles (BEVs) refer to vehicles
propelled exclusively by electric motors. The
source of power stems from the chemical energy
stored in battery packs which can be recharged on
the electricity grid. The scope of such vehicles
strongly depends on the battery and battery charger
developments.
EV battery chargers can be classified as on-board
and off-board with unidirectional or bidirectional
power flow. Unidirectional charging limits
hardware requirements, simplifies interconnection
issues, and tends to reduce battery degradation. A
bidirectional charging system supports charge from
the grid, battery energy injection back to the grid,
and power stabilization with adequate power
conversion.
In order to make the charging easy, onboard
chargers have been developed. The charger should
to be able to plug into a socket and moreover, it
should to be a grid friendly in order not to pollute
the electrical network.
The most general charger topologies includes an
acdc converter with power factor correction (PFC)
[1] followed by an isolated dcdc converter. There
are many high efficiency full bridge dc-dc
converters [2]-[3] that can be used as the second
stage converter. Phase shifted gating scheme [4]-
[5] for full bridge dc-dc converter is most
commonly used. Soft switching for the switches is
achieved using an external inductor in addition to
the leakage inductance of the transformer and the
output capacitance of the switch. This converter
has many improvements [6]-[7] but these
improvements increase the number of components
and also losses.
Current fed topologies with capacitive output filter
naturally minimize diode rectifier ringing since the
transformer leakage inductance is effectively
placed in series with the supply side inductor .In
addition, high efficiency can be achieved with
ZVS, using pulse width modulation technique.

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II. THE PROPOSED TWO STAGE BATTERY
CHARGER
The proposed on-board charger is shown in Fig.
1.The proposed charger consists of a front end
power factor correction converter and a second
stage full bridge dc-dc converter.

A. Front-End First Stage AC-DC PFC Rectifier
The interleaved PFC consists of two CCM boost
converters in parallel, which operate 180 out of
phase [ 8] [9] .The input current is the sum of the
inductor currents in LB1 and LB2. Since the
inductor ripple currents are out of phase, they tend
to cancel each other and reduce the input ripple
current.

B. Second Stage ZVS Full-Bridge DC-DC
Converter
The primary side of the second stage converter
consists of a full-bridge inverter. However, instead
of driving the diagonal bridge switches
simultaneously, the lower switches (Q3 and Q4)
are triggered at a fixed 50% duty cycle and the
upper switches (Q1 and Q2) are pulse width
modulated.



Fig 1.The proposed electric vehicle battery charger

This converter has six operating intervals. The
operating waveforms of full bridge dc-dc converter
with timing intervals are shown in Figure 2. The
operating intervals are determined by the ON/OFF
states of the four primary switches. In the analysis
that follows, the power semiconductor switches
have been modeled with parallel diodes and
parasitic capacitances. The rectifiers are assumed to
be ideal and the resonant inductor includes the
transformer leakage inductance.

Fig 2.Timing interval for full bridge dc-dc
converter

A. Interval 1
In interval 1, switches Q1 and Q4 are ON and Q2
and Q3 are OFF. The primary current flows
through Q1, resonant inductor L
R
, transformer
primary and Q4, which is shown in Fig.3.The rate
of change of current ( ) through L
R
depends
on the difference between the input voltage Vin
and the output voltage Vo. During this mode power
flows to the output through rectifier diodes D
R1
and
D
R4
and also energy is stored in L
R
. The resonant
inductor current using initial condition
= 0 is given by




Fig 3.Equivalent circuit for Interval 1

B. Interval 2
During Interval 2 the current through the inductor
L
R
does not reach zero on reaching the instant T2
and the rectifier diodes D
R1
and D
R4
are ON. At the
end of this interval,


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The equivalent circuit for this interval is
as shown in the Fig.4.


Fig 4.Equivalent circuit for Interval 2

C.Interval 3
At T2, Q3 turns ON and Q4 turns OFF. This toggle
time depends on the resonant delay that occurs
prior to Q2 turning ON. When Q3 is ON and Q4
OFF, the inductor current which flows through Q4
finds an alternate path by charging/discharging the
parasitic capacitances of switches Q4 and Q2 until
the body diode of Q2 is forward biased. Switch Q2
can be turned ON with ZVS if the resonant delay is
properly set. At T3 the complete energy stored in
is transmitted to the output and the current
becomes zero and the rectifier diodes D
R1
and D
R4

turn OFF. The resonant inductor current
using initial condition = is given by




Fig 5.Equivalent circuit for Interval 3

D. Interval 4
In interval 4, switches Q2 and Q3 are ON and Q1
and Q4 are OFF. The primary current flows
through Q2, inductor L
R
, transformer primary and
Q3. The rate of increase of the current ( )
through L
R
is proportional to the difference
between the input voltage V
in
and the output
voltage Vo. In this mode power is transferred to the
output through output diodes D
R2
and D
R3
and
moreover energy is stored in L
R
. The equivalent
circuit for this interval is as shown in the Fig.6.


Fig 6.Equivalent circuit for Interval 4

E. Interval 5
During Interval 5 the current through the resonant
inductor does not reach zero and the rectifier
diodes D
R3
and D
R4
are ON. The equivalent circuit
for this mode is shown in Fig.7


Fig 7.Equivalent circuit for Interval 5

F. Interval 6
This interval is the negative equivalent of the
interval 3 as shown in Fig.8.


Fig 8.Equivalent circuit for Interval
III. SIMULATION
A.Simulation Without Power factor Corrector

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The simulink circuit diagram of the system without
PFC is shown in Fig.9
.


Fig.9 Simulink circuit without PFC


B.Simulation With Power factor Corrector


Fig 10 Simulink circuit with PFC
Fig.10 illustrates the simulink circuit diagram of
the system with PFC. The power factor
measurement block is shown in Fig.11





Fig.11.Power factor measurement block


C.Simulation Results


Fig.12 Input voltage and current


Fig.13. Power factor corrector output voltage

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Fig.14 Pulses to the ZVS converter


Fig.15 Voltage Across Transformer Primary Windings



Fig.16 Output DC Voltage across Full Bridge DC-DC
Converter



Fig.17 Input AC Voltage and Current without PFC


VII. CONCLUSIONS

The project presents an electric vehicle battery
charger using an improved ZVS full bridge dcdc
converter with capacitive output filter. The detailed
operating intervals were considered and the
simulation results were examined. The input power
factor with and without PFC has been discussed
and compared. The second stage of the proposed
charger attains soft switching for the full-bridge
primary switches, clamps the voltage across the
output rectifier to the output voltage and the current
through the rectifier diodes has a low ( ),
which helps to reduce reverse recovery losses.

REFERENCES
[1] B. S. Singh, B.N. ; Chandra, A. ; Al-Haddad, K.
; Pandey, A. ; Kothari, D.P. ; , "A review of
single-phase improved power quality AC-DC
converters," Industrial Electronics, IEEE
Transactions on vol. 50, pp. 962 - 981 2003.
[2] J. A. Sabate, V. Vlatkovic, R. B. Ridley, F. C.
Lee, and B. H. Cho, Design considerations for
high-voltage high-power full-bridge zero-
voltageswitched PWM converter, in Proc.
IEEE Appl. Power Electron.Conf. Expo., 1990,
pp. 275284.
[3] Y. Jang and M. M. Jovanovic, A new family
of full-bridge ZVS converters, IEEE Trans.
Power Electron., vol. 19, no. 3, pp. 701708,
May 2004.
[4] A. J. Mason, D. J. Tschirhart, and P. K. Jain,
New ZVS phase shift modulated full-bridge
converter topologies with adaptive energy
storage for SOFC application, IEEE Trans.
Power Electron., vol. 23, no. 1, pp. 332342,
Jan. 2008.
[5] B.-Y. Chen and Y.-S. Lai, Switching control
technique of phase-shift controlled full-bridge
converter to improve efficiency under light-load
and standby conditions without additional
auxiliary components, IEEE Trans. Power
Electron., vol. 25, no. 4, pp. 10011012, Apr.
2010.
[6] G.-B. Koo, G.-W. Moon, and M.-J. Youn,
Analysis and design of phase shift full bridge
converter with series-connected two
transformers, IEEE Trans. Power Electron.,
vol. 12, no. 2, pp. 411419,Mar.2004.
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Methods Enriching Power and Energy Development (MEPED) 2014 39 | P a g e


[7] X.Wu, X. Xie, J. Zhang, R. Zhao, and Z. Qian,
Soft switched full bridge DCDC converter
with reduced circulating loss and filter
requirement,IEEE Trans. Power Electron., vol.
22, no. 5, pp. 19491955, Sep. 2007.
[8] L. Balogh ; R. Redl, "Power-factor correction
with interleaved boost converters in continuous-
inductor-current mode," in IEEE Applied
Power Electronics Conference and
Exposition,1993, pp. 168 174.
[9] M. M. Yungtaek Jang; Jovanovic, "Interleaved
Boost Converter With Intrinsic Voltage-
Doubler Characteristic for Universal- Line PFC
Front End," IEEE Transactions on Power
Electronics, vol. 22, pp. 1394 1401, July
2007.
ACKNOWLEDGEMENT
With deep gratitude and due regards I whole
heartedly and sincerely acknowledge with thanks
the opportunity provided to me by our respectful
guide ,Mrs. K.E.Lakshmiprabha, Assistant
Professor of the department, for her efforts and
very encouraging and proper guidance for the
completion of the project. I thank my parents for
their benevolence and blessings which stood me in
good stead during the course of the project.

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A Comparative Study on Various Dc-Dc Converter
Configurations for Industrial Drives
D.Kanimozhi
1
, Prof K.Balakrishnan
2
PG Scholar, Karpaga Vinayaga College of Engineering & Technology, Chennai, India
1
Professor , Karpaga Vinayaga College of Engineering & Technology, Chennai, India
2


ABSTRACT
A DC-DC converter consisting of resonant boost
converter followed by an LCL type Series Resonant
Converter (SRC) with isolation transformer and
capacitive output filter can provide ZVS (Zero
Voltage Switching) and hence high efficiency for all
load conditions. The load current in industrial drives
will vary from light load to full load. Usually the
efficiency of the drives will be maximum at full load.
It will be economical if the drive is designed to work
with high efficiency at all load conditions. The LCL
type series resonant converter consists of a bridge
inverter, LC resonant circuit, high frequency isolation
transformer and a diode bridge rectifier. The inverter
is switched to generate alternating current pulses in
primary, which will induce emf in secondary and the
emf is rectified and filtered to get constant dc for the
drive motor. Here another separate closed loop
control is employed by using PID control logic.

Keywords: Dc to Dc converter ,LCL type series
resonant converter ,zero voltage switching

I. INTRODUCTION
Power electronics is the field of electrical engineering
related to the use of emiconductor devices to convert
power from the form available from a source to that
required by a load. The load may be AC or DC, single-
phase or three-phase, and may or may not need isolation
from the power source [1-5]. The power source can be a
DC source or an AC source (single-phase or three-phase
with line frequency of 50 or 60 Hz), an electric battery, a
solar panel, an electric generator or a commercial power
supply [6-8]. A power converter takes the power
provided by the source and converts it to the form
required by the load. The power converter can be an AC-
DC converter, a DC-DC converter, a DC-AC inverter or
an AC-AC converter depending on the application
II COMPARISON OF VARIOUS DC DC
CONVERTER CONFIGURATIONS
1. fixed-frequency LCL SRC with an inductive output
filter
2. fixed frequency phase shifted ZVS PWM full bridge
converter
3. fixed-frequency LCL SRC with an capacitive output
filter
A. Fixed Frequency LCL SRC with an inductive
output filter:
This converter operates in lagging Power factor mode for
a very wide change in load and the supply voltage
variations.Thus facilitates ZVS for all the primary
switches. The peak current through the switches
decreases with load current and is approximately
clamped to the load current

B. Fixed frequency phase shifted ZVS PWM full
bridge converter
This converter has reduced peak current stresses
compared to a resonant converter. The ZVS for the
switches is realized by using the leakage inductance of
the transformer (together with an external inductor) and
the output capacitance of the switch.Although various
improvements have beensuggested for this converter , all
of them use the increased number of components and
suffer from one or another disadvantage (limited ZVS
range or high voltage ringing on the secondary-side
rectifier diodes or loss of duty cycle).
C. Fixed Frequency LCL SRC with capacitive
output filter
The converter operates in lagging powerfactor mode for a
very wide change in load and the supply voltage
variations, thus ensuring ZVS for all the primary
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switches [9-10]. The peak current through the switches
decreases with load currentIn the case of first two
configurations, a snubber circuit is needed across the
output rectifier to clamp the voltage ringing due to diode
junction capacitance with the leakage inductance of the
transformer

III TWO STAGE APPROACH
LCL SRC with capacitive output filter has better
performance compared to other configurations, this
converter cannot alsomaintain ZVS for wide change in
input voltage and requires small Lr , which is very
difficult to realize in practice. Therefore, the proposed
solution is to boost the input voltage and then use the
LCL SRC with capacitive output filter as a second stage.
When this converter is operated with almost fixed input
voltage, duty cycle variation required is the least among
all the three converters. Thus, in this two-stage approach,
a ZVT boost converter generates approximately 100V as
the input (Vbus) to the resonant converter for the
specified input voltage (4060 V) while delivering the
output voltage of Vo =60V. This approach not only
achieves ZVS for all the switches but also simplifies the
design of Lr and Cs resonant components.

IV BLOCK DIAGRAM


The output voltage from the PV panel is given to the
ZVT boost converter.The stepped up voltage is then
given to the LCL series resonant converter.The resonant
tank in the LCL series resonant converter is series with
the load and act as a voltage divider.By changing the
frequency of the input voltage, the impedance of the
resonant tank will change.This impedance will divide the
input voltage with load.At resonant frequency maximum
gain obtained.The stepped up voltage is given to the
capacitive output filter and to the load.
V DC - DC CONVERTER
DC-DC converters are electronic devices used whenever
to change DC electrical power efficiently from one
voltage level to another. They are needed because unlike
AC, DC cannot simply be stepped up or down using a
transformer. In many ways, a DC-DC converter is the DC
equivalent of a transformer.Typical applications of DC
DC converters are where 24V DC from a truck battery
must be stepped down to 12V DC to operate a car radio,
CB transceiver or mobile phone; where 12V DC from a
car battery must be stepped down to 3V DC, to run a
personal CD player; where 5V DC on a personal
computer motherboard must be stepped down to 3V, 2V
or less for one of the latest CPU chips; where the 340V
DC obtained by rectifying 240V AC power must be
stepped down to 5V, 12V and other DC voltages as part
of a PC power supply;
P
in
= P
out
+ P
losses
Where Pin is the power fed into the converter, Pout is the
output power and Plosses is the power wasted inside the
converter.Of course if there is a perfect converter, it
would behave in the same way as a perfect transformer.
There would be no losses, and Pout would be exactly the
same as Pin.then say that:
V
in
. I
in
= V
out
.
Iout
Or by re-arranging, we get:
V
out
/V
in
= I
in
/I
out
In other words, if we step up the voltage we step down
the current, and vice-versa.Of course theres no such
thing as a perfect DC-DC converter, just as there are no
perfect transformers. So we need the concept of
efficiency, where:
Efficiency (%) = P
out
/P
in
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Nowadays some types of converter achieve an efficiency
of over 90%, using the latest components and circuit
techniques. Most others achieve at least 80-85%, which
as you can see compares very well with the efficiency of
most standard AC transformers.

A.DIFFERENT TYPES OF DC - DC
CONVERTERS
There are many different types of DC-DC converter, each
of which tends to be more suitable for some types of
application than for others. For convenience they can be
classified into various groups, however. For example
some converters are only suitable for stepping down the
voltage, while others are only suitable for stepping it up;
a third group can be used for either.Another important
distinction is between converters which offer full
dielectric isolation between their input and output
circuits.
B. NON-ISOLATING CONVERTERS
The non-isolating type of converter is generally used
where the voltage needs to be stepped up or down by a
relatively small ratio (say less than 4:1), and there is no
problem with the output and input having no dielectric
isolation. Examples are 24V/12V voltage reducers,
5V/3V reducers and 1.5V/5V step-up converters.There
are five main types of converter in this non-isolating
group, usually called the buck, boost, buck-boost, and
Cuk and charge-pump converters
C.BOOST (STEP-UP) CONVERTER
The boost converter converts an input voltage to a higher
output voltage. The boost converter is also called a step-
up converter. Boost converters are used in battery
powered devices, where the electronic circuit requires a
higher operating voltage than the battery can supply, e.g.
notebooks, mobile phones and camera-flashes. The
switch S, is turned on and off by a pulse-width-
modulated control voltage Vcont..When switch S is
closed, diode is reversed. Thus output is isolated. The
input supplies energy to the inductor i.e., the voltage
across L is equal to Vin and the current I
L
increases
linearly
When switch S is opened, the current I
L
flows through
the diode and charges the output capacitor C. Thus the
output stage receives energy from the input as well as
from the inductor. Hence the output across the load is
large. The function of the boost converter can also be
described in terms of energy balance. During the on-time
of the switch the inductance is charged with energy and
during the off-time of the switch this energy is
transferred from the inductor through the diode to the
output capacitor. Output voltage is maintained constant
by virtue of large C.
D. LCL Type Series Resonant Converter
There are two types of high frequency resonant
convertors; series resonant and parallel resonant. While a
series resonant convertor has a problem on voltage
regulation, parallel resonant convertors have lower
efficiency due to reduced circulating currents. The main
advantages of resonant convertor operating in the above
resonance (lagging power factor) is that the circuit will
not require lossy snubber and di/dt limiting inductors. A
dc/dc high-frequency link LCL-type series resonant
converter suitable for operation above resonance. Below,
the half bridge version is shown.The LCL resonant
converter will create a smooth sinusoidal wave from the
choppy square wave output from the switching circuit.
The LCL term refers to an arrangement of electrical
inductors and capacitors (wire coils and charged plates)
which filter and define the shape of the signal.
E. HIGH FREQUENCY TRANSFORMER
High-frequency (HF) transformer isolated, HF switching
dc-to- dc converters are suitable for this application due
to their small size, light weight, and reduced cost. To
increase their efficiency and to further increase the
switching frequency while reducing the size, cost, and
electromagnetic interference problems, soft-switching
techniques will be used in this paper. Due to the high
power requirement, an interleaved multi cell
configuration that uses three cells in parallel with each
cell being phase shifted by 120. Each cell shares equal
power and the thermal losses are distributed uniformly
among the cells. Also, the input/output ripple frequency
of three-cell configuration becomes three times the
input/output ripple frequency of each cell. There are three
major types of HF transformer isolated soft switching
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converter configurations possible: 1) voltage fed resonant
converters 2) current fed resonant converters and 3)
fixed-frequency resonant transition zero-voltage
switching (ZVS) pulse width modulation (PWM) bridge
converters.
F. ENERGY EFFICIENCY
Energy consumption can be reduced if energy efficiency
is increased. In the end energy saved is the cheapest
energy. In turn, drive technology can help to improve the
energy efficiency of many production lines, as the energy
for nearly all process of production and materials
transport is provided by electrical drives. Also in the case
of hydraulically and pneumatically operated drives, the
basic energy source is an electric motor that powers the
hydraulic pump or the air compressor. Futher more there
are many ancillary processes in the infrastructure of a
plant that are also equipped with electrical drives.In order
to obtain drives with a high energy efficiency, there are
no quick solutions such as those available when buying a
fridge.
VI SOFT SWITCHING TECHNIQUES
There are two types of resonant soft switching depending
on whether the voltage across switch or the current
through switch is made zero.
A . Zero-Current Switching (ZCS)
A switch that operates with ZCS has an inductor in series
with it and a series blocking diode if the switch is bi-
directional. The switch is turned on with ZCS as the
series inductor slows down the rate of rise of current after
voltage across switch goes to zero. If a negative voltage
from a resonant circuit is made to appear across the
switch-inductor combination, then the current through
switch will naturally reduce to zero and switch is turned
off with ZCS.
B. Zero-Voltage Switching (ZVS)
A switch that operates with ZVS has an anti- parallel
diode and a capacitor across it. If negative current is
forced to flow through the antiparalle1 diode then voltage
across switch reduces to zero and then the switch is
turned on with ZVS. During turn-off the capacitor across
switch reduces the rate of rise of voltage across device as
current reduces to zero ZVS is preferred over ZCS
because with ZVS the parasitic switch capacitance
dissipates its energy into the load. If there were no ZVS
this parasitic capacitance would dissipate as heat in the
switch which lowers the efficiency of the system.In this
project, the converter employs another LC resonant
circuit designed to resonate at switching frequency so
that ZVS condition is achieved during both buck and
boost operating modes.
VII MODES OF OPERATION
A. Mode 1(Between ot0 and ot1)
Periodic switching of the resonant energy tank voltage
between +Vs/2 and Vs/2 generates a square-wave
voltage across the input terminal. Since the output
voltage is assumed to be a constant voltage Vo, the input
voltage to the full-bridge rectifier is Vo when iLr2 (t) is
positive and is Vo when iLr2 (t) is negative.

Fig.6.1 Equivalent circuit of Mode I

In this mode, the power switches are turned on naturally
at zero voltage and at zero current. Therefore, the current
through the active power switch is negative after turning
on and positive before turning off. Although the current
in the switches is turned on at zero voltage and zero
current to eliminate turn-on losses, the switches are
forced to turn off a finite current, thus allowing turn-off
losses exit. Fortunately, small Capacitors can be placed
across the switches to function as snubber in order to
eliminate turn-off losses.
B. Mode 2 (Between ot1 and ot2):
The cycle starts at ot1 when the current iLr1 resonant
tank resonates from negative values to zero. At ot2,
before the half-cycle of resonant current iLr1 oscillation
ends, switch S1 is forced to turn off, forcing the positive
current to flow through bottom freewheeling diode D2.
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Fig6.2 .Equivalent circuit of Mode 2
Figure shows the equivalent circuit. The positive dc input
voltage applied across the resonant tank causes the
resonant current that flows through the power switch to
go quickly to zero.
C. Mode 3 (Between ot3 and ot4)
A turn-off trigger signal is applied to the gate of the
active power switch S1. The inductor current then
naturally commutates from active power switch S1 to
freewheeling diode D2. Mode III begins at ot3, then the
system is considered as unstable. The L indices are
calculated for all the load buses and the maximum of the
L indices gives the proximity to the system to voltage
collapse.

Fig.6.3 Equivalent circuit of Mode 3

When diode D2 is turned on, subsequently producing a
resonant stage between inductors Lr1, Lr2 and capacitor
Cr. Inductors Lr1, Lr2, and capacitor Cr resonate. Before
ot4, trigger signal vgs2 excites active power switch S2.
This time interval ends when iLr1 (t) reaches zero at
ot4. Figure shows the equivalent circuit.

D.Mode 4 (Between ot4 and ot5)
When capacitor voltage iLr2 is positive, rectifier diodes
DR1 and DR2 are turned on with zero-voltage condition
at instant ot4. Figure shows the equivalent circuit.
When inductor current iLr2 changes direction, rectifier
diodes DR1 and DR2 are turned off at instant ot5, and
Mode IV ends.

Fig6.4 .Equivalent circuit of Mode 4

When driving signal Vgs1 again excites active power
switch S1, this mode ends and the operation returns to
mode I in the subsequent cycle. During the positive half-
cycle of the inductor current iLr2, the power is supplied
to the load through bridge rectifier diodes DR1 and DR2.
During the negative half-cycle of the inductor current, the
power is supplied to the load through bridge rectifier
diodes DR3 and DR4.

VIII SIMULATION RESULT
A.GATE PULSES OF S1,S2,S3 AND S4


B.INPUT VOLTAGE AND CURRENT
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C. OUTPUT VOLTAGE AND CURRENT

D. EFFICIENCY


E.INPUT RIPPLE CURRENT

F.OUTPUT RIPPLE CURRENT

IX.CONCLUSIONS
The loaded-resonant converter with a bridge rectifier is
developed for the application of dc-to dc energy con-
version. The circuit structure is simpler and less
expensive than other control mechanisms, which require
many components. The developed topology is
characterized by zero-voltage switching, reduced
switching losses, and increased energy conversion
efficiency. The project is done with the help of
MATLAB software.
REFERENCES
[1] A. P. Bergen, Integration and dynamics of a
renewable regenerative hydrogen fuel cell system,
Ph.D. dissertation, Dept. Mechanical Eng.,
Univ.Victoria, Victoria, BC, Canada, 2008.
[2] D. Shapiro, J. Duffy, M. Kimble, and M. Pien,
Solar-powered regenerative PEM electrolyzer/fuel
cell system, J. Solar Energy, vol. 79,pp. 544550,
2005.
[3] F. Barbir, PEM electrolysis for production of
hydrogen from renewable energy sources, J. Solar
Energy, vol. 78, pp. 661669, 2005.
[4] R. L. Steigerwald, High-frequency resonant
Transistor DC-DC converter,
IEEE Trans. Ind. Electron., vol. 31, no. 2, pp.
181-184 may 1984.
[5] R. L. Steigerwald, A Comparison of half-bridge
resonant converter topologies, IEEE Trans. Power
Electron., vol. 3, no. 2, pp. 174182,Apr. 1988.
[6] J. A. Sabate and F. C. Lee, Off-line application of
the fixed-frequency clamped-mode series resonant
converter, IEEE Trans. Power Electron.,vol. 1, no. 1,
pp. 3947, Jan. 1991.
[7] F. S. Tsai, J. Sabate, and F. C. Lee, Constant-
Frequency zero voltage switched,
clamped-mode parallel-resonant converter, in Proc.
IEEE Int.Telecommun. Energy Conf., 1989, pp. 17.
[8] A. K. S. Bhat, Fixed frequency PWM series-
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Methods Enriching Power and Energy Development (MEPED) 2014 46 | P a g e

Parallel resonant converter,
in Proc. IEEE Ind. Appl. Soc. Annu. Meet.,
1981 vol 1 pp. 11151121.
[9] A. K. S. Bhat, Analysis and design of a fixed-
frequency LCL-type series resonantconverter with
capacitive output filter, IEE Proc.: Circuits,Devices
Syst., vol. 144, no. 2, pp. 97103, Apr. 1997.
[10] A. K. S. Bhat, Analysis and design of LCL-type
resonant converter,IEEE Trans. Ind. Electron., vol.
41, no. 1, pp. 118124, Feb. 1994.

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High Step-Up Single-Stage SCI Dc-Dc Converter Using
Pulse Width Modulation

R. Dhamodharan
1
, B. Paramaeswara Reddy
2
PG Scholar, Karpaga Vinayaga College of Engineering & Technology, Chennai, India
1
Professor , Karpaga Vinayaga College of Engineering & Technology, Chennai, India
2
Dhamodharan5303@gmail.com
1
,Parameswarareddyborra@yahoo.in
2


ABSTRACT
In battery operated vehicles, the battery voltage has
to be stepped up to very high value to drive the
motor. Hence it is planned to build up a mainly
efficient high step up Switched Inductor Capacitor
(SIC) dc-dc converter for such applications. In SIC
converters, an LC-circuit with high quality factor (Q-
factor) is employed to increase the dc input voltage
to required high voltage level. For this, MOSFET
power switch is employed to make and break a high
current pulse through the inductance. When current
is made to flow through inductance, energy is stored
in inductance and when this current is cut the stored
energy in inductance is transferred to capacitance,
which results In a high voltage across capacitor.
Closed loop PID control is also povided to achieve the
desired output voltage.

Keywords: DCDC converter, resonant, single-stage,
switched-capacitor inductor
(SCI).Capacitor,inductor,Mosfet.

I. INTRODUCTION
The basic switched-mode dcdc converters counting
buck ,boost, buckboost, cuk, zeta, and sepic have been
used in various electronic application due to their many
compensation such as simple structure, excellent
performance, high efficiency, easy design, and simple
control circuit. The resonant converters such as single-
ended and bridge type are also very popular in the last
decade [1-4]. And the basic switched-capacitor (SC)
converters also have wide application as their advantages
of nonmagnetic components employed and small size
and high power density [5-8].





Fig1.1 Conventional SC/switched-inductor converter.

II.NEW FAMILY OF SCI CONVERTERS



Fig 2.1(a ) Dual-input step-up converter (b) Single-input step-up
converter. (c) Dual-input step-down converter. (d) Single-input step-
down converter. (e) Inverting step-up converter.
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A family of SCI converters is shown in Fig. 2. Each of
the circuits uses only one active switch Q and a very
small resonant inductor Lr which is working to limit the
current peak caused by capacitor C1 when the switch Q
is turned ON. The two energy storage components C1
and L1 are alternately connected in parallel and series
according to different switching states. shows the dual-
input step-up converter member .The two energy storage
components C1 and L1 are charged in parallel by input
sources V1 and V2 , correspondingly, when switch Q is
turned ON, and discharging in series to output terminal
when Q is turned OFF. When the values of the inductor
L1 and the capacitor C1 both are large practically and the
switching regularity is high enough, the voltage across
the capacitor C1 can be regarded as constant and is equal
to the input voltage level V1 , and the current flowing
though L1 can be also regarded as constant. Based on
voltsecond equilibrium across L1 , the voltage level
association of the output and inputs. can be expressed as
VO = V1 +1(1 d)V2 (1) where d is the duty ratio of the
converter, V1 and V2 are input voltages, and VO is the
output voltage. . 2(b) shows the single-input step-up
converter member. It is actually the special version of the
dual-input step-up converter when its two input terminals
both are connected to the same power source Vin , i.e.,
V1 = V2 = Vin . Its voltage transfer relationship therefore
can be derived from (1) and expressed as VO =2 d (1
d)Vin . (2) Fig. 2(c) shows the dual-input step-down
converter member. Its two energy storage components C1
and L1 are charged in series by the difference levels of
the two input sources V1 and V2 when the switch Q is
turned OFF, and discharge in parallel to output terminal
when Q is turned ON. The situation for the normal
operation of this converter is that the level of V1 is higher
than V2 . Based on the same assumption ]p/ that L1 and
C1 both are large reasonably and the switching frequency
is high enough, the voltage across the capacitor C1 can
be regarded as constant and is the same as the output
voltage level VO . And the voltage level relationship of
the output and inputs can be also derived by using volt
second balance across L1 and then expressed as VO = V1
(1 d)V2 . (3)The single-input step-down converter
member shown in is the special version of the dual-input
step-down converter [see Fig. 2(c)] when its lower level
input terminal V2 is connected together with the output
terminal VO as the new output, i.e., V2 = VO . Its voltage
transfer relationship therefore can be derived from (3)
and expressed as VO =1(2 d)Vin . (4)In addition to
aforementioned members, the new family also includes
an inverting step-up converter member as shown in Fig.
2(e). When switch Q is turned ON, L1 and C1 are
charged in parallel and discharges in series when switch
is turned OFF. Therefore, the voltage across C1 is the
same as input voltage Vin . The voltage transfer
relationship also can be derived using the same method
abovementioned and expressed as VO = 1(1 d)Vin .
(5) However, there is no member in Fig. 2 that can
provide high step-down and inverting step-down output
levels.


Fig 2.2 Block diagram of converter circuit


III Modes of operation
The operation of the proposed converter is as follows:

I State1: Switch S and Diode D1 ON, Diode
D2 OFF (t0-t1)
II State2: Switch S ON Diodes D1 and D2 OFF
(t1-t2)
III State3: Switch S and Diode D1 OFF, Diode D2
ON (t2-t3)


STATE 1

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Fig 3.1 STATE 1

state 1 : Working

When the switch is turned ON, diode D2 is reverse
biased and D1 is forward biased. The resonant inductor
Lr is connected in series with C1 to form a resonant tank.
The input voltage V1 is developed across the resonant
tank that causes the resonant current Ic1 gradually
increases from zero in a sinusoidal manner; C1 begins to
be charged and its voltage increases from its minimum
value.

STATE 2



2 Fig 3.2 STATE

STATE 2 Working

After the resonance stops, both the diodes are overturn
biased and the switch continues to conduct. The inductor
current Il1 continues to rise linearly through the switch.
Since there is no current flowing through C1, its voltage
is maintained at the maximum value.

STATE 3


Fig 3.3 STATE 3

STATE 3 Working

When switch is turned OFF, diode D2 is forward biased
and D1 is reversely biased.
The capacitor C1 , the inductor L1 , and input source V2
are connected in series and discharge the maximum
voltage to output Vo .

IV DETAILED ANALYSIS AND DESIGN
CONSIDERATIONS

There are two inductors employed in each converter
member of the new family, the energy transfer inductor
L1 and the resonant inductor Lr . The function of L1 is to
transfer energy while Lr is just used to limit the current
peak caused by the capacitor C1 when the switch Q is
turned ON. Specifically, when switch Q is turned ON, the
capacitor C1 begins to be charged or to discharge, the
charging or discharging current will soar to a very high
peak at the moment of Q being ON if there are not any
measures to limit it. For this reason, a small inductor Lr
is added and connected in series with C1 to form a
resonant tank with the resonant frequency
fO =1/2LrC1 during the switching ON period. With
the resonant inductor, the charging or discharging current
of C1 gradually increases from zero when switch Q is
turned ON. In order to ensure that the current changes
back to zero before switch Q is turned OFF, the switch
conduction time should be longer than half of a period of
the resonant frequency, i.e.,dTS1(where TS and d are
the switching cycle period and duty ratio, respectively).

A. State Analysis for the Dual-Input Step-Up
Converter
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For all members of the new family of SCI converters,
there are three working states for each of them in one
period of switching cycle. Taking the dual-input step-up
converter member



Fig 4.1 waveform of dual-input step-up converter
VI. SIMULATION RESULTS


Fig. 6.1. Simulink diagram of proposed converter


fig 6.2 Source voltage v1 and v2


Fig 6.3 Source Currents I1 and I2



Fig.6.4 .Control signal waveforms

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Fig.6.5.Output voltage and current waveforms
VII. CONCLUSIONS
A family of single-stage SCI converters with different
voltage gains has been proposed in this paper. The
proposed converters employ two energy transfer
components (one SC and one inductor) and do not use
the cascade method like conventional SC/switched-
inductor converters [9-14]. The energy stored in the two
components both directly come from input power sources
and then directly
been released to
output terminal.
This design can
meet the high
efficiency
requirement
with a simple
structure. A
resonance
method is used
in this paper to
limit the current
peak caused by
the SC. Detailed analysis and design considerations are
also introduced. Compared with traditional switched-
mode converters, the proposed converters can provide
higher or lower voltage gains and the switch stress is
lower. The family includes two dual-input members
which can be used in two power sources applications.
The simulation and experimental results of the converter
members [see Fig. 1(a) and (b)] confirm their
functionality and verify the theoretical analysis
presented. Furthermore, the measured results of
efficiency and voltage under different output power are
compared with conventional converters, which indicate
that the proposed step-up converters 1(a) and (b)] can
meet high efficiency and good voltage regulation. The
other members of the proposed family have also been
simulated and their operations have been confirmed. The
same conclusion can be made to other members of the
proposed family because of similar structure and the
same design philosophy [15]. Of course, there are also
some regrets for the family of converters. For instance,
the output voltage of the single-input step-up converter
member [see Fig. 2(b)] is always higher than twice the
input voltage and is only suitable for high voltage gain
applications. Similar problem is also found in the high
step-down member [see Fig. 3(a)]. In addition, there is no
member in the family that can provide both higher and
lower voltage levels than input voltage under different
duty ratios. However, all these regrets will be the
direction of the further.

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no. 1, pp. 129137, 2010.






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A High Efficiency ZCS-ZVS Buck Converter with
Coupled Inductor

Josna Ann Joseph
1
, S.Bella Rose
2

1
PG Scholar, Karpaga Vinayaga College of Engineering and Technology, Chennai
2
Professor, Karpaga Vinayaga College of Engineering and Technology, Chennai


ABSTRACT
A novel topology for a soft-switching buck dc dc
converter with a coupled inductor is proposed. The
soft-switching buck converter has advantages over
the traditional hard- switching converters. The
most significant advantage is that it offers a lower
switching loss. This converter operates under a
zero-current switching condition at turn on and a
zero-voltage switching condition at turn off. It
presents the circuit configuration with a least
components for realizing soft switching. Because of
soft switching, the proposed converter can attain a
high efficiency under heavy load conditions.
Likewise, a high efficiency is also attained under
light load conditions, which is significantly
different from other soft switching buck converters

Keywords: Buck converter, coupled inductor, soft
switching, zero-current switching (ZCS), zero-
voltage switching (ZVS).
I. INTRODUCTION
Buck converters are step-down DC-DC converters that
are widely being used in different electronic devices
like laptops, cell phones and also electric vehicles to
obtain different level of voltages. These converters are
nothing but, high frequency switching devices
operating on PWM principle. The need for a lighter
and smaller electronic devices propels the need for
reduced size of converters operating at higher load
currents. With all these inadvertent conditions the
switching frequency has jumped from KHz range to
MHz range.
The switching devices are made to turn on and turn off
the entire load current at high di/dt, and also withstand
high voltage stress across them. Due to these two
effects there is an increased power losses in these
converters and reduces the efficiency significantly.
High switching frequency can be used to drop sizes
and weights of converters. Still, if converters work
under hard-switching conditions, switching losses will
rise as switching frequency increases, and the total
efficiencies will collapse. Soft switching technologies
are the best techniques to diminish switching losses,
and improve efficiencies and reliabilities. Thus, the
sizes of heat sinks can be reduced. The total weights
and sizes of converters will also be reduced. There are
many methods to gather soft switching, and the most
common is using extra quasi-resonant circuits. By
adding auxiliary switches, capacitors and inductors,
zero-current-switching (ZCS) conditions or zero-
voltage switching (ZVS) conditions can be simply
achieved in quasi-resonant converters. But, high
current stresses and high voltage stresses for power
switches are also created. It is not favorable to select
the suitable rank of power switches, because there are
additional conduction losses when using higher
voltage power switches. Moreover, in some
converters, auxiliary switches work under hard-
switching conditions. Thus, additional power losses
will be produced. Due to auxiliary switches, the
control technique is more complicated than that of
conventional pulse width modulation converters, and
extra measuring circuits of voltage and current are
desired. Great amount of research is done to develop
soft-switching techniques in dcdc converters. In these
converters, it is desirable to control the output voltage
by pulsewidth modulation (PWM) because of its
simplicity and constant frequency. The switch is
turned off under ZVS condition, due to the small
leakage inductance of the coupled inductors, a small
voltage spike appears across the switch, and then, the
switch voltage rises slowly to its final value. Thus,
actually, the switch is turned off under almost ZVS
condition even though the spike peak is usually much
smaller than the switch maximum voltage [1].
The switching loss mechanisms include the current
and voltage overlap loss during the switching interval
and the capacitance loss during turn on. The diode
reverse recovery also causes an additional conduction
loss and further contributes to the current and voltage
overlap loss. Active or passive soft-switching methods
have been reported to reduce these switching losses.
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Recently, passive soft switching has received renewed
inspection as a better alternative to active methods,
because they do not require an extra switch or
additional control circuitry. The two necessary
components that must be added to the circuit to
achieve passive zero-current turn on and zero-voltage
turn off are a small inductor and capacitor. The
inductor provides zero-current turn on of the active
switch and limits the recovery current of the diodes
while the capacitor provides zero-voltage turn off of
the active switch. Traditionally, the Inductor and
capacitor have been placed in series and parallel with
the active switch, respectively. However, many other
locations are possible and can lower the component
count and reduce switch stress.[2]
To create ZC condition for switch turn-on is to have a
snubber inductor in series with the switch or diode.
However, at turnoff, this inductor will cause a voltage
spike on the switch. Therefore, a pulse current source
is required to provide the output current, and, thus, the
switch can be turned off under ZC condition while
preventing the voltage spikes. To reduce the number
of circuit elements, the pulse current source path and
the required snubber inductor to decrease turn-on
losses can be combined for a buck converter. A pulse
voltage source can be applied to the snubber inductor
and create the required pulse current source at switch
turnoff.[3]
The pulsewidth modulation technique is praised for its
high power capability, fast transient response, and
ease of control. The pulsewidth-modulated (PWM)
dcdc converters have also been widely used in
industry. For minimization of size and weight,
increasing switching frequency in the PWM converter
is required. However, increasing switching frequency
will result in more switching losses and
electromagnetic interference (EMI). Recently, for
solving this problem, a number of soft-switching
PWM techniques are available, aimed at combining
required features of both the conventional PWM and
resonant techniques. The zero-voltage-switching
(ZVS) methods are necessary for the majority of
semiconductor devices such as MOSFETs, since the
turn-on loss produced by the output capacitance is
large. The zero-current-switching (ZCS) approaches
are suitable for the minority of carrier semiconductor
devices. [4].
In most soft-switching converters, efficiencies can be
improved significantly under heavy load conditions,
but as in [5] effects are not good under light load
conditions. It is generally because of additional power
dissipations of auxiliary circuit . To solve the low-
efficiency problem at a light load, based on a ZVS
converter, an improved soft-switching buck converter
with coupled inductor is proposed.


Fig. 1. Topology of the proposed ZCSZVS buck converter.


Fig. 2 . The theoretical current waveforms of L
1
, L
2
, and L
3
of the proposed converter


II. PRINCIPLE OF OPERATION

Fig. 1 shows topology of the proposed ZCSZVS
buck converter. In this topology, inductors L
1
and L
2

are coupled [6][7]inductors. S
1
and D
1
are the main
power switches, like a conventional buck converter.
D
2
is an extra diode. The theoretical current
waveforms of L
1
, L
2
, and L
3
of the proposed converter
at steady state are shown in Fig.2. The main switch S1
and the diode D1 are in off condition .The load current
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is freewheeling through the D2. Because L3 is very
small, the current of L3 drops quicker than that of L1,
and also reduces to zero before S1 turns ON. It offers
the ZCS condition for S1. Due to snubber capacitor
Cr1, S1 can turn OFF under a ZVS condition. Cp1 is
the parasitic capacitance of the MOSFET S1.
Associated on the waveforms of the inductor currents,
one switching period is allocated into five intervals, as
shown in Fig.2, Equivalent circuits for each interval
are established. In Fig.2, k
ij
shows a slope of inductor
currents at a different mode, where i denotes the
number of the inductor and j represents the number of
the different operating mode. The detailed theoretical
analyses for each mode will be given as follows.
A. Mode 1 [t0t1]:
At t
0
, S
1
is triggered to conduct. Due to L
3
, i
s1
will
increase slowly, so S
1
can turn ON under a ZCS
condition. Resonance occur between L
3
and C
r1
.Then,
i
3
and i
1
will increase, and i
2
will go down. Since L
3
is
very small, the current-rising level of L
3
is larger than
L
1
. At t
1
, i
3
and i
1
are equal. It means that D
2
turns
OFF automatically, and this mode ends. Fig 3(a)
shows Equivalent Circuit of Mode 1.
B. Mode2 [t1t2 ]
At t1, i
3
and i
1
are identical, and both increase linearly
and i
2
is zero. In this mode, D
2
is always OFF, and the
branch of L
2
does not work. At t
2
, S
1
turns OFF, and
this mode ends. It is similar to a conventional buck
converter. Fig 3(b) shows Equivalent Circuit of Mode
2.
C. Mode 3 [t2t3]
This begins with turn-off of S1, and then a
resonance occurs between inductors (L
1
, L
3
), parasitic
capacitor C
p1
, and snubber capacitors C
r1
. C
p1
is
charged, and C
r1
is discharged at the equal time. When
the voltage across C
r1
diminishes to zero, D
1
will
conduct. Because C
p1
is very small, it can be
neglected. Fig 3(c) shows Equivalent Circuit of Mode
3.

D. Mode 4 [t3t4]:
At t3 D
1
conducts, then D
2
will
conduct.When D1 conducts , voltage across output
inductor changes polarity .Because indutors L1 and L2
are tightly coupled .The voltage Vd2 become
negetive.Then D2 begines to conduct.Fig 3(d) shows
Equivalent Circuit of Mode 4.

E. Mode 5 [t4t5]
In this mode S1 and D1 are OFF, then a small
resonance between L
3
and C
r1
occurs, in which i
3

oscillates around zero and the amplitude is pretty
small, so i
3
is supposed to zero in this mode.As shown
in Fig. 2, the current just flows through L
1
and L
2
, i.e.,
i1 is equal to i
2

(a)


(b)

(c)


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(d)


(e)
Fig. 3. Equivalent circuits for each operation mode
of buck mode. (a) Mode 1, t0 t1 . (b) Mode 2, t1 t2 . (c)
Mode 3, t2 t3 . (d) Mode 4, t3 t4 . (e) Mode 5, t4 t5

A common method of controlling this type of
circuit is pulse width modulation (PWM), which
controls the power switch by applying a voltage signal
to its gate and varying its ON and OFF times. The
ratio of ON time to switching period is the duty cycle.
With pulse-width modulation control, the regulation of
output voltage is achieved by varying the duty cycle of
the switch, keeping the frequency of operation
constant. Duty cycle refers to the ratio of the period
for which the power semiconductor is kept ON to the
cycle period. Idea of coupled inductor to create soft
switching and L1 is the main inductor[8]-[11].
Coupled inductors are used extensively in electrical
applications. Their properties allow for increasing or
decreasing voltage and current, transferring
impedance through a circuit, and they can isolate two
circuits from each other electrically.
When the ideal switches of a dc-dc converter
are implemented using current unidirectional and/or
voltage-unidirectional semiconductor switches, one or
more new modes of operation known as discontinuous
conduction modes (DCM) can occur. The
discontinuous conduction mode arises when the
switching ripple in an inductor current or capacitor
voltage is large to cause the polarity of the applied
switch current or voltage to reverse, the current- or
voltage-unidirectional assumptions made in gathering
the switch with semiconductor devices are violated.
The DCM is commonly witnessed in dc-dc converters
and rectifiers, and can also sometimes happen in
inverters or in other converters containing two-
quadrant switches. The discontinuous conduction
mode typically occurs with large inductor current
ripple in a converter operating at light load and
containing current-unidirectional switches. Since it is
usually required that converters operate with their
loads removed, DCM is frequently encountered.
Indeed, some converters are purposely designed to
operate in DCM for all loads.

III. SIMULATION
A. Simulation Circuit Diagram
The SIMULINK model of the buck converter is
shown in the Fig.4 and PWM generation via
Matlab is shown in figure 6. The design
parameters are listed as follows: input
voltage=24V, output voltage=12V, switching
frequency=20 kHz.



Fig 4 Simulation circuit for the proposed system



Fig 5 PWM generation
B. Simulation Results
Detailed Matlab simulation studies are carried out to
verify the circuit, and to predict the performance of
the converter under various load conditions. Fig.6
shows the buck converter input voltage, figure 7
shows the output voltage and figure 8 shows the
output current of the ZCS-ZVS buck converter. Figure
9 shows the inductor current of the small inductor.
The current of the small inductor is discontinuous. The
inductor ripple current magnitude depend on the
chosen inductor value , input output voltages and
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switching frequency of the converter. The inductor
ripple current does not depend on the load current.
When the output current reduces below the ripple
level , the inductor current can go negative .This
negative current discharges the output capacitor and
causes additional losses.


Fig 6 Input voltage of proposed converter

Fig 7 Output Voltage of Proposed Converter


Fig 8 Output Current of Proposed

Fig 9 Inductor Current (L
3
) of Proposed Converter
CONCLUSION
A soft-switching buck converter with coupled inductor
has been proposed. By making inductor L3 to work
under DCM, ZCS turn on and ZVS turn off for S1 are
achieved. The detailed theoretical studies of the
operating principle at steady state have also given.
Moreover, no auxiliary MOSFET is added in this
topology, so the control method is as simple as that of
a conventional buck converter.
REFERENCES
[1] Reza Amini and Hosein Farzanehfard Novel
Family of PWM Soft-Single-Switched DCDC
Converters With Coupled Inductors IEEE Trans.
on Ind. Electron.,, Vol. 56, No. 6, June 2009
[2] K. Mark Smith and Keyue Ma Smedley
Properties and Synthesis of Passive Lossless
Soft-Switching PWM Converters IEEE Trans.
Power Electron., Vol. 14, No. 5, September 1999
[3] E. Adib and H. Farzanehfard, Family of zero-
current transition PWM converters, IEEE Trans.
Ind. Electron., vol. 55, no. 8, pp. 30553063, Aug.
2008
[4] C.-M. Wang, A new family of zero-current-
switching (ZCS) PWM converters,IEEE Trans.
Ind. Electron., vol. 52, no. 4, pp. 11171125, Aug.
2005.
[5] Y. Zhang and P. C. Sen, A new soft-switching
technique for buck, boost,and buckboost
converters, IEEE Trans. Ind. Appl., vol. 39, no.
6,pp. 17751782, Nov./Dec. 2003
[6] H.-L. Do, Zero-voltage-switching synchronous
buck converter with a coupled inductor, IEEE
Trans. Ind. Electron., vol. 58, no. 8, pp. 3440
3447, Aug. 2011.
[7] W. Li, J. Xiao, J. Wu, J. Liu, and X. He,
Application summarization of coupled inductors
in DC/DC converters, in Proc. 24th Annu. IEEE
Appl.Power Electron. Conf. Expo. , Feb. 1519,
2009, pp. 14871491.
[8] W. Yu, J.-S. Lai, and S.-Y. Park, An improved
zero-voltage switching inverter using two coupled
magnetics in one resonant pole, IEEE Trans.
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Methods Enriching Power and Energy Development (MEPED) 2014 58 | P a g e


Power Electron., vol. 25, no. 4, pp. 952961, Apr.
2010.
[9] Y. Berkovich and B. Axelrod, Switched-coupled
inductor cell for DCDC converters with very
large conversion ratio, IET Power Electron.,vol.
4, no. 3, pp. 309315, Mar. 2011.
[10] M. R. Mohammadi and H. Farzanehfard, New
family of zero-voltagetransition PWM bi-
directional converters with coupled inductors,
IEEE Trans. Ind. Electron., vol. 59, no. 2, pp.
912919, Feb. 2012.
[11] C.-T. Tsai and C.-L. Shen, Interleaved soft-
switching buck converter with coupled inductors,
in Proc. IEEE Int. Conf. Sustain. Energy Technol.,
Nov. 2427, 2008, pp. 877882.

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A Novel Inverter with Virtual DC Bus for Non Linear Load
PV Power System

E.Nirmal kumar
1
S.kamalakkannan
2
PG Scholar, Karpaga Vinayaga College of Engineering & Technology, Chennai, India
1

Associate Professor, Karpaga Vinayaga College of Engineering & Technology, Chennai, India
2


ABSTRACT
The DC/AC inverters are used in grid-coupled
Photovoltaic (PV) energy fabrication systems as
the power meting out interface between the PV
power source and the electric grid. Compared to
the grid-coupled PV inverters that have galvanic
separation (either on the DC, or on the AC
side),the transformer-less PV inverters have the
advantages of lower cost, higher efficiency,
smaller size and lower weight. In the transformer-
less topology, the common-mode (CM) ground
leakage current may emerge on the parasitic
capacitor between the PV panels and the ground.
The transformer-less inverter is anticipated with
virtual DC bus to condense the leakage current
and electromagnetic losses. The PIC
microcontroller generates all control signals which
regulates the output voltage of DC/AC inverter
.Closed loop MPPT control is also provided to
achieve the desired output voltage .

Keywords - Common mode current,
Transformer-less Inverter, Unipolar SPWM
Technique, Virtual DC Bus, photovoltaic.

I. INTRODUCTION
The distributed photovoltaic (PV) power fabrication
systems have received rising attractiveness in both
the commercial and housing areas. In most occasions,
the inverters are used to afford for the PV power into
the utility grid. It is essential for the PV inverter to be
of high efficiency, due to the relatively high price of
the PV panels. Small size is also firmly wanted for
the low-power and single-phase systems especially
when the inverters are installed indoor. In the
conventional grid-connected PV inverters, either a
line frequency or a high frequency transformer is
utilized to provide a galvanic separation between the
grid and the PV panels. Removing the isolation
transformer can be an valuable way out to enhance
the efficiency and condense the size and cost. If the
transformer is not there, the common-mode (CM)
ground leakage current may emerge on the parasitic
capacitor between the PV panels and the ground. The
continued existence of the Common Mode current
may condense the power transfer efficiency, enhance
the grid current distortion, weaken the electric
magnetic compatibility, and more essentially give
rise to the safety threats. The proposed scheme is to
develop an improved transformer-less inverter with
virtual DC bus to eliminate common mode leakage
current for a PV connected power system by using
unipolar sinusoidal pulse width modulation (SPWM).
Other transformerless inverter topologies: (a)
Karschny inverter [8] (b) paralleled-buck inverter [9]
(c) H6 inverter with capacitor voltage divider [10]
II. VIRTUAL DC BUS CONCEPT
The idea of the virtual DC bus is shown in fig 2.1. By
linking the grid neutral line straight to the negative
pole of the PV panel, the voltage across the parasitic
capacitance C
PV
is clamped to zero. This prevents any
leakage current flowing through it.With reference to
the ground point N, the voltage at midpoint B is
either zero or +V
dc
, according to the state of the
switch bridge. The intention of introducing the virtual
DC bus is to create the negative output voltage,
which is essential for the function of the inverter. If a
appropriate technique is used to transmit the energy
between the real bus and the virtual bus, the voltage
across the virtual bus can be kept identical as the real
one. The positive pole of the virtual bus is linked to
the ground point N, so that the voltage at the
midpoint C is either zero or V
dc
. The spotted line in
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the fig 2.1 indicates that this link may be realized
directly by a wire or indirectly by a power switch.
With points B and C coupled jointly by a smart
selecting switch, the voltage at point A can be of
three different voltage levels, specifically +V
dc
, zero,
and V
dc
.Since the Common Mode current is
eliminated as expected by the configuration of the
circuit, there is no restriction on the modulation
scheme, which means that the superior modulation
technology such as the unipolar SPWM can be used
to persuade a variety of PV applications.

Fig.2.1 Virtual dc bus concept
III. DERIVED TOPOLOGY AND
MODULATION SCHEME
From the virtual DC bus idea, a new inverter
topology is derived as a model to show the merit of
the planned methodology, which is shown in Fig. 3.1.
It consists of five power switches S
1
S
5
and only one
single filter inductor L
f
. The PV panels and capacitor
C
1
form the real DC bus though the virtual DC bus is
provided by C
2
.With the switched capacitor
technology, C
2
is charged by the real DC bus through
S
1
and S
3
to maintain a constant voltage. This
topology can be modulated with the unipolar SPWM
.The investigation is introduced as follows.

Fig 3.1Proposed topology
A. UNIPOLAR SPWM
The unipolar SPWM waveform of the planned
inverter is shown in Fig. 3.2. The gate drive signals
for the power MOSFETs are generated according to
the comparative value of the modulation wave u
g

and the carrier wave u
c
. During the positive half
grid cycle, u
g
>0, S
1
and S
3
are turned ON and S
2
is
turned OFF, while S
4
and S
5
commutate
complementally with the carrier frequency. The
capacitors C
1
and C
2
are in parallel and the circuit
rotates between the states 1 and 2 as shown in Fig.
3.1. During the negative half cycle, u
g
<0, S
5
is
turned ON and S
4
is turned OFF. S
1
and S
3

commutate with the carrier frequency synchronously
and S
2
commutates in balance to them. Now the
circuit rotates between the states 3 and 2. At state 3,
S
1
and S
3
are turned OFF while S
2
is turned ON. The
negative voltage is generated by the virtual DC bus
C
2
and the inverter output is at negative voltage
level. At state 2, S
1
and S
3
are turned ON while S
2
is
turned OFF. The inverter output voltage V
an
equals
zero; for the moment, C
2
is charged by the DC bus
through S
1
and S
3
.
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Fig 3.2 Unipolar SPWM for the proposed topology
IV OPERATION STATES OF TRANSFORMER-
LESS INVERTER
The various operation states of different
switches (S1-S5) are tabulated as below and are
illustrated in figs.4.1 to 4.4.
TABLE I Different states
STATES SWITCHES
S1 S2 S3 S4 S5
1 ON OFF ON ON OFF
2 ON OFF ON OFF ON
3 OFF ON OFF OFF ON
4 OFF ON OFF ON OFF
A. STATE I
In the positive half grid cycle, u
g
> 0, S
1
and S
3

are turned on and S
2
is turned off, while S
4
and
S
5
commutate complementally with the carrier
frequency. The capacitors C
1
and C
2
are in
parallel and the circuit rotates between state 1
and state 2
B. STATE II
In the negative half cycle, u
g
< 0,S
5
is turned on
and S
4
is turned off. S
1
and S
3
commutate with
the carrier frequency synchronously and S
2

commutates in complement to them.The circuit
rotates between state 3 and state2.
C. STATE III
At state 3, S
1
and S
3
are turned off while S
2
is
turned on. The voltage across capacitor C
2

generated by the virtual DC bus and the inverter
output voltage are at negative level.
D. STATE IV
At state 4, S
1
and S
3
are turned off while S
2
is
turned on. The inverter output voltage V
an
equals
zero, meanwhile C
2
is charged by the DC bus
through S
1
and S
3
.

Fig 4.1

Fig 4.2
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Fig 4.3

Fig 4.4
Fig 4.1- 4.4 Operation states of transformer less-inverter

V. CURRENT PATH DURING
COMMUTATION
A derived topology main concept is to reduce the
common mode current path. Here the various current
paths of proposed topology during commutation is
shown clearly below. It has four states of operation
during the switching over of one state to other. This
current path has figured out clearly.
.

Fig 5.1 State 2

Fig 5.2 State 3

Fig 5.3 Transition state between 2 and 3
VI. SIMULATION RESULTS
A simulink model of PIC microcontroller based
transformer-less Inverter with virtual DC bus concept
for a non linear load- solar power system is shown in
fig.6.1. Fig 6.2 and fig 6.3 shows the Input, Output
voltage and current waveforms of proposed system
respectively. The output of transformer-less inverter
with virtual DC bus concept is fed to non linear load
arrangement through a well developed
microcontroller based inverter drive system. The
better THD range of proposed topology is shown in
fig 6.4 .The gating signals for MOSFET based
transformerless inverter and firing pulses for the
inverter are shown in fig 6.5. Fig 6.6 and 6.7 shows
the reactive power generation and output voltage
waveform of proposed system.
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Fig 6.1 Simulink model of proposed transformer-less
inverter

Fig.6.2 Input voltage and current waveforms of inverter

Fig.6.3 Output voltage and current waveforms of inverter

Fig 6.4 Total Harmonic Distortion

Fig 6.5 Unipolar SPWM Pulse Generation


Fig 6.6 Simulation waveform for reactive power
generation.

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Fig 6.7 Output voltage waveform of inverter
VII. CONCLUSIONS
The idea of the virtual DC bus is proposed to resolve
the Common Mode Current difficulty for the
transformer-less PV-connected inverter. By linking
the negative pole of the DC bus straight to the grid
neutral line, the voltage on the stray PV capacitors
clamped to zero. This eliminates the Common Mode
current entirely. In the meantime a virtual DC bus is
formed to provide the negative voltage level. The
essential DC voltage is only half of the half bridge
result while the presentation in eliminating the CM
current is superior to the full-bridge-based inverters.
Based on this design, a new inverter topology is
projected with the virtual DC bus concept by
adopting the switched capacitor technology. It
consists of only five power switches and a single
filter inductor. The proposed topology is especially
fitting for the small-power single-phase applications,
where the output current is comparatively small so
that the extra current strain caused by the switched
capacitor does not cause severe stress for the power
devices and capacitors. With outstanding presentation
in eliminating the Common Mode current, the virtual
DC bus concept provides an exceptional key for the
transformer-less PV connected inverters.
REFERENCES
[1] R.W. Erickson and A. P. Rogers, A micro inverter for
building-integrated photovoltaics, in Proc. 24th Annu.
IEEE Appl. Power Electron. Conf. Expos., Feb. 1519,
2009, pp. 911917.
[2] Stefanos Saridakis, Eftichios Koutroulis IEEE Optimal
Design of Modern Transformer less PV Inverter
Topologies Department of Electronic and Computer
Engineering, Technical University of Crete, Chania,
GR-73100.
[3] Tarak Salmi, Mounir Bouzguenda, Adel Gastli and
Ahmed Masmoudi A Novel Transformer less
InverterTopologywithoutZeroCrossingDistortionInter
national journal of renewable energy research Tarak
Salmi et al., Vol.2, No.1, 2012.
[4] Eftichios Koutroulis, Frede Blaabjerg Methods for
the Optimal Design of Grid-Connected PV
InvertersInternationalJournalOf Renewable Energy
Research, IJRER E .Koutroulis, F.Blaabjerg , Vol.1,
No.2, pp.54-64 ,2011.
[5] M. Martino1, C. Citro, K.Rouzbehi, P. Rodriguez
Efficiency Analysis of Single-Phase Photovoltaic
Transformer-less Inverters European Association
fortheDevelopmentofRenewableEnergies,
Environment and Power Quality (EA4EPQ).
[6] Lars E. Norum, Fritz Schimpf Grid connected
Converters for Photovoltaic, State of the Art, Ideas
for Improvement of Transformer less Inverters
NORPIE/2008, Nordic Workshop on Power and
Industrial Electronics, June 9-11, 2008.
[7] Xiaoqiang Guo, Marcelo C. Cavalcanti, Alexandre
M. Farias, and josep M. Guerrero Single-carrier
ModulationforNeutral-Point-Clamped
InvertersinThree-phaseTransformerless
photovoltaic SystemsPowerElectronics for Energy
Conversation and Motor drive of Hebei province ,
Department of
ElectricalEngineering,,YanshanUniversity,Qinhuan
gdao
[8] K. Dietrich, German PatentWechselrichter: DE
19642522 C1, Apr. 1998.
[9] S. V. Araujo, P. Zacharias, and R. Mallwitz,
HighlyefficientsinglephaseTransformerlessinverter
sforgrid-con
nectedphotovoltaicsystems,IEEETrans. Ind.
Electron., vol. 57, no. 9, pp. 31183128, Sep. 2010.
[10] D. Barater, G. Franceschini, and E. Lorenzani,
Unipolar PWM for transformer-less grid-
connected converters in photovoltaic plants, in
Proc. Int.Conf. Clean Electr. Power, Jun. 911,
2009, pp. 387392.
International Journal for Research and Development in Engineering (IJRDE)
www.ijrde.com


Methods Enriching Power and Energy Development


An Efficient Technique
using Quasi-Resonant Boost Half Bridge Converter
S.Revathi
PG Scholar, Karpaga Vinayaga College of
Assistant Professor, Karpaga Vinayaga College of Engineering & Technology, Chennai, India
ABSTRACT
Isolated boost DC-DC converters are finding an
increase in demand in many applications such as
fuel cell, PV systems and hybrid electric vehicles.
The DC-DC converters should possess high
voltage conversion ratio as the output obtained
from a single PV panel or a fuel cell is low.
Isolated boost converter is best suit
step-up due to small input current ripple, low
diode voltage rating and lower transformer ratio.
Quasi-Resonant Boost Half Bridge (BHB)
converter is one of the most suitable candidates
for high-current and high step-up voltage. It
consists of two half bridge converters, a
transformer and an output side rectifier. The two
half bridge circuits convert the input DC voltage
to AC, to which the QR principle is applied so
that switching losses are reduced. The AC voltage
obtained is given to the high
transformer and the output of the transformer is
further given to rectifier and also filtered using
capacitors. External capacitors are additionally
added to the boost half bridge converter to
further reduce the switching losses.
Keywords: Isolated boost DC-DC converters
Quasi-Resonant Boost Half Bridge Converter
high frequency transformer, external capacitors

I. INTRODUCTION
Quasi-Resonant converters, a high efficiency
resonant tank circuit connected around the switch
(transistor or freewheeling diode) employed to shape
the switch current and voltage so that high voltage
are not presented simultaneously. As a result stress
and switching losses in the devices are greatly
reduced. Depending on the high frequency resonant
circuit is connected to the switch; the QRCs can be
either ZCS-QRC or ZVS-QRC.
Quasi resonant Boost Half Bridge (QRBHB)
converter is one of the most suitable candidates for
International Journal for Research and Development in Engineering (IJRDE)
ISSN: 2279-0500 Special Issue
Methods Enriching Power and Energy Development (MEPED) 2014
n Efficient Technique for High Step-Up Application
Resonant Boost Half Bridge Converter

Revathi
1
, Dhivya Assistant Professor
2
Karpaga Vinayaga College of Engineering & Technology, Chennai, India
, Karpaga Vinayaga College of Engineering & Technology, Chennai, India

DC converters are finding an
nd in many applications such as
fuel cell, PV systems and hybrid electric vehicles.
DC converters should possess high
voltage conversion ratio as the output obtained
from a single PV panel or a fuel cell is low.
Isolated boost converter is best suited for high
up due to small input current ripple, low
diode voltage rating and lower transformer ratio.
Resonant Boost Half Bridge (BHB)
converter is one of the most suitable candidates
up voltage. It
wo half bridge converters, a
transformer and an output side rectifier. The two
half bridge circuits convert the input DC voltage
to AC, to which the QR principle is applied so
that switching losses are reduced. The AC voltage
obtained is given to the high frequency
transformer and the output of the transformer is
further given to rectifier and also filtered using
capacitors. External capacitors are additionally
added to the boost half bridge converter to

DC converters,
Bridge Converter,
high frequency transformer, external capacitors.
Resonant converters, a high efficiency
resonant tank circuit connected around the switch
freewheeling diode) employed to shape
the switch current and voltage so that high voltage
are not presented simultaneously. As a result stress
and switching losses in the devices are greatly
reduced. Depending on the high frequency resonant
ected to the switch; the QRCs can be
Quasi resonant Boost Half Bridge (QRBHB)
converter is one of the most suitable candidates for
high-current and high step-up application. In this
project a Quasi-Resonant switching technique fo
Boost Half Bridge (BHB) with active clamping is
introduced by which the turn-off switching loss is
reduced significantly. Half Bridge Boost Converter
is used to obtain high step-up output. Use of two
Half Bridge circuit produces the double boost
output. Efficiency of the converter is improved by
incorporating the soft switching technique of Zero
Voltage Switching with the reduction of turn
losses.
Fig.1. Block diagram of proposed system

II. PROPOSED TOPOLOGY
The proposed QRBHB converter consists
input filter inductors, four MOSFET switches, and
two auxiliary capacitors at the low voltage side. The
topology is basically two high
transformers and one output side rectifiers
employed for isolation, step-up, and rectification
International Journal for Research and Development in Engineering (IJRDE)
e: pp- 065-069
65 | P a g e
Up Application
Resonant Boost Half Bridge Converter
Engineering & Technology, Chennai, India
1

, Karpaga Vinayaga College of Engineering & Technology, Chennai, India
2

up application. In this
Resonant switching technique for a
Boost Half Bridge (BHB) with active clamping is
off switching loss is
reduced significantly. Half Bridge Boost Converter
up output. Use of two
Half Bridge circuit produces the double boost
. Efficiency of the converter is improved by
incorporating the soft switching technique of Zero
Voltage Switching with the reduction of turn off

Fig.1. Block diagram of proposed system
PROPOSED TOPOLOGY
The proposed QRBHB converter consists of two
input filter inductors, four MOSFET switches, and
two auxiliary capacitors at the low voltage side. The
topology is basically two high-frequency
and one output side rectifiers which are
up, and rectification,
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Methods Enriching Power and Energy Development (MEPED) 2014 66 | P a g e


are connected in series so that the diode-voltage
rating becomes half of the output voltage.


Fig.2. Proposed boost half bridge converter

The use of separate clamp capacitors for each phase
helps mitigate, without the need for current sensors,
the current imbalance problem caused by volt
second imbalance between the two inductors.
Furthermore, owing to the capacitor connection at
both sides of the transformer, there must be no dc
offset in the magnetizing current. In the proposed
converter, capacitors Cr1 Cr4 are used to not only
limit transient-surge voltage caused by transformer
leakage inductance, but also resonate with the
resonant inductors Lr1and Lr2 during switch turn-on
process so as to reduce turn-off current. The
resonant frequencies of the tanks Lr1-Cr1and Lr1-
Cr2 are defined, respectively, by

f
r1
=

.
(1)
f
r2
=

.
(2)
Fig.3. shows key waveforms of the proposed
converter to illustrate the operating principle. The
two legs are interleaved with a 180 phase shift, and
the upper and lower switches of each leg are
operated with asymmetrical complementary
switching to regulate the output voltage.


Fig.3. Waveforms of the proposed converter
III. MODES OF OPERATION
1) Mode 1 operation: When applied voltage to the
circuit a current starts flowing the circuit. But the
switches will conduct only when gate pulses are
given. When voltage is given, current iL1 starts
flowing through the path Vi positive, L1, S2 (D),
Cr2, Cr1and negative. When current flows in this
manner the capacitors Cr1 and Cr2 will get charged.
The current from Cr1 is getting divided to S1 and
negative of Vi. The above current path for upper
side of the transformer. Lower side of the
transformer current iL2 is Vi positive, iL2 (Cr3 &
S3), Lr2, transformer primary, Cr3, negative of the
Vi.
Switch S2 and S3 are turned ON at the moment S1
is turned OFF and ends at the moment capacitor
voltage reflected in the secondary, n, vCr, becomes
greater than capacitor voltage vCo1. Each switch
carries both the input-inductor current and the
leakage-inductor current. The voltage across the
leakage inductor of the transformer is a difference
between an auxiliary capacitor voltage (Vcr1 or
Vcr2) and an output-capacitor voltage (Vco1, Vco2,
Vco3, Vco4) referred to the primary.
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2) Mode 2 operation: In the proposed converter
capacitor Cr2 resonates with inductor Lr1. The
current flows from the L1, Lr1 transformer primary,
Cr2, S2, Cr1 and Vi negative. And the primary side
voltage is induced to the transformer secondary and
its rectified, filtered the output voltage in the output
side transformer. Second half bridge current path is
Vi positive, lower side transformer, Lr2, S3,
negative and its Cr3 discharging.
3) Mode 3 operation: During this mode, first half
bridge converter current path is Vi positive, L1, Lr1,
Cr1 and Cr2 discharging through the switch S2, S1
(Cq1) and Vi negative. In second half bridge,
current flows from L2 to Vi through the switch S3.
4) Mode 4 operation: In this mode, the switch S2 is
turned off and S1 is turned on. The capacitor is
discharging though the path Cr1, Lr1, S1 and
negative. Second bridge, the current flow is L2, Lr2,
Cr4, S4, Cr2 and negative. D3 and Co3 rectifier and
filters the output.
5) Mode 5 operation: The S1 is still conducting by
the source current. In bridge II, the current path is
L2, Lr2, S3 and negative.

Fig.4. Circuit diagram of mode 1 operation

Fig.5. Circuit diagram of mode 2 operation

Fig.6. Circuit diagram of mode 3 operation

Fig.7. Circuit diagram of mode 4 operation

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Fig.8. Circuit diagram of mode 5 operation

IV. SIMULATION RESULTS
The proposed Quasi-Resonant Boost Half Bridge
converter is simulated using MATLAB/Simulink
software package. The voltage gain is obtained to be
8. The increase in efficiency is higher than the PWM
current fed isolated converter.
For an input voltage of 20V, at 50 KHz the output
voltage of 145V and the power of 212W are
obtained. Thus a voltage gain of 7.3 is achieved. The
input and output waveforms are shown in Fig. 12 &
Fig 13.

Fig.9. Simulation diagram of proposed system

Fig.10. Input voltage and current waveforms

Fig.11.Output voltage and current waveforms
V. CONCLUSIONS
This work explains a Quasi-Resonant Boost Half
Bridge converter. The proposed converter achieves
ZVS turn ON of switches and ZCS turn OFF of
diodes. The turn OFF current of switches is reduced
by the resonant operation. By adding an external
capacitor across the lower switches the switching
losses can be further reduced. High voltage gain and
efficiency can be obtained. The proposed system
achieves a voltage gain of 7.3 and an efficiency of
58% greater than the converter.

REFERENCES

[1] Pan Xuewei, Student Member, IEEE, and Akshay K.
Rathore, Senior Member, IEEE, Novel Interleaved
Bidirectional Snubber less Soft-Switching Current-Fed
Full-Bridge Voltage Doubler for Fuel-Cell Vehicles
IEEE TRANSACTIONS ON POWER ELECTRONICS,
VOL. 28, NO.12, DECEMBER 2013.

[2]Zhe Zhang, Member, IEEE, Ziwei Ouyang, Student
Member, IEEE, Ole C. Thomsen, Member, IEEE, and
Michael A. E. Andersen, Member, IEEE, Analysis and
Design of a Bidirectional Isolated DCDC Converter for
Fuel Cells and Super capacitors Hybrid System, IEEE
International Journal for Research and Development in Engineering (IJRDE)
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Methods Enriching Power and Energy Development (MEPED) 2014 69 | P a g e



TRANSACTIONS ON POWER ELECTRONICS, VOL.
27, NO. 2, FEBRUARY 2012.

[3] Eung-Ho Kim; Bong-Hwan Kwon; , "Zero-Voltage-
and Zero-Current-Switching Full- Bridge Converter With
Secondary Resonance, Industrial Electronics., IEEE
Transactions on, vol. 57, no. 3, pp. 1017-1025, March
2010.

[4] Tsai-Fu Wu, Senior Member, IEEE, Yung-Chu Chen,
Jeng-Gung Yang, and Chia-Ling Kuo, Isolated
Bidirectional Full-Bridge DCDC Converter With a
Flyback Snubber, IEEE TRANSACTIONS ON POWER
ELECTRONICS, VOL. 25, and NO. 7, JULY 2010.

[5] H. Kim, C. Yoon, and S. Choi, An improved current-
fed ZVS isolated boost converter for fuel cell application,
IEEE Trans. Power Electron., vol. 25, no. 9, pp. 2357
2364, Sep. 2010

[6] J. Kwon and B. Kwon, High step-up active-clamp
converter with input current doubler and output-voltage
doubler for fuel cell power systems, Trans. Power
Electron., vol. 1, no. 1, pp. 108115, Jan. 2009.

[7] S. Han, H. Yoon, G. Moon, M. Youn, Y. Kim, and K.
Lee, A new active clamping zero-voltage switching
PWM current-fed half-bridge converter, Trans. Power
Electron., vol. 20, no. 6, pp. 12711279, Nov.2005.
[8] R. Watson and F. C. Lee, A soft-switched, full-bridge
boost converter employing an active clamp circuit, in
Proc. IEEE Conf. Power Electronics., Spec. Conf., Rec.,
2005, vol. 2,pp. 2005.
[9] S. Y. (Ron) Hui and Henry S. H. Chung , Resonant
and Soft-switching Converters, Department of
Electronic Engineering, City University of Hong K ng,
Tat Chee Avenue, Kowloon,HongKon

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A Novel PWM Technique for Integrated Boost
Resonant Converters

Rose Philip
1
, Prof A.Balamani
2

1
P G scholar EEE Department, Karpaga Vinayaga College of Engineering and Technology,Chennai, India

2
Professor and Head, EEE Department ,Karpaga Vinayaga College of Engineering and Technology,Chennai,
India




ABSTRACT
Effective photovoltaic power conditioning
requires well-organized power conversion and
accurate maximum power point tracking to
neutralize the effects of panel mismatch, shading,
and variation in power output during a daily
cycle.This project presents a unique method for
widening the input range of pulse-width
modulation (PWM) of integrated resonant
converters and it maintains high conversion
efficiency. The technique primarily unites
constant-on, constant off, and fixed-frequency
control depending on the required duty cycle.
With hybrid-frequency control, the circuit also
retains zero current switching for the output
diodes, minimizes switching loss, and eliminates
circulating energy at the transformer across the
entire operating range.

Keywords: PWM, ZVS, Integrated resonant
converter, MPPT, ZCS.

I. INTRODUCTION
Rising prices for traditional fossil fuel sources,
coupled with rapidly falling prices for poly-
crystalline silicon panels, has resulted in an
increased acceptance rate for PV systems. The
voltage obtained is less, so it has to be boosted up to
a high value for various applications. Here
Integrated Boost converter with closed loop control
is focused.
With the most primitive switched-mode power
converters, it became evident that higher frequencies
allow smaller L's and C's and this result in smaller,
lighter, and less costly systems. The down side to
moving to higher frequencies, however, are the
problems of greater vulnerability to parasitic
capacitance and leakage inductance, larger stress in
the switching devices, and increased EMI and RFI.
A typical DC-DC converter is encompasses of
active switches such as MOSFETs or IGBTs,
diodes, magnetic components for example inductors
and transformers, and static devices like capacitors.
Magnetic components are heavier and needs more
volume than any other parts in a power electronic
converter. The size of the magnetic components is
conversely proportional to the switching frequency
of the DC-DC converter. In order to decrease the
volume and weight of converter, higher switching
frequency must be chosen [1].
A resonant mode system proffers the potential of
obtaining the benefits while avoiding many of the
disadvantages of higher frequencies. With a
resonant circuit in the power path, the switches can
be arranged to operate at either zero current or
voltage points in the waveform, greatly reducing
their stress levels; the resonant sine wave minimizes
higher frequency harmonics reducing noise levels;
and since the circuit now needs inductance and
capacitance, parasitic elements may improve rather
than detract from circuit performance. With the
benefits power systems operating in the range of 500
kHz to 2.0 MHz are practical and in fact are already
being produced by a few pioneering
manufacturers[2].

A. Boost Converter
The boost is an acknowledged non-isolated power
stage topology, sometimes called a step-up power
stage. Power supply designers desires the boost
power stage because the needed output is always
more than the input voltage. The input current for a
boost power stage is unremitting, or non-pulsating,
because the output diode conducts simply during a
segment of the switching cycle. The output capacitor
provides the entire load current for the remaining of
the switching cycle.
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A power stage can work in continuous or
discontinuous inductor current mode. In continuous
inductor current mode, current flows continuously in
the inductor during the whole switching cycle in
steady-state operation[3]. In discontinuous inductor
current mode, inductor current is zero for a segment
of the switching cycle. It begins at zero, achieves
peak value, and return to zero through each
switching cycle. It is advantageous for a power stage
to stay in only one mode over its expected operating
conditions because the power stage frequency
response alters significantly between the two modes
of operation.

B. Integrated Boost Resonant Converters
The boost action when integrated into the resonant
converter forms an integrated boost converter.
Allows the resonant action to add four primary
benefits:
1) The output diodes D1 and D2 attain zero current
switching (ZCS);
2) Switching loss in the primary-side MOSFETs is
equal to a standard synchronous boost;
3) The transformer has no circulating energy;
4) The resonant stage gain is fixed and equivalent to
the transformer turns ratio (1:n) [4].

II. OPERATION OF THE PROPOSED
SYSTEM
A. Block Diagram
The block diagram of the proposed system is shown
below. The system is having a closed loop control.
In other words it can be called as feedback control.
Feedback control increases the accuracy and the
robustness of the system. The input to the system is
small DC voltage at around 9v to 12v from solar
panel. In this project the maximum power point of
the solar panel is tracked using Perturb and
Observation technique.

The IBR circuit contains
1. Boost circuit consisting of an inductor
and four MOSFETs
2. Resonant circuit consisting of four
capacitors and leakage inductor[5].

The DC input to full bridge inverter is inverted to
AC and given to the primary of high frequency
transformer, it is then rectified using diode full
bridge and given to the load. The gate pulses to the
MOSFETs are given by the controller circuit, which
in turn is produced based on the difference between
the reference voltage from MPPT and IBRs output
voltage. While designing the hardware an opto-
coupler will be placed in between the controller and
the IBR circuit. This is done in order to isolate the
high voltage power circuit from low voltage
controller part.




Fig. 2.1 Block Diagram of proposed System


B. Circuit Topology

Fig. 2.2 Circuit Topology of proposed System

The circuit can operate in a wide range of duty cycle
which is automatically adjusted and hence switching
period can be changed continuously. Here the width
of the pulses given to the switches are varying
automatically based on the insolation to ensure
maximum power at the output. Both fixed frequency
control and variable frequency control ,based on
feedback is possible. Double bridge IBR circuit is
proposed for further improving the voltage gain.
The circuit has a boost part, which encompasses an
inductor and four switches. The resonant part
includes four capacitors namely C1, C2, C3 and C4
along with the leakage inductor. Because Q1, Q2
and Q3, Q4 are switched complementary to one
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another, the input inductor L operates in the
continuous conduction mode (CCM) and under no
conditions becomes discontinuous. The inductor
current rises linearly during modes 3 and 4, and
decreases linearly during modes 1 and 2. The energy
transfer between the combinations of C1, C2 and
C3, C4 is resonant, occurring only during modes 1
and 3. Though the boost converter is integrated into
the resonant circuit, the two elements are effectively
decoupled as long as the resonant modes are allowed
to fully complete. Thus, the consequent voltage gain
is merely the product of a boost converter voltage
gain and the gain of the resonant stage.

Mode 1


Figure 2.3 Circuit for Mode 1 Operation

Beginning with the turn off of Q3 and Q4 preceding
to t
0
, the current in the input inductor L flows into
the body diode of Q1, discharging its parasitic
capacitance and charging C1 and C2.Therefore Q1
is turned ON under ZVS conditions at t
0
. The upper
input-side capacitor C1 starts resonating with the
transformer leakage inductance L
k
and the output-
side capacitors, C3 and C4, through D1and D2.
Once the transformer current resonates back to zero,
D1 and D2 prevents the continue resonating in the
reverse direction, ending mode 1. The length of
mode 1 is given by

Mode 2
Q1 and Q2 are still active, however it only conduct
the input inductor current. The resonant elements
conduct zero current during this interval. Mode 2
ends with the turn-off of Q1 and Q2 and later the
turn-on of Q3 and Q4.


Figure 2.4 Circuit for Mode 2 Operation

Mode 3


Figure 2.5 Circuit for Mode 3 Operation
After the turn-off of Q1 and Q2, but prior to the
turn-on of Q3 and Q4, the inductor current is still
charging the series combination of C
1
and C
2
,
through the body diode of Q1. When Q3 and Q4 are
turned ON, the body diode of Q1and Q2 are hard
commutated. At t
2
, C2 starts to resonate with L
k
and
the parallel combination of C3 and C4 , through the
diode D2 .Simultaneously, the inductor current rises
linearly through Q2.Once the transformer current
resonates back to zero, D2 blocks the continued
oscillation, marking the end of mode 3.


Mode 4


Figure 2.6 Circuit for Mode 4 Operation

The inductor current continues to flow through the
lower device, increasing until Q3and Q4 turned off
and the circuit returns to mode 1.

III. CLOSED LOOP CONTROL
TECHNIQUE

The input voltage reference is generated by the
maximum-power-point tracking (MPPT) loop,
passing a reference to the input voltage control
loop[6].

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Figure 3.1 Closed loop control technique

The usual output of the digital compensator is
the only required input to the hybrid-frequency
modulator, and the output works normally with a
PWM comparator that requires both a switching
period length and a value for the main switch on-
time [7]. Once the required on-time and the
maximum switching period are determined, each
individual duty ratio corresponds to one switching
period and on-time combination.

IV. SWITCHING PERIOD ANALYSIS
UNDER PROPOSED MODULATION

The converter operates in constant on-time control
for duty ratios less than 50% [8]. The converter



Figure 4.1 Switching Period Analysis Under Proposed
Modulation

operates in constant off-time control for duty ratios
greater than 50%. Thus along the designed operating
range, neither the on-time nor the off-time will
decrease below a specified minimum. The total
switching period, defined as the sum of the on-time
and off-time, reaches a minimum at 50% duty cycle,
reducing the ac flux density in the transformer. For
duty ratios outside the desired operating range, the
converter operates in fixed frequency [9].
TABLE 1

Table showing various T
sw
, T
on
and T
off



V. SIMULATION
A. Simulation Circuit
The figure below shows the simulation circuit of the
entire project showing solar panel [10] connected as
the input to the full bridge IBR circuit. The pulses to
the switches are generated through MATLAB
program[11].



Figure 5.1 Complete Simulation Circuit


A. Simulation Results

The various simulation results are given below. The
simulation result for input voltage from the solar
panel is shown in Fig 5.2.Its value is 11V.The
simulation result for primary side voltage of
transformer is shown in Fig.5.4 with 30V. The
secondary side voltage of transformer is shown in
Fig.5.5 with a value of 194V. The output voltage
across the IBR circuit is shown in the diagram
Fig.5.6.Its value is 193V. The simulation result for
output current of IBR circuit is shown in Fig.5.7,
with a value of 0.0193A. The pulses generated using
MATLAB program for the switches Q1 and Q2 is
shown in Fig.5.8.

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Methods Enriching Power and Energy Development (MEPED) 2014 74 | P a g e




Figure.5.2 Input Voltage from Solar Panel.



Figure.5.4 Primary Voltage of Transformer



Figure.5.5 Secondary Voltage of Transformer



Figure.5.6 Output Voltage of IBR Circuit.




Figure.5.7 Output Current of IBR Circuit

Figure 5.8 Pulses Generated for Q1

Figure 5.8 Pulses Generated for Q2 at various insolations.

VI. CONCLUSIONS

The small DC voltage from Solar Panel is boost up
to a high value using full bridge IBR circuit. Solar
panel is modeled with MPPT technique to ensure
maximum power is been obtained. The algorithm
uses fixed frequency, constant-on, and constant off
techniques depending on the required duty cycle.
Thus at high or low duty cycles, the converter
operates under fixed frequency control to limit the
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maximum switching period and prevent magnetic
saturation. The closed loop control technique
developed thus provides a high voltage gain.

REFERENCES

[1] C.-A. Yeh and Y.-S. Lai,Digital pulse width
modulation technique for a synchronous buck
dc/dc converter to reduce switching
frequency, IEEE Trans. Ind. Electron., vol.
59, no. 1, pp. 550561, Jan. 2012.
[2] R Beiranvand, B.Rashidian,M.R.Zolghadri,
and S.M.H.Alavi, Optimizing the
normalized dead-time and maximum
switching frequency of a wide-adjustable-
range LLC resonant converter, IEEE Trans.
Power Electron., vol. 26, no. 2, pp. 462472,
Feb. 2011.
[3] J.Sun,Small-signal modeling of variable
frequency pulse width modulators,IEEE
Trans. Aerosp. Electron. Syst., vol. 38, no.
3, pp. 11041108, Jul. 2002
[4] C.-E. Kim, G.-W. Moon, and S.-K. Han,
Voltage doubler rectified boost integrated
half bridge (VDRBHB) converter for
digital car audio amplifiers, IEEE Trans.
Power Electron., vol. 22, no. 6, pp. 2321
2330, Nov.2007
[5] Z. Liang, R. Guo, J. Li, and A. Q. Huang,
A high-efficiency PV module integrated
dc/dc converter for PV energy harvest in
FREEDM systems, IEEE Trans. Power
Electron., vol. 26, no. 3, pp. 897909, Mar.
2011.
[6] Simulation & Proposed Hardware
Implementation of MPPT controller for a
Solar PV system. International Journal of
Advanced Electrical and Electronics
Engineering, (IJAEEE)
[7] An Integrated Boost Resonant Converter for
Photovoltaic Applications., IEEE
TRANSACTIONS ON POWER
ELECTRONICS, VOL. 28, NO. 3, MARCH
2013
[8] Mathematical Modeling of Photovoltaic
module and simulation.
[9] M. H. Todorovic, L. Palma, and P. N. Enjeti,
Design of a wide input range dc-dc
converter with a robust power control scheme
suitable for fuel cell power conversion,
IEEE Trans. Ind. Electron., vol. 55, no. 3, pp.
12471255, Mar. 2008.
[10] X.Wang, F. Tian, and I. Batarseh,
Highefficiency parallel post regulator for
wide range input dc-dc converter, IEEE
Trans. Power Electron., vol. 23, no. 2, pp.
852858, Mar. 2008.
[11] www.mathworks.com.
ACKNOWLEDGEMENT
With profound gratitude and due regards I whole
heartedly and sincerely acknowledge with thanks the
opportunity provided to me by my guide Prof A.
Balamani, Professor and Head, Department of
Electrical and Electronics Engineering, for his
painstaking efforts and very encouraging and proper
guidance without which this project could not have
been completed. I thank our various faculty
members and friends for their timely help and
guidance in one way or other which went a long way
in the completion of this project. The love and
support of family is irreplaceable in both life and
graduate education, I will be failing in duty if I dont
thank my parents for their benevolence and
blessings which stood me in good stead during the
course of the project.


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Energy Efficient Zeta Converter with Coupled
Inductor for PV Applications

S.Subasree
1
, Prof A.Balamani
2
PG Scholar, Karpaga Vinayaga College of Engineering & Technology, Chennai, India
1

Professor and Head, Karpaga Vinayaga College of Engineering & Technology, Chennai, India
2


ABSTRACT
Dual-stage micro-inverters are generally used in
grid-connected photovoltaic (PV) systems. The
high step-up DC/DC converter is essential for the
grid-connected micro-inverter because the input
voltage from a single solar panel is very small. A
DC/DC Zeta converter with coupled inductor
which operates at moderate duty ratios is
proposed. High voltage gain is achieved by
employing high turns ratio to coupled inductor.
The leakage-inductor energy of the coupled
inductor is efficiently recycled to the load by
additional capacitors and diodes and thus
efficient energy-conversion is possible. The stress
on the active switch is also restrained. The
proposed Zeta converter with coupled inductor
topology is simulated and the results are
obtained. The voltage conversion ratio of 8 is
obtained for the proposed converter. The
increase in efficiency in terms of power is 58.66%
when compared to the conventional PWM Zeta
converter.

Keywords: Zeta Converter, Coupled Inductor

I. INTRODUCTION
Due to the decrease in worlds fossil fuel energy and
its inability to meet the energy demand in the near
future has lead to the use of renewable energy. As
the worlds photovoltaic (PV) market is growing
rapidly, the role of grid-connected PV systems in
distribution energy systems will become important,
and the PV inverter will also play an irreplaceable
role in this increasing market. The ac module, which
has been proposed to improve these problems, is
called the micro-inverter. Solar micro-inverter is an
inverter integrated to each solar panel module. The
dual-stage micro-inverter combines a high step-up
DC/DC converter and DC/AC inverter. By using
this dual-stage micro-inverter we can achieve
efficiency as high as the conventional PV string-
type inverter. The DC/DC converters used in the
dual-stage micro-inverter of the grid-connected PV
systems require high step-up voltage conversion.



Fig.1. Dual-Stage Micro Inverter

II. CONVENTIONAL PWM ZETA
CONVERTER

The pulse width modulation (PWM) Zeta converter
is a step up/down converter of non- inverting
polarity type and it can be designed to achieve low-
ripple output current with separate inductors
[1]
. Zeta
converter is used in power factor correction and
voltage regulation designs. The conventional Zeta
converter is configured of two inductors, a series
capacitor and a diode
[2]
. The most common
operating modes of these PWM converters are the
continuous inductor current mode (CICM or CCM)
and discontinuous inductor current mode (DICM or
DCM).
A. Continuous Conduction Mode
In CCM mode the switch has two sub-intervals in a
switching period.
Considering,
D
1
- the switch-on duty cycle
D
2
- the diode-on duty cycle
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Fig. 2 Circuit diagram of PWM Zeta Converter

Assuming 100% efficiency, the duty cycle, D
1
, for a
Zeta converter operating in CCM is given by
D
1
= Vo/ (V
i
+ Vo)
where, V
i
and Vo are the input and output voltages
of PWM Zeta converter. This can be rewritten to
obtain the output voltage of the converter in CCM
mode,


D
1max
occurs at V
i(min)
and D
1min
occurs at V
i(max)
.
The DC voltage conversion ratio of PWM Zeta
converter with CCM is obtained as,



B .Discontinuous Conduction Mode
In DCM the switching period is divided into three
sub-intervals. The third time interval of operation
cycle is non-zero, not that either inductor current is
discontinuous. The three distinct time intervals are
namely D
1
T
s
, D
2
T
s
and D
3
T
s
with D
1
+ D
2
+ D
3
=
1 for a constant switching frequency. D
3
is the
switch and diode off ratio. The output voltage of the
converter in DCM is


The DC voltage conversion ratio is obtained as



III. COUPLED INDUCTOR
The coupled inductor consists of two
separate inductors wound on the same core; they
typically come in a package with the same length
and width as that of a single inductor of the same
inductance value, only slightly taller. The price of a
coupled inductor is also typically much less than the
price of two single inductors. The windings of the
coupled inductor can be connected in series, in
parallel, or as a transformer. Most of the coupled
inductors have the same number of turns i.e., a 1:1
turns ratio but some newer ones have a higher turns
ratio. The coupling coefficient, K, of coupled
inductors is typically around 0.95, much lower than
a custom transformers coefficient of greater than
0.99
[3]


The leakage inductance of the coupled inductors can
be employed to control the diode current falling rate
and to alleviate the diode reverse-recovery
problem
[4]
. A coupled inductor with a lower-voltage-
rated switch is used for raising the voltage gain
(whether the switch is turned on or turned off)
[5]
.
Moreover, a passive regenerative snubber is utilized
for absorbing the energy of stray inductance so that
the switch duty cycle can be operated under a wide
range, and the related voltage gain is higher than
other coupled-inductor-based converters
[5]
.
By replacing the input inductors of DC/DC
converters with a cell formed by a coupled inductor
and a diode leads to a family of converters with high
voltage ratio
[6]
. The energy accumulated in the
leakage inductance is transferred to the load through
the diode. Thus the stress in the switch is also
significantly reduced
[7]
.

IV. ZETA CONVERTER WITH COUPLED
INDUCTOR

The circuit configuration of the proposed DC to DC
converter is shown in Fig 3. This topology is
basically derived from a conventional Zeta converter
by replacing the input inductor by a coupled
inductor. The turns ratio of the coupled inductor
increases the voltage gain
[8]
and the secondary
winding of the coupled inductor is in series with a
switched capacitor for further increasing the
voltage
[9]
. In Fig 3 S
1
is the floating active switch.
The primary winding N
1
of a coupled inductor is
similar to the input inductor of the conventional
boost converter, except that capacitor C
1
and diode
D
1
recycles the leakage-inductor energy from N
1
.
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The secondary winding N
2
is connected with another
pair of capacitor C
2
and diode D
2
which recycles the
leakage inductor energy from N
2
. Now N
2
, C
2
and
D
2
all three are in series with N
1
. The diode D
3

connects to the output capacitor C
3
and load R.


Fig. 3.Circuit diagram of the proposed system

Certain assumptions are made for the simplification
of the circuit analysis.

1) All components are ideal, except for the
leakage inductance of coupled inductor.
2) The turns ratio n of the coupled inductor winding
is equal to N
2
/N
1
.
3) The ON-state resistance R
DS(ON)
and all parasitic
capacitances of the main switch S
1
are neglected.
The equivalent series resistance (ESR) of the
capacitors C
1
, C2 and C
3
and the parasitic resistance
of coupled-inductor are neglected.
4) The forward voltage drops of the diodes D
1
, D2
and D
3
are also neglected. The capacitors C
1
, C2 and
C
3
are sufficiently large that the voltages across
them are considered to be constant. The various
modes of operation for the proposed converter in
continuous-conduction mode (CCM) are described
as follows.

A. CCM Operation
Mode I [t
0
, t
1
]:
In the transition interval [t
0
, t
1
], switch S
1
and diode
D
2
conducts. The current flow path is shown in
Fig.4. The source voltage V
in
is applied on
magnetizing inductor L
m
and primary leakage
inductor L
k1
; meanwhile, L
m
also releases its energy
to the secondary winding, and also charges capacitor
C
2
along with the decrease in energy. Thus the
charging current i
D2
and i
C2
also decreases. The
secondary leakage inductor current i
Lk2
is declines
according to i
Lm
/n .This mode ends when the
increasing i
Lk1
equals the decreasing i
Lm
at t = t
1
.



Fig.4. Current flow path in Mode I
Mode II [t
1
, t
2
]:
In the interval [t
1
, t
2
], switch S
1
remains ON and
diode D
3
conducts. The source energy V
in
is series
connected with C
1
, C
2
, secondary winding N
2
, and
L
k2
to charge output capacitor C
3
and load R.
Meanwhile, magnetizing inductor L
m
is also
receives energy from V
in
. The current flow path is
shown in Fig.5. The i
Lm
, i
Lk1
, and i
D3
are increasing
because the V
in
is crossing L
k1
, L
m
and primary
winding N
1
. L
m
and L
k1
are storing energy from V
in
;
meanwhile, V
in
is also in series with N
2
of coupled
inductor and capacitors C
1
and C
2
are discharging
their energy to capacitor C
3
and load R, which leads
to increase in i
Lm
, i
Lk1
, i
DS
, and i
D3
. This mode ends
when switch S
1
is turned off at t = t
2
.


Fig.5. Current flow path in Mode II


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Mode III [t
2
, t
3
]:
In the interval [t
2
, t
3
], switch S
1
is turned OFF and
only diodes D
1
and D
3
conducts. The current flow
path is shown in Fig.6. The secondary leakage
inductor L
k2
keeps charging C
3
when switch S
1
is
off. The energy stored in leakage inductor L
k1
flows
through diode D
1
to charge capacitor C
1
instantly
when S
1
turns off. The voltage across S
1
is the
summation of V
in
, V
Lm
, and V
Lk1
. Currents i
Lk1
and
i
Lk2
are rapidly declining, but i
Lm
is increasing
because L
m
is receiving energy from L
k2
. Once
current i
Lk2
drops to zero, this mode ends at t = t
3.



Fig. 6.Current flow path in Mode III
Mode IV [t
3
, t
4
]:
During the transition interval [t
3
, t
4
], the energy
stored in magnetizing inductor L
m
releases
simultaneously to C
1
and C
2
. The current flow path
is shown in Fig 7. Only diodes D
1
and D
2
are
conducting. Currents i
Lk1
and i
D1
are persistently
decreased because leakage energy still flows
through diode D
1
and continues charging capacitor
C
1
. The Lm is delivering its energy through the
coupled inductor and D
2
to charge capacitor C
2
. The
energy stored in capacitors C
3
is constantly
discharged to the load R. Currents i
Lk1
and i
Lm
are
decreasing, but i
D2
is increasing. This mode ends
when current i
Lk1
is zero at t = t
4
.



Fig.7. Current flow path in Mode IV
Mode V [t
4
, t
5
]:
During the interval [t
4
, t
5
], magnetizing inductor L
m

is constantly transferring energy to C
2
. The current
flow path is shown in Fig 8, and only diode D
2
is
conducting. The i
Lm
is decreasing due to the
magnetizing inductor energy flowing continuously
through the coupled inductor to secondary winding
N
2
and D
2
to charge capacitor C
2
. The energy stored
in capacitors C
3
is constantly discharged to the load
R. The voltage across S
1
is the summation of V
in
and
V
Lm
. This mode ends when switch S
1
is turned on at
the the next switching period.

Fig. 8.Current flow path in Mode V


The typical waveform of several major components
during one switching period is shown in Fig. 9.

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Fig. 9. Typical waveforms of the proposed converter at
CCM operation
V. STEADY STATE ANALYSIS OF
PROPOSED CONVERTER IN CCM
For the simplification of the steady-state
analysis, only modes II and IV are considered for
CCM operation, and the leakage inductances at
primary and secondary sides are ignored.
From mode II;
v
Lm
= V
in

v
N2
= nV
in

From mode IV;
v
Lm
= -V
c1

-v
N2
= V
c2


By applying a volt-second balance on the
magnetizing inductor Lm we get,

= 0


= 0

By solving the above two equations the voltages
across C1 and C2 are obtained as

1

The output voltage during mode II is,
V
o
= V
in
+ V
c1
+ V
N2
+V
c2

1


The dc voltage gain M
CCM
can be found as follows:


1
1


Voltage gain (M
CCM
) as a function of duty ratio (D)
by various turns ratio (n) is represented by a graph
and the straightness of the curve accounts for the
correction between turns ratio n and duty ratio (D)
under the voltage gain M
CCM
= 8.


Fig. 10. M
CCM
as a function of D by various turns
ratios, and the turns ratio versus duty ratio under voltage
conversion is 8
VI. SIMULATION RESULTS
The proposed Zeta converter with coupled inductor
turns ratio of n=3, which is basically derived from a
conventional PWM Zeta converter, is simulated
using MATLAB/Simulink software package. The
voltage gain is obtained to be 8. The increase in
efficiency is found to be 58% higher than the
conventional Zeta converter.
For an input voltage of 20V, at 50 KHz the output
voltage of 145V and the power of 212W are
obtained. Thus a voltage gain of 7.3 is achieved. The
input and output waveforms are shown in Fig. 12 &
Fig 13.
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Fig. 11.Simulation Diagram of proposed Zeta converter
with coupled inductor



Fig.12. Input voltage and current waveforms



Fig.13.Output voltage and current waveforms

VII. CONCLUSIONS
This work explains a DC/DC Zeta converter with
coupled inductor for dual-stage micro inverter. The
turns ratio of the coupled inductor increases the
voltage gain and the secondary winding of the
coupled inductor is in series with a switched
capacitor for further increasing the voltage. The
energy of the leakage inductor of the coupled
inductor is recycled to the load by using additional
capacitors and diodes. Thus the voltage stress across
the active switch is restrained and hence low ON-
state resistance is obtained. The proposed system
achieves a voltage gain of 7.3 and an efficiency of
58% greater than the conventional Zeta converter.

REFERENCES

[1] T. F. Wu, S. A. Liang, and Y. M. Chen Design
optimization for asymmetrical ZVS-PWM Zeta
converter, IEEE Trans. Aerosp. Electron. Syst.,
vol.39,no.2,pp.521532,2003.

[2]Elena Niculescu, Dorina Mioara-Purcaru, Marius-
Cristian Niculescu, Ion Purcaru And Marian Maria
A Simplified Steady-State Analysis of the PWM
Zeta Converter Proceedings of the 13th WSEAS
International Conference on Circuits,pp.108-113.

[3]Jeff FalinCoupled inductors broaden DC/DC
converter usage, Analog Applications
Journal,Texas Instruments Incorporated pp. 10-
12,2010.

[4] R. J. Wai and R. Y. Duan, High step-up
converter with coupled inductor, IEEE Trans.
Power Electron., vol. 20, no. 5, pp. 1025
1035,2005.

[5] L. S. Yang, T. J. Liang, H. C. Lee, and J. F.
Chen, Novel high step-up dc-dc converter with
coupled-inductor and voltage-doubler circuits,
IEEE Trans. Ind. Electron., vol. 58, no. 9, pp. 4196
4206,2011.

[6] Qun Zhao and Fred C. Lee High-Efficiency,
High Step-Up DCDC Converters Ieee
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Transactions On Power Electronics, Vol. 18, No.
1,pp.65-73,2003.

[7] B. Axelrod, Y. Berkovich, S. Tapuchi, and A.
Ioinovici, Steep conversion ration Cuk, Zeta, and
sepic converters based on a switched coupled-
inductor cell, in Proc. IEEE Power Electron. Spec.
Conf , pp. 30093014,2008.

[8] J. Falin,(2010) Designing dc/dc converters
based on ZETA topology, Analog Appl,pp.16
21,http://focus.ti.com/lit/an/slyt372/slyt372.pdf

[9] B. Axelrod, Y. Berkovich, and A. Ioinovici,
Switched-capacitor/ switched-inductor structures
for getting transformerless hybrid dc-dc PWM
converters, IEEE Trans. Circuits Syst. I, Reg.
Papers, vol. 55, no. 2, pp. 687696,2008.

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DC- DC Buck Converter for Low Voltage High Current using
Three State Switching Cell

V.Vanitha
1
, Prof K.Balakrishnan
2
PG Scholar, Karpaga Vinayaga College of Engineering & Technology, Chennai, India
1

Professor , Karpaga Vinayaga College of Engineering & Technology, Chennai, India
2


ABSTRACT
This paper presents a pulse width modulation dcdc
non isolated buck converter using three-state
switching cell, organized by two active switches, two
diodes, and two coupled inductors. One part of the
load power is processed by the active switches,
reducing the peak current through the switches to half
of the load current, as higher power levels can be
attained by the propose topology. The size of reactive
elements, i.e., inductors and capacitors, is also
decreased since the ripple frequency of the output
voltage is twice the switching frequency. Due to the
fundamental characteristics of the topology, total
losses are distributed between all semiconductors.
Another advantage of this converter is the
reduced region for discontinuous conduction mode
when compared to the conventional buck converter or,
in other words, the operation range in continuous
conduction mode is increased, as confirmed by the
static gain plot. The theoretical approach is detailed
complete qualitative and qualitative analyses by the
application of the three-state switching cell to the buck
converter operating in non overlapping mode (D
<0.5). Besides, the mathematical analysis and
development of an experimental proto type rated at 1
kW are carried out. The main experimental results are
presented and adequately discussed to clearly identify
its claimed advantages.

Key WordsBuck converter, DcDc converters,
three-state switching cell (3SSC).

I. INTRODUCTION
Pulsewidth modulation (PWM) dcdc converters are
widely employed in numerous applications, e.g., audio
amplifiers [1], uninterruptible power supplies [2],
fuel cell powered systems [3], and fork lift vehicles [4]In
order to dazed such limitation, several soft switching
methods have been introduced in the literature. Soft
switching is theoretical to reduce the overlap between
voltage and current during the commutation, and can be
classified in either active or passive methods, as one
must choose between the above-mentioned snubber
for a given application. Active methods can reduce
the switching losses by using auxiliary switches. As the
power rating increases, it is frequently required to
secondary converters in series or in parallel. By using
interleaving techniques in high current
applications, the currents through the switches become
just portions of the input current [11]. Interleaving
successfully doubles the switching frequency and also
partially cancels the input and output ripples, as the size
of the energy storage inductors and differential-mode
EMI filter in resulting operations can be reduced.
A. Continuous Conduction Mode
In CCM mode the switch has two sub-intervals in a
switching period Considering,
D
1
- the switch-on duty cycle
D
2
- the diode-on duty cycle


Fig 1(a) Buck Converter

D
1
= Vo/ (V
i
+ Vo)
where,
V
i
and Vo are the input and output voltages of buck
converter. This can be rewritten to obtain the output
voltage of the converter in CCM mode,


D
1max
occurs at V
i(min)
and D
1min
occurs at V
i(max)
. The DC
voltage conversion ratio of buck converter with CCM is
obtained as,
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B .Discontinuous Conduction Mode

In DCM the switching period is divided into three sub-
intervals. The third time interval of operation cycle is
non-zero, not that either inductor current is discontinuous.
The three distinct time intervals are namely D
1
T
s
, D
2
T
s

and D
3
T
s
with D
1
+ D
2
+ D
3
= 1 for a constant switching
frequency.D
3
is the switch and diode off ratio. The output
voltage of the converter in DCM is


The DC voltage conversion ratio is obtained as



II. COUPLED INDUCTOR

The coupled inductor consists of two separate inductors
wound on the same core; they typically come in a package
with the same length and width as that of a single inductor
of the same inductance value, only slightly taller. The
price of a coupled inductor is also typically much less
than the price of two single inductors. The windings of
the coupled inductor can be connected in series, in
parallel, or as a transformer. Most of the coupled
inductors have the same number of turns i.e., a 1:1 turns
ratio but some newer ones have a higher turns ratio. The
coupling factor K, of coupled inductors is naturally
around 0.95, much lower than a tradition transformers
coefficient of greater than 0.99
.

The leakage inductance of the coupled inductors can be
working to control the diode current falling rate and to
improve the diode reverse-recovery problem. A coupled
inductor with a lower-voltage-rated switch is used for
floating the voltage gain (whether the switch is turned on
or turned off). Furthermore, a passive regenerative
snubber is employed for absorbing the energy of stray
inductance so that the switch duty cycle can be operated
under a wide range, and the related voltage gain is higher
than other coupled-inductor-based converters.
By replacing the input inductors of DC/DC converters
with a cell designed by a coupled inductor and a diode
leads to a family of converters with high voltage ratio.
The energy stored in the leakage inductance is transferred
to the load through the diode. Thus the stress in the switch
is also significantly reduced.

III. BUCK CONVERTER WITH COUPLED
INDUCTOR

Fig 3. Circuit diagram
The circuit configuration of the proposed DC to
DC converter is shown in Fig 3. This topology is basically
derived from a conventional buck converter by replacing
the input inductor by a coupled inductor. The turns ratio
of the coupled inductor increases the voltage gain and the
secondary winding of the coupled inductor is in series
with a switched capacitor for further increasing the
voltage. In Fig 3 S
1
is the floating active switch. The
primary winding N
1
of a coupled inductor is similar to the
input inductor of the conventional boost converter, except
that capacitor C
1
and diode D
1
recycles the leakage-
inductor energy from N
1
. The secondary winding N
2
is
connected with another pair of capacitor C
2
and diode D
2

which recycles the leakage inductor energy from N
2
. Now
N
2
, C
2
and D
2
all three are in series with N
1
.
In the proposed system, the dc supply can be obtained by
rectifying the standard 250V, 50Hz ac supply. So that the
converter can be directly operated from standard ac
supply. In this converter two power switches are
connected in parallel to primary of high frequency
transformer for large load currents. To achieve large step-
down voltage ratios the power switches are turned ON
and OFF alternatively with a time gap so that there will be
Four switching states.
State1: Switch1 ON, Switch2 OFF
State2: Both Switch OFF
State3: Switch1 OFF, Switch2 ON
State4: Both switch OFF
The desired output voltage is achieved efficiently using
PID closed loop control. The output is measured using R-
Load. The Voltage measurement block measures the
instantaneous voltage between two electric nodes. The
output provides a simulink signal that can be used by
other simulink blocks. The output of the system can be
seen through the scope.
A .MODE 1 OPERATION
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Stage 1 [t0, t1]:
Initially, switch S1 is turned ON, while switch S2 is
turned OFF. The current through the inductor is divided in
two parts. The first part flows through T1 and D2 with
energy being delivered to the load. The second part flows
through T2 and S1. Current sharing is continued since the
number of turns for T1 and T2 is the same.

Fig 3(a) Circuit diagram of mode 1 operation
B. MODE 2 OPERATION
Stage2 [t1, t2]:
Switch S1 is turned OFF, while switch S2 remains OFF.
The voltage across inductor L is inverted. Diode D1 is
forward biased while D2 remains conducting. The energy
stored in L during the previous stage is then transferred to
the load. The current flows through T1T2, according to
the given polarity, what reasons the magnetic flow in the
primaryto be null. The current returns to the source
analogously to the preceding stage. This stage finishes
when S2 is turned ON.
Fig 3(b) Circuit diagram of mode 2 operation


Fig 3(c) diagram of mode 3 operation

C. MODE 3 OPERATION
Stage 3 [t2, t3]:
Due to symmetry of the circuit, this stage is similar to the
first one, although switch S2 is turned ON instead and S1
remains turned OFF. Diode D1 keeps conducting and D2
is reverse biased.
D. MODE 4 OPERATION
Stage 4[t3, t4]: Switch S1 is turned OFF, while switch S2
remains OFF. The voltage across inductor L is inverted.
Diode D1 is forward biased while D2 remains conducting.
The energy stored during the earlier stage is then
transmitted to the load. The current yields to the source
analogously to the previous stage. This stage varnishes
when S2 is turned ON.

Fig 3(d) Circuit diagram of mode 4 operation

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IV.SIMULATION RESULTS

Fig 4(a) Input and output waveform of voltage and current
waveform


Fig 4(b) Efficiency waveform


Fig 4(c) Output waveform 1

fig 4(d) Output waveform 2

The proposed method can be seen as the integration of
the interleaving technique and three SSC. The following
expedient characteristics can be then addressed to the
introduced topology:
1) Reduced dimension, weight, and capacity of
magnetics, which are designed for twice the switching
frequency analogously to the interleaved buck converter.
2) The current stress through each main switch is equal
to half of the total output current, allowing the use of
semiconductors with lower current ratings.
3) Losses are spread among the semiconductors, leading
to better heat distribution and subsequently more efficient
use of the heat sinks.
4) Part of the input power, i.e., 50%, is directly
transferred to the load through the diodes and the coupled
inductors (autotransformers), and not through the main
switches. As a consequence, conduction and switching
losses are reduced. This is the main difference between
the functionality of this approach and that of the
interleaved buck topology.
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5) The use of three SSC permits the parallel connection of
switches and, therefore, inexpensive power devices and
drives can be used.
6) Energy is transferred from the source to the load during
most part of the switching period, which is a distinct
characteristic of the proposed converter, since in other
buck type converters, it only occurs during half of the
switching period. As a consequence, reduction of current
peaks and also conduction losses are expected.
7) The drive circuit of the main switches becomes less
complex because they are connected to the same reference
node, what does not occur in the interleaved buck
converter.

V. CONCLUSION
A dcdc buck converter based on the 3SSC has been
attainable. When the 3SSC is employed the current is
distributed among the semiconductors. Furthermore, only
part of the energy from the input source flows through the
active switches, while the remaining part is directly
transferred to the load without being processed by these
switches, i.e., this energy is delivered to the load through
passive components, such as the diodes and the
transformer windings. Despite the increase in the number
of semiconductors, the current levels on these devices are
reduced, enabling the use of inexpensive switches and
simplified command circuits because the isolated drive is
not required like in the interleaved buck converter. In
front of these characteristics, its use is recommended for
high-power high-current applications where the
traditional approach may be inadequate, while good
current sharing is achieved. In addition, the overall losses
are distributed among all semiconductors ,reducing the
heat sink efforts. The reactive components operate with
twice the switching frequency, with significant
reduction in weight and volume of such components.
Considering the operation in NOM (D <0.5) and the same
ratings, the following characteristics can be addressed
with the3SSC-based converter if compared with the
conventional buck topology:
1) Augmented number of semiconductor elements
2) Operating area in CCM is wider
3) Ripple current through the inductor is reduced, in
addition to the currents through the switches
4) Reactive elements are designed for twice the switching
frequency, causing the required precarious inductance to
be smaller, for example;
5) only 50% of the power is delivered to the load through
the main switches due to the magnetic coupling between
the transformer winding. Besides, an significant
advantage of the proposed converter operating in OM (D
>0.5) is the continuous wildlife of the input current,
which is essentially discontinuous in the conventional
buck converter, what may lead to the use of an input filter
for some applications.

VI.REFERENCES
[1] M. Berkhout and L. Dooper, Class-D audio
amplifiers in mobile applications,IEEE Trans. Circuits
Syst. I, Reg. Papers, vol. 57, no. 5,pp. 9921002, May
2010.
[2] E. K. Sato,M. Kinoshita, Y.Yamamoto, and T.
Amboh, Redundant highdensity
high-efficiency double-conversion uninterruptible power
system,IEEE Trans. Ind. Appl., vol. 46, no. 4, pp. 1525
1533, Jul./Aug. 2010.
[3] S. V. Araujo, R. P. Torrico-Bascope, and G. V.
Torrico-Bascope, Highly efficient high step-up
converter for fuel-cell power processing based onthree-
state commutation cell, IEEE Trans. Ind. Electron., vol.
57, no. 6,pp. 19871997, Jun. 2010.
[4] Z. Amjadi and S. S. Williamson, Power-electronics-
based solutions for plug-in hybrid electric vehicle energy
storage and management systems,IEEE Trans. Ind.
Electron., vol. 57, no. 2, pp. 608616, Feb. 2010.
[5] G. Yao, Y. Shen,W. Li, and X. He, A new soft
switching snubber for the interleaved boost converters,
in Proc. 35th Annu. IEEE Power Electron. Spec. Conf.,
Jun. 2004, pp. 37653769.
[6] I.Matsuura, K. M. Smith, Jr., and K. M. Smedley, A
comparison of active and passive switching methods for
PWMconverters, in Proc. 29th Annu.IEEE Power
Electron. Spec. Conf., May 1998, vol. 1, pp. 94100.
[7] G. Hua and F. C. Lee, Soft-switching techniques in
PWM converters,IEEE Trans. Ind. Electron., vol. 42, no.
6, pp. 595603, Dec. 1995.
[8] K. Fujiwara and H. Nomura, A novel lossless passive
snubber for softswitching
boost-type converters, IEEE Trans. Power Electron.,
vol. 14,no. 6, pp. 10651069, Nov. 1999.
[9] D. S. Oliveira, Jr., C. E. A. Silva, R. P. Torrico-
Bascope, F. L. Tofoli,C. A. Bissochi, Jr., J. B. Vieira, Jr.,
V. J. Farias, and L. C. de Freitas,Analysis, design, and
experimentation of a double forward converter with soft
switching characteristics for all switches, IEEE Trans.
Power Electron., vol. 26, no. 8, pp. 21372148, Aug.
2011.
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[10] J. P. Rodrigues, S. A. Mussa,M. L.Heldwein, and A.
J. Perin, Three-level ZVS active clamping PWM for the
dcdc buck converter, IEEE Trans.Power Electron., vol.
24, no. 10, pp. 22492258, Aug. 2009.
[11] Y. Jang and M. M. Jovanovic, Interleaved boost
converter with intrinsic voltage-doubler characteristic for
universal-line PFC front end, IEEE Trans. Power
Electron., vol. 22, no. 4, pp. 13941401, Jul. 2007.
[12] D. J. Perreault and J. G. Kassakian, Distributed
interleaving of paralleled power converters, IEEE Trans.
Circuits Syst. I, Fundam.Theory Appl., vol. 44, no. 8, pp.
728734, Aug. 1997.
[13] S. V. Araujo, R. P. Torrico- Bascope, and G. V.
Torrico-Bascope, Highly efficient high step-up
converter for fuel-cell power processing based on three-
state commutation cell, IEEE Trans. Ind. Electron., vol.
57, no. 6, pp. 19871997, Jun. 2010.
[14] S. V. Araujo, R. P. Torrico-Bascope, G. V. Torrico-
Bascope, and L. Menezes, Step-up converter with high
voltage gain employing three state switching cell and
voltagemultiplier, in Proc. Power Electron. Spec. Conf.,
2008, pp. 22712277.
[15] R. A. da Camara, C.M. T. Cruz, and R. P. Torrico-
Bascope, Boost based on three-state switching cell for
UPS applications, in Proc. Brazilian Power Electron.
Conf., 2009, pp. 313318.

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A High voltage gain Dc-Dc Boost Converter Integrated with
Voltage Multiplier Module
K.Suganya
1
, M.Purushothaman
2
PG Scholar, Karpaga Vinayaga College of Engineering & Technology, Chennai, India
1

Assistant Professor, Karpaga Vinayaga College of Engineering & Technology, Chennai, India
2



ABSTRACT
A new high step-up converter is projected for a
photovoltaic system. An asymmetrical interleaved
high step-up converter achieves high step up gain
through a voltage multiplier module. The voltage
multiplier module is organised by a conventional boost
converter and coupled inductors. A conventional boost
converter is incorporated to achieve a considerably
higher voltage conversion ratio. This configuration
reduces the current stress through each power switch.
And also constrains the input current ripple, which
decreases the conduction losses of MOSFETs. Since
the energy stored in leakage inductances is recycled to
the output terminal, the efficiency of the system is
improved.
Keywords - Asymmetrical Interleaved Converter,
Coupled Inductor, High step up, PV system, Voltage
multiplier module.

I. INTRODUCTION

Mounting energy shortage has valued the use of
renewable energy systems like PV system. But the energy
obtained from renewable systems is considerably low.
Thus, high step-up dc-dc converters are widely engaged
in many renewable energy applications [7]. Photovoltaic
systems are predicted to play an important role in future
energy creation [12]. These systems convert light energy
into electrical energy, and by using step-up converter they
transfer low voltage into high voltage.


II. CONVENTIONAL ASYMMETRICAL
INTERLEAVED CONVERTER
An asymmetrical interleaved converter is extensively
used for achieving high step-up conversion and for high-
power application [14]. A conventional boost converter
and two coupled inductors are located in the voltage
multiplier module, which is mounted on a boost converter
to form an asymmetrical interleaved structure. Primary
windings of the coupled inductors are engaged to reduce
the input current ripple, and secondary windings of the


coupled inductors are connected in series to lengthen the
voltage gain.

Fig.1. Circuit diagram of proposed system
The proposed converter operates in continuous
conduction mode (CCM). The duty cycles during steady
operation are interleaved with a 180 phase shift and it is
greater than 0.5

III. MODES OF OPERATION

Mode 1 [t0, t1]: At t=t0, The power switches S1 and S2
are turned ON. Now all the diodes are reversed-biased
and the Magnetizing inductors Lm1 and Lm2 as well as
leakage inductors Lk1 and Lk2 are linearly charged by the
input voltage source Vin.

Mode 2 [t1, t2]: At t=t1, the power switch S2 is turned
OFF, therefore the diodes D2 and D4 are turned ON. The
energy stored in the magnetizing inductor Lm2 is
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transferred to the secondary side and it charges the output
filter capacitor C3. The input voltage source, and the
energy stored in magnetizing inductor Lm2, leakage
inductor Lk2, voltage-lift capacitor Cb is discharged to
the output filter capacitor C1 through the diode D2,
thereby extending the voltage on C1 .

Mode 3 [t2, t3]: At t=t2, the diode D2 automatically turns
OFF because the overall energy stored in the leakage
inductor Lk2 is entirely released to the output filter
capacitor C1. The Magnetizing inductor Lm2 transfers
energy to the secondary side and it charges the output
filter capacitor C3 through the diode D4 until t3.

Mode 4 [t3, t4]: At t=t3, the power switch S2 is turned
ON and all the diodes are turned OFF. Now all the diodes
are reversed-biased and the Magnetizing inductors Lm1
and Lm2 as well as leakage inductors Lk1 and Lk2 are
linearly charged by the input voltage source Vin.

Mode 5 [t4, t5]: At t=t4, the power switch S1 is turned
OFF, therefore diodes D1 and D3 are turned ON. Now
the energy stored in the magnetizing inductor Lm1 is
transferred to the secondary side and it charges the output
filter capacitor C2. The input voltage source and the
energy stored in the magnetizing inductor Lm1 is
completely released to the voltage-lift capacitor Cb
through the diode D1, which supplies extra energy to Cb.

Mode 6 [t5, t0]: At t=t5, the diode D1 is automatically
turns OFF because the entire energy stored in the leakage
inductor Lk1 is totally released to voltage-lift capacitor
Cb. Now the magnetizing inductor Lm1 transfers energy
to the secondary side and it charges the output filter
capacitor C2 through the diode D3 until t0.

IV. VOLTAGE GAIN

From the equivalent circuit of the proposed
converter, the first phase converter is considered as a
conventional boost converter. Thus the voltage
derived from VCb can be expressed as,

(1)
When the power switch S1 is switched ON and the
power switch S2 is turned OFF, the voltage VC1 can
be derived from,

+

=

(2)
The energy transformation from the primary side
charges the output filter capacitors C2 and C3. When the
power switch S2 is in turn-on state and the power switch
S1 is in turn-off state, VC2 is equal to the induced voltage
of Ns1 and the induced voltage of Ns. And when the
power switch S1 is in turn-on state and the power switch
S2 is in turn-off state, VC3 is also equal to induced
voltage of Ns1 and the induced voltage of Ns2.
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Fig.2. Modes of operation of the proposed system




Fig.3. Steady Waveform of the Proposed Converter at CCM


As a result, voltages Vc2 and Vc3 can be derived
from,

= .

1 +

(3)


Fig.4. Voltage Gain versus Turns Ratio n and Duty Cycle

The output voltage V
0
can be derived from,

(4)

The voltage gain of the proposed asymmetrical interleaved
converter is expressed as,

(5)
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When the duty cycle is merely 0.6, the voltage gain reaches 10
at a turns ratio n of 1. The voltage gain reaches 30 at a turns
ratio n of 5.


V. SIMULATION CIRCUIT DIAGRAM


Fig.5. Simulation Circuit of the Proposed System


VI. SIMULATION RESULTS



Fig.6.Voltage and Current Waveform of MOSFET S1 And S2


Fig.7. Voltage and Current Waveform of Diodes D1 And D2

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Fig.8. Voltage and Current Waveform of Diodes D3 And D4



Fig.9. Voltage and Current at CCM

Fig.10. Voltage and Current Waveform of Proposed System



Fig.11. Efficiency Waveform of the Proposed System

VII. CONCLUSION

This paper has offered the principles, steady state
analysis, and experimental results for a proposed
asymmetrical interleaved converter. The proposed
converter has been successfully employed in an
efficiently high step-up conversion without an excessive
duty ratio. The interleaved PWM scheme decreases the
currents that pass through each power switch and
constrained the input current ripple. The experimental
results indicate that leakage energy is recycled through
capacitor Cb to the output terminal. The voltage stresses
over the power switches are also restricted. Higher
efficiency is obtained. Thus, the proposed asymmetrical
interleaved converter is suitable for PV systems and other
renewable energy applications which need high step-up
and high-power energy conversion.

REFERENCES
[1] W. Li,W. Li, X. He, D. Xu, and B.Wu, General derivation
law of non isolated high-step-up interleaved converters with
built-in transformer, IEEE Trans. Ind. Electron., vol. 59, no. 3,
pp. 16501661, Mar. 2012.
[2] W. Li and X. He, Review of Nonisolated high-step-up
DC/DC converters in photovoltaic grid-connected
applications, IEEE Trans. Ind. Electron., vol. 58, no. 4, pp.
12391250, Apr. 2011.
[3] R. J. Wai, W. H. Wang, and C. Y. Lin, High-performance
stand-alone photovoltaic generation system, IEEE Trans. Ind.
Electron., vol. 55, no. 1,
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[4] S. K. Changchien, T. J. Liang, J. F. Chen, and L. S. Yang,
Novel high step-up DC-DC converter for fuel cell energy
conversion system, IEEE Trans. Ind. Electron., vol. 57, no. 6,
pp. 20072017, Jun. 2010.
[5] Y. P. Hsieh, J. F. Chen, T. J. Liang, and L. S. Yang, Novel
high step-up dcdc converter with coupled-inductor and
switched-capacitor techniques for a sustainable energy system,
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Dec. 2011.
[6] S. M. Chen, T. J. Liang, L. S. Yang, and J. F. Chen, A
safety enhanced, high step-up dc-dc converter for ac
photovoltaic module application,
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Apr. 2012.
[7] J. T. Bialasiewicz, Renewable energy systems with
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[8] W. Li and X. He, A family of isolated interleaved boost and
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[9] D.Wang, X. He, and J. Shi, Design and analysis of an
interleaved flyback forward boost converter with the current
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[10] W. Li, Y. Zhao, Y. Deng, and X. He, Interleaved
converter with voltage multiplier cell for high step-up and high-
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[11] W. Li, Y. Zhao, J. Wu, and X. He, Interleaved high step-
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[13] C. T. Pan and C. M. Lai, A high-efficiency high step-up
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An Efficient Power Management Technique by Integrating Bi-
Directional Inverter with Buck-Boost Converter
S. Suriya
1
, K.E. Lakshmiprabha
2

1
PG Scholar, Karpaga Vinayaga College of Engineering and Technology, Chennai, Tamilnadu, India
2
Assistant Professor, Karpaga Vinayaga College of Engineering and Technology, Chennai, Tamilnadu, India


ABSTRACT
A single-phase bi-directional inverter with two
buck/boost maximum power point trackers (MPPTs) for
DC distribution applications. In a dc-distribution system,
a bi-directional inverter is essential to control the power
flow between dc bus and ac grid, and to regulate the dc
bus to a certain range of voltages. Since the photovoltaic
(PV) array voltage can vary from 0 to 600 V, especially
with thin-film PV panels, the MPPT topology is formed
with buck and boost converters to operate at the dc-bus
voltage around 120 V, reducing the voltage stress of its
followed inverter. In the proposed system battery back-
up can be employed for PV for better stabilization. The
system can be tested with the help of MATLAB software
using Simulink.

Keywords- Maximum Power Point Trackers (MPPT),
BUCK/BOOST converter, Bi-directional inverter.

I. INTRODUCTION
Power electronics is the field of electrical engineering
related to the use of semiconductor devices to convert power
from the form available from a source to that required by a
load. The load may be AC or DC, single-phase or three-
phase, and may or may not need isolation from the power
source. The power source can be a DC source or an AC
source (single-phase or three-phase with line frequency of
50 or 60 Hz), an electric battery, a solar panel, an electric
generator or a commercial power supply. A power converter
takes the power provided by the source and converts it to the
form required by the load. The power converter can be an
AC-DC converter, a DC-DC converter, a DC-AC inverter or
an AC-AC converter depending on the application. There are
some renewable energy resources that have attracted the
researches over many years [1]-[3] such as photovoltaic,
wind, tidal and geothermal energy. Many transformer less
inverter topologies were proposed [5]-[7] to avoid leakage
ground current running through PV arrays and ground.
Recently a conventional two-stage configuration is usually
adopted in the PV inverter systems [4]. Renewable energy
sources are becoming increasingly important recently with
focus turning towards clean electricity generation. In
particular, photovoltaic (PV) or solar power systems are one
of the most promising and attractive renewable energy
sources due to their low operational and maintenance costs,
pollution free power generation, long life cycles, and noise
free operation. Prior to installation, performance and
efficiency of solar power conditioning systems have to be
evaluated. Moreover, experimental validation and
verification of solar power conditioning systems under a
wide range of different environmental and load conditions
have to be done.
Solar or PV cells are used to directly convert sunlight into dc
power. PV cells exhibit nonlinear output current-voltage
characteristic. This current-voltage curve is characterized
with a unique maximum power point (MPP) and depends on
environmental conditions (solar irradiance, cell temperature,
wind speed, etc) and PV cell fabrication material.
Accordingly, a maximum power point tracking (MPPT)
algorithm is required in solar power conditioning systems in
order to maximize the generated output power.
In addition battery backup is also employed for PV array for
better stabilization. So in this project it is proposed a MPPT
based power management system for parallel connected PV
arrays by integrating buck-boost dc-dc converter with single
phase inverter. Recently a new control strategy of limiting
the dc-link voltage fluctuation was developed [8] for a back-
to-back pulse width modulation converter in a doubly fed
induction generator (DFIG) for wind turbine systems.
For dc-micro grid applications, the grid connection and
rectification has to be fulfilled by the bidirectional inverter
to regulate the dc bus to a certain range of voltages. There is
some wide inductance variation during the operation of the
inverter. This will be normalized by designing controller and
selecting key components to make inverter normal operation.
This approach was proposed by Tsai-Fu Wu [9].
Recently a dc-bus voltage control with a three-phase
bidirectional inverter was proposed [10] which includes one
line-cycle regulation approach (OLCRA) and one-sixth line-
cycle regulation approach (OSLCRA) which take into
account dc-bus capacitance and control dc-bus voltage to
track a linear relationship between the dc-bus voltage and
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inverter inductor current. There is a detailed operation
analysis, controller design, and realization of a high-power
bidirectional quasi-Z-source inverter (BQ-ZSI) for electric
vehicle applications was proposed recently [11]. A dedicated
voltage controller with feed-forward compensation was
designed to reject the disturbance and stabilize the dc-link
voltage during a non-shoot-through state. Recently a hybrid
electric vehicle (HEV) based on a bidirectional z-source
nine-switch inverter [12] was proposed to allow bidirectional
power flow.
A bidirectional buck-boost cascade inverter was proposed by
Honglin Zhou [13]. This proposed inverter has the features
like bidirectional operation with bipolar buck-boost output
voltage, reduced output distortion, reduced size and weight
with only one main energy storage component, decoupled
linear controller design and a good steady-state with
dynamic performance including wide operation range, strong
robustness to load and input voltage variations, fast dynamic
response, and good overload protection.
A circuit configuration, a circuit topological family, a buck-
mode active clamped circuit, and an instantaneous output
voltage feedback control strategy of
combined bidirectional buckboost dcdc chopper-
mode inverter with high-frequency (HF) link (HFL) were
proposed [14] recently. The circuit configuration is
composed of two identical isolated bidirectional buck-boost
dc-dc choppers with the same input and output filters.
The dc capacitors voltage unbalancing is the main technical
drawback of a Diode-Clamped Multilevel Inverter (DCMLI),
with more than three levels. A voltage-balancing circuit
based on buck-boost chopper connected to the dc link of
DCMLI is a reliable and robust solution to this problem. A
recent study was presented [15] with four different schemes
for controlling the chopper circuit to achieve the capacitor
voltages equalisation. These can be broadly categorised as
single-pulse, multi-pulse and hysteresis band current control
schemes.
II. SOLAR POWER
The solar cell is the basic unit of a PV system. An individual
solar cell produces direct current and power typically
between 1 and 2 W, hardly enough to power most
applications. Solar Cell or Photovoltaic (PV) cell is a device
that is made up of semiconductor materials such as silicon,
gallium arsenide and cadmium telluride, etc. that converts
sunlight directly into electricity. The voltage of a solar cell
does not depend strongly on the solar irradiance but depends
primarily on the cell temperature. PV modules can be
designed to operate at different voltages by connecting solar
cells in series. When solar cells absorb sunlight, free
electrons and holes are created at positive/negative junctions.
If the positive and negative junctions of solar cell are
connected to DC electrical equipment, current is delivered to
operate the electrical equipment.
Renewable energy sources are becoming increasingly
important recently with focus turning towards clean
electricity generation. In particular, photovoltaic (PV) or
solar power systems are one of the most promising and
attractive renewable energy sources due to their low
operational and maintenance costs, pollution free power
generation, long life cycles, and noise free operation. Prior
to installation, performance and efficiency of solar power
conditioning systems have to be evaluated. Moreover,
experimental validation and verification of solar power
conditioning systems under a wide range of different
environmental and load conditions have to be done.
Solar or PV cells are used to directly convert sunlight into dc
power. PV cells exhibit nonlinear output current-voltage
characteristic. This current-voltage curve is characterized
with a unique maximum power point (MPP) and depends on
environmental conditions (solar irradiance, cell temperature,
wind speed, etc) and PV cell fabrication material.
Accordingly, a maximum power point tracking (MPPT)
algorithm is required in solar power conditioning systems in
order to maximize the generated output power

III. MPPT ALGORITHM
The nonlinear current-voltage characteristic of PV cells is
characterized with a unique MPP, which is highly dependent
on weather and load conditions. An MPPT algorithm is an
analog or digital based technique allows the PV cell to
operate at the MPP at any given environmental conditions.
MPPT controllers or algorithms are integrated with solar
power conditioning systems to maximize the output power
extracted from PV generator. Various MPPT techniques
have been proposed including, perturbation and observation
(P&O), incremental conductance, fractional open-circuit
voltage, fractional short-circuit current, fuzzy logic
controller, neural network, ripple correlation control, and dc
link capacitor droop control.
The perturbation and observation method is the most
commonly implemented technique among other algorithms
although oscillations around the MPP can occur. In this
technique, the controller adjusts the output voltage of the PV
cell based on its instantaneous output power. The
incremental conductance algorithm uses the slope of the
power-voltage curve of the PV cell to determine the voltage
reference. The derivative of the cell output power with
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respect to the cell output voltage at the MPP is zero. This
method requires more computations relative to the P&O but
may reach the MPP faster.
MPPT or Maximum Power Point Tracking is an algorithm
that included in charge controllers used for extracting
maximum available power from PV module under certain
conditions. The voltage at which PV module can produce
maximum power is called maximum power point (or peak
power voltage).Maximum power varies with solar radiation,
ambient temperature and solar cell temperature. The MPPT
system is shown in Fig. 1

Fig 1: MPPT system

The MPPT is responsible for extracting the maximum
possible power from the photovoltaic and feed it to the load
via the boost converter which steps up the voltage to
required magnitude. The main aim will be to track the
maximum power point of the photovoltaic module so that
the maximum possible power can be extracted from the
photovoltaic module. The incremental conductance
algorithms utilized for MPPT to increase the efficiency of
the system. The MPPT configuration check is shown in Fig.
2.


Fig 2: Flowchart of online MPPT configuration check
IV. P & O METHOD
The MPPT controller tracks the maximum output power of a
PV array based on the perturbation and observation tracking
method. At the beginning, the controller will determine the
operation mode of the proposed MPPT. When the MPPT is
operated in boost mode, inductor current iLm is equal to
output current iPV of the PV array; thus, the output power of
the PV array can be expressed as follows:
PPV boost(n) = vPV(n) iLm(n)

On the other hand, when the proposed MPPT is
operated in buck mode, inductor current iLm is equal to
output current io ; thus, the output power of the PV array can
be expressed as follows:

PPV buck(n) = vdc(n) iLm(n)

With this control algorithm, the controller tracks the peak
power by increasing or decreasing the duty ratio periodically.
In this studied PV inverter system, there is a shared auxiliary
power supply for the MPPTs and the inverter. Because the
switching frequencies of the MPPT (25 kHz) and the
inverter (20 kHz) are different, their switching noises might
affect the accuracy of voltage and current sampling,
especially under high-power condition. To avoid noise
interference, the MPPTs are synchronized with the inverter,
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and the controller will update the duty ratio of the MPPT
power stage every ten line cycles at the zero crossing of the
line voltage. Additionally, since the single-phase PV inverter
system has a twice line-frequency ripple voltage on the dc
bus, this synchronization approach can also eliminate the
ripple voltage effect and determine accurate output power of
the PV arrays. When the output power of the PV arrays can
be determined accurately, the proposed controller can track
the maximum power point precisely.

Fig 3: Functional block diagram of proposed system

Here the solar cell is represented by a block named
Photovoltaic cell. The MPPT and gating signal generator
are shown in a single unit called MPPT with Gating Signal
During boost operation, a LC-circuit with high quality factor
(Q-factor) is employed to amplify the dc input voltage to
required high voltage level. Here, a MOSFET power switch
is employed to make and break a high current pulse through
the inductance. When current is made to flow through
inductance, energy is stored in inductance and when this
current is cut the stored energy in inductance is transferred
to capacitance, which results in a high voltage across
capacitor and this high voltage is filtered and fed to dc-bus.
During buck operation, the high dc voltage is chopped by
using a MOSFET power switch in series with a source and
then the resultant pulsating dc is filtered and fed to dc-bus. A
bidirectional inverter is also interfaced to dc bus which is
used for energy transfer from dc bus to ac grid and vice
versa. When the dc power is excess, the inverter is used to
convert excess dc power to ac power and inject to grid, and
when there is efficiency in dc power the inverter is used to
convert ac power to dc power and supply to dc bus.
Pulse generators are employed to produce switching pulses
and pwm. The Simulation is done with the help of
MATLAB Software using Simulink. The Voltage
Measurement block measures the instantaneous voltage
between two electric nodes .The output provides a Simulink
signal that can be used by other Simulink blocks. The output
of the system can be viewed through the scope.

Fig 4: Circuit Diagram for Proposed System
V. CIRCUIT DISCRIPTION
When the PV voltage is greater than the DC bus output
voltage the MPPT will operate as a buck converter. During
this buck mode M1 is on and the current flow is from M1 to
Lm so the inductor is continuously charging here and the
inductor current will increase. When M1 is turned off then
the inductor will discharge and the current will flow through
the diode D1 and D2. During this buck mode iLm=ipv.
When the PV voltage is lesser than output dc voltage then
MPPT will operate as a boost converter. Now M1 and M2
gets turn ON. Now the current flow is from M1-Lm-M2.So
the inductor Lm continuously gets charging. When M2 gets
off then the inductor Lm will start to discharge and the
current flows through the diode D2.During this boost mode
iLm=Io


Fig 5: Simulation Circuit

I. SIMULATION RESULTS
The Simulation results for this work are shown in the
following fig.
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Fig 6: Output Voltages from Solar Panel 1&2


Fig 7 Output Voltage of Converter 1


Fig 8 Output Voltage of Converter 2

Fig 9: Total Output Voltage of the Converter


Fig 10: AC Output Voltage without Filter


Fig 11: AC Output Voltage with Filter


Fig 12; AC Output Current

VI. CONCLUSION
A single-phase bidirectional inverter with two buck/boost
MPPTs has been designed and implemented. The inverter
controls the power flow between dc bus and ac grid, and
regulates the dc bus to a certain range of voltages. A droop
regulation mechanism according to the inductor current
levels has been proposed to balance the power flow and
accommodate load variation. Integration and operation of
the overall inverter system contributes to dc-distribution
applications significantly. The simulation is done with the
help of MATLAB software.
REFERENCES
[1] J. M. Carrasco, L. G. Franquelo, J. T. Bialasiewicz, E.
Galvan, R. C. P. Guisado, Ma. A. M. Prats, J. I. Leon, and N.
Moreno-Alfonso, Power-electronic systems for the grid
integration of renewable energy sources: a survey, IEEE
Trans. Ind. Electron., vol. 53, no. 4, pp. 10021016, Aug.
2006
[2] L. N. Khanh, J.-J. Seo, T.-S. Kim, and D.-J. Won, Power-
management strategies for a grid-connected PV-FC hybrid
system, IEEE Trans. Power Deliv., vol. 25, no. 3, pp. 1874
1882, Jul. 2010.
[3] Y. K. Tan and S. K. Panda, Optimized wind energy
harvesting system using resistance emulator and active
rectifier for wireless sensor nodes, IEEE Trans. Power
Electron., vol. 26, no. 1, pp. 3850, Jan. 2011
[4] J. Selvaraj and N. A. Rahim, Multilevel inverter for grid-
connected PV system employing digital PI controller, IEEE
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Transactions on Ind. Electron., vol. 56, no. 1, pp. 149158,
January,2009.R. Chen et al., Toward Secure Distributed
Spectrum Sensing in Cognitive Radio Networks, IEEE
Commun. Mag., vol. 46,pp. 5055, Apr. 2008.
[5] J.-M. Shen, H.-L.Jou, and J.-C.Wu, Novel transformer less
grid connected power converter with negative grounding for
photovoltaic generation system, IEEE Transactions on
Power Electron., vol. 27, no. 4, pp. 18181829, April, 2012.
[6] S. V. Araujo, P. Zacharias, and R. Mallwitz, Highly efficient
single-phase transformer less inverters for grid-connected
photovoltaic systems, IEEE Transactions on Ind. Electron.,
vol. 57, no. 9, pp. 31183128, September, 2010.
[7] T. Kerekes, R. Teodorescu, P. Rodriguez, G. Vazquez, and E.
Aldabas, A new high-efficiency single-phase transformer
less PV inverter topology, IEEE Transactions on Ind.
Electron., vol. 58, no. 1, pp. 184191, January, 2011.
[8] J. Yao, H. Li, Y. Liao, and Z. Chen, An improved control
strategy of limiting the dc-link voltage fluctuation for a
doubly fed induction wind generator, IEEE Transactions on
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[9] Tsai-Fu Wu, Kun-Han Sun, Chia-Ling Kuo and Chih-Hao
Chng, Predictive current controlled 5-kW Single-Phase
Bidirectional Inverter with Wide Inductance Variation for
DC-Microgrid Applications, IEEE Transactions on Power
Electronics., vol. 25, no. 12, pp. 3076-3084, October 2010.
[10] Wu. T-F, Chang C-H, Lin L-C and Chang Y-R, DC-Bus
Voltage Control with a Three-Phase Bidirectional Inverter for
DC Distribution Systems, IEEE Transactions on Power
Electronics., vol. 28, no. 4, pp. 1890-1899, October 2012.
[11] Feng Guo, Lixing Fu, Chien-Hui Lin, Cong Li, Woongchul
Choi and Jin Wang, Development of an 85-kW Bidirectional
Quasi-Z-Source Inverter With DC-Link Feed-Forward
Compensation for Electric Vehicle Applications, IEEE
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5488, December 2013.Ftjf
[12] Dehghan S.M, Mohamadian M and Yazdian A, Hybrid
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Switch Inverter, IEEE Transactions on Vehicular
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[13] Honglin Zhou, Shuai Xiao, Geng Yang and Hua Geng,
Modeling and Control for a Bidirectional Buck-Boost
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A Dual-Input DCDC Converter Combining a Boost-Half-
Bridge Cell and a Voltage-Fed Full-Bridge Cell

M.VinothKumar
1
, Dhivya Assistant Professor
2

PG Scholar, Karpaga Vinayaga College of Engineering & Technology, Chennai, India
1

Assistant Professor, Karpaga Vinayaga College of Engineering & Technology, Chennai, India
2



ABSTRACT
This letter presents a new zero-voltage-
switching (ZVS) isolated dcdc converter which
combines a boost half-bridge (BHB) cell and a
full-bridge (FB) cell, so that two different type of
power sources, i.e., both current fed and voltage
fed, can be coupled effectively by the proposed
converter for various applica-tions, such as fuel
cell and supercapacitor hybrid energy system.
By fully using two high- frequency transformers
and a shared leg of switches, number of the
power devices and associated gate driver circuits
can be reduced. With phase-shift control, the
converter can achieve ZVS turn-on of active
switches and zero-current switching (ZCS) turn-
off of diodes. In this letter, derivation, analysis,
and design of the proposed converter are
presented. Finally, a 2550 V input, 300400 V
output prototype with a 600 W nominal power
rating is built up and tested to demonstrate the
effectiveness of the proposed converter topology.

Key Words- Boost half-bridge (BHB), dcdc
converter, dual-input, phase-shift, soft switching
and hybrid.

I. INTRODUCTION

The unregulated dc output voltage, the low
dynamics, and the discontinuity of renewable
energy sources, like solar energy and fuel cell,
generally, it is well known that not only a front-end
dcdc converter as an interface circuit is required,
but also an auxiliary power supply is needed to
compensate or regulate output power seamlessly at
different load conditions [1][3]. Therefore, an
efficient hybrid renew-able power conversion
system has become an interesting topic. In terms of
the applications with a galvanic isolation, various
system configurations have been investigated in the
last decade, and usually they can be divided into
three categories, i.e., direct hybridization, multiple-
stage conversion and multiple-port con-version
[4][9]. With different specifications and
requirements, the adequate converter and/or
configuration can be adopted. This letter proposes a
new step-up isolated dcdc converter with dual-
input ports by combining a current-fed BHB cell
[10], [11] and a voltage-fed FB cell, and the
proposed converter can be used in applications
such as hybrid electric vehicles, photovoltaic power
generation systems, and fuel cell systems [8].
Based on the cir-cuit topology, the derivation
process of the proposed converter is introduced.
The steady-state operating principles and features
are explained so as to demonstrate the merits of the
converter. Design considerations on some critical
parameters are studied. Finally, representative
experimental results from a 600-W proto-type are
provided to validate the proposed concept. The
salient advantages of the proposed converter can be
summarized as follows:

Ability of dual-input connection;
Reduced number of power devices and their
associated gate driver components;
ZVS turn-on of the main switches;
ZCS turn-off of the diodes without reverse
recovery issue.

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Fig.1.Schematic of a dual-input converter with BHB and
FB cells.
II. PROPOSED SOFT-SWITCHED DCDC
CONVERTER
In order to hybridize the two inputs, i.e., V
in1

and V
in2
, a BHB cell can be paralleled with an FB
cell by adopting a mutual low voltage dc bus as
shown in Fig. 1. Because of the similarity of the
pulse width modulation pattern of BHB and FB
cells, the switch legs I and II can be merged as a
common bridge. Hereby, a new topology with full
function but a simpler connection com-pared to
the previous discrete cells is derived and
illustrated in Fig. 2. The proposed converter
consists of a current-fed port and a voltage-fed
port, which provides a larger flexibility in
practical applications with different type of power
sources. Transformers T
1
and T
2
which have the
turn ratios as n
1
: n
2
= 2:1 in this study are
connected in a special way: the dotted termi-nals
of the primary windings are connected in the
conjunction point A, while two secondary
windings are connected in series (it is also
possible to connect them in parallel depending on
different requirements). A voltage doubler circuit
is employed on the secondary side and the voltage
ringing over the diodes can inherently be clamped
by the output capacitor C
3
or C
4
. L
2
is essentially
the sum of the transformer leakage inductance and
an extra inductance. A dc blocking capacitor C
b
is
added in series with the primary winding of T
2
in
order to avoid trans-former saturation caused by
any asymmetrical operation in the FB circuit.


Fig.2.Topology of the proposed hybrid dc-dc converter.

Same as the dual active bridge (DAB) converters
[12], the pro-posed converter can be viewed as a
voltage source v
p
interfaced to another voltage
source v
s
through the energy interfacing element L
2

as shown in Fig. 3. In steady state, the timing
diagram and the key waveforms of the proposed
converter controlled by phase-shift angle between
the switch pairs, S
1
, S
2
and S
3
, S
4
, are presented in
Fig. 4, where V
L
= n
1
V
in1
, V
H
=
1
2
V
o
, and T
s
is
the switching period. In this letter, only the
symmetrical operation condition, i.e., the switching
duty cycle D is 50%, is discussed, so that S
1
and S
2

as well as S
3
and S
4
have the complementary
driving signals that gives V
in2
= 2V
in1
. Accordingly
output voltage and power transferred can only be
regulated by the phase-shift angle of the two
poles of the input bridge. The power factor of the
high frequency ac loop can be evaluated by the
angle which represents the phase delay between
the sec-ondary voltage and current. In order to
avoid high reactive power in the converter, the
regulated phase-shift angle will be limited in the
range: 0 , in the practical applications [13].
Since the output diode rectifier is current driven,
the following constrains must be satisfied: 1) when
i
s
is positive, v
s
must be positive; and 2) when i
s
is
negative, v
s
must be negative, and thereby based on
the waveforms shown in the Fig. 4(a), the operation
principle of the converter can be explained as
follows.
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Fig. 3 Timing diagram and typical waveforms

III. MODES OF OPERATION
During [t
0
, t
2
], as shown in Fig. 5(a), the body
diodes of S
1
and S
4
conduct and v
p
is clamped to a
voltage of 2V
L
until i
s
decreases with a slope (2V
L
+
V
H
)/L
2
to zero at t
2
. At t
0
, S
1
turns ON under ZVS.
During [t
2
, t
3
], when i
s
becomes positive and flows
through D
1
, S
1
and S
4
will conduct and i
s
increases
with a slope (2V
L
V
H
)/L
2
, as shown in Fig. 5(b).
During [t
3
, t
5
], when S
4
turns OFF at t
3
, C
S

3
and
C
S

4
start to resonate with L
2
until V
C S

3
= 0, and
then S
3
can turn ON under ZVS. Current in the
primary side flows through S
1
and D
S

3
that makes
v
p
equal to V
L
, and i
s
decreases with a slope (V
H

V
L
)/L
2
. The equivalent circuit is given in Fig. 5(c).
After t
5
the second half switching cycle starts.
Obviously, the diodes on the secondary side will
always turn OFF under ZCS in the whole operation
range.


IV.DESIGN CONSIDERATIONS
Generally, ZVS can be deduced on the precondition
that the anti parallel diode of switch must conduct
before the switch is triggered. In other words, the
main devices are turned OFF with a positive
current flowing and then the current diverts to the
opposite diode which allows the in-coming
MOSFET to be switched on under zero voltage.
Therefore, ZVS constraints depend on the
magnitude of primary side currents, i.e., (n1 + n2)*,
and , and have the relationships at driving instant

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In fact, the condition for S1, S3, and S4 can be
easily satisfied, so ZVS can achieve over the whole
load range and is independent on the converters
parameters. While to ensure the ZVS turn-on of S2,
the following function of the circuit parameters and
the control variables must be satisfied:

For converters with low input voltage and high
current, turnoff loss of the switches on the low
voltage side is the predominating factor of the
switching loss [2], which cannot be ignored and is
closely related to the stress of switch-off current.
Moreover, during converter design, it is also
necessary to compute the root mean square (rms)
values of the switch current to estimate conduction
loss as for choosing MOSFETs, especially for the
power devices located in the high current path. As
an example, when input voltage is 30 V, Fig. 9
plots the values of transient turn-off current and
rms current of the devices on the primary side as a
function of . It can be seen that the current stress
is not distributed equally and among the switches,
S2 will have to handle highest current stress and
also high conduction loss owing to the BHB
structure [14]. Both the turn-off transient current
and the rms current of S2 are approximately
proportional to the phase-shift angle that means for
same output power, if decreases, switching and
conduction losses of S2 will become less, so as a
result the system efficiency can be improved.
Regarding to this fact as well as the ZVS operation,
an optimal design and trade off between switching
loss and conduction loss may be considered for the
future research.

IV. SIMULATION RESULTS
Fig.5. Simulation diagram of proposed system
Fig.6.Input Current
Fig.7.Input Voltage

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Fig.8.Output Voltage and Current
V. CONCLUSIONS
This project, proposed an improved switching
method for a dual input DC- DC converter
combining a boost half bridge cell and a voltage
fed full bridge cell for high step-up applications.
This circuit structure helps for mitigating without
the need for current sensors and the current
imbalance problems in existing system. The half
bridge and full bridge cells combining DC- DC
converter achieves ZVS turn ON of switches and
ZCS turn OFF of diodes. The new technique of
combining half bridge and full bridge inverters
gives an efficient result. A soft-switched isolated
dcdc converter with the ability of handling two
independent inputs is derived, investigated, and
designed.

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[5] W. Liu, J. Chen, T. Liang, R. Lin, and C. Liu,
Analysis, design, and control of bidirectional cascaded
configuration for a fuel cell hybrid power system, IEEE
Trans. Power Electron., vol. 25, no. 6, pp. 15651575,
Jun. 2010
[6] H. Tao, A. Kotsopoulos, J. L. Duarte, and M. A. M.
Hendrix, Transformer-coupled multiport ZVS
bidirectional DCDC converter with wide input range,
IEEE Trans. Power Electron., vol. 23, no. 2,pp. 771781,
Mar. 2008
[7] H. Krishnaswami and N. Mohan, Three-port series-
resonant DCDC converter to interface renewable energy
sources with bidirectional load 4902 IEEE transactions
on power electronics, vol. 28, no.11, November 2013 and
energy storage ports, IEEE Trans. Power Electron., vol.
24, no. 10, pp. 22892297, Oct. 2009.
[8] Z. Zhang, Z. Ouyang, O. C. Thomsen, and M. A. E.
Andersen, Analysis and design of a bidirectional
isolated dcdc converter for fuel cells and super-
capacitors hybrid system, IEEE Trans. Power Electron.,
vol. 27, no. 2, pp. 848859, Feb. 2012.
[9] Z. Zhang, O. C. Thomsen, M. A. E. Andersen, and H.
R. Nielsen, Dual input isolated full-bridge boost DC-DC
converter based on the distributed transformers, IET
Power Electron., vol. 5, no. 7, pp. 10741083, Aug. 2012
[10] C. Yoon, J. Kim, and S. Choi, Multiphase DC-DC
converters using a boost-half-bridge cell for high-voltage
and high-power applications, IEEE Trans. Power
Electron., vol. 26, no. 2, pp. 381388, Feb. 2011
[11] S. Jiang, D. Cao, Y. Li, and F. Z. Peng, Gird-
connected boost-half-bridge Photo voltaic micro inverter
system using repetitive current control and maximum
power point tracking, IEEE Trans. Power Electron., vol.
27, no. 11, pp. 47114722, Nov. 2012
[12] F. Krismer and J. Kolar, Efficiency-optimized high
current dual active bridge converter for automotive
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Unity-Power-Factor Operation of High Performance Single-
Phase ACDC Soft Switched Converter Based on Boost
Active Clamp Topology

R.Sivakumar
1
, N.Ananthan
2
, J .S. Sathiyanarayanan
3
1,2
PG Students, Arunai College of Engineering, Tiruvannamalai.
3
Professor, Arunai College of Engineering, Tiruvannamalai.


ABSTRACT
In this paper, a single phase acdc converter in
modular approach used for single phase pulse
width modulated active clamped, zero-voltage-
switched boost converter is presented. The active
clamp technique is used for zero-voltage switching
of the main and auxiliary switches. The operating
modes, analysis, and design considerations for the
proposed converter are explained. To evaluate the
performance of the proposed converter, finally
simulation and experimental results for a
prototype converter is presented. The proposed
converter operates at almost unity power factor
with reduced output filter size. The output voltage
is regulated without affecting zero-voltage-
switching, even under unbalanced input voltages.
Also one non linear load is added parallel with the
proposed converter and its performance are
analyzed with and without non linear load.
I. INTRODUCTION
Usage of Power electronic converters is ever
increasing in the processing of electrical energy in
industrial applications such as adjustable speed
drives, SMPS, UPS, etc [1-5]. The converters with
high power factor are increasingly required in
industries. In high-power range, mainly a three phase
system is employed. Most of Power electronics
system which get connected to AC utility mains use
diode rectifiers at the input , the nonlinear nature of
diode rectifiers cause significant line currents
harmonics generations thus they degrade,
Power quality
Increase losses
Failure of some crucial medical equipments
Loss of efficiency and so on.
Therefore, stringent international harmonics standard
are imposed, and hence power factor corrections
circuits are in-corporate in Power electronics system.
Earlier, to reduce rectifier-generated harmonics,
expensive and bulky filter inductors and capacitors
were installed [6-7].The above filters effectively
eliminate only certain harmonics. The active power
line conditioners (APLCs) used for harmonics
reductions are generally hard switched, hence the
components are subjected to high-voltage stresses
which increases further with increase in the switching
frequency. Hard switching results in low efficiency,
large. Electromagnetic interference (EMI).Soft
switching can also be achieved using resonant
converters [8-9]. But it has some of the draw backs,
like Resonant tank circuits are required to be
designed at a much higher KVA/Kw rating. Due to
the above reasons we prefer High performance AC-
DC Soft Switched Converter based on Boost active
clamp topology
A. CIRCUIT DESCRIPTION
Fig.1 shows a simplified circuit diagram of a single-
phase acdc converter. The proposed converter
consists of a small line filter comprising of Lf and Cf
followed by single-phase line rectifier (D1-D4) and a
very small high-frequency bypass capacitor Cin.
Unlike the conventional boost converter, in addition
to the boost inductor Lb and the high-frequency (HF)
rectifier output diode D; the resonant inductor Lr in
series and resonant capacitor Cr in parallel are
connected to the main switch Sm. The auxiliary
switch Sa with series connected clamping capacitor
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Cc is connected between the drain of the Sm and the
cathode of the D. The small capacitor Cn is used as a
high-frequency bypass filter at the output of each
module. Both the switches are driven in a
complementary manner. The single output filter
capacitor Co is used at the output of the proposed
three-phase converter whose size get reduced
drastically owing to the fact that, like the three-phase
active rectifier, the dominant ripple frequency is six
times the input source frequency. By sensing boost
inductor current, output dc and input ac voltages,
gating pulses are generated accordingly using PFC-
PWM IC and fed to Driver IC. Drive IC provides
complementary gate drive pulses with sufficient dead
band. A PCB-mounted miniature current LEM is
used for sensing the boost inductor current. When
boost inductor current exceeds the set limit, drive
pulses are disabled, hence the converter is protected.
Proposed converter uses average current mode
control. In average current mode control, boost
inductor current is continuously monitored and
controlled to follow the reference signal proportional
to ac line voltage. Thus, input current is sinusoidal.
To regulate output voltage, a multiplier circuit
controls the amplitude of the sinusoidal current
reference signal in accordance with the voltage error
signal generated using the output voltage and
rectified input ac voltage. When the load decreases,
the output voltage increases. To maintain constant
load voltage, the control circuit senses the load
voltage and the pulse width are automatically reduced
in the switching cycle and the output voltage is
regulated and maintained almost constant. The
control circuit varies the duty ratio in switching
cycles over the input supply voltage cycle, as the
instantaneous input supply voltage is varying over the
cycle.

Fig.1 The proposed converter
Table:1.1 components of converter
s.no component values
1
MOSFET(Sm,Sa)

IRFP460

2
Boost inductor

1.75mH

3
Resonant inductor

8.624 H

4
Resonant Capacitor

0.47 nF

5
Input capacitor

1 F

6
Output capacitor

1 F

7
Clamping capacitor

1.1F

B. Operating Principle
To simplify the analysis and operating modes of the
circuit, the following assumptions are made.
[1] The semiconductor devices, inductors, and
capacitors are ideal.
[2] The output filter capacitor Co is large enough to
maintain constant output voltage Vo.
[3] The rectified output voltage Vin is constant over
one switching cycle as switching frequency is very
high compared to ac input frequency.
[4] The boost inductor Lb is much larger than Lr and
clamping capacitor Cc is much larger than capacitor
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Fig.2 Key waveforms of the proposed converter.
Mode 1(t0-t1): Fig.3(a) shows the operating state of
the circuit during this interval. The auxiliary switch
Sa is already in an off-state. The body diode of the
main switch Sm starts conducting, and the output
diode D continues conduction. During this mode, the
boost inductor current ilD continues to decrease and
the output diode current ID also starts decreasing.
The negative resonant inductor current I lr continues
to decrease. This mode ends when it decreases to
zero, and the body diode of the main switch Sm
ceases to conduct. To turn-on the main switch Sm
with ZVS, a gate pulse must be applied during this
interval.

Fig.3: mode 1
Mode 2(t1-t2): Fig.3(b) shows the operating state of
the circuit during this interval. At t1, the main switch
Sm turns on and starts carrying the positive resonant
inductor current iLr. Thus, ZVS of switch Sm is
achieved. The boost inductor current ilb continues to
decrease. This mode ends when output diode current
iD becomes zero

Fig.3: mode 2
Mode 3(t2-t3): During this mode, the main switch
continues to conduct as shown in Fig.3.(c). A load is
supplied by the output filter capacitor. Input power is
stored in boost inductor Lb and resonant inductor Lr.
Therefore, the boost inductor current ilb starts
increasing. The resonant inductor current ilr
continues to increase. This mode ends when the main
switch Sm is turned off.

Fig.3: mode 3
Mode 4(t3-t4): As shown in Fig.3(d), the current,
which was flowing through the main switch, is
diverted to resonant capacitor Cr. The voltage across
the main switch (Vcr) starts increasing from zero, and
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when it reaches Vo, this mode ends. As soon as the
main switch voltage reaches approximately equal to
Vo, the output diode D starts conducting. The body
diode of the auxiliary switch Sa starts conducting
only after the main switch voltage reaches (Vo+Vcc)
. Since the interval between the start of conduction of
the diode D and the start of conduction of the body
diode of auxiliary switch is very small compared to
switching cycle, this is not treated as a separate

Fig.3: mode4
Mode 5(t4-t5): Fig. 3(e) shows the operating state of
the circuit during this interval. The boost inductor
current ilb starts decreasing. The output diode D
continues conducting and its current iD starts
increasing. If clamping capacitor Cc is large, then
clamping capacitor voltage Vcc is almost constant,
and inductor current ilr decreases linearly, otherwise
varies resonantly. This mode ends when the resonant
inductor current ILR becomes zero. Thus, the body
diode of the auxiliary switch ceases to conduct.
During this interval, a gate pulse must be applied to
auxiliary switch in order to achieve ZVS.

Fig.3: mode 5
Mode 6: As shown in Fig.3(f), the auxiliary switch
starts conducting. Thus, ZVS of switch is achieved.
The boost inductor current continues to decrease.
This mode ends when the auxiliary switch is turned
off.

Fig 3: mode 6
Mode 7: Fig.3(g) shows the operating state of the
circuit during this interval. The boost inductor current
continues to decrease. The voltage continues to
decrease due to negative inductor current. When
becomes zero, the body diode of the main switch
starts conducting and this mode ends. The resonant
inductor and the resonant capacitor form a resonance
circuit. To achieve ZVS of the main switch, must
reach zero at the end of this mode. This requirement
compels that stored energy in the resonant inductor
must be greater than resonant capacitor.


Fig.3: mode7
SIMULATION AND EXPERIMENTAL
RESULTS
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A. THEORITICALY ANALYSED WAVEFORMS
For inductors, Litz wires NELC175/40SPSN which
has 175 strands of 40 AWG is used. This reduces the
effective resistance of inductor as well as its skin
effects. For boost inductor, N87 ferrite core (Siemens
make) and for resonant inductor, N87 ferrite core
(Siemens make) is used. Fig.4(a) shows the simulated
clamping capacitor voltage, boost inductor current
and resonant inductor current at full load,
respectively. Fig.4(b) of boost inductor current shows
that the converter operates in continuous conduction
mode (CCM). The maximum resonant inductor
current is the same as that of maximum boost
inductor. The voltage across the clamping capacitor
is maximum at full load, which is 23.5 V in this case.
The experimental switch voltages and currents at full
load are shown in Fig5, and it is evident that both the
switches operate with ZVS. It is seen that the
proposed converter maintains unity power factor
even under unbalanced input voltages. Under
unbalanced input voltages, neutral current will have
triple harmonics. The performance characteristics of
the proposed converter under variable load condition
are given in Fig. 6. It is observed that the efficiency
varies from 94.9% to 92.5%, power factor varies
from 0.999 to 0.997, and total harmonic distortion
(THD) varies from 1.1% to 2.7% from full load to
25% of full load. In a hard-switched converter,
efficiency is nearly about 90% .The proposed
converter has a higher efficiency compared to other
soft switched converter.

Fig 4. Simulation results at full load. (a) Clamp capacitor
voltage (Vcc),
(b) boost inductor current (iLb ), and (c) resonant inductor
current (iLr )

Fig. 5. Experimental main switch voltage (vsm ) and main
switch current (ism ), and auxiliary switch voltage (vsa )
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and auxiliary switch current (isa ) at full load (scales: 200
V/div., 5 A/div., 1 _s/div. (zoom view)).

Fig 6. Experimental performance characteristics of the
proposed converter (a)efficiency, (b) power factor, and (c)
% THD.

Fig. 7. Experimental main diode current (i D) and
resonant inductor current (iLr ) at full load (scales:
5/div., 5 _s/div.).

Fig 8. Source current and voltage waveform

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Fig 9. Output current and voltage waveform
CONCLUSION
High power quality single phase and three-phase ac
dc converters are being widely used in the industries.
In this project, a single-phase module of acdc
converter used for three phase module adopting
active clamped boost topology has been presented.
The operating modes, analysis of the circuit, and
design considerations are explained. The simulation
and experimental results on laboratory prototype are
presented. The experimental results are in good
agreement with simulation results. The proposed
converter has smaller output filter capacitor and
lesser component count as compared to other
topologies. It operates at almost unity power factor,
low THD, and high efficiency. In addition, it
maintains unity power factor and regulated output
voltage with ZVS over the wide range of the load
even-with unbalanced input voltages.
REFERENCES
[1] B. Singh, B. N. Singh, A. Chandra, K. Al-Haddad, A.
Pandey, and D.P. Kothari, A review of three-phase
improved power quality acdcconverters, IEEE Trans.
Ind. Electron., vol. 51, no. 3, pp. 641660, Jun. 2004.
[2] B. M. Saied and H. I. Zynal, Minimizing current
distortion of a threephasebridge rectifier based on line
injection technique, IEEE Trans.
Power Electron., vol. 21, no. 6, pp. 17541761, Nov. 2006.
[3] M. R. Ramteke, H. M. Suryawanshi, and K. L. Thakre,
Single-phaseresonant converter in three-phase system in
modular approach, EPE
J., vol. 16, no. 4, pp. 513, Dec. 2006.
[4] A. K. S. Bhat and R. L. Zheng, Analysis and design of
a three-phase LCC-type resonant converter, IEEE Trans.
Aerospace Electron. Syst.,
vol. 34, no. 1, pp. 508518, Apr. 1998.
[5] S. S. Tanavade, H. M. Suryawanshi, and K. L. Thakre,
Novel single-phase ac-to-dc convertor using three-phase
modified series-parallel resonant converter, IEE Proc.
Elect. Power Appl., vol. 152, pp. 10271035, Jul. 2005.
[6] R. L. Steigerwald, A comparison of half bridge
resonant converter topologies, IEEE Trans. Power
Electron., vol. 3, no. 2, pp. 174182,
Apr. 1988.
[7] T.-F. Wu and S.-A. Liang, A systematic approach to
developingsingle-stage soft switching PWM converters,
IEEE Trans. Power Electron., vol. 16, no. 5, pp. 581593,
Sep.. 2001.
[8] R. Watson, F. C. Lee, and G. C. Hua, Utilization of an
active clamp circuit to achieve soft switching in flyback
converters, IEEE Trans. Power Electron., vol. 11, no. 1,
pp. 162169, Jan. 1996.
[9] J. A. Cobos, O. Garcia, J. Uceda, J. Sebastian, and E.
Cruz, Comparison of high efficiency low output voltage
forward topologies, in Proc.
IEEE PESC, 1994, pp. 887894.
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Wireless Electrical Energy Transfer

Nanda Kumar K
1
, N. Naha Renjini
2
and Rasmi Rajan
3


1,2,3
Assistant professor, EEE Department, Hindustan University, Chennai



ABSTRACT
The paper will detail the need and usefulness of
wireless power transmission and furthermore
the feasibility of using inductive coupling as the
means for wireless power transmission.
Nowadays usage of smart phones, laptops and
other portable electronic devices has been
increased. The users of these portable devices
need to recharge their devices in order to get an
uninterrupted service. The main problem faced
by them while recharging those devices is a need
of charging device. These problems can be
overcome by using a wireless connection
between the device and the output port. The
wireless connection can be made possible by
using the electromagnetic waves.

1. INTRODUCTION
The subject matter of the report will be directed
towards the knowledge level of an electrical
engineer. Thus some points about general circuits
may not be explicitly stated as they have been
taken as common knowledge for the intended
audience [1-8]. However, it is intended that anyone
with an interest in electrical circuits and more
importantly transformer theory or electromagnetic
fields would be able to understand and follow the
subject matter outlined in the following document.
The first section of the document will explicitly
illustrate the problem and what the group intended
to accomplish. With the complexity of the problem
in mind and what we must accomplish our team
then began research on the available means to
transmit power without a physical connection.
Once the initial background research was
accomplished it was necessary to layout the
advantages and disadvantages of all the available
means for wireless power transmission [5-10].
Once all the necessary criteria for each system were
known we chose the best solution for the problem.
After our team had chosen upon using inductive
coupling us all began to review the major theories
that would determine the constraints of the system
and what pieces of hardware must be designed to
achieve the transmission of wireless power.
Furthermore because we are transmitting power
through the surrounding area we had to be sure that
our system would not endanger others and be FCC
(Federal Communication Commission) compliant.
Once the basic system components were known our
team divided up the work load, set the necessary
deadlines, and began designing the following
circuits and hardware: power supply, oscillator,
transmission coil, receiving coil, and LED flashing
circuit. After the entire system was integrated into a
working unit it was time to determine how well the
system operated and the feasibility of wireless
power transfer through inductive coupling.
Additionally, future improvements that could
greatly improve the overall system will be
discussed.
1.1 Problem Statement
For the completion of this project, we had to
wirelessly transfer the power of an AC oscillating
waveform into a DC voltage on the receiving end
which will be used to light an LED to demonstrate
the instantaneous power transfer [11-15]. The
frequency of oscillation of the AC signal must not
exceed 100MHz. The power transfer needs to be
done over a two feet distance or greater. The
transferred AC power needs to be converted to DC
power and boosted up enough to drive a low power
display design, such as an LED in continuous
mode. The whole system must be FCC compliant.

1.2 Possible Solutions
In our research, as well as practical knowledge, we
knew of three possibilities to design a device [16-
17]. There are the use of antennas, inductive
coupling, and laser power transfer. In addition, we
had to be aware of how antennas and inductive
coupling would be affected by the frequency we
select.

1.2.1 Antenna
Antennas are the traditional means of signal
transmission and would likely work. In initial
research, it appears that system utilizing antennas
can receive power gains based upon the shape and
design of the antenna. This would allow more
power actually being sent and received while also
have a small input power. The difficulty comes in
the trade off of antenna size versus frequency. In
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attempting to stay in a lower frequency, one would
be require using antennas of very large size.

1.2.2 Inductive Coupling
Inductive coupling does not have the need for large
structures transfer power signals. Rather, inductive
coupling makes use of inductive coils to transfer
the power signals. Due to the use of coils rather
than the antenna, the size of the actual transmitter
and receiver can be made to fit the situation better.
The tradeoff is for the benefit of custom size, there
will be a poor gain on the solenoid transmitter and
receiver.

1.2.3 Laser Power Transmission
The concept of laser power transmission is
addressed in the research of NASA and NASDA
solar programs. Lasers would allow for a very
concentrated stream of power to be transferred
from one point to another. Based upon available
research material, it appears that this solution
would be more practical for space to upper
atmosphere or terrestrial power transmission. This
option would not be valid to accomplish our tasks
because light wavelengths are higher than the
allowable operational frequencies.

2. BLOCK DIAGRAM & DESCRIPTION


Figure 2.1 Block Diagram

2.1 Block Diagram Description
A transformer is a static electrical device that
transfers energy by inductive coupling between its
winding circuits. A bridge rectifier is used for
conversion of an alternating current (AC) input into
a direct current (DC) output. A crystal oscillator is
an electronic oscillator circuit that uses the
mechanical resonance of a vibrating crystal of
piezoelectric material to create an electrical signal
with a very precise frequency. This frequency is
commonly used to provide a stable clock signal for
the driver circuit. The most common type of
piezoelectric resonator used is the quartz crystal, so
oscillator circuits incorporating them became
known as crystal oscillators. In order to generate
the maximum amount of flux which will induce the
largest voltage on a receiving coil, a large amount
of current must be transferred into the transmitting
coil. The oscillator is not capable of supplying the
necessary current, thus the output signal from the
oscillator will then be passed through a power
amplifier (Power MOSFET) to produce the
necessary current.

A loop antenna is a radio antenna consisting of a
loop (or loops) of wire, tubing, or other electrical
conductor with its ends connected to a balanced
transmission line. Within this physical description
there are two very distinct antenna designs: the
small loop (or magnetic loop) with a size much
smaller than a wavelength, and the resonant loop
antenna with a circumference approximately equal
to the wavelength. Small loops have a poor
efficiency and are mainly used as receiving
antennas at low frequencies. Self-resonant loop
antennas are larger. They are typically used at
higher frequencies, especially VHF and UHF,
where their size is manageable.
One of the major improvements made to the
coupling circuit was accomplished by impedance
matching. When a capacitor is put in series with the
transmitter coil and it is tuned to its resonant
frequency, then the phase differences of the
capacitor and inductor are equal and opposite.
jwL =-1/jwC
When this occurs the load will appear purely
resistive and the maximum amount of real power
will be transferred into the transmission coil as
voltage and current are in phase. This maximum
power transfer to the transmitter will ensure the
maximum amount of current which will produce
the most magnetic flux.
At the receiver circuit we utilized the same
concepts of impedance matching to tune the
receiver circuit to the same resonant frequency as
of the transmitter. This ensures that the maximum
power is transmitted to the receiver coil.
A parallel resonance circuit was used to maximize
voltage output to the load at the receiving end. A
LED is used in our circuit to indicate the power is
received by the receiver.
2.2 Circuit Diagram & Description
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Figure 2.2 Circuit Diagram
2.3 Power MOSFET, Transmission & Receiving
Circuit

Figure 2.3 Transmission & Receiving Circuit
In order to generate the maximum amount of flux
which will induce the largest voltage on a receiving
coil, a large amount of current must be transferred
into the transmitting coil.
The oscillator is not capable of supplying the
necessary current, thus the output signal from the
oscillator will then be passed through a power
amplifier to produce the necessary current. The key
design aspects of the power amplifier are
generating enough current while producing a clean
output signal without large harmonic distortions. If
the output from the amplifier was not clean with
harmonic distortions the system would cease to be
FCC compliant.
Transmitter and Receiver Design
The transmitter and receiver circuit combined can
be called the coupling circuit. It is the heart of the
entire system as the actual wireless power transfer
is carried out here. The efficiency of the coupling
circuit determines the amount of power available
for the receiver system as well as how far the LED
can be from its actual power source.

Solenoid Design
A solenoid configuration was used for the design of
the transmitter and receiver. A solenoid is a long
cylinder upon which wire is wound in helical
geometry as shown in figure 2. The magnetic field
at the center of the solenoid is very uniform.
Usually, the length of a solenoid is several times of
its diameter. The longer the solenoid the more
uniform the magnetic field at the middle. In this
way a solenoid is a very practical way to generate a
uniform controlled magnetic field .


Figure 2.4 Flux density in a solenoid

The magnetic flux density in a solenoid can be
approximated by the following equation:

B =
0
nI

Where B is the magnetic flux density,
0
is the
permeability of free space, n is number of turns of
wire per unit length and I is the current flowing
through the wire. To maximize the flux linked to
the receiver coil, it is imperative to increase the
magnetic flux density as much as possible.
The equation shows that one of the ways to
increase B is to increase the current (I) going into
the wire. Since all wires have some resistance, this
process requires increase in the voltage put across
the wires which can result in more heating in the
coil. B can also be increased by increasing n. This
can be accomplished by decreasing the wire size or
winding wires closely. Winding wires closely can
increase the overall resistance of the coil and thus
increase the heating in the coil. Another way of
increasing n is by winding several layers of wire
which can cause insulations problems as well as
decrease the diameter to length ratio. It is apparent
that there are several parameters that we have to
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manipulate to select the appropriate tradeoff that
might fit our systems needs.

As the input power to our transmitter is limited to
1W, it certainly limits the amount of current that
can be pushed through the transmitter coil. Thus
one of the design goals of the team was to keep the
resistance low to maximize the current. In addition
to that, we also strived to increase the number of
turns per unit length without drastically
increasing the resistance. Initially our team
was using shielded wire for the coils. A major
advancement was made in decreasing wire size
by replacing it with magnetic wires. This wire
is common copper wire but rather than having
a thick insulation over the copper, it is simply
coated in enamel which keeps the overall
diameter of the wire much thinner compared to
shielded wire. Magnetic wires also have low
resistance and therefore can carry much higher
current.
We also utilized two complete layers of wires for
the transmitter coil to increase the number of turns
even more.

These steps improved the performance of our
system to a great extent.
Initial Experimentation
In addition to the solenoid parameters, it was also
necessary to determine certain parameters such as
relative size of the transmitter and receiver coil, the
orientation of the coils, the turns ratio as well as the
operating frequency. To establish these parameters,
we conducted few experiments. For our
experiments we made two handmade inductive
coils of different diameters (approximately 1.5 ft
and 6 inches), but with equal turns (N=10). First we
tried supplying the large diameter coil with a 7 volt
21 kHz sine waveform to act as the transmitter and
the small diameter coil was placed next to it at
various distances and the resulting voltage received
was measured.

Figure 2.5 Bigger Transmitter and Smaller Receiver Coil

Next we conducted the same experiment however
this time the coils were oriented in such a way
where they were along the same axis as shown
below.

Figure 2.6 Transmitter and Receiver Coil sharing the
same axis
The following data was collected with this
arrangement.

BIG LOOPS
transmitter

SMALL
LOOPS
receiver

Separation distance

MEASURED VOLTAGE

3inches

7V

30mV

BIG LOOPS FOR
TRANCEIVER
SMALL LOOPS
FOR RECEIVER
Separat
ion
distance
MEASURED VOLTAGES
0inch 7V 43mV
2inches 7V 18mV
5inches 7V 8mV
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Higher frequency is preferred for greater power
transmission over all distances. This agrees with
Faradays Law as the induced voltage is dependent
on the frequency. The large number of turns at the
transmitter would create more magnetic flux
density which can result in high flux linkage. The
major concern at the receiver was to find the
optimum number of turns while keeping the
resistance of the receiver coil minimal. Further
experimentation showed that the turns ratio of
transmitter and receiver coil had no effect on the
system whatsoever due to the large distance
between the coils.
From these simple tests we realized four major
points of emphasis that would be crucial in
designing an efficient inductive coupling system:
The coils should be oriented such that they
share the same axis
The receiver should be larger than the
transmitter
The higher the frequency the more power
can be transferred over a given distance
After conducting several experiments with
longer solenoids and different number of
turns, we arrived at the final parameters
that seem to provide the maximum power
transfer between the transmitter and
receiver coils.
3. HARDWARE DESCRIPTION

3.1 System Design
With all the necessary background research
completed it became clear what basic design
components the entire system would require. First
we needed a method to power the transmission side
of the system. The power supply would then power
an oscillator which would provide the carrier signal
with which to transmit the power. Oscillators are
not generally designed to deliver power, thus it was
necessary to create a power amplifier to amplify the
oscillating signal. The power amplifier would then
transfer the output power to the transmission coil.
Next, a receiver coil would be constructed to
receive the transmitted power. However, the
received power would have an alternating current
which is undesirable for lighting a LED. The entire
system can be seen in the figure.


Figure 3.1 Project hardware
3.2 Power Supply Enclosure

Figure 3.2 Power Supply Enclosures
The main design aspects our team wanted to
incorporate in the power supply was that it could
use the 230 V AC voltage found in any basic wall
outlet, and use that voltage to power any necessary
circuits to the system. Initially, 230volts is too large
for our small circuits so we incorporated a small
transformer to step down the voltage. Furthermore
for any basic electrical components it would be
necessary to have a DC power supply available,
thus the stepped down AC voltage converted to DC
by a full-wave bridge rectifier. The full-wave
bridge rectifier is the KBU4D. Large capacitors
were then connected to the output of the full-wave
bridge rectifier to ensure that a steady DC voltage
could be maintained.
3.3 Crystal oscillator, Driver Circuit & MOSFET
Enclosure
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Figure 3.3 Crystal oscillator & Driver Hardware
During the operation, the oscillation is being
sustained by the crystal oscillator by taking a
voltage signal from a quartz resonator. The signal
is fed back to the resonator after being amplified. In
this circuit, the frequency is being micro tuned by
the presence of 47 F capacitor. The 1 6Hz
converted frequency can be obtained from the pin
12 of IC as it serves as its output. Based on the
components used in the circuit, it will no longer
require additional adjustments for the circuit to
function well.
3.4 Transmitting and Receiving antenna

Figure 3.4 Transmitting antenna

Figure 3.5 Receiving antenna
4. FUTURE IMPROVEMENTS
There are several improvements that can be made
to the system to increase its overall performance.
The oscillator output wasnt a very clean sine wave
signal which increased the harmonic distortion of
the signal. A pure sine wave can be generated by
using better filters at the output. Currently our
system is powered by a transformer that provides
+18V/-18V volt rails. Our system can work with
lower power. Thus one of the future improvements
could be an implementation of a solar cell array to
make our system more mobile. The coupling circuit
can be made more efficient by altering the design
in several ways. Increasing the input current to the
transmitter coil would definitely enhance its
performance. We can also make the signals more
directional in the z direction by using a conical coil
as a transmitter instead of the solenoid coil.
5. CONCLUSION

Large number of institutions such as medical,
industrial, educational etc. need wireless electricity
transmission mechanism for its products to work
efficiently, effectively and at potentially reduced
costs. Plus it reduces the hassle of wires, non-
rechargeable batteries and power cords at small
scale. On the other hand transmission
of power using wireless electricity mechanism
helps to reduce the cost of power
being supplied. Plus the source of power is clean
and environmental friendly. The proposed research
would attain following goals:
1. Development of wireless electric
transmission mechanism for small scale
(private sector) which is efficient and
effective
2. Development of wireless electric
transmission mechanism for large scale
(public sector) which is efficient, effective
and aimed at lower electricity production
cost.
3. Determine whether the radiations from the
wireless electric transmission system have
biological impact.

REFERENCES

[1] G. L. Peterson, THE WIRELESS
TRANSMISSION OF ELECTRICAL
ENERGY, IEEE[online document], 2004,
[cited 12/10/04],
http://www.tfcbooks.com/articles/tws8c.htm
[2] [U.S. Department of Energy, Energy Savers:
Solar Power Satellites, [online document] rev
2004 June 17, [cited 12/10/04],
http://www.eere.energy.gov/consumerinfo/fact
sheets/l123.html
[3] S. Kopparthi, Pratul K. Ajmera, "Power
delivery for remotely located Microsystems,"
International Journal for Research and Development in Engineering (IJRDE)
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Methods Enriching Power and Energy Development (MEPED) 2014 119 | P a g e



Proc. of IEEE Region 5, 2004 Annual Tech.
Conference, 2004 April 2, pp. 31-39.
[4] Tomohiro Yamada, Hirotaka Sugawara,
Kenichi Okada, Kazuya Masu, Akio Oki and
Yasuhiro Horiike,"Battery-less Wireless
Communication System through Human Body
for in- vivo Healthcare Chip,"IEEE Topical
Meeting on Silicon Monolithic Integrated
Circuits in RF Systems, pp. 322-325, Sept.
2004.
[5] Category:Radio spectrum -Wikipedia, the free
encyclopedia, [online document], 2004 Aug
26 [cited 12/11/04],
http://en.wikipedia.org/wiki/Category:Radio_s
pectrum.
[6] Zia A. Yamayee and Juan L. Bala, Jr.,
Electromechanical Energy Devices and Power
Systems, John Wiley and Sons, 1947, p. 78.
[7] Code of Federal Regulations, Title 47, Volume
1,Revised as of October 1, 2003 ,From the U.S.
Government Printing Office via GPO Access,
CITE: 47CFR15.3, Page 686-689
[8] Oscillator Basics, October 2004,
http://www.electronics-
tutorials.com/oscillators/oscillator- basics.html
DiscreteSemiconductors, 2N2222, November
2004,
http://www.semiconductors.philips.com/acroba
t_download/datasheets/2N2222_CNV_2.pdf.
[9] All Data Sheets, AD711JN Operational
Amplifier, November 2004,
http://www.alldatasheet.com/datasheet-
pdf/view/AD/AD711JN.html.
[10] 2.3 Class B September 2004, http://www.st-
andrews.ac.uk/~www_pa/Scots_Guide/audio/p
art2/page2.html.
[11] Texas Insturments, OPA13442 Operational
Amplifier, September 2004,
http://focus.ti.com/lit/ds/sbos058/sbos058.pdf.
[12] Digikey, TIP31 BJT,
http://rocky.digikey.com/WebLib/On-
Semi/Web%20Data/TIP31_A_B_C,%20TIP32
_A_B_C.pdf.
[13] Digikey,TIP42,BJT,http://rocky.digikey.com
/WebLib/ST%20Micro/Web%20Data/TIP41A,
B,C_42A,C.pdf.
[14] Barry.Solenoid Physics (Barrys CoilGun
Design Site) [online] 2004,
http://www.oz.net/~coilgun/theory/solenoidphy
sics.htm (Accessed: September 27, 2004).
[15] Fawwaz T. Ulaby, Fundamentals of Applied
Electromagnetics 2001 Media Edition, Prentice
Hall, 2001.
[16] The Spark Transmitter. 2. Maximising Power,
part 1. November 2004,
http://home.freeuk.net/dunckx/wireless/maxpo
wer1/maxpower1.html
[17] R. Victor Jones, Diode Applications, [Online
Document], 2001 Oct 25, [cited 2004 Dec 11],
http://people.deas.harvard.edu/~jones/es154/lec
tures/lecture_2/diode_circuits/diode_appl.html



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Speed Control of PMBLDC Motor Using PFC Cuk
Converter for Air-Conditioner

K.Barathi
1
, S.Suganthi
2

1
PG Scholar in Power Electronics and Drives, Mailam Engineering College, India
2
Professor, Department of Electrical and Electronics Engineering, Mailam Engineering College, India

ABSTRACT
The diode bridge rectifier incorporating DC
DC cuk converter fed from single phase AC
mains is designed to drive a permanent magnet
brushless DC motor (PMBLDCM). The cuk
converter power switch is driven with the aid of
single stage power factor correction (PFC)
converter control. The closed loop operation of
sliding mode controller (SMC) is designed
within the power factor correction (PFC)
converter circuit. The permanent magnet
brushless DC motor (PMBLDCM) is controlled
with the help of DC DC cuk converter input
fed to the three phase voltage source inverter
(VSI) bridge circuit which inturn to regulate
the motor. The electronic commutator is used to
operate the three phase voltage source inverter
(VSI) bridge rectifier which is used to run
PMBLDC and it drives an air conditioning
compressor. Thus the speed of the permanent
magnet brushless DC motor (PMBLDCM) is
controlled with the help of the controller and
produce better output performance with the
reduction in total harmonic distortion (THD).
The output performance characteristic of the
SMC controller is compared with the
conventional (PI) controller. Thus in this
proposed work SMC controller is designed to
provide reduction in total harmonic distortion
and the better speed control over a wide range
of variation of the input ac mains of the
PMBLDC system. This proposed work is
constructed for the main application of air
conditioner. The power quality is improved as
the total harmonic distortion (THD) is reduced
for this system and their corresponding
simulation results are developed with the help of
MATLAB SIMULINK software.
Keywords: Power factor correction (PFC),
Permanent magnet brushless DC (PMBLDC)
motor, Sliding Mode controller (SMC), Cuk
converter, Voltage Source Inverter (VSI).
I. INTRODUCTION
The main features of permanent magnet brushless
DC (PMBLDC) motor as wide speed range with
high efficiency and low maintenance leads to their
vast use of applications in low power appliances [2]
[5]. The 3 synchronous motor has rugged
construction with the permanent magnet rotor. The
electrical commutation in permanent magnet
brushless DC motor is achieved by power switches
of 3 VSI. With the maintenance of air
conditioner temperature at the reference set value,
the PMBLDC motor in the application of air
conditioning compressor provides better efficiency.
When PMBLDC motor is operated under speed
controlled, the air conditioner leads to constant
torque operation. The air conditioner with
PMBLDC motor used for low power appliances
due to their advantages as reduced running rate,
extended life and reduction of mechanical stress
and electrical stress.
Among different converter configuration, power
factor correction (PFC) converter is more expected
for a permanent magnet brushless DC (PMBLDC)
motor [5], [6]. The IEC 61000 3 2 standards of
power quality for low power appliances [8], give
attention on nearer to unity pf and low harmonic
contents which is drawn by these drives from ac
mains.
Though there are many works describing about
permanent magnet brushless DC (PMBLDC) motor
with PFC converter topologies such as battery
charging applications and PFC converter with
switched mode power supplies. This proposed
work deals with the speed control of permanent
magnet brushless DC (PMBLDC) motor
integrating with power factor correction (PFC)
converter. In this work, the DC DC Cuk
converter is employed as a power factor correction
(PFC) converter. Since DC DC Cuk converter has
advantageous such as small output filter and wide
range of output voltage with the continuous input
and output currents than other converter topologies
[9] [10].

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II. SPEED CONTROL METHOD OF
PROPOSED SYSTEM
The speed control method of permanent magnet
brushless DC (PMBLDC) motor for air
conditioner compressor with the aid of sliding
mode controller which drives DC DC cuk
converter is designed and shown in block diagram
representation in Fig.1.

Fig.1.Speed Control Method of Proposed System
The proposed system block diagram explains the
control operation and speed control of permanent
magnet brushless DC (PMBLDC) motor. The
single stage AC source is used for the generation of
reference current which also has the input I
c
from
SMC controller output. This reference current
generator is used to produce the output of current
I
d
*. The current I
d
*
act as the input to PWM current
controller which compares with current I
d
obtained
from the output of diode bridge rectifier. The error
output from the PWM current controller act as
pulse generating signal for the power
semiconductor switches of DC DC cuk converter.
The input for sliding mode controller is generated
from the output error signal of DC DC cuk
converter voltage V
dc
comparison with reference
voltage V
dc
*
. The permanent magnet brushless DC
(PMBLDC) used for the application air
conditioner compressor is fed from three voltage
source inverter (VSI). The voltage source inverter
(VSI) get the driving signals with the aid of
electronic commutator.
Thus the cuk converter is mainly used to control
the speed of permanent magnet brushless DC
(PMBLDC) motor with the aid of dc link voltage
input to the voltage source inverter (VSI). The
power semiconductor switches of metal oxide
semiconductor field effect transistor (MOSFET)
and insulated gate bipolar transistor (IGBT) are
used for the proposed power factor correction
(PFC) converter and voltage source inverter (VSI)
circuit for the high and low frequency operation
respectively. The electronic commutator output is
generated based upon the Hall Effect sensor
signals. The switching sequence of the power
semiconductor switching sequence and the hall
effect signals are tabulated and shown in TABLE I
[6], [11].
TABLE I
ELECTRONIC COMMUTATOR OUTPUT
BASED UPON HALL EFFECT SENSOR
SIGNALS


From the TABLE I show that the values of 0 and
1 as the operation of ON and OFF condition of
power semiconductor switches IGBTs of the
voltage source inverter (VSI). The upper switches
are named in order as S
a1
, S
b1
, S
c1
and the lower
switches as S
a2
, S
b2
, S
c2
.

III. SLIDING MODE CONTROLLER
The sliding mode controller is mainly an adaptive
control which generates the robust characteristics
of a system with the load torque T
L
disturbance and
also parameter variation. The drive response is used
to slide along a path or reference trajectory with the
help of switching algorithm. The sliding mode
controller is used for the various applications as
drive applications, machine tool control and also
for converter applications. The sliding mode
controller is generally a variable structure
controller.
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The sliding surface of the system is considered as
trajectory or path along the switching sequence
waveform is shown in Fig.2. The sliding surface
s with the time control switching conditio
or 0 is represented in this figure as s>0 or s<0
respectively. The chattering effect in the system is
reduced with the help of developing any one of the
piece wise linear functions as shown in Fig.3.
Fig.2. General sliding mode surface along the switches
waveforms



Fig.3.Piece Wise Linear Functions
The sliding mode controller for the closed loop
control of the system is shown in Fig.4.
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The sliding surface of the system is considered as
trajectory or path along the switching sequence
waveform is shown in Fig.2. The sliding surface
s with the time control switching condition of 1
or 0 is represented in this figure as s>0 or s<0
respectively. The chattering effect in the system is
the help of developing any one of the
wise linear functions as shown in Fig.3.

along the switches

The sliding mode controller for the closed loop
control of the system is shown in Fig.4.
Fig.4.Sliding Mode Controller of the Closed Loop
Control System.
The voltage loop generates voltage error due to the
disturbances if the DC DC cuk converter is under
open loop control. The PI controller is used to
eliminate this error and produce the current i
voltage loop of the system is given by the equation
representation as,
I
*
= I
1d
+ I
c
The current loop for the switching manifold of
sliding mode current controller is represented by
the equation as:
S= I
1
I*

The control signal for the cuk converter power
switches with the aid of piece
function characteristics of sign as:
U = 0.5 (1 sign(s)) = 1if S<0 or if S>0
The condition of sliding mode existence can be
derived with a candidate Lyapunov function can be
P = 0.5S
2
>0 if S 0
Differentiating this equation as:
S = - (1 u)


With Eq. (3.2.15), the derivative of P is
P = ss

2 21


The sufficient condition for P < 0 is
2E 2L1i* V1- V1 < 0
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Fig.4.Sliding Mode Controller of the Closed Loop
tage error due to the
DC cuk converter is under
open loop control. The PI controller is used to
eliminate this error and produce the current i
c
. The
voltage loop of the system is given by the equation
The current loop for the switching manifold of
sliding mode current controller is represented by
converter power
switches with the aid of piece wise linear
function characteristics of sign as:
sign(s)) = 1if S<0 or if S>0
The condition of sliding mode existence can be
derived with a candidate Lyapunov function can be
0


With Eq. (3.2.15), the derivative of P is
1 1
The sufficient condition for P < 0 is
V1 < 0
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In the steady state, one has L
1
I* = 0 due to constant
I*, V2 = Vd, V1d = V1, and V2 = E V1 < 0 due
to Eq.(3.2.10). The inequality 12 leads to
0 < E L
1
I* < E V
2


And also, V
2
is negative and |V
2
| can be greater
than or less than E.

IV. SIMULATION RESULTS

The simulation result of the proposed system is
shown in following figures. The Fig.5.1. shows
response of the pulse generated to the cuk converter
power switches. The Fig.5.2. shows the output
voltage response of cuk converter with the
reference set point of 298V. The Fig.5.3. shows
the response of speed control characteristics for the
reference set point of 298V. The Fig.5.4. shows the
response of THD analysis of proposed system with
SMC controller. The TABLE II shows the
performance of the proposed system result with the
representation of THD%, rate of speed, DC link
voltage V
dc
, the supply current I
s
.



Fig.5.1. Pulse Generated to Cuk Converter



Fig.5.2. Output voltage of Cuk converter with the
reference set point of 298V.


Fig.5.3. Output speed waveform for the reference set
point of 298V.
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Fig.5.4.THD analysis for proposed system using SMC
controller.

TABLE II
PERFORMANCE OF THE PROPOSED SYSTEM
RESULT


V. CONCLUSION
In this proposed work, the better speed control of
the system was obtained with the help of sliding
mode controller (SMC) and the reference value of
DC link voltage V
dc
which is referred as reference
speed. The simulation result performance was also
obtained for this proposed work with the reduction
in the total harmonic distortion (THD) value due to
SMC controller, which is less than the result
obtained with conventional (PI) controller. Thus
one of the power quality (PQ) problem (reduced
THD value) is limited in this proposed system.
REFERENCES
[1] T. Kenjo and S. Nagamori, Permanent Magnet
Brushless DC Motors.Oxford, U.K.: clarendon,
1985.
[2] T. J. Sokira and W. Jaffe,Brushless DC Motors:
Electronic Commutation and Control. New York:
Tab, 1989.
[3] J. R. Hendershort and T. J. E. Miller, Design of
Brushless PermanentMagnet Motors. Oxford, U.K.:
Clarendon, 1994.
International Journal for Research and Development in Engineering (IJRDE)
ISSN: 2279-0500 Special Issue:
Methods Enriching Power and Energy Development (MEPED) 2014

Fig.5.4.THD analysis for proposed system using SMC
FORMANCE OF THE PROPOSED SYSTEM
In this proposed work, the better speed control of
the system was obtained with the help of sliding
mode controller (SMC) and the reference value of
which is referred as reference
speed. The simulation result performance was also
ed for this proposed work with the reduction
in the total harmonic distortion (THD) value due to
SMC controller, which is less than the result
obtained with conventional (PI) controller. Thus
one of the power quality (PQ) problem (reduced
ited in this proposed system.
T. Kenjo and S. Nagamori, Permanent Magnet
Brushless DC Motors.Oxford, U.K.: clarendon,
T. J. Sokira and W. Jaffe,Brushless DC Motors:
Electronic Commutation and Control. New York:
and T. J. E. Miller, Design of
Brushless PermanentMagnet Motors. Oxford, U.K.:
[4] J. F. Gieras and M. Wing,Permanent Magnet Motor
TechnologyDesign and Application. New York:
Marcel Dekker, 2002.
[5] B. Singh, B. N. Singh, A. Chandra, K. Al
A. Pandey, and D. P. Kothari, A review of single
phase improved power quality ac
IEEE Trans. Ind. Electron., vol. 50, no. 5, pp. 962
981, Oct. 2003.
[6] N. Mohan, M. Undeland, and W. P. Robbins,Power
Electronics: Converters, Applications a
Hoboken, NJ: Wiley, 1995. Limits for Harmonic
Current Emissions (Equipment Input Current
Per Phase), Int. Std. IEC 61000-3-2, 2000
[7] R. A. Kordkheili, M. Yazdani-Asrami, and A. M.
Sayidi., Making DC-DC converters easy to
understand for undergraduate students,in 2010
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33.
[8] T. F. Wu and S. A. Liang, A systematic approach
to developing single-stage soft switching PWM
sonverters, IEEE Trans. Power Electron., vol. 16,
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[9] H. T. moon, H. S. Kim and M. J. Youn, A
Discret Time Predictive Current Control for
PMSM IEEE Trans. Power Electronic., vol.18,
no.1, pp. 464-472, Janvier. 2003.
[10] B.BOSSOUFI, M.KARIM, S.IONITA,
A.LAGRIOUI, The Optimal Direct Torque
Control of a PMSM drive: FPGA
Implementation with Matlab & Simulink
Simulation Journal of Theoretical and Applied
Information Technology JATIT, pp63
No.2, 30th June 2011.
V
dc
THD Speed
298 1.15% 1501
265 1.29% 1327
233 1.25% 1159
200 1.24% 999.37
183 1.26% 899.3
151 1.15% 731.1
135 1.27% 648.9
104 1.28% 490.3
International Journal for Research and Development in Engineering (IJRDE)
Special Issue: pp- 120-124
124 | P a g e
J. F. Gieras and M. Wing,Permanent Magnet Motor
Design and Application. New York:
B. Singh, B. N. Singh, A. Chandra, K. Al-Haddad,
A. Pandey, and D. P. Kothari, A review of single-
phase improved power quality acdc converters,
IEEE Trans. Ind. Electron., vol. 50, no. 5, pp. 962
N. Mohan, M. Undeland, and W. P. Robbins,Power
Electronics: Converters, Applications and Design.
Hoboken, NJ: Wiley, 1995. Limits for Harmonic
Current Emissions (Equipment Input Current16 A
2, 2000
Asrami, and A. M.
DC converters easy to
graduate students,in 2010
IEEE Conf. on Open Systems, Dec. 2010, pp. 28-
T. F. Wu and S. A. Liang, A systematic approach
stage soft switching PWM
sonverters, IEEE Trans. Power Electron., vol. 16,
T. moon, H. S. Kim and M. J. Youn, A
Discret Time Predictive Current Control for
PMSM IEEE Trans. Power Electronic., vol.18,
B.BOSSOUFI, M.KARIM, S.IONITA,
A.LAGRIOUI, The Optimal Direct Torque
ntrol of a PMSM drive: FPGA-Based
Implementation with Matlab & Simulink
Simulation Journal of Theoretical and Applied
Information Technology JATIT, pp63-72, Vol. 28
I
s
7.003
8.025
6.721
5.23
4.875
3.794
3.289
2.355
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Methods Enriching Power and Energy Development (MEPED) 2014 125 | P a g e



A ZVS-PWM Three Phase Current Fed Push Pull DC-DC
Converter with Reduced Harmonics

Arunraj.M
1
, Dhinesh.AR
2,
Jenson George
3
, Priya.S
4
, K Sathiyasekar
5

1,2, 3
UG Student, Department of EEE, S.A. Engineering College, Chennai.
4
Assistant professor, Department of EEE, S.A. Engineering College, Chennai.
5
Professor, Department of EEE, S.A. Engineering College, Chennai.


Abstract- In this paper, a ZVS-PWM three-phase current
fed pushpull dcdc converter with reduced harmonics is
proposed. When compared to single-phase topologies, the
three-phase dcdc conversion increases the power density,
uses the magnetic core of the transformer more efficiently,
reduces the stress on switches, and requires smaller filters
since the frequency for its design is higher. The proposed
converter employs an active clamping technique by
connecting the primary side of the transformer to a multi
level inverter and a clamping capacitor and secondary
side with three-phase full wave rectifier. This circuit
allows the energy from the leakage inductances to be
reused, increasing the efficiency of the converter. If
appropriate parameters are chosen, soft-commutation of
the switches (ZVS) can also be achieved. The soft-
commutation improves the efficiency even further, allows
higher switching frequencies is to be used, and reduces the
electromagnetic interference significantly. Applications
such as fuel cell systems, transportation, and
uninterruptable power supplies are some examples that
can benefit from the advantages presented by this
converter.
Index TermsActive clamping, dcdc power conversion,
multiphase, soft-commutation, matlab.
I.INTRODUCTION
Three-phase systems are well known by their use in electric
power generation transmission and distribution. The cost
saving that they provide by employing less material than
single-phase systems assured success in these areas and led to
three-phase rectifiers, inverters, and also dcdc converters.
After this, other three-phase dcdc converter topologies were
developed and compared, and techniques to increase the
efficiency even more using soft-commutation [2][4] and
reducing the number of semiconductors in the output rectifier
bridge were studied. Most studies conclude that the three-
phase structures perform better than their single-phase
counterparts [5]. Depending on the topology, the voltage
across the switches is not naturally clamped, requiring
passive voltage clampers that dissipate energy stored in the
leakage inductances [6][8] to prevent overvoltage which
reduces efficiency. In order to avoid this problem, active
clamping techniques have already been presented for single-
phase converters and have successfully reused the energy that
would be dissipated both in nonisolated [9] and isolated
topologies [10].
The introduction of high-frequency three-phase transformers
on dcdc converters brought the possibility of increasing
power density, using the magnetic cores more efficiently and
reducing the current stress on power switches. In addition,
the increase in the high-frequency component seen by the
filters allowed the use of much smaller inductors and
capacitors. The voltage across the switches is not naturally
clamped, requiring passive voltage clampers that dissipate
energy stored in the leakage inductances to prevent
overvoltage.
In this topology, a full three-phase bridge and a clamping
capacitor on the primary side of the transformer are
responsible for the active clamping without the need for an
extra switch [11]. Compared to single phase inverter
multilevel inverter reduces harmonics and enhances the
efficiency compared to the converter in [1]. In the future, the
proposed converter could be applied as a high-efficiency
alternative to many applications such as the energy
processing of photovoltaic arrays and fuel cell systems
[12][13] or automotive devices and fuel cell powered
vehicles [14], where the three-phase dcdc conversion is
already showing its benefits.
II.PROPOSED ZVS PWM THREE PHASE DC-DC
CONVERTER
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A. Circuit Description
The circuit for the proposed ZVS-PWM three phase current
fed push pull dc-dc converter is shown in Fig.1. Switches
S1-S12 and capacitor C
g
1-C
g
6 is added to the converter
presented in [8] for active clamping. Inductance Ld1, Ld2,
Ld3 are responsible for maintaining current during the
commutation level. They represent the sum of the leakage
inductance of the transformer and an external inductance,
which is added to each phase if needed.

Fig 1. simplified version of the active clamped zvs-pwm push-pull
dc-dc converter with 11-level inverter.
B. Modulation
The gate signals are generated by the comparison of the
modulating signal VM and ten triangular carriers 36
o
of
phase from each other. V
G1
, V
G2
, V
G3
, V
G4
, V
G5
V
G6
, V
G7
,
V
G8
, V
G9
, V
G10
, V
G11
and V
G12
are the gate signals of S
1
, S
2
,
S
3
,S
4
,S
5
,S
6
,S
7
,S
8
,S
9
,S
10
,S
11
and S
12
respectively, and
V
G1
, V
G2
, V
G3
, V
G4
, V
G5
V
G6
, V
G7
, V
G8
, V
G9
, V
G10
,
V
G11
and V
G12
are the gate signals of S
1
, S
2
, S
3
,S
4
,S
5

,S
6
,S
7
,S
8
,S
9
,S
10
,S
11
and S
12
switches respectively.
The converter proposed in this paper can work in all the
twelve regions simultaneously as defined TABLE I which is
different from [1][8]. Thus decreasing the switching losses.
TABLE I
OPERATION REGIONS
Region Duty cycle Switches
simultaneously on
R1
0< D <


None
R2

< D <


Up to two
R3

< D <


Up to three
R4

< D <


Up to four
R5

< D <


Up to five
R6

< D <


Up to six
R7

< D <


Up to seven
R8

< D <


Up to eight
R9

< D <


Up to nine
R10

< D <


Up to ten
R11

< D <


Up to eleven
R12

< D < 1
Up to twelve
In this paper, this converter will be analyzed for operation in
region R12. Operating in region R12 proves the principle of
the active clamping in this topology for the worst case as,
higher the duty cycle is, the higher is the voltage across the
switches. A good design for the other regions could achieve
an even better result.
C. Working
At the beginning all the switches are kept open. In this stage
no current will flow through the transformer. So the sine
wave will have zero carriers and zero step will be produced.
Now in the next step switch S
1
and S
2
are switched ON,
keeping all the other switches OFF. In this stage current from
V
G1
will pass through the switch S
1
and S
2,
then to inductor
L
d1
and finally to the rectifier bridge. Thus producing the
positive step one output from the inverter. Now switch S
3
and
S
4
are switched ON keeping switch S
1
and S
2
ON and all
other switches OFF. This will produce a current output from
the equivalent voltage of bridge 1 and 2. Bridge 1 and 2 are
interconnected and thus the current from them is the voltage
equivalent. To get third positive step we will switch ON the
combination of 1-2 and 2-3 bridges and thus increasing the
number of bridges raising the positive step.
To obtain the negative part of the 11 step output the voltage
from V
G1
is applied to the opposite leg of the bridge1 that is
to the switch S
1
and S
2
. Thus the first negative output is
obtained. To obtain the second negative step output switch
S
3
and S
4
is switched ON keeping the switch S
1
and S
2
ON
and keeping all other switches OFF.
Thus the bridges will be operated in the order of 1-2,1-3,1-
4,1-5,1-6,2-4,2-6,3-4,3-5,4-6,5-6

III.SIMULATION
Simulation circuit for the project is shown in Fig 2. The
output from the 11 level inverter is shown in Fig. 3. The
output voltage produced for the input of 36V is produced in
the Fig. 4
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Fig 2.MATlab simulation circuit for zvs-pwm push pull dc-dc
converter

Fig 3. 11-level step output from the multi level inverter

Fig 4. Output voltage from the rectifier
IV. PROROTYPE DESCRIPTION
A prototype implementing the proposed converter was built
in order to validate the simulation results. The prototype is
made for single phase and the output with respect to three
phases is validated. The main specifications and components
used are shown in TABLE II. A photograph of the prototype
can be seen in Fig. 5.



Fig 5.Photograph of prototype

TABLE II
MAIN SPECIFICATION AND COMPONENTS OF THE
PROTOTYPE

Description Quantity Values
Input voltage(Vi) - 36V
Output Voltage(Vo) - 71V
7 tapping step-down
transformer
2 230/12V
3 tapping step down
transformer
1 230/6/12/24V
Step up transformer 1 6/12V
Polypropylene output
capacitor
4 1000F/63V
External commutation
capacitor
12 1000f/25V
MOSFETS 12 IRF840
RECTIFIERS 4 MUR860
PIC Mi-Controller 1 PIC16F877A
Optocoupler 16 TLP250


V.CONCLUSION
In this paper, a ZVS-PWM three-phase current-fed pushpull
dcdc converter with reduced harmonics has been proposed.
The operation stages were described, and the main
waveforms were plotted. A prototype was built for a rated
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power of 4 kW based on the parameters calculated in the
design example. This prototype was able to operate with
active clamping and soft-commutation (ZVS) of the
MOSFETs. The waveforms acquired through the matlab
validate the output, and the measured efficiency for full load
was 93.2%, remaining above 94% for most of the load range.
As an isolated topology, this converter presents competitive
efficiency and can be applied with good performance as an
energy processing stage for many renewable sources. The
most suitable applications include distributed generation,
uninterruptable power supplies, and transportation.

REFERENCES

[1] Romero Leandro Andersen and Ivo Barbi, A ZVS-PWM Three-
Phase Current-Fed PushPull DCDC Converter, IEEE Trans. Ind.
Electron., vol. 60, no. 3, pp 838-846 march 2013.

[2] R. W. A. A. De Doncker, D. M. Divan, and M. H. Kheraluwala,
A three-phase soft-switched high power-density dc/dc converter for
high-power applications, IEEE Trans. Ind. Appl., vol. 27, no. 1, pp.
63 73, Jan./Feb. 1991.

[3] J. Jacobs, A. Averberg, and R. De Doncker, A novel three-phase
dc/dc converter for high-power applications, in Proc. Power
Electron. Spec. Conf., Aachen, Germany, vol. 3, pp. 18611867.

[4] D. S. Oliveira, Jr. and I. Barbi, A three-phase ZVS PWM dc/dc
converter with asymmetrical duty cycle for high power
applications, IEEE Trans. Power Electron., vol. 20, no. 2, pp. 370
377, Mar. 2005.

[5] J. Aguillon-Garcia and G. W. Moon, A high efficiency three-
phase ZVS PWM converter utilizing a positive double-star active
rectifier stage for server power supply, IEEE Trans. Ind. Electron.,
vol. 58, no. 8, pp. 3317 3329, Aug. 2011.

[6] S. V. G. Oliveira and I. Barbi, A three-phase step-up dcdc
converter with a three-phase high frequency transformer, in Proc.
IEEE ISIE, Dubrovnik, Croatia, Jun. 2005, vol. 2, pp. 571576.

[7] S. V. G. Oliveira and I. Barbi, A three-phase step-up dcdc
converter with a three-phase high-frequency transformer for dc
renewable power sources applications, IEEE Trans. Ind. Electron.,
vol. 58, no. 8, pp. 35673580, Aug. 2011.

[8] R. L. Andersen and I. Barbi, A three-phase current-fed push
pull dcdc converter, IEEE Trans. Power Electron., vol. 24, no. 2,
pp. 358368, Feb. 2009.
[9] C. M. C. Duarte and I. Barbi, An improved family of ZVS-
PWM active clamping dc-to-dc converters, IEEE Trans. Power
Electron., vol. 17, no. 1, pp. 17, Jan. 2002.

[10] F. J. Nome and I. Barbi, A ZVS clamping mode-current-fed
pushpull dcdc converter, in Proc. IEEE ISIE, Pretoria, South
Africa, Jul. 710, 1998, vol. 2, pp. 617621.

[11] H. Cha, J. Choi, and P. N. Enjeti, A three-phase current-fed
dc/dc converter with active clamp for low-dc renewable energy
sources, IEEE Trans. Power Electron., vol. 23, no. 6, pp. 2784
2793, Nov. 2008.

[12] S. R. Moon and J. S. Lai, Multiphase isolated dcdc converters
for low voltage high-power fuel cell applications, in Proc. 22nd
Annu. IEEE APEC, Anaheim, CA, Feb. /Mar. 2007, pp. 10101016.

[13] H. Cha and P. Enjeti, A novel three-phase high power current-
fed dc/dc converter with active clamp for fuel cells, in Proc. Power
Electron. Spec. Conf., Orlando, FL, Jun. 2007, pp. 24852489.

[14] L. Tang and G.-J. Su, Experimental investigation of a soft-
switching three-phase, three-voltage bus dc/dc converter for fuel cell
vehicle applications, in Proc. IEEE Power Electron. Spec. Conf.,
Rhodes, Greece, Jun. 2008, pp. 585591.
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Novel Approach to Reduce Harmonic Distortion using
Pseudorandom PWM Technique
S. Saravanan
1
, D. Dhinakaran
2
, J. Yuvaraj
3

1
Assistant professor, Department of Electrical and Electronics Engineering
ARM College of Engineering and Technology, Chennai, India.
2,3
Research Scholar, Department of Electrical and Electronics Engineering
ARM College of Engineering and Technology, Chennai, India.

ABSTRACT
Several methods have been used to eliminate or
minimize harmonics of Multilevel Inverter (MLI)
output. Even though several methods have been
proposed, we are unable to reach minimum Total
Harmonic Distortion (THD). A new carrier
modulation technique (Pseudorandom Carrier
Modulation) for multilevel inverter is proposed in
this paper. Conventionally single triangular carrier
is used to produce the fixed frequency PWM
signal and cause discrete frequency harmonics,
Electro-magnetic interference and audible
switching noise. The proposed pseudorandom
carrier is produced through the random selection
of two triangular signals that are of same
frequency but in opposite phase. The random
selection of triangular carrier is decided by the
Pseudorandom Binary Sequence (PRBS). The
PRBS bits are generated using shift registers and
EXCLUSIVE OR gates. Multiplexers are used as
random selectors to produce the pseudorandom
(PR) frequency carrier waveform. The produced
random carrier is modulated using any modulation
technique to produce PWM signals for switching
devices. The modulated signals are used for the
H-bridge multilevel inverter. Here the PWM
pulses for each HBML inverter switches can be
obtained by comparing the sinusoidal reference
signal with the phase disposition arrangement of
eight random carriers to obtain nine level output
voltage. The multilevel inverter with
Pseudorandom Carrier Modulation drives a 5HP
Induction motor with reduced THD compared to
conventional method.
Keywords: Pseudorandom Pulse Width
Modulation, Pseudorandom Numbers, Linear
Feedback Shift Register (LFSR), Multilevel
Inverter and Harmonics
I. INTRODUCTION
Integrating multilevel inverters into medium and
high voltage industrial applications such as motor
drives, Flexible AC Transmission System (FACTS)
equipment, HVDC and renewable energy systems
is the issue of many ongoing researches. The main
advantages of multilevel inverters includes High
power and voltage ratings, power quality, more
electromagnetic compatibility, lower switching
losses, higher efficiency, higher voltage capability
and lower total harmonic distortion. Basically there
are three conventional topologies for multilevel
inverters such as Flying Capacitor, diode-clamped
and cascaded multi-level inverter with separate dc
sources [1-5]. Among them, the cascaded
multilevel inverter has received special attention
due to its modularity and simplicity of control
method. The principle operation of this inverter is
based on synthesizing the desired output voltage
waveform from several steps of voltage, which is
typically obtained from DC voltage sources. The
best way to reduce the audible switching Noise
radiated from the induction motor is to increase the
PWM switching frequency up to 20 kHz [6-7]. By
such a method, the Noise problem can be solved,
but it increases the switching loss of the inverter.
Generally, the random PWM scheme can be
implemented by using a microcontroller based on
space vector PWM or just hardware circuits.
Random pulse position PWM scheme randomly
varies the pulse position in every switching cycle.
Although many random PWM schemes have been
reported, the randomized switching frequency
modulation is the most popular technique. The
randomized switching frequency modulation can be
achieved through randomly varying the slope of the
PWM carrier triangular wave. In order to
implement the randomized switching frequency
modulation, using just hardware circuits, a PWM
triangular carrier generation circuit with
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randomized frequency is needed. This circuit must
be made using high-precision analog and digital
elements [8-10].
In this paper, a pseudorandom triangular carrier
modulation is proposed and its total harmonic
distortion is discussed. The proposed
pseudorandom carrier is acquired by randomly
composing two triangular carriers, each of the same
fixed frequency, but of opposite phase. The random
selection of the two triangular carriers is decided by
low or high states of the pseudorandom binary
sequence (PRBS) random bits. Linear Feedback
Shift Register (LFSR) is used for the generation of
PRBS random bits. Here PRB sequences are
generated using 8 bit and 12 bit LFSR. The
comparative study has been proposed. Multiplexers
with two input/one output, which generates the
resultant carrier with pseudorandom frequency, are
used as random selector of the PRBS random bits.
To verify the proposed scheme, a 170 V
rms
single-
phase 9-level H-Bridge Multilevel (HBML)
inverter to drive a 5HP Capacitor Start Induction
Motor was simulated. Experiment shows that the
less total harmonic distortion (THD) for output
voltage of a multilevel inverter and induction motor
main winding current are discussed. Finally, the
proposed scheme can be applicable to the existing
power electronics converters, by changing the fixed
switching frequency triangular carrier generator
into the proposed random carrier generator.
II. PSEUDORANDOM CARRIER
SCHEME
The overall Block diagram of a Pseudorandom
Carrier Modulation Technique is shown in Figure
1. The proposed method having function generator
to generate two triangular carriers each of opposite
in phase but frequency and magnitude are same.
The random selection of two carriers can be done
through multiplexer. The multiplexer needs control
signals to select any one of the signal to composite.
The control signals are the pseudorandom bits
(PRB) which can be generated through Linear
Feedback Shift Register (LFSR). Now the
pseudorandom carrier is generated through
multiplexer with the help of pseudorandom bits.

Figure 1: Pseudorandom Carrier Modulation Scheme
overall block diagram
The Pseudorandom carrier is compared with the
help of phase decomposition comparator. The
phase decomposition comparator gives the PWM
signals for the multilevel inverter. Initial value of
LFSR is called Seed. An LFSR is a shift register
that, when clocked, advances the signal through the
register from one bit to the next most-significant
bit. Some of the outputs are combined in exclusive-
OR configuration to form a feedback mechanism.
A linear feedback shift register can be formed by
performing exclusive-OR on the outputs of two or
more of the flip-flops together and feeding those
outputs back into the input of one of the flip-flops.
Linear feedback shift registers make extremely
good pseudorandom pattern generators. When the
outputs of the flip-flops are loaded with a seed
value (anything except all 0s, which would cause
the LFSR to produce all 0 patterns) and when the
LFSR is clocked, it will generate a pseudorandom
pattern of 1s and 0s. Note that the only signal
necessary to generate the test patterns is the clock.
A maximal-length LFSR produces the maximum
number of PRPG patterns possible and has a
pattern count equal to 2n 1, where n is the
number of register elements in the LFSR. It
produces patterns that have an approximately equal
number of 1s and 0s and have an equal number of
runs of 1s and 0s. Because there is no way to
predict mathematically if an LFSR will be maximal
length, Peterson and Weldon have compiled tables
of maximal-length LFSRs to which designers may
refer.
Table 1: Truth Table of Multiplexer
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PRBS State Output R
0 C


1 C
Table 1 shows the truth table of the multiplexer
illustrating the relation between PRBS states and
output R, which is dependent only on C and
shown in Figure. 2, the triangular carriers with
fixed frequency C and the triangular carriers with
fixed frequency with opposite phase C

the 21 multiplexer. Frequency of C and


equal. Then C and C

are randomly selected by the


output PRBS bits 0 or 1 of the random bits
generator. Choice of C and C

is dependent on the
output P of the PRBS random bits generator. In
case that the P is 1 then .R is selected as C, and if P
is 0 then R is selected as C


Figure 2: Pseudorandom Carrier Generation
Consequently, it means that the proposed random
carrier R can be synthesized with a pseudorandom
frequency. Because the proposed random carrier R
is made from the two triangular waveforms with
same fixed frequency, but of opposite phase, the
proposed scheme is named pseudorandom carrier
scheme.
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ISSN: 2279-0500 Special Iss
Methods Enriching Power and Energy Development (MEPED) 2014

shows the truth table of the multiplexer


illustrating the relation between PRBS states and
output R, which is dependent only on C and C

. As
shown in Figure. 2, the triangular carriers with
fixed frequency C and the triangular carriers with
C

are input to
the 21 multiplexer. Frequency of C and C

are
are randomly selected by the
output PRBS bits 0 or 1 of the random bits
is dependent on the
generator. In
R is selected as C, and if P
Figure 2: Pseudorandom Carrier Generation
Consequently, it means that the proposed random
carrier R can be synthesized with a pseudorandom
frequency. Because the proposed random carrier R
is made from the two triangular waveforms with
same fixed frequency, but of opposite phase, the
me is named pseudorandom carrier
Figure 3: Detailed waveforms of Pseudorandom carrier
Generation
Figure 3 shows the detail waveforms of the
proposed method in Figure. 1 the output P of the
PRBS random bits generator is similar to the
conventional random leadlag PWM. The random
leadlag PWM is the early version among random
PWM, and its pulses are randomly placed between
first position and last position in the modulation
interval.
Figure 4: Simulated waveforms of generated Pseudo
random carrier using 2 kHz carriers C and C
The modulation is done using phase shifted
Pseudorandom carriers and sinusoidal reference
signal. Figure 5 shows the phase shifted
pseudorandom carrier with sinusoidal reference
signal. For 9-level inverter output 8
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Figure 3: Detailed waveforms of Pseudorandom carrier
Figure 3 shows the detail waveforms of the
proposed method in Figure. 1 the output P of the
PRBS random bits generator is similar to the
lag PWM. The random
lag PWM is the early version among random
PWM, and its pulses are randomly placed between
first position and last position in the modulation
Figure 4: Simulated waveforms of generated Pseudo-
dom carrier using 2 kHz carriers C and C
The modulation is done using phase shifted
Pseudorandom carriers and sinusoidal reference
signal. Figure 5 shows the phase shifted
pseudorandom carrier with sinusoidal reference
level inverter output 8 carriers (A to
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H) are required to produce 4 pairs of PWM signals
for four H-Bridges as shown in figure 6. A & B
pulses are used for bridge1, C & D pulses are used
for bridge2, E & F pulses are used for bridge3 and
G & H pulses are used for bridge4. For 5-level
inverter output 4 carriers are enough to produce 2
pairs of PWM signals for two H-Bridges. The
carrier frequency is increased to get less distorted
quality output. Here carrier frequency is selected as
2kHz and 4kHz for comparison. The
Pseudorandom PWM signals are used as switching
signals for cascaded multilevel inverter switches
which gives the output of 9-level, 50Hz, 170 Vrms.
This output voltage used to drive the 5HP
Capacitor Start Induction Motor. The multilevel
inverter output voltage is subjected to FFT analysis
for the calculation of THD and to determine
harmonic spectra.

Figure 5: Simulated phase shifted Pseudorandom carriers
with sine wave
II. SIMULATED
EXPERIMENTALSYSTEM
Multilevel inverter is used for the verification
of PRPWM Technique. H-Bridge MLI is
selected for the experimental setup. Figure 6
shows the experimental setup of a 170-Vrms
single phase HBML inverter based on the
proposed method. The insulated-gate bipolar
transistors (IGBTs) are chosen as the switching
devices of H-bridge inverters. A switched-
mode power supply (SMPS) (Vd= 60 V) are
adopted as dc voltage sources of each H-bridge
inverters (cell inverters). The resultant voltage
(V0 = 170Vrms) is synthesized by adding the
output voltages (V1,V2,V3,V4) of each H-
bridge inverters, and it supplies to 5HP
Capacitor Start Induction Motor. A cascade
connection of four H-bridge inverters produced
a nine-level output waveform. For isolation of
each H-bridge inverters and load, a coupling
transformer with winding ratio 1:1 is
employed.

Figure 6: Single phase Cascaded Multilevel Inverter
In general, the switching frequency of random
PWM scheme for dc-to-ac inverter is below 5
kHz. Hence, the carrier frequency of the
proposed scheme is selected as 2 kHz and
4kHz. Figure 2 illustrates the configuration of
the proposed pseudorandom carrier generator.
As shown in Figure 2, a triangular carrier
waveform with fixed frequency and clock
pulses for PRBS random bit generator are
generated. The PRBS random bits generator is
implemented, using a shift register and an
EXCLUSIVE OR.

Figure 7: Simulated Experimental System
The bidirectional switch is employed as a
multiplexer, and it generates the pseudorandom
frequency carrier R. To apply it to a multilevel
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inverter, the resultant carrier R is arranged for
phase disposition, where four carriers (R1
~R4) are in phase, as shown Figure 5. The
PWM pulses (1-cell ~4-cell) of each HBML
inverters can be obtained by comparison a
reference sinusoidal waveform with the phase-
disposition arrangement of eight
pseudorandom carriers. The output of the
inverter is applied to the 5HP Capacitor Start
Induction Motor. Figure 7 shows the simulated
circuit using MATLAB/SIMULINK.
IV. SIMULATION RESULTS
The generated Pseudorandom PWM is used for
multilevel inverter switching which gives the
output voltage of 170 Vrms as shown in Figure
8. The output of the multilevel inverter drives
the 5HP Induction motor. Figure 9 illustrates
the harmonic spectra analysis for the MLI
output voltage using Figure 9(a). SPWM
Technique and Figure 9(b). PRPWM
Technique with 12 bit LFSR and 4kHz Carrier
Frequency. The result shows the best
performance than conventional.

Figure 8: H-Bridge 9-level inverter output voltage


(a)

(b)
Figure 9: Harmonic Spectrum of MLI output voltage
using (a). SPWM Technique, (b). PRPWM Technique
with 12 Bit LFSR and 4kHz Carrier
Here it shows that it has four bridges, those are
having separate DC sources, every bridge having
four controllable switches and the pulses for the
controllable switches. Every separate DC sources
giving +60V inputs to the bridges. The pulse
generation for those switches are explained in the
above chapters. The output of the individual
bridges is shown in figure 6. The 9-level output
voltage waveform is shown in figure 8. The RMS
voltage of the multilevel inverter output voltage is
about 170Vrms.
The output of the inverter is used to feed Induction
Motor of rating 5HP, 240V, 50Hz. The
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Methods Enriching Power and Energy Development (MEPED) 2014 134 | P a g e


performance of Induction Motor is shown in fig 10.
The Induction Motor performance parameters are
a).Main winding current (amp), b).Auxiliary
winding current (amp), c). Capacitor Voltage
(volts), d).Electromagnetic Torque (Nm), e). Rotor
Speed (rpm).

TABLE 2: Comparative Study of Harmonics In MLI
Output Voltage For Different PWM Techniques

Conventio
nal Method
(SPWM)
Pseudorandom PWM
8bits 12bits
2kHz 2kHz 4kHz 2kHz 4kHz
V
rms
182.5V
178.4
V
169.7
V
169.8
%
169.7
V
V
Pea
k

258.1V
252.3
V
240V
240.1
%
240V
TH
D
11.78%
6.87
%
7.69
%
7.56%
7.69
%
H
3
3.88%
1.89
%
0.02
%
0.05%
0.03
%
H
5
2.36%
1.73
%
0.01
%
0.05%
0.02
%
H
7
1.38%
0.97
%
0.03
%
0.03%
0.05
%
H
9
0.47%
0.49
%
0.06
%
0.11%
0.02
%
H
11
0.42%
0.32
%
0.06
%
0.05%
0.04
%
H
13
0.34%
0.20
%
0.05
%
0.17%
0.05
%
H
15
1.21%
0.28
%
0.00
%
0.10%
0.02
%
H
17
1.81%
0.11
%
0.02
%
0.07%
0.04
%
H
19
0.91%
0.06
%
0.04
%
0.25%
0.15
%



Figure 10: Performance of Induction motor driven with
9-level Inverter
V. CONCLUSION
In this paper, the simulation of the proposed
method is quite simple and it has the merit that the
random carrier can be generated from fixed
frequency carrier. A pseudorandom frequency
carrier scheme has been proposed as a new method
to generation a random carrier. The proposed
scheme produces the pseudo triangular carrier
waveform with the random frequency through the
random composition of the two triangular carriers,
each of the same fixed frequency but of opposite
phase. The random composition of two triangular
carriers can be done through multiplexer with the
help of pseudorandom bit sequence generated by
the 2kHz Linear Feedback Shift Register. The
pseudorandom carriers are used to produce the
PWM pulses for the 170-Vrms single-phase 9 level
HBML inverter. The multilevel inverter has four H-
bridges which are having input of 60V DC in
individual H-bridges. For the PWM generation
pseudorandom carriers and sinusoidal signals were
used. The multilevel inverter output is used to drive
the 5HP Induction motor. The pseudorandom
PWM technique is done for the different
configurations such as Pseudorandom PWM
technique with 8bit shift register and 2 KHz carrier
frequency, Pseudorandom PWM with 8bit shift
register and 5 KHz carrier frequency,
Pseudorandom PWM 12bit shift register and 2 KHz
carrier frequency and Pseudorandom PWM 12bit
shift register and 5 KHz carrier frequency. The
harmonic distortion of multilevel inverter voltage
for these configurations are studied and compared.
From the analysis the Pseudorandom PWM with
8bit shift register, 2 KHz carrier frequency shows
the improved results when we taking multilevel
inverter output voltage. If we took lower order
harmonics redution as a parameter for analysis,
PWM with 8bit shift register, 5 KHz carrier
frequency shows the improved results. Finally, the
proposed random carrier generator is simulated
using MATLAB/SIMULINK, the proposed scheme
can be applicable to the existing power electronics
converters by changing the fixed switching
frequency triangular carrier generator into the
proposed random carrier generator.
REFERENCES
International Journal for Research and Development in Engineering (IJRDE)
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Methods Enriching Power and Energy Development (MEPED) 2014 135 | P a g e



[1] Young-Cheol Lim, Seog-Oh Wi, Jong-Nam Kim, and
Young-Gook Jung, A Pseudorandom Carrier
Modulation Scheme, IEEE transactions on power
electronics, vol. 25, no. 4, april 2010
[2] F.Mihalic and D. Kos, Reduced conductive EMI in
switched-mode dc-dc power converters without EMI
filters: PWM versus randomized PWM, IEEE Trans.
Power Electron., vol. 21, no. 6, pp. 17831794, Nov.
2006.
[3] M. M. Bech, J. K. Pedersen, and F. Blaabjerg,
Random modulation techniques with fixed switching
frequency for three-phase power converters, IEEE
Trans. Power Electron., vol. 15, no. 4, pp. 753761, Jul.
2000.
[4] C. M. Liaw and Y. M. Lin, Random slope PWM
inverter using existing system background noise:
Analysis, design and implementation, IEE Proc. Electr.
Power Appl., vol. 147, no. 1, pp. 4554, 2000.
[5] V. Blasko, M. M. Bech, F. Blaabjerg, and K.
Pedersen, A New hybrid random pulse width modulator
for industrial drives, in Proc. IEEE APEC2000, pp.
932938.
[6] S. Y. R. Hui, I. Oppermann, and S. Sathiakumar,
Microprocessor-based random PWM schemes for DC-
AC power conversion, IEEE Trarns. Power Electron.,
vol. 12, no. 2, pp. 253260, Mar. 1997.
[7] K. S. Kim, Y. G. Jung, and Y. C. Lim, A new hybrid
random PWM scheme, IEEE Trans. Power Electron.,
vol. 24, no. 1, pp. 192200, Jan. 2009.
[8] A. M. Hava and E. Un, Performance analysis of
reduced common-mode voltage PWM methods and
comparison with standard PWM methods for three-phase
voltage-source inverters, IEEE Trans. Power Electron.,
vol. 24, no. 1, pp. 241259, Jan. 2009.
[9] D. V. Ghodke, K. Chatterjee, and B. G. Fernandes,
Three-phase three level, soft switched, phase
shiftedPWMDCDC converter for high-power
applications, IEEE Trans. Power Electron., vol. 23, no.
3, pp. 12141227, Jun. 2008.
[10] R. Yang, B. Zhang, D. Qiu, and Z. Liu, Time
frequency and wavelet transforms of EMI dynamic
spectrum in chaotic converter, IEEE Trans. Power
Electron., vol. 24, no. 4, pp. 10831092, Apr. 2009.

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Photovoltaic Based implementation of Coupled Inductor
Interleaved Boost Converter with LC Filter for Ripple Free
Current

S.Tony Richard
1
, R.G.Nirmala
2


1
(M.E Power Electronics and Drives, St. Josephs College of Engineering, India)
2
(Assistant Professor, Department of EEE, St. Josephs College of Engineering, India)


ABSTRACT
This paper presents coupled inductor interleaved boost
converter with LC filter for ripple free current. In
addition to coupled inductor interleaved boost converter
two LC filter and one coupled inductor is added to
proposed circuit. So the proposed converter achieves
reduced input and output current ripple. Hence the
ripple ratio of input and output current is reduced. In
order to verify that, a proposed converter of 20v input
voltage from PV panel and 40v output voltage operating
at 50 khz is constructed. And simulations are verified by
using MATLAB Simulink. So the ripple free proposed
circuit is used for various photovoltaic generation
purpose.


Key words Coupled inductor,dc-dc converter, Mutual
inductance
1. INTRODUCTION
Nowadays, boost converter is used in most of the
photovoltaic generation application. It uses PV panel as a
electrical source. Here input current has more ripple, which
is directing from the PV panel is a major problem in dc-dc
boost converter.
The input current ripple of the dc-dc converter is
inversely proportional to input inductor current value. So the
larger inductor value results in low ripple, on other
increasing the inductor value the total weight of the
converter gets increased [1-3]. The proposed converter aims
that without increasing the inductor value the ripple should
be reduced. So that interleaving of the converter technique is
used. By using interleaving technique the ripple is reduced
but the weight of the converter is not reduced.
So that the new technique called coupled inductor
interleaved boost converter technique is used. Here the
ripple is reduced than interleaving technique and the weight
of the converter is reduced since the core is shared, and
inductor was coiled in single core [4-5]. However, the
leakage inductance of the coupled inductor increases the
current stress of the output diodes. The soft switching
technique is the solution for this type of the problem but
however, the control strategy of this circuit is too complex
and not cost-effective.
In order to overcome the disadvantage of
conventional converters, the new topology called coupled
inductor interleaved boost converter with LC filter is
developed. This converter uses two coupled inductor and
two LC filter connected series to the coupled inductor. Here
the LC filter is used to eliminate di / dt and gives ripple free
input and output current.



Fig.1 PV Panel



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Fig.1 Proposed Coupled inductor interleaved boost converter
with LC Filter
II. COUPLED INDUCTOR INTERLEAVED
BOOST CONVERTER AND ITS OPERATING
PRINCIPLE
If the two inductors were coupled together, the input
and output current ripple can be reduced than interleaved
boost converter. We can get high power density because of
using only one core. The coupled inductor interleaved boost
converter has same switching sequence as the conventional
converter. However, the leakage inductance of the coupled
inductor increases the current stress of the output diodes,
introducing extra electromagnetic interference (EMI)
problems ,the circuit is simplified into two typical stages and
the corresponding equivalent circuits is shown below


Fig.2 Coupled inductor interleaved boost converter

Mode 1 [ t0, t1 ]:At t0, S1 turns ON and switch S2 turns
OFF. During this period, the inductor L1 linearly charged by
the input voltage. Due to this IL1 increases linearly. Due to
reverse bias condition Do1 maintains OFF stage, because of
the voltage stress across the diode is equal to the output
voltage. Meanwhile the energy stored in the inductor L2
gets transferred to load Ro, because of the coupled relation
between two inductor ,the current IL2 decreases more.



Fig.3 Mode 1

Mode 2 [ t1 , t2 ]:At t1.both switches S1 and S2 are in
OFF state ,meanwhile the energy from inductor L1 and L2
gets transfer to the load Ro. So the current across the
inductor IL1 and IL2 decreases linearly. During this the
voltage across the switch S1 and S2 equals to the output
voltage .In this mode the coupled inductor branches still
work as a filter to minimize the input and output current
ripple.



Fig.4 Mode 2

Input current ripple is given by

2 2. .

.


Input ripple current is given by

2 15 10

2 10.605 10

. 36 10.605 10

15 10

. 50
15 10

10.605 10


40 20
40
. 10


.

Input ripple current ratio is given by

*100


.

*100
. %
Output ripple current is given by
.

Output ripple current ratio is given by

*100


.
.
*100
. %

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III.COUPLED INDUCTOR INTERLEAVED
BOOST CONVERTER WITH LC FILTERAND
ITS OPERATIONAL PRINCIPLE

Mode 1 [ t0, t1 ]:At t0, S1 turns ON and switch S2 turns
OFF. During this period, the inductor L1 linearly charged by
the input voltage. Due to this IL1 increases linearly. Due to
reverse bias condition Do1 maintains OFF stage, because of
the voltage stress across the diode is equal to the output
voltage. Meanwhile the energy stored in the inductor L2 gets
transferred to load Ro, because of the coupled relation
between two inductor, the current IL2 decreases more. Due
to this the zero current rippleis achieved.


Fig.5 Mode 1


Equations



Mode 2 [ t1 , t2 ]: At t1.both switches S1 and S2 are in
OFF state ,meanwhile the energy from inductor L1 and L2
gets transfer to the load Ro. So the current across the
inductor IL1 and IL2 decreases linearly. During this the
voltage across the switch S1 and S2 equals to the output
voltage .In this mode the coupled inductor branches still
work as a filter to minimize the input and output current
ripple



Fig.6 Mode 2

Equations



Here,Input ripple current is given by

.

1 2
0.98515 10

15 10


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5.395 10

2 10

3.4 10

2 36 50
5.395 10

15 10

2 10

15 10

3.4 10




40 20
40
. 10



Input ripple current is given by
0.25A

Input ripple current ratio is given by



0.25
10

. %

Output ripple current is given by
0.0015A

Input ripple current ratio is given by



0.0015
2.38

. %

IV. SIMULATION RESULTS

A 20v-40v proposed dc-dc converter operating at
50 khz switching frequency is designed and simulated to
verify the proposed concept. Simulations of the proposed
converter are carried out in MATLAB and the key
parameters are listed in Table I. Duty cycle of each
converter is 0.5. Here the PV panel also simulated by using
SIMULINK. And the output of the PV panel is about 20V
dc voltage. Which are used as a input source to proposed
converter.




Fig.7 Matlab Simulation diagram of PV Panel



Fig.8Matlab Simulation diagram of conventional converter

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Fig.9 Matlab Simulation diagram of proposed converter





Fig.10 PV Panel output voltage waveform


Fig.11 Conventional converter-Input current ripple waveform




Fig.12 : Conventional converter-Output current ripple
waveform




Fig.13 Proposed converter-Input current ripple waveform
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Fig.14 Proposed converter-Output current ripple waveform

Table I: Input parameters

S.No Parameters Value
1 Input voltage (

20 V
2 Output voltage (

40 V
3 Switching frequency (

) 50 Khz
4 Main Inductor

15 H
5 Coupled inductor (
,

) 2 H
6 Inductor (

3.4H
7 Coupling coefficient (K) 0.985
8 Capacitor (

10 F
9 Output capacitor (

470 F





































Table II: Simulation output summary


V. CONCLUSION

It is concluded that, the proposed converter achieves
huge reduction of input current ripple. Which are from PV
panel connected to dc-dc converter.In addition to that the
load side output current ripple also reduced. At last, a 20v
input40v output PV type prototype circuit is implemented
to verify the expected performance. The simulation and
experimental results shows that the proposed converter
achieves input and output current ripple reduction than
conventional one. It shows that the proposed converter has
great potential to be used in photovoltaic generating system.

VII.REFERENCES

S
.
N
O
PARAMETERS
COUPLED
INDUCTOR
INTERLEA
VED BOOST
CONVERTE
R
COUPLED
INDUCTO
R
INTERLE
AVED
BOOST
CONVERT
ER WITH
LC
FILTER
1
INPUT CURRENT
RIPPLE (A)
2.9 0.25
2
INPUT CURRENT
RIPPLE RATIO
(%)
20.71 2.5
3
OUTPUT
CURRENT RIPPLE
(A)
0.00166 0.0015
4
OUTPUT
CURRENT RIPPLE
RATIO (%)
0.0877 0.063
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1. J. R. Pinheiro, H. A. Grundling, D. L. R. Vidor, and J. E.
Baggio,Control strategy of an interleaved boost power factor
correction converter, in Proc. IEEE Power Electron. Spec. Conf.,
1999, pp. 137142

2. M. Pahlevaninezhad, P. Das, J. Drobnik, P. K. Jain, and A.
Bakhshai, AZVS interleaved boostAC/DC converter used in plug-
in electric vehicles, IEEE Trans. Power Electron., vol. 27, no. 8,
pp. 35133529, Aug. 2012.

3. Y. Jang and M. M. Jovanovic, Interleaved boost converter with
intrinsic voltage-doubler characteristic for universal-line PFC front
end, IEEE Trans. Power Electron., vol. 22, no. 4, pp. 13941401,
Jul. 2007.

4. S. Park, Y. Park, S. Choi, W. Choi, and K. B. Lee, Soft-
switched Interleaved boost converters for high step-up and high-
power applications, IEEE Trans. Power Electron., vol. 26, no. 10,
pp. 29062914, Oct. 2011.

5. R. Martinelli and C. Ashley, Coupled inductor boost converter
with input and output ripple cancellation, in Proc. Appl. Power
Electron. Conf. Expo., 1991, pp. 567572

6. Y. Hu,Y.Xie, H. Tian, and B. Mei, Characteristics analysis of
two channel interleaved boost converter with integrated coupling
inductor, in Proc.IEEE Power Electron. Spec. Conf., Jun. 2006,
pp. 16.





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Power Quality Issues, Problems and
Solution: Special Feature

Vipul Kumar
1
, Om Shivam
2
, Raj Kumar Sharma
3
, Tanmaya Kumar Patel
4
*EEE, Dr. M.G.R. Educational and Research Institute, University, Maduravoyal, Chennai- 95, TamilNadu,
India



ABSTRACT
This paper outlines the power quality problems,
issues and its solution. The Power generation
industry is undergoing major changes and
increasingly power quality is at the forefront.
Industry as a whole is concerned about the
reliability of supply, whether it is disturbances,
interruptions or major outages to be able to
manage the power quality. Power quality is an
issue that is becoming increasingly important to
electricity consumers at all levels of usage.
Sensitive equipment and non-linear loads are now
more commonplace in both the
industrial/commercial sectors and the domestic
environment. Because of the power quality issues
now days affecting the electricity supply that were
once considered acceptable by electricity
companies and users are now often considered a
problem to the users of everyday equipment. In
solution part some of the method related
international standards, the effect of power quality
problems and methods to improve the power
quality problems.

Keywords: IEEE 519, Power quality problems,
Voltage Sag, Harmonics, International Electrical
Standards.

I. INTRODUCTION
This paper analyzes the key issues in the Power
Quality [27] [28] problems [1] [2], especially the
present trend towards more distributed generations and
consequent restructuring of power transmission and
distribution networks. As the prominent power quality
problems [3] are Voltage sags and harmonics. The
origin, consequences and mitigation techniques of
voltage sag and harmonics problems have been
discussed in detail [1]. Sag is defined as the variation
of RMS voltage from its normal value for a time
greater than 0.5 cycles of the power frequency but less
than or equal to 60 seconds. Short duration variation is
caused by fault conditions, the energization of large
loads which requires high starting current. Harmonics
are a sinusoidal component of a periodic wave or
quantity having a frequency that is an integral multiple
of the fundamental power frequency. The equation
representing a harmonic frequency is f
h
= f
1
* h.
Harmonic distortion exists due to the nonlinear
characteristics of the devices and loads on the power
system, these devices act as current sources that inject
harmonic currents into the power system. Important
Power quality standards are defined in the IEEE, IEC,
CENELEC, ANSI, and NER. The most universally
accepted standards for power quality are IEC and IEEE
standards. For research purposes, the flexibility and the
ability of easy prototyping are often more crucial
aspects than computational efficiency.

A. Power Quality Problems & Issues:
In recent survey says that the 50% of all Power
Quality problems are related to grounding, ground
bones, and neutral to ground voltages, ground loops,
ground current or other ground associated issues.
Electrically [2] [3] [6] [9] [27] operated or connected
equipment is affected by Power Quality. The
commonly used terms those describe the parameters of
electrical power that describe or measure power
quality are Voltage sags, Voltage variations,
Interruptions [16][17][18][19] Swells, Brownouts,
Blackouts, Voltage imbalance, Distortion, Harmonics,
Harmonic resonance, Inter harmonics, Notching,
Noise, Impulse, Spikes (Voltage), Ground noise,
Common mode noise, Critical load, Crest factor,
Electromagnetic compatibility, Dropout, Fault,
Flicker, Ground, Raw power, lean ground, Ground
loops, Voltage fluctuations,
Transient[4][8][10][24][30], Dirty power, Momentary
interruption, Over voltage, Under voltage, Nonlinear
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load, THD, Trip lens, Voltage dip, Voltage regulation,
Blink, Oscillatory transient[26][36] etc. The
distortion in the quality of supply power can be
introduced /enhanced at various stages; however,
some of the primary sources of distortion
[1][2][3][23][27][28] can be identified as below:
i. Power Electronic Devices
ii. IT and Office Equipments,
iii. Arcing Devices,
iv. Load Switching,
v. Large Motor Starting,
vi. Embedded Generation,
vii. Electromagnetic Radiations and Cables,
viii. Storm and Environment Related Causes etc.

While power disturbances occur on all electrical
systems [4][7][23], the sensitivity of todays
sophisticated electronic devices makes them more
susceptible to the quality of power supply [2] [3]. A
power voltage spike can damage valuable components.
Some of the common power quality issues [19] [25]
and their prominent impact are summarized in the table
1 below:

Table 1: Various power quality problems, causes
and their effects
Problems Causes Effects
Voltage
Sags
Faults in the
transmission or
distribution
network.
Connection of
heavy loads or
motors.
Tripping of contractors
and electromechanical
relays, Disconnection
and loss of efficiency in
electric rotating
machines, etc.
Voltage
Spikes
Lightning,
Switching of lines
or power Factor
correction
capacitors,
removing of
heavy loads.
Destruction of
components and of
insulation materials,
Data processing errors
or data loss,
Electromagnetic
interference, etc.
Voltage
Swells
Start/stop of
heavy loads,
Poorly
dimensioned
power sources,
Poorly regulated
transformers.
Flickering of lighting
and screens, Damage or
stoppage or damage of
sensitive equipment, etc.
Voltage
fluctuation
Arc furnaces,
Frequent start/stop
of electric Motors
Most consequences are
common to under
voltages, Flickering of
(for instance
elevators),
oscillating loads.
lighting and screens, etc.
Voltage
Unbalance
Large 1 phase
loads (induction
furnaces, traction
loads), Incorrect
distribution of
loads by The three
phases of the
system.
The most affected loads
are three phase
induction machines,
Increase in the losses,
etc.
Harmonic
Distortion
Switched mode
power supply,
Fluorescent
lighting, 3-phase
rectifier,
Adjustable speed
drive
Conductor overheating,
Neutral overloads,
Increased probability of
occurrence of resonance,
Nuisance tripping of
thermal protections,
Loss of efficiency in
electric machines, etc.

B. Power Quality Standards:

Power quality [27] is a worldwide issue [17] [18] [20],
and keeping related standards current is a never-
ending task. It typically takes years to push changes
through the process. Most of the ongoing work of the
IEEE in harmonic standards [3] [20] [23] [30]
development has shifted to modifying Standard 519-
1992.

1. IEEE 519
i. IEEE 519 Standards for Current
Harmonics.
ii. IEEE Standard for Voltage Harmonics.

2. IEC 61000-3-2 and IEC 61000-3-4 (formerly
1000-3-2 and 1000-3-4).
i. IEC 61000-3-2 (1995-03)
ii. IEC/TS 61000-3-4 (1998-10
3. IEEE Standard 141-1993, Recommended
Practice for Electric Power Distribution for
Industrial Plants.
4. IEEE Standard 142-1991, Recommended
Practice for Grounding of Industrial and
Commercial Power Systems.
5. IEEE Standard 446-1987, Recommended
Practice for Emergency and Standby Power
Systems for Industrial and Commercial
Applications.
6. IEEE Standard 493-1997, Recommended
Practice for Design of Reliable Industrial and
Commercial Power Systems.
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Methods Enriching Power and Energy Development


7. IEEE Standard 1100-1999, Recommended
Practice for Powering and Grounding Sensitive
Electronic Equipment.
8. IEEE Standard 1159-1995,
Practice for Monitoring Electric Power Quality.
9. IEEE Standard 1250-1995, Guide for Service to
Equipment Sensitive to Momentary Voltage
Disturbances.
10. IEEE Standard 1346-1998 Recommended
Practice for Evaluating Electric Power System
Compatibility with Electronic Process
Equipment.
11. Standards related to Voltage Sag and Reliability.
12. Standards related to Flicker.
13. Standards related to Custom Power.
14. Standards related to Distributed Generation.

II. SOLUTION TO POWER Q
PROBLEMS
Power quality problems [3] [5] [13] [16] [
basically start at four levels of the system that delivers
electric power, first one, includes Power plants and the
entire area transmission system. The second one is
Transmission lines, major substations where as third
one includes distribution substations, primary [17]
[18], and secondary power lines, and distribution
transformers and last and fourth one includes service
equipment and building wiring.


Figure 1: Present Power system components end to end
(generation to household user).

Their performance of the devices depends on the
power rating and the speed of response.
However, with the restructuring of the power
sector and with the shifting trend towards
distributed and dispersed generation, the line
conditioning systems or utility side solutions will
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ISSN: 2279-0500 Special Iss
Methods Enriching Power and Energy Development (MEPED) 2014
1999, Recommended
Practice for Powering and Grounding Sensitive
1995, Recommended
Practice for Monitoring Electric Power Quality.
1995, Guide for Service to
Equipment Sensitive to Momentary Voltage
1998 Recommended
Practice for Evaluating Electric Power System
with Electronic Process
Standards related to Voltage Sag and Reliability.
Standards related to Custom Power.
Standards related to Distributed Generation.
QUALITY
problems [3] [5] [13] [16] [19] can
basically start at four levels of the system that delivers
electric power, first one, includes Power plants and the
entire area transmission system. The second one is
Transmission lines, major substations where as third
ibution substations, primary [17]
], and secondary power lines, and distribution
transformers and last and fourth one includes service

Figure 1: Present Power system components end to end
to household user).
Their performance of the devices depends on the
power rating and the speed of response.
However, with the restructuring of the power
sector and with the shifting trend towards
distributed and dispersed generation, the line
conditioning systems or utility side solutions will
play a major role in improving
supply quality [21] [10]; some of the effective
and economic measures can be identified as
summarized in the below:

Proper designing of the Load equipment.
Application of passive, active and hybrid
harmonic filters.
Proper designing of the power supply
system
Application of voltage compensators.
Use of uninterruptible power supplies
(UPSs)
Reliability of standby power
Constant Voltage Transformers
Grid Adequacy
Lightening and Surge Arresters
Electronic tap changing transformer
Thyristor Based Static Switches
Distributed Generation (DG)
Reciprocating engines
Micro turbines
Fuel Cells
Energy Storage (restoring technologies)
Electrochemical batteries
Flywheels
Super capacitors
SMES (Superconducting Magnetic
Energy Storage)
Compressed air
The various power quality disturbances as shown
table 2 and suitable mitigating devices are
tabulated below:

Table 2 : Power Quality disturbances with mitigating
equipments.
Type
of
Equip
ments
Types of Disturbances
Tr
an
sie
nt
S
a
g
S
w
ell
Inte
rru
ptio
n
Dist
orti
on
(Ha
rmo
nics)
Surge
Suppr
essor
Ye
s
N
o
N
o
No No
Filter No N N No Yes
International Journal for Research and Development in Engineering (IJRDE)
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145 | P a g e
play a major role in improving the inherent
]; some of the effective
and economic measures can be identified as
Proper designing of the Load equipment.
Application of passive, active and hybrid
Proper designing of the power supply
Application of voltage compensators.
Use of uninterruptible power supplies
Reliability of standby power
Constant Voltage Transformers

Lightening and Surge Arresters
Electronic tap changing transformer
Thyristor Based Static Switches


Energy Storage (restoring technologies)
Superconducting Magnetic
The various power quality disturbances as shown
table 2 and suitable mitigating devices are
Table 2 : Power Quality disturbances with mitigating
Types of Disturbances
Fli
ck
er
N
oi
se
Fre
que
ncy
De
via
tio
ns
No
N
o
No
No Y No
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Methods Enriching Power and Energy Development (MEPED) 2014 146 | P a g e



o o es
Isolati
on
Transf
ormer
Ye
s
N
o
N
o
No No No
Y
es
No
Voltag
e
Regul
ator
No
Y
e
s
Y
es
No No No
N
o
No
Power
Condit
ioner
Ye
s
Y
e
s
Y
es
No No No
N
o
No
UPS
Ye
s
Y
e
s
Y
es
Yes Yes
Ye
s
Y
es
Yes
SPS No
N
o
N
o
Yes No No
N
o
No

III. COMMON PROBLEMS
Define After studying the paper I got the most the
common problems in the power system is voltage sag
[16] and harmonics [17] [18] [19] [21].
A. Voltage sags
By IEEE, is a reduction in voltage for a short time
.The voltage reduction magnitude is between 10%and
90% of the normal root mean square voltage at
50Hz/60Hz. Voltage sags is the most common type of
power quality disturbance in the distribution system. It
can be caused by a fault in the electrical network or by
the starting of a large induction motor. The available
voltage sag mitigation devices described below.

Reactive power compensation principle
compensator.
Shunt Compensation.
Series Compensation
Traditional VAR generators.
Fixed or mechanically switched
capacitors.
Synchronous Condensers
Thyristorized VAR Compensators
Self Commuted VAR Compensators.
Commuted VAR Compensators
Semiconductor Devices used for
Self-Commutated VAR
Compensators.
Comparison between Thyristorized
and Self commutated Compensators.
New VAR Compensators Technology
Static Synchronous Compensator
(STATCOM).
Static Synchronous Series
Compensator (SSSC).
Dynamic Voltage Restorer (DVR)
Unified Power Flow Controller
(UPFC).
Interline Power Flow Controller
(IPFC)
Superconducting Magnetic Energy
Storage (SMES)
VAR Generation Using Coupling
Transformers.
i. Comparison between Thyristorized and
Self Commuted Compensators

As compared with thyristor - controlled capacitor [12]
and reactor banks, self-commutated VAR
compensators have the following advantages and
summarize the comparative merits of the main types
of VAR compensators [14] [24] [26]. The significant
advantages of self commutated compensators [28] as
tabulated in table 3 make them an interesting
alternative to improve compensation [29]
characteristics and also to increase the performance of
AC power systems.
Table 3: Comparison of Basic Types of
Compensators [25].

Synchro
nous
Conden
ser
Static Compensator

Self
commu
tated
Compe
nsator
TCR
(with
shunt
Capacito
rs if
Necessar
y)
TSC
(with
TCR if
Necessar
y)
Accura
cy of
Compe
nsation
Good
Very
Good
Good,
very
good
With
TCR
Excelle
nt
Control
Flexibil
ity
Good
Very
Good
Good,
very
good
With
TCR
Excelle
nt
Reactiv
e Power
Capabil
ity
Leading/
Lagging
Lagging/
Leading
Indirect
Leading/
Lagging
Indirect
Leading
/Laggin
g
Control
Continu
ous
Continuo
us
Discontin
uous
(cont.
Continu
ous
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Methods Enriching Power and Energy Development (MEPED) 2014 147 | P a g e



With
TCR)
Respon
se Time
Slow
Fast, 0.5
to 2
cycles
Fast, 0.5
to 2
cycles
Very
fast but
depends
on the
control
system
and
switchin
g
frequen
cy
Harmon
ics
Very
Good
Very
high
(larger
size
filters are
needed)
Good,
filters are
Necessar
y with
TCR
Good,
but
depends
on
switchin
g
pattern
Losses
Moderat
e
Good,
but
increase
in
lagging
mode
Good,
but
increase
in
leading
mode
Very
good,
but
Increase
with
Switchi
ng
frequen
cy
Phase
Balanci
ng
Ability
Limited Good Limited
Very
good
with 1-f
units,
limited
with 3-f
units
Cost High Moderate Moderate
Low to
moderat
e

B. Harmonics
It is a sinusoidal component of a periodic wave or
quantity having a frequency that is an integral
multiple of the fundamental power frequency.
Available solution for harmonizing:
Passive filters
Active filters
Active Series
Active Shunt
Hybrid of Active Series and Passive
Shunt
Hybrid of Active Shunt and Active
Series
The different types of filters [6] [9] [11] [12] [15] its
various applications and differentiate as per the
preferable filter are tabulated below in table 4:

Table 4: Active filter's for compensation in order of
preference. Active filters Configuration with higher number
of * is more preferred.
S. no
Compensati
on for
particular
Application
Active Filters
Acti
ve
Seri
es
Act
ive
Shu
nt
Hyb
rid
of
Acti
ve
Seri
es
and
Pass
ive
Shu
nt
Hyb
rid
of
Acti
ve
Shu
nt
and
Acti
ve
Seri
es
I.
Voltage
Harmonics
**
*

*
*
*
II.
Current
Harmonics

*
*
*
*
*
*
III.
Reactive
Power

*
*
*
*
*
*
IV.
Load
Balancing

*

V.
Voltage
Regulation
**
*
*
*
*
*
VI.
Neutral
Current

*
*
*

VII.
Voltage
balancing
**
*

*
*
*
VIII.
Voltage
Flicker
**
*
*
*

*
IX.
Voltage Sag
& Dips
**
*
*
*
*
*
X.
Current
harmonics
&
Reactive
power

*
*
*
*
*
*
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Methods Enriching Power and Energy Development







Figure.2. sample labels of electrical household
equipments. (Source BEE)

IV. CONCLUSION

The Power quality is important in all the area
well-defined field with rising interest being shown in
the solutions to problems, equipment, regulations and
statistical analysis of customers expected levels of
disturbance. Due to rising non-linear load
harmonic problems are increased. This paper deals the
important universal power quality standard. Power
quality measures can be applied both at the user end
and also at the unity level. The equipment to
the power quality issues. This paper wi
beginners to understand the power quality.
REFERENCES
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Methods Enriching Power and Energy Development (MEPED) 2014

Figure.2. sample labels of electrical household
equipments. (Source BEE)


Power quality is important in all the areas. It is
defined field with rising interest being shown in
the solutions to problems, equipment, regulations and
statistical analysis of customers expected levels of
linear loads the
his paper deals the
important universal power quality standard. Power
quality measures can be applied both at the user end
equipment to improve
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beginners to understand the power quality.
Haddad, Ambrish
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[7] I. Takahashi, "A flywheel energy storage system
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[9] F. Z. Peng, H. Akagi, and A. Nabae, "A study of
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[12] P. Enjeti, W. Shireen, and I. Pitel
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[13] K. K. Sen and A. E. Emanuel, "Unity power
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[14] A. Alexandrovitz, A. Yair, and E. Epstein,
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[15] J. Uceda, F. Aldana, and P. Martinez
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[16] T. J. E. Miller, Reactive Power Control in
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[17] J. S. Subjak Jr. and J. S. Mcquilkin, "Harmonics
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vol. 6, pp. 1690-
H. Akagi, Y. Tsukamoto, and A. Nabae,
"Analysis, design of an active power filter using
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I. Takahashi, "A flywheel energy storage system
having distorted power compensation," in Proc.
1083.
H. Akagi, Y. Tsukamoto, and A. Nabae,
design of an active power filter using
series voltage source PWM converters,"
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J. C. Wu and H. L. Jou, "A new UPS scheme
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J. H. Choi, G. W. Park, and S. B. Dewan,
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[19] IEEE Working Group on Power System
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[20] Orr J. A., and Eisenstein B.A., Summary of
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1994, pp. 131-135.
[21] Carnovale, Daniel J., Price and Performance
Considerations for Harmonic Solutions. Power
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[22] Ching-Yin Lee, Wei-Jen Len, Yen-Nien Wang
and Jyh-Cheng Gu, Effects of Voltage
Harmonics on the Electrical and Mechanical
Performance of a Three-phase Induction Motor,
IEEE, 1998.
[23] M. H. J. Bollen, Understanding Power Quality
ProblemsVoltage Sags and Interruptions
Piscataway, New York: IEEE Press, 2000.
[24] M.H.Haque Compensation of distribution
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Power Tech Proceedings, 2001 IEEE Porto ,
Volume: 1 , 10-13 Sept. 2001 Pages:5 pp. vol.1
[25] F. Z. Peng, H. Akagi, and A. Nabae,
Compensation characteristics of the combined
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[26] N.G. Hingorani and L. Gyugyi, Understanding
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[27] John Stones and Alan Collinsion Introduction to
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[28] Ray Arnold Solutions to Power Quality
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[29] J. W. Dixon , Y. del Valle, M. Orchard, M.
Ortzar, L. Morn and C. Maffrand, A Full
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Methods Enriching Power and Energy Development (MEPED) 2014 150 | P a g e




An Efficient Way of Improving Power Quality in Facility
Side Using Modified UPQC (Unified Power Quality
Controller)
M.Balaji
1
V.Dhamodharan
2
K.Veerakavi
3
Department of EEE,VelTechMultiTechDr.RangarajanDr.Sakunthala Engineering College.

ABSTRACT
The main aim of this paper is to improve, the
power quality in the Facility side i.e. in
Distribution side by the help of the Unified
Power Quality Conditioner. The UPQC is a
customer power device, which is used to mitigate
the power quality problems. By the help of the
UPQC, the various power quality concerns such
as voltage sag, swell, harmonics can be
eliminated. In our paper the modified, three
phase four wire distribution is used to control
the reactive power in the line. And also it uses,
the both voltage source inverter which are
connected in back to back manner with the help
of reduced d.c. link capacitor. A detailed
approach for the design of the VSI with
capacitor has been carried out with the help of
the MATLAB Simulink and graphs are shown
and the prototype model also developed.
keywords: customer power device, DC link
capacitor, harmonics, unified power quality
conditioner, voltage source inverter.
I.INTRODUCTION
With the advancement of power electronics and
digital control technology, the renewable energy
sources are increasingly being connected to the
distribution systems [1-4]. On the other hand, with
the proliferation of the power electronics devices
,nonlinear loads and unbalanced loads have
degraded the power quality (PQ) in the power
distribution network. Custom power devices have
been proposed for enhancing the quality and
reliability of electrical power. Unified Power
Quality Conditioner (UPQC) is a versatile custom
power device which consists of two inverters
connected back-to-back and deals with both load
current and supply voltage imperfections. UPQC
can simultaneously act as shunt and series active
power filters. The series part of the UPQC is known
as dynamic voltage restorer (DVR). It is used to
maintain balanced, distortion free nominal voltage
at the load. The shunt part of the UPQC is known
as distribution static compensator (DSTATCOM).
This paper proposes a new topology/structure that
can be realized in UPQC-based applications, in
which the series transformer neutral used for series
inverter, can be used to realize a 3P4W system
even if the power supplied by utility is three phase
three-wire (3P3W) [5-7]. This new functionality
using UPQC could be useful in future UPQC-based
distribution systems. The unbalanced load currents
are very common and yet an important problem in
3P4W distribution system. In case of the UPQC,
the dc-link voltage requirement for the shunt and
series active filters is not the same [8-10]. Thus, it
is a challenging task to have a common dc-link of
appropriate rating in order to achieve satisfactory
shunt and series compensation. The shunt active
filter requires higher dc-link voltage when
compared to the series active filter for proper
compensation [11-13]. In order to have a proper
compensation for both series and shunt active filter,
the researchers are left with no choice rather
common dc-link voltage based on shunt active filter
requirement. The simulation studies are carried out
using MATLAB Simulink, and detailed results are
presented in the paper .prototype of three-phase
UPQC is developed in the laboratory to verify the
proposed concept, and the detailed results are
presented in this paper .
II THREE PHASE FOUR WIRE
DISTRIBUTION SYSTEM
Generally, a 3P4W distribution system is realized
by providing a neutral conductor along with three
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Methods Enriching Power and Energy Development (


power conductors from generation station or by
utilizing a three-phase Y transformer at
distribution level. Fig. 1 shows a 3P4W network in
which the neutral conductor is provided from the
generating station itself, whereas Fig. 2 shows a
Fig 1: 3P4W network with
conductor
III .PROPOSED THREE PHASE UPQC
In this section, the details of the proposed three
phase Unified Power Quality Conditioner
were described. The proposed model consists of
two inverters, which are connected back
manner along with the d.c. link capacitor. It
consists of both the series active filter and the shunt
active filter [13-17]. The Four Wire distribution
system involves four leg to control the VSI in the
circuit, but in this model the fourth leg is avoided,
it can be achieved by the usage of the splitlink
capacitor [18-20]. But the usage of the capacitor
will lead to increase the rating of the capacitor,
since both the series active filter as well as the
shunt active filter needs different rating of the
capacitor. Because the active series filter require
the largest rating of the capacitor while the shunt
active filter requires the low value capacitance. In
our proposed model, the both active and series
filter are combined by the help of the single
capacitor and also the rating of the capacitor also
reduced, the control of the each leg independent
also achieved. By the controlling the leg
independently, the switching frequency get reduce

IV DESIGN OF C
F
FOR PROPOSED
MODEL
The design of the C
f
depends on the value to which
the dc-link voltage is reduced. In general the
with only non-linear components of the current is
International Journal for Research and Development in Engineering (IJRDE)
ISSN: 2279-0500 Special Issue:
Enriching Power and Energy Development (MEPED) 2014
power conductors from generation station or by
Y transformer at
distribution level. Fig. 1 shows a 3P4W network in
which the neutral conductor is provided from the
generating station itself, whereas Fig. 2 shows a
3P4W distribution network considering a
transformer.





with neutral
Fig 2: 3P4W distribution network considering a
transformer
III .PROPOSED THREE PHASE UPQC
In this section, the details of the proposed three
phase Unified Power Quality Conditioner (UPQC)
were described. The proposed model consists of a
two inverters, which are connected back-back
manner along with the d.c. link capacitor. It
consists of both the series active filter and the shunt
. The Four Wire distribution
tem involves four leg to control the VSI in the
circuit, but in this model the fourth leg is avoided,
it can be achieved by the usage of the splitlink
. But the usage of the capacitor
will lead to increase the rating of the capacitor,
e both the series active filter as well as the
shunt active filter needs different rating of the
capacitor. Because the active series filter require
the largest rating of the capacitor while the shunt
active filter requires the low value capacitance. In
r proposed model, the both active and series
filter are combined by the help of the single
capacitor and also the rating of the capacitor also
reduced, the control of the each leg independent
By the controlling the leg
tching frequency get reduce
and the control of the VSI also achieved
effectively. The proposed system works for both
the power quality problems such as voltage sag and
swell. In this topology, the system neutral was
connected to the negative terminal of th
along with the capacitor C
f
in series with the
interfacing inductance of the active shunt filter
passive capacitor C
f
has the capability
apart of there active power required by
and the active filter will compensate
reactive power and the harmonics present
load. The addition of capacitor in series
interfacing inductor of the shunt act
significantly reduce the dc-link voltage requirement
and consequently reduces the average
frequency of the switches.
Fig.3 Modified UPQC
FOR PROPOSED
depends on the value to which
link voltage is reduced. In general the load
linear components of the current is
very rare, and most of the electrical loads are
combination of the linear inductive and non
loads. The design of the value of C
f
the maximum load current, i.e., with
load impedance to ensure that the
will perform satisfactorily at all other
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151 | P a g e
3P4W distribution network considering a Y

3P4W distribution network considering a Y
and the control of the VSI also achieved
effectively. The proposed system works for both
the power quality problems such as voltage sag and
swell. In this topology, the system neutral was
connected to the negative terminal of the dc bus
in series with the
ance of the active shunt filter. The
capability to supply
required by the load,
compensate the balance
harmonics present in the
in series with the
active filter will
oltage requirement
erage switching
UPQC
very rare, and most of the electrical loads are
combination of the linear inductive and non-linear
f
is carried out at
with the minimum
that the designed C
f
all other loading
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Methods Enriching Power and Energy Development (MEPED) 2014 152 | P a g e



conditions. If S
max
is the maximum kVA rating of
a system and V
base
is the base voltage of the
system, then the minimum impedance in the system
is given as Zmin = V 2Base / Smax== |Rl+ jXl|
(say). In order to achieve the unity power factor,
the shunt active filter current needs to supply the
required reactive component of the load current,
i.e., the fundamental imaginary part of the filter
current should be equal to the imaginary part of the
load current. The filter current and load current in a
particular phase are given
I
filter
= Vinv1 Vl1 / Rf+ j(Xlf Xcf)

I
load
=Vl1/ Rl+ jXl

where, Xlf= 2fLf, Xl = 2fLl, Xcf= 1/2fCf, and f
is the supply frequency of fundamental voltage.
Neglecting the interfacing resistance and equating
the imaginary parts of the above equations. to rate
the dc-link voltage at lower value than
conventional design. The designer has a choice to
choose the value of dc-link voltage to be reduced,
such that the LC filter in the active filter leg of
each phase offers minimum impedance to the
fundamental frequency and higher impedance for
switching frequency components. In the modified
topology along with the series capacitor in the
shunt active filter, the system neutral is connected
to the negative terminal of the dc bus capacitor.
This will introduce a positive dc voltage
component in the inverter output voltage. This is
because, when the top switch is ON, +Vd bus
appears at the inverter output, and 0 V appears
when the bottom switch is ON. Thus, the
inverter output voltage will have dc voltage
component along with the ac voltage. The dc
voltage is blocked by the series capacitor, and thus
the voltage across the series capacitor will be
having two components, one is the ac component,
which will be in phase opposition to the PCC
voltage, and the other is the dc component.
Whereas, in case of the conventional topology, the
inverter output voltage varies between +Vdc when
top switch is ON and Vdc when the bottom
switch ON. Similarly, when a four-leg topology
is used for shunt active filter with a single dc
capacitor, the inverter output voltage varies
between +Vd bus and Vd bus. Thus the value of
the capacitor had been chosen for the proposed
model.
V. GENERATION OF REFERENCE
COMPENSATOR CURRENT

In this work, the load currents are unbalanced and
distorted, these currents flow through the feeder
impedance and make the voltage at terminal
unbalanced and distorted. The series active filter
makes the voltages at PCC balanced and sinusoidal.
However, the voltages still contain switching
frequency components and they contain some
distortions. If these terminal voltages are used for
generating the shunt filter current references, the
shunt algorithm results in erroneous compensation
To remove this limitation of the algorithm,
fundamental positive sequence v+ la1(t), v+lb1(t),
and v+lc1(t) of the PCC voltages are extracted and
are used in control algorithm for shunt active filter.
The expressions for reference compensator currents
are given in. In this equation, Pl avg is the average
load power, P loss denotes the switching losses and
ohmic losses in actual compensator, and it is
generated using a capacitor voltage PI controller.
The term Pl avg is obtained using a moving
average filter of one cycle window of time T in
seconds. The term is the desired phase angle
between the source voltage and current. Once the
reference quantities and the actual quantities are
obtained from the measurements, the switching
commands for the VSI switches are generated
using hysteresis band current control method.
Hysteresis current controller scheme is based on a
feedback loop, generally with two-level
comparators. The switching commands are issued
whenever the error
limit exceeds a specified
tolerance bandh. Unlike the Predictive
controller,
the hysteresis controller has the
advantage of peak current limiting capacity apart
from other merits such as extremely good dynamic
performance, simplicity in implementation and
independence from load parameter variations. The
disadvantage with this hysteresis method is that the
converter switching frequency is highly dependent
on the ac voltage and varies with it. The switching
control for shunt active filter is given as follows.
If ifa ifa+ h1, then bottom switch is turned ON
whereastop switch is turned OFF (Sa= 0, S_a= 1).
If ifa ifa h1, then top switch is turned ON
whereas bottomswitch is turned OFF (Sa = 1, S_a=
0).
Similarly the switching commands for series active
filter are given as follows. If vdvra vdvra+ h2,
then bottom switch is turned ON whereas top
switch is turned OFF (Saa= 0, S_aa= 1). If vdvra
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Methods Enriching Power and Energy Development (MEPED) 2014 153 | P a g e


vdvra h2, then top switch is turned ON
whereasbottom switch is turned OFF (Saa= 1, S_
aa= 0). The control circuitry for both the topologies
is same andis shown.. Only six switching
commands are to begenerated. These six signals
along with the complementarysignals will control
all the 12 switches of the two inverters. The values
of the reference voltage and the current are
estimated and by the help of the controller, the
values are comparing and the values are used to
trigger the gate pulse,




Fig 4: Control Circuit

VI SIMULATION RESULT



Fig 5: Three phase line to line voltage


Fig 6: Three phase line to line voltage


Fig 7: Triggering Pulse For Switch
Sa,Sb,Sc,Sa1,Sb1,Sc1


Fig 8: DC Link Voltage


Fig 9: Three Phase Voltage
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Methods Enriching Power and Energy Development (



Fig 10: Three Phase Output Current

Fig 11: Power Quality output


Fig 12: THD of output current
Table 1: Average switching frequenc
Inverter Switches (Khz)
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Enriching Power and Energy Development (MEPED) 2014

: Three Phase Output Current

output

of output current
ency of the


VII CONCLUSION
By the help of the Unified Power Quality
Conditioner, the voltage sag, swell and other power
quality problem can be removed. The design of the
modified three phase four wire topology had given
and the reduction of the dc link capacitor are
discussed. The reduction of average switching loss
can be achieved by the help of the control of each
leg independently. The control circuit for the
UPQC and the generation of the reference current
are also explained. The output of the UPQC for the
various conditions had been explained by the help
of the simulation result. The average switching loss
details are explained in the tabulated manner
the study, it is found that the modified topology has
less average switching frequency, less THDs in the
source currents, and load voltages with reduced dc
link voltage as compared to the conventional
UPQC topology.

REFERENCE

[1]. R.Gupta, A.Ghosh, and A.Joshi, Characteristic
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[2]. B.Singh and J. Solanki, A comparison of control
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[3]. S.Rahmani,N.Mendalek,andK.Al
Haddad,Experimentaldesignofanonlinearcontrolte
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[4]. V.Corasaniti,M.Barbieri,P.Arnera,andM.
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[5]. M.Milane Montero, E. Romero-
Barrero-Gonzalez, Hybrid multi co
conditioner topology for high-power applications,
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154 | P a g e
By the help of the Unified Power Quality
Conditioner, the voltage sag, swell and other power
quality problem can be removed. The design of the
modified three phase four wire topology had given
and the reduction of the dc link capacitor are
eduction of average switching loss
can be achieved by the help of the control of each
leg independently. The control circuit for the
UPQC and the generation of the reference current
are also explained. The output of the UPQC for the
been explained by the help
of the simulation result. The average switching loss
details are explained in the tabulated manner. From
the study, it is found that the modified topology has
less average switching frequency, less THDs in the
and load voltages with reduced dc-
link voltage as compared to the conventional
R.Gupta, A.Ghosh, and A.Joshi, Characteristic
analysis for multi sampled digital implementation of
- loop modulation
IEEE Trans. Ind
2392,Jul.2009.
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Gonzalez, Hybrid multi converter
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IEEE Trans. Ind. Electron., vol. 58, no. 6, pp. 2283
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[6]. J.Nielsen, M.Newman, H.Nielsen, and F.Blaabjerg,
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[7]. Y.W.Li,P.C.Loh, F.Blaabjerg, and D.Vilathgamuwa,
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[8]. Y.W.Li,D.MahindaVilathgamuwa,
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[9]. J.BarrosandJ.Silva,Multileveloptimalpredictivedyna
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[10]. D.Vilathgamuwa, H.Wijekoon,and S.Choi, A
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[11]. M.Kesler and E.Ozdemir, Synchronous-reference-
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[12]. K.H.Kwan, Y.C.Chu, and P.L.So, Model-based
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[13]. V.Khadkikar and A.Chandra, A novel structure for
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1902,Sep./Oct.2009.

[14]. V.Khadkikar and A.Chandra, A new control
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between shunt and series inverters, IEEE Trans
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[15]. H.Akagi and R.Kondo, A transformerless hybrid
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[16]. H.Jou,K.Wu,J.Wu,C.Li,and M.Huang, Novel
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[17]. T.Zhili,L.Xun, C.Jian, K.Yong, and D.Shanxu, A
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[18]. M.Brenna,R. Faranda, and E. Tironi, A new
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[19]. V.George and M.K.Mishra, DSTATCOM
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Power Quality Management in Commercial Buildings
Harish Kumar.S
1
,Vengatesh.V
2
,Bhuvaneswaran.E
3
123
Electrical and Electronics Engineering, SVIST,Tiruvallur,Tamilnadu,India


ABSTRACT
This paper presents a study of distributed
passive harmonic filter design to minimize
harmonic distortions caused by nonlinear loads
in commercial buildings. Unfortunately, no
single universally suitable representation has
been accepted as a prototype for this power
component. The main objectives in this study
are: 1) to improve the power factor, 2) to reduce
current and voltage distortions to standard
limits, and 3) to reduce electrical losses. In this
sense, several measurements that were carried
out in our college campus, have characterized as
the main harmonic distribution current sources
the third, fifth, and seventh harmonic
components. According to the results obtained
and considering the impacts caused in the
distribution grid, a distributed filtering strategy
is proposed using passive detuned filters of low
costs to be installed in the customers.
Key wordsHarmonics, measurement,
passive detuned filters, power distribution
systems, power quality.
I. INTRODUCTION
Almost all modern commercial buildings take their
supplies at 415 volts from the secondary of the
delta/ star connected 11kV/415V transformers. In
recent years a large number of distorting, non-
linear load such as computer equipments have been
extensively used in commercial buildings. The
result of using such highly non-linear load is that
the current waveform is distorted, causing
excessive harmonic voltages to be generated.
Although modern non-linear loads such as
computer equipments are small in size (power
consumption), but they are large in number. For
example a 3 floor building could have as many as
300 PCs [1-5]. Also the close proximity of many of
these commercial buildings (Hotels, offices,
departmental stores, shopping centres, and
hospitals) will definitely contribute to the distortion
of the electric power quality of feeder which
supplies these buildings. Harmonic currents
injected by some of these loads are usually too
small to cause a significant distortion in
distribution networks. However, when operating in
large numbers, the cumulative effect has the
capability of causing serious harmonic distortion
levels [5-10]. These do not usually upset the end-
user electronic equipment as much as they overload
neutral conductors and transformers and, in
general, cause additional losses and reduced power
factor [1014].
The low-voltage customers of a distribution grid
may be considered as harmonic current sources that
typically produce the third, fifth, and seventh
harmonic components with significant distortion
level, and the ninth and 11th current har-monics
with less significance [15]. In order to better
evaluate the impacts that those distributed
harmonic sources have in the power quality, a set
of measurements was carried out in our college
campus. Those measurements were carried out
directly at college energy installation [16]. Based
on the obtained results, prototypes of low-cost-
detuned passive filters were designed,
manufactured, and installed in our college
facilities. The projected filters are series RLC
filters that are detuned in the fifth, and seventh
harmonic components. In this paper, results
comparing the impacts over the distribution grid
considering the adoption of this proposed strategy
of harmonic filtering at the low voltage customers
are presented.
The main objectives in this study are:
1) to improve the power factor of the customer's
electrical installation;
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2) to reduce current and voltage distortions to
standard limits;
3) to reduce active and reactive losses.

Fig 1:Proposed system with the 5kVAr Capacitor and
5kVAr De-tuned Reactor filter for
the Electrical lab section in our college campus.

Fig 2: Represent the control circuit diagram for the
control block that is to Start and Stop
the Capacitor from remote location. Section II presents
some considerations about the f results used to determine
the filter parameters. The results obtained with the
application of the filter at domestic customers are in
Section IV. Section V presents the conclusions of the
paper.
II. FILTER DESIGN
This work proposes the use of a series passive R of
189Hz ie.,p=7%, which corresponds, respectively,
to the third, fifth, and seventh harmonic
components. The project consists in the
determination of the R, L, (resistance, inductance,
and capacitance, respectively) values for each
branch of the filter that is to be connected in
parallel with the nonlinear customer's load in order
to obtain the minimal impedance at the desired
detuning frequencies. According to the type of
customer, one-phase, two three, six, or nine
branches, and may be installed at the customer's
energy entrance, which is connected at the low-
voltage side of the distribution transformer, a three-
phase customer. At the tuning frequency (w0), the
inductive and capacitive are equal, resulting in the
relationship given in (1) [3]


The filter's impedance is given as
Zf = R+j(wL-1/Wc)
where Zf is the filter's impedance at frequency W0,
expressed ohms ().
Considering the resistance equal to 0.5 in (2) and
the capacitance C varying according to the interval
of 2F<=C<= 50F due to commercial reasons, one
can obtain the values that represent the locus of
minimum Zf for the frequencies of 50, 180, 300,
and 420 Hz, with the inductance varying according
to the interval of 2mH <=L<=200mH. A good
solution, which simultaneously minimizes the filter
impedance some specific harmonic frequency and
maximizes the filter impedance to 50 Hz in order to
limit the losses caused by current at fundamental
frequency, may be obtained. At the same
frequency, the capacitance value is inversely
proportional to the inductance value, and one may
choose a combination that has a capacitor value
that may be easily available in the market. It is also
recommended to give preference to pairs of
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inductor and capacitor with smaller dimensions and
low weight. However, when the loads are not in
operation, the passive filter becomes power factor
correction capacitor if it is not completely isolated
from the load. The passive filter then injects
excessive reactive power (KVAR) causing voltage
regulation problem to the network at light or no
load. This problem can be overcome by using the
Active or a Hybrid Filters. But the cost of those
filters are so high as compared to the passive
filters. Because in this case we are handling the
residential and commercial loads ie., low level
customers.So cost much be taken into the
consideration. So as an Engineer we must required
to give a exact solution with good result and a
suitable price inorder to keep the Quality of Power
to a Standard level which inturn will save a huge
amount to Kilowatts and reduce the losses greatly.
TABLE I
EXAMPLE OF CURRENT MEASUREMENT AT
ATYPICAL SINGLE-PHASE CUSTOMER
Harmonics Order RMS Current
Fundamental (I1) 490A
3rd (I3) 108A
5th (I5) 092A
7th (I7) 050A

TABLE II
VALUES FOR L AND C OF THE PASSIVE
SINGLE-PHASE SHUNT FILTER
Frequency (Hz) L (mH) C (F)
180 78 10
300 47 6
420 24 6
For this we brought a solution that we can able to
operate the series detuned capacitor bank from the
remote location of the user.The fig.2 shows the
control circuit diagram so the start/stop from the

remote location to the capacitor bank based upon
the load requirement can be applied.
III. COMPUTER SIMULATION
The proposed strategy is to design a passive tuned
filter at the third, fifth, and seventh harmonic
components and to apply that filter to all of the
customers of the energy distribution grid that
present the same energy consumption
characteristic, mainly current capacities and
voltage levels. To the filter design, typical single-
phase and three-phase customers fed by a
distribution transformer of 45 kVA, 13.8
kV/220/127 V, with a leakage reactance of 3.5%,
were chosen. The values of the fundamental current
(I1) and of the harmonic currents I3, I5, and I7, as
shown in Table I, are typical values that were
obtained through measurements carried out in
many single-phase customers. These current values
are used to design and manufacture single-phase
filters to be installed in single-phase customers
with similar harmonic characteristics. For testing
capacitance values varying from 2 to 10 F the
corresponding inductance values were obtained
aiming the maximization of filter's impedance at
fundamental frequency in order to assure that a
minimum portion of the current at that frequency
will pass the filter and, at the same time,
minimizing the harmonic impedance under interest,
considering the limitations of the R, L, and C
components: resistance can neither be very large
because the filter's impedance cannot be higher
than the system's impedance nor very small,
because it would not represent a real value. The
capacitance and inductance values are constrained
by size and cost limitations, which would make the
installation of the filters at the consumers'
Fig.3:Third harmonic current (180 Hz) that is filtered [I(I3) in black] &
third harmonic current that is generated by the load [I(L3) in gray].
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residences infeasible.


After several simulations using the software
PSPICE, the best to performance obtained has
provided the results shown in Table II for the
branches of third, fifth, and seventh harmonics that
form rent the single-phase filter adopted. In all
cases, the values of the branches' resistances, due to
project reasons, were specified as 0.5. This
resistance corresponds to the project value to be
attained when manufacturing the respective
inductors. The results of the PSPICE simulations
for the values of L, C, and R chosen for the
branches of the filter are shown in Figs. 3-6,
respectively, for the branches of the third, fifth, and
seventh harmonics. In those graphs, it can be
observed that the harmonic currents (in gray) are
being filtered in some percentage, and that the
currents in the fundamental frequency that cross the
filter's branches are less than 0.8 A. It should be
pointed out that in the PSPICE simulations that the
equivalent impedance of the system was considered
as being the impedance of the transformer, and not
the Thevenin's equivalent impedance at the point of
the consumer's connection in the grid. Despite that
inaccuracy, the results obtained with the filter have
shown a filtering rate of 41.76, 34.78, and 54.00%
for the third, fifth, and seventh harmonic currents,
respectively, when compared with the case without
the filter. It is worth mentioning that the grounding
resistance used in these simulations is not the
theoretical value of 0.5 assumed earlier, but the
real value of 23 that is very common to be found
among the low-voltage customers of the
distribution grid. This is the main reason why the
theoretical results presented in Figs. 3-6 do not
filter completely the harmonic currents as expected
of a good filter design.
IV. APPLICATION OF THE FILTERS AT
DOMESTIC CUSTOMERS
After the installation of the designed filter in our
colleges of the low-voltage distribution grid, its
operation was monitored continuously in order to
evaluate its performance according to the natural
variation of the loads. It should be noticed that the
filter was projected for a certain load condition and
that the configuration of the distribution grid and
its parameters do not necessarily correspond to the
projected conditions. The measurements performed
in threephase of the EB Supply in our college are
shown next. It was observed, in general, that the
filter presented a load-depending behavior. Its
performance was better in some periods when the
load condition was next to that considered in the
filter design.
A. Three Phase Measurements of Our College
Main Building:
The power quality has been reviewed and different
terminologies of power quality were introduced.
International professional bodies have established
standards by which PQ could be defined as
mentioned earlier on. One of such bodies is the
European Standard EN-50160 [15]. What may be
considered as quality power to one customer may
not meet the standard required by another end user.
Therefore Benchmarking indices serving as metrics
came to be developed. Benchmark levels for
Fig.6:Fifth harmonic
current of the customer
with 23- grounding
resistance
Fig. 4: Fifth harmonic
current (300 Hz) that is
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electricity suppliers, consumers and even
manufacturers have been introduced. Some of these
International bodies include Electric Power
Research Institute (EPRI), Institute of Electrical
Electronics Engineering (IEEE), International
Electrotechnical Commission (IEC), American
National Standards Institute (ANSI) and National
Electrical Manufacturers Association (NEMA).
Quality of service is determined by first selecting
the metrics to be used, deciding on what PQ data to
be collected and then determining the pattern of the
data with predetermined target level set by both the
power supplier and the consumer. The supplier, the
consumer and the regulatory agencies need to reach
a compromise. Another level considered to be very
important is the Performance Level introduced by a
specific consumer, which is different but always
higher or equal to the Benchmark values.
In this a commercial buildings case study was
introduced and investigated. The case study
consists of real data which was collected over a
period of time in our academic Institution. The
building consists of equipments associated with
probably with more computers, TVs, florescent
lighting with magnetic and electronic ballasts,
motors, as well as the usual electric loads and
various electronic devices for the laboratory. The
data was then analysed for each of the phases, the
results



critically analysed and some recommendations
proposed for improvement of the quality. The
below graph will tell about the level of Current and
Voltage Harmonics in our College Campus. Also
the total KW and ITHD,VTHD,5th,7th level
Current Harmonics readings are being recorded
during the time of measurement. The
Measurement is carried out by two ways one is
Without Filter and another is With Filter. From this
we able to see the effect of Filter which is being
employed to reduce the level of current and voltage
Harmonics to a level.


Fig.7:5th level Current Harmonics Without Filte&
Fig.8:Total Current Harmonic Distortion(ITHD)
WithFilter

Fig.9:5th level Current Harmonics Without Filter
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Fig.10:5th level Current Harmonics With Filter

Fig.11:7th level Current Harmonics Without Filter

Fig.12:7th level Current Harmonics With Filter


Fig.14:Total Voltage Harmonic Distortion(VTHD)
With Filter
Fig.13:Total Voltage Harmonic Distortion(VTHD)
Without Filter
Figs. 7-12 show the ITHD%, 5th and 7th level
Current Harmonics performance when the
harmonic filter is installed in phases A, B, and C,
respectively, of a three-phase customer. The
measurements were performed in small periods of
time in order to have as small a deviation of the
system operation state as possible for the two
measured conditions: with the filter and without the
filter.A reduction ITHD% was observed in some
periods, depending on the load variation. After the
measurement it was shown that the voltage
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harmonic distortion at the input was not high. The
maximum total harmonic distortion did not reach
5% as shown in Fig.13 during the data collection
period. The maximum was 4.3% on line 3. The
EN50160 gives the limit of 8% for THDV for LV
system, in monitoring for a period and Fig.13shows
that the highest THDV was 4.3% on phase 3.
Therefore the limit is not violated The individual
voltage harmonics showed that the 5th and 7th
harmonics are present as. The highest distortion
was the 5th harmonic which was 3%, and the 7th
harmonic was about 2.5%. The International
standard EN50160 gives the limits of 5th harmonic
distortion to be 6% and the 7th to be 5%. These
limits were not violated.

V. CONCLUSION:
The harmonic impacts over the distribution grid
produced by currents injected by low-voltage
customers ie from the college campus can be
reduced by the use of passive filters detuned to the
frequencies of 189, 300, and 420 Hz,ie,. p=7%,14%
which correspond to the third, fifth, and seventh
harmonics, respectively. In this sense, this paper
presented some preliminary results involving the
installation of de-tuned passive filters in some
customers of the low-voltage distribution grid.
Although it has not been observed, a regular
reduction in the harmonic current distortion for all
load conditions, as was expected with the passive
filter, the use of the filter has contributed, in the
average, to better performance of the domestic
electrical plant concerning:
Power factor improvement;
THDV% reduction;
Reduction of reactive power demand from the
grid.
If this distributed filtering strategy is to be applied
to a considerable number of customers in the low-
voltage distribution grid, it is expected that the
system will exhibit, in general, better performance
with respect to power-quality indicators
Fig.13:Total Voltage Harmonic Distortion(VTHD)
Without Filter Fig.14:Total Voltage Harmonic
Distortion(VTHD) With Filter concerning voltage
and current distortions. Also, due mainly to the
capacitance presented by the passive RLC
proposed filter, there is a local reactive power
compensation for each individual customer that
may sum up to a large amount when considering
the set of customers in the distribution grid. This
strategy is of low-cost implementation and may
alleviate the reactive power required from the grid,
but special attention must be given to the problem
of harmonic resonance that may arise when using
the distributed filtering strategy.
Future Research:
There are many points which can be further
investigated in this field. Some of these points are
summarised below:
- The present approach establishing a relation
between voltage and power consumption both for
active and reactive power is not conclusive. It was
proved that power consumption figures would be
significantly less at lower voltage level, but more
investigations into residential, commercial and
industrial loads are needed to establish this. When
commercial consumers voltage level increases
significantly it produces high unwanted power
consumption, because of heavy presence of passive
and resistive loads.
This needs further research. - Mass application of
Compact fluorescent lamps with electronic gear in
modern and commercial establishments is
becoming as bad in generating harmonic distortions
as computers and other SMPS. These CFLs cause
network voltage distortion, occurring due to their
distorted currents, with high level of harmonic
components. Further research analyses dealing with
the influence of CFLs on power systems are
necessary, especially on massive residential
distribution network intermingled with modern
commercial buildings. The production of harmonic
currents causing corresponding system harmonic
voltage, mostly the triple-n harmonics could mean
major power quality problems for the MV/LV
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subtransmission transformers of the delta-wye
types.

REFERENCES:
[1] M. E. de Lima Tostes, U. H. Bezerra, J. N.
Garcez, A. A. A. Tupiassu, and C. A. Sena,
"Development of experimental models for
harmonic representation of low voltage customers,"
in Proc. 2001 IEEEPorto Power Tech, Porto,
Portugal.
[2] Chapman, D.; Power Quality Application Guide
- The Cost of Poor Power Quality; Copper
Development Association.
[3] Bollen, M.H.J. Understanding Power Quality
Problems IEEE Press Series on Power
Engineering.
[4] IEEE 519:1992, IEEE Recommended Practices
and Requirements for Harmonics Control in
Electrical Power Systems.
[5] R. Lamerica, A. Prudenzi, E. Tiroli, and D.
Zaninelli, "A model of large load areas for
harmonic studies in distribution networks," IEEE
Trans. Power Del., vol. 12, no. 1, pp. 418- 425,.
[6] IEEE 1159; IEEE Recommended Practice for
Monitoring Electric Power Quality.
[7] IEC 61000-4-3; Testing and measurement
techniques Power quality measurement methods,
pp. 81, 7, 19.
[8] Ewalk, F.; Masouum, M. A. S.; Power Quality
in Power Systems and Electrical Machines.
Elsevier Academic Press 2008.
[9] Jain Sandesh, Thakur Shivendra Singh and
Phulambrikar S.P, Improve Power Factor and
Reduce the Harmonics Distortion of the System,
Research Journal of Engineering Sciences ISSN
2278 9472 Vol. 1(5), 31-36, November (2012).
[10] Hussein A. Kazem, Harmonic Mitigation
Techniques Applied to Power Distribution
Networks, Hindawi Publishing Corporation
Advances in Power Electronics Volume 2013,
Article ID 591680.
[11] A.Mansoor,W. M. Grady, A. H. Chowdhury,
andM. J. Samotyi, An investigation of harmonics
attenuation and diversity among distributed single-
phase power electronic loads, IEEE Transactions
on Power Delivery, vol. 10, no. 1, pp. 467473,
1995.
[12] A. Mansoor, W. M. Grady, R. S. Thallam, M.
T. Doyle, S. D.Krein, andM. J. Samotyj, Effect of
supply voltage harmonics on the input current of
single-phase diode bridge rectifier loads,IEEE
Transactions on Power Delivery, vol. 10, no. 3, pp.
14161422, 1995.
[13] G. Carpinelli, F. Iacovone, P. Varilone, and P.
Verde, Single phase voltage source converters:
analytical modelling for harmonic analysis in
continuous and discontinuous current conditions,
International Journal of Power and Energy
Systems,vol. 23, no. 1, pp. 3748, 2003.
[14] E. F. El-Saadany and M. M. A. Salama,
Reduction of the net harmonic current produced
by single-phase non-linear loads due to attenuation
and diversity effects, International Journal of
Electrical Power and Energy Systems, vol. 20, no.
4, pp. 259268, 1998.
[15] T. Key and J. S. Lai, Analysis of harmonic
mitigation methods for building wiring systems,
IEEE Transactions on Power Systems, vol. 13, no.
3, pp. 890897, 1998.
[16] EN 50160:2000, Voltage characteristics of
electricity supplied by public distribution systems.
ACKNOWLEDGEMENT
We deeply indebted to our Management for
supporting and facilities to make this as a
successful project.
We thank PROJCET GUIDE Mr.Ethirajulu for
having given technical information and suggestions
to carry out this project.
We thank Mr.Thagarajan,Project Co-Ordinator for
having given us extreme moral support and gave
permissions to use the literature and data collection
during working hours.
We thank Dr. Duraivel, principal, SVIST for his
consistent encouragement to complete the Protect .
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We thank Mr.ChellaMuthu for valuable guidance
and permit us to use equipment for the real time
analysis.
We thank Mr.Paranthaman for his valuable
guidance and support interms of practically.
We thank Mr.Renny Son for his support in last
minute of our project and the guidance.
We thank all our Department faculty members of
Electrical and Electronics Engineering and Faculty
members of Other Department for their suggestions
to carry out this project.

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Fault Detection and Compensation in Low Voltage AC
System Using UPFC
M.Kamatchi Valli
1
, Asst Prof M.Vennila
2


1
PG Scholar,Karpaga Vinayaga College Of Engineering & Technology, Chennai, India

2
Assistant Professor, Karpaga Vinayaga College Of Engineering & Technology, Chennai, India



ABSTRACT
The goals of the proposed scheme are to detect
the fault in the bus between devices and to
separate the faulted section so that the system is
operating without affecting the complete system.
A fault in ac power system involves reactive
power loss. It is proposed to develop a UPFC
device to compensate the reactive power loss
during faults in low voltage ac system. In the
proposed system fault compensation will be
employed, so that system will have fault override
capability during transient faults or short
duration faults. Closed loop PID control is also
provided to pull off the required output voltage.
The Simulation is primed with the help of
MATLAB Software using Simulink.

Keywords: Unified Power Flow Control, DC-DC
Converters, Inverter

I.INTRODUCTION

DC-DC converters are electronic devices
used whenever we want to change DC electrical
power efficiently from one voltage level to another.
They are needed because unlike AC, DC cannot
simply be stepped up or down using a transformer.
In many ways, a DC-DC converter is the DC
equivalent of a transformer [1-2]. The DC energy
from one voltage level to another to be changed,
while wasting as little as possible in the process. In
other words, we want to perform the conversion
with the highest possible efficiency [3-4]. Another
important distinction is between converters which
offer full dielectric isolation between their input
and output circuits, and those which dont.
Needless to say this can be very important for some
applications, although it may not be important in
many others.



II. AC-DC CONVERTER
An ac to dc converter is an integral part of
any power supply unit used in the all electronic
equipments. Also, it is used as an interface between
utility and most of the power electronic equipments.
These electronic equipments form a major part of
load on the utility. Generally, to convert line
frequency ac to dc, a line frequency diode bridge
rectifier is used. To reduce the ripple in the dc
output voltage, a large filter capacitor is used at the
rectifier output. But due to this large capacitor, the
current drawn by this converter is peaky in nature.
The input current is rich in low order
harmonics. Also, as power electronics equipments
are increasingly being used in power conversion,
they inject low order harmonics into the utility. Due
to the presence of these harmonics, the total
harmonic distortion is high and the input power
factor is poor. Due to problems associated with low
power factor and harmonics, utilities will enforce
harmonic standards and guidelines which will limit
the amount of current distortion allowed into the
utility and thus the simple diode rectifiers may not
in use. So, there is a need to achieve rectification at
close to unity power factor and low input current
distortion. Initially, power factor correction
schemes have been implemented mainly for heavy
industrial loads like induction motors, induction
heating furnaces etc., which forms a major part of
lagging power factor load. However, the trend is
changing as electronic equipments are increasingly
being used in everyday life nowadays. Hence, PFC
is becoming an important aspect even for low
power application electronic equipments.AC/DC
line commentated converter or, as they also called
converter with natural communication or passive
rectifier, are the most usual choice application,
where a single-phase and three- phase supply is
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available. This is due to simplicity of the circuits
requiring a minimum number of active and passive
components. Thyristors are the main line-
communes power switches. The term line-
commutated describes the type of commutation. to
turn on a thyristors, an injection of a current pulse
into its gate is required. In low power applications,
vehicle, medicine, and household devices, where
there is no ac supply or where reactive current and
harmonics caused by a line commutation would be
unreachable, it is accepted to employ forced
commutated converter having a more complex
circuitry and sometimes involving higher losses. A
special situation exists also with dc and ac loads,
where the response of a line-commuted converter
may be insufficient to cope with the stringent
dynamic and energy efficiency demand and where
an additional converter supplied by a dc link and
operated with a higher switching frequency is
necessary.

III.UNIFIED POWER FLOW
CONTROLLER (UPFC)

A combination of static synchronous
compensator (STATCOM) and a static series
compensator (SSSC) which are coupled via a
common dc link, to allow bidirectional flow of real
power between the series output terminals of the
SSSC and the shunt output terminals of the
STATCOM, and are controlled to provide
concurrent real and reactive series line
compensation without an external electric energy
source. The UPFC, by means of angularly
unconstrained series voltage injection, is able to
control, concurrently or selectively, the
transmission line voltage, impedance, and angle or,
alternatively, the real and reactive power flow in
the line. The UPFC may also provide independently
controllable shunt reactive compensation. In UPFC,
which combines a STATCOM and an SSSC the
active power for the series unit (SSSC) is obtained
from the line itself via the shunt unit STATCOM.
The latter is also used for voltage control with
control of its reactive power. This is a complete
controller for controlling active and reactive power
control through the line, as well as line voltage
control. Additional storage such as super
conducting magnet connected to the dc link via an
electronic interface would provide the means of
further enhancing the effectiveness of the UPFC.
The controller exchange of real power with an
external source, such as storage is much more
effective in control of system dynamics than
modulation of the power transfer within a system.
The UPFC was derived for the real time
control and dynamic compensation of ac
transmission systems, providing multifunctional
flexibility required to solve many of the problems
facing the power delivery industry. Within the
framework of traditional power transmission
concepts, the UPFC us able to control,
simultaneously or selectively, all the parameters
affecting power flow in the transmission line (i.e.,
voltage, impedance, and phase angle), and this
unique capability is signified by the adjective
unified in its name. Alternatively, it can
independently control both the real and reactive
power flow in the line. The reader should recall
that, for all the Controllers discussed in the
previous chapters, the control of real power is
associated with similar change in reactive power,
i.e., increased real power flow also resulted in
increased reactive line power. In order to increase
the system reliability and provide flexibility for
future system changes, the UPFC installation was
required to allow self-sufficient operation of the
shunt converter as an independent STATCOM and
the series converter as an independent Static
Synchronous Series Compensator (SSSC). It is also
possible to couple both converters together to
provide either shunt only or series only
compensation over a doubled control range.

IV.UPFC OPERATION STRATEGY

During system disturbances, mechanically
switched shunt capacitor banks and associated
controls are generally slow to react. Under actual
system contingency conditions, all of these banks
may not switch on (hunting concerns) or some may
over-correct the voltage and lock-out. To resolve
this situation, the UPFC is required to maintain a
predetermined reactive power margin to maximize
the shunt converters dynamic reactive power
reserve for system contingency conditions. This
ensures that the controllable reactive power range
of the shunt converter is available at all times to
compensate for dynamic system disturbances. The
shunt capacitor banks will be switched on and off to
maintain the reserve UPFC and SVC margins
during steady state load fluctuations.
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V.DESCRIPTION OF THE UPFC

The Unified Power Flow Controller is
designed to meet the defined system
requirements, in particular, to provide fast
reactive shunt compensation. In order to
increase the system reliability and provide
flexibility for future system changes, the UPFC
installation was required to allow self-
sufficient operation of the shunt converter as
an independent STATCOM and the series
converter as an independent Static
Synchronous Series Compensator (SSSC). It is
also possible to couple both converters
together to provide either shunt only or series
only compensation over a doubled control
range.

VI.BLOCK DIAGRAM



Figure 1.Represent the block diagram of the proposed
system

VII.BLOCK DIAGRAM DESCRIPTION
A fault in ac power system involves
reactive power loss. Its proposed to develop a
UPFC device to compensate the reactive power loss
during faults in low voltage ac system. The
proposed system consists of one inverter, two
converter, and UPFC device between each line and
ground. Both ac and dc source, power-electronic
converters are required to connect a variety of
sources and loads to a common bus. Using a dc bus
requires fewer stages of conversion. The proposed
scheme detects the fault and separates the faulted
section so that the rest of the system keeps
operating. The loop-type dc bus is suggested for the
proposed scheme to make the system robust under
faulted conditions. It has also been reported that the
loop-type bus has good system efficiency especially
when the distribution line is not long. Closed loop
PID control is also provided to achieve the desired
output voltage. Pulse generators are employed to
produce switching pulses and PWM. The Voltage
Measurement block measures the instantaneous
voltage between two electric nodes.

VIII.SIMULATION CIRCUIT



Figure 2. Represent the simulation circuit for the
proposed system

The above circuit gives the simulation
circuit for fault detection and isolation in dc bus
using UPFC. DC voltage from battery is given to
converter and also AC voltage is given to ac-dc
converter where dc voltage is obtained as output.
The dc voltage is given to inverter and then to load.
Fault is occurred in between inverter and load. The
faulted current is made to flow to the UPFC and
then to transformer and then to load without
affecting the load.

IX. SIMULATION RESULTS
Simulation results for the simulation
diagram is given below. The figure(3-a) gives the
output voltage measured form the inverter. The
figure(3-b) gives the current waveform measured at
the output of inverter. The figure(3-c) gives the
voltage waveform when measured before the load.
The figure(3-d) gives the current waveform when
measured before the load. The figure(3-e) gives the
current waveform of the UPFC. The figure(3-f)
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gives the voltage waveform of the UPFC. The next
figure(3-g) results the compensated voltage during
faulted condition. Figure(3-h) gives the comparison
of load voltage and source voltage.



Figure 3a. Source voltage obtained from inverter output.



Figure 3b.Source current obtained from inverter output.



Figure 3c.Load voltage which is obtained before the load.


Figure 3d.Load current obtained before the load



Figure 3e.Result is for UPFC current


Figure 3f. Result is for UPFC voltage

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Figure 3g.Result is for compensated voltage during
fault condition



Figure 3h. Result is for comparing load voltage and
source voltage

X.CONCLUSION

A fault detection and isolation scheme for
the low-voltage dc-bus micro grid system is
developed with compensation method. The
proposed protection scheme is capable of detecting
abnormal fault current in the bus and separating the
faulted segment to avoid the entire system
shutdown. The UPFC regulates the voltage of the
bus as well as regulates the active and reactive
power of the buses and the lines within specified
limits. So the efficiency will be improved.

XI.REFERENCES

[1] Frede Blaabjerg, Remus Teodorescu, Marco Liserre,
and Adrian V. Timbus Overview of Control and Grid
Synchronization for Distributed Power Generation
Systems IEEE Transactions on Industrial Electronics,
Vol. 53, No. 5, October 2006.
[2] WanMin Fei, YanLi Zhang, and ZhengYu L, Novel
Bridge-Type FCL Based on Self-Turnoff Devices for
Three-Phase Power Systems IEEE Transactions on
Power Delivery, Vol.23, NO. 4, October 2008.
[3] Lianxiang Tang and Boon-Teck Ooi, Locating and
Isolating DC Faults in Multi-Terminal DC Systems
IEEE Transactions on Power Delivery, Vol. 22, No. 3,
JULY 2007.
[4] Daniel Salomonsson, Lennart Sder, and Ambra
Sannino, Protection of Low-Voltage DC Microgrids
IEEE Transactions on Power Delivery, Vol. 24, No. 3,
July 2009.

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Using Distributed Power Flow Controller to Compensate
Unbalanced Currents in Transmission Line

V.Aathithya
1
, S. Suresh
2
EEE Department, B.S.Abdur Rahman University, Chennai, Taminadu, India


ABSTRACT

Distributed Power Flow Controller is a new
device within the family of FACTS. The DPFC has
the same control capability as the UPFC, but with
much lower cost and higher reliability. This paper
addresses one of the applications of the DPFC
namely compensation of unbalanced currents in
transmission systems. Since the series converters
of the DPFC are single phase, the DPFC can
compensate both active and reactive, zero and
negative sequence unbalanced currents. To
compensate the unbalance, two additional current
controllers are supplemented to control the zero
and negative sequence current respectively.

Keywords: FACTS, DPFC, modelling ,
Unbalanced currents, Zero sequence


I. INTRODUCTION

There is a great demand of power flow
control in power systems of the future and
combined FACTS devices are the most suitable
devices [1-3]. However, due to the cost and the
reliability issues given above, there are many
hurdles to the widespread application of
combined FACTS devices. The new concept is
Distributed Power Flow Controller (DPFC). It is
a combined FACTS device, which has taken a
UPFC as its starting point. The DPFC has the
same control capability as the UPFC;
independent adjustment of the line impedance,
the transmission angle and the bus voltage. The
DPFC eliminates the common DC link that is
used to connect the shunt and series converter
back-to- back within the UPFC. By employing
the Distributed FACTS concept as the series
converter of the DPFC, the cost is greatly
reduced due to the small rating of the
components in the series converters. Also, the
reliability of the DPFC is improved because of
the redundancy provided by the multiple series
converters [4-5]. The elimination of the
common DC link also allows the DSSC concept
to be applied to series converters. In that case,
the reliability of the new device is further
improved due to the redundancy provided by the
distributed series converters [6]. By applying the
two approaches eliminating the common DC
link and distributing the series converter, the
UPFC is further developed into a new combined
FACTS device: the Distributed Power Flow
Controller (DPFC), as shown in fig 1




Fig 1. Flow chart from UPFC to DPFC

II. DISTRIBUTED POWER FLOW
CONTROLLER (DPFC)

By introducing the two approaches outlined in
the previous section (elimination of the common DC
link and distribution of the series converter) into the
UPFC, the DPFC is achieved. Similar as the UPFC,
the DPFC consists of shunt and series connected
converters. The shunt converter is similar as a
STATCOM, while the series converter employs the
DSSC concept, which is to use multiple single-phase
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converters instead of one three-phase converter. Each
converter within the DPFC is independent and has its
own DC capacitor to provide the required DC
voltage. DPFC configuration shown in fig 2



Fig. 2 DPFC configuration

As shown, besides the key components - shunt
and series converters, a DPFC also requires a high
pass filter that is shunt connected to the other side of
the transmission line and a star-delta transformer on
each side of the line. The unique control capability of
the UPFC is given by the back-to-back connection
between the shunt and series converters, which allows
the active power to freely exchange. To ensure the
DPFC has the same control capability as the UPFC, a
method that allows active power exchange between
converters with an eliminated DC link is required.

III. DPFC OPERATING PRINCIPLE

A)ACTIVE POWER EXCHANGE WITH
ELIMINATED DC LINK
Within the DPFC, the transmission line
presents a common connection between the AC ports
of the shunt and the series converters. Therefore, it is
possible to exchange active power through the AC
ports. The method is based on power theory of non-
sinusoidal components. According to the Fourier
analysis, non-sinusoidal voltage and current can be
expressed as the sum of sinusoidal functions in
different frequencies with different amplitudes. The
active power resulting from this non-sinusoidal
voltage and current is defined as the mean value of
the product of voltage and current. Since the integrals
of all the cross product of terms with different
frequencies are zero, the active power can be
expressed by:



Where V
i
and I
i
are the voltage and current at the
i
th
harmonic frequency respectively, and is the
corresponding angle between the voltage and current.
Equation shows that the active powers at different
frequencies are independent from each other and the
voltage or current at one frequency has no influence
on the active power at other frequencies. The
independence of the active power at different
frequencies gives the possibility that a converter
without a power source can generate active power at
one frequency and absorb this power from other
frequencies.
By applying this method to the DPFC, the
shunt converter can absorb active power from the grid
at the fundamental frequency and inject the power
back at a harmonic frequency. This harmonic active
power flows through a transmission line equipped
with series converters. According to the amount of
required active power at the fundamental frequency,
the DPFC series converters generate a voltage at the
harmonic frequency, thereby absorbing the active
power from harmonic components. Neglecting losses,
the active power generated at the fundamental
frequency is equal to the power absorbed at the
harmonic frequency.
For a better understanding, Figure 3 indicates
how the active power is exchanged between the shunt
and the series converters in the DPFC system. The
high-pass filter within the DPFC blocks the
fundamental frequency components and allows the
harmonic components to pass, thereby providing a
return path for the harmonic components. The shunt
and series converters, the high pass filter and the
ground form a closed loop for the harmonic current.

B) USING THIRD HARMONIC COMPONENTS
Due to the unique features of 3
rd
harmonic
frequency components in a three-phase system, the
3
rd
harmonic is selected for active power exchange in
the DPFC.
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Fig.3 Active power exchange between DPFC converters

In a three-phase system, the 3
rd
harmonic in
each phase is identical, which means they are zero-
sequence components. Because the zero-sequence
harmonic can be naturally blocked by star-delta
transformers and these are widely incorporated in
power systems (as a means of changing voltage),
there is no extra filter required to prevent harmonic
leakage. As introduced above, a high-pass filter is
required to make a closed loop for the harmonic
current and the cut-off frequency of this filter is
approximately the fundamental frequency. Because
the voltage isolation is high and the harmonic
frequency is close to the cut-off frequency, the filter
will be costly. By using the zero-sequence harmonic,
the costly filter can be replaced by a cable that
connects the neutral point of the star-
delta transformer on the right side in Fig 3 with the
ground. Because the delta winding appears open-
circuit to the 3rd harmonic current, all harmonic
current will flow through the Y-winding and
concentrate to the grounding cable as shown in Fig 4.
Therefore, the large high-pass filter is eliminated.


Fig. 4 Utilize grounded star-delta transformer to filter zero-
sequence harmonic

Another advantage of using the 3
rd
harmonic to
exchange active power is that the grounding of the
star-delta transformers can be used to route the
harmonic current in a meshed network. If the network
requires the harmonic current to flow through a
specific branch, the neutral point of the star-delta
transformer in that branch, at the side opposite to the
shunt converter, will be grounded and vice versa. Fig
5 shows a simple example of routing the harmonic
current by using the grounding of the star-delta
transformer. Because the floating neutral point is
located on the transformer of the line without the
series converter, it is an open-circuit for 3
rd
harmonic
components and therefore no 3
rd
harmonic current
will flow through this line.




Fig.5 Route the harmonic current by using the grounding of
the star-delta Transformer

The harmonic at the frequencies like 3rd, 6th,
9th... are all zero-sequence and all can be used to
exchange active power in the DPFC. However, the 3
rd

harmonic is selected, because it is the lowest
frequency among all zero-sequence harmonics. The
relationship between the exchanged active power at
the i
th
harmonic frequency and the voltages
generated by the converters is expressed by the well
known the power flow equation and given as:



Where X
i
is the line impedance at i
th

frequency|V
Sh
|and|V
se
| the voltage magnitudes of the
i
th
harmonic of the shunt and series converters, and
(
sh,i

se,i
) is the angle difference between the two
voltages. As shown, the impedance of the line limits
the active power exchange capacity. To exchange the
same amount of active power, the line with high
impedance requires higher voltages. Because the
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transmission line impedance is mostly inductive and
proportional to frequency, high transmission
frequencies will cause high impedance and result in
high voltage within converters. Consequently, the
zero-sequence harmonic with the lowest frequency
the 3
rd
harmonic has been selected.

IV. ADVANTAGES AND LIMITATION OF
THE DPFC

The DPFC can be considered a UPFC that
employs the D-FACTS concept and the concept of
exchanging power through the 3rd harmonic. In this
way, the DPFC inherits all their advantages:




High controllability:
The DPFC can simultaneously control all the
parameters of the transmission network: line
impedance, transmission angle and bus voltage.
High reliability:
The redundancy of the series converter gives
high reliability without increasing cost. In addition,
the shunt and series converters are independent and
failure of one will not influence the other converters.
Low cost:
There is no phase-to-phase voltage isolation
required between the series converters of different
phases. The power rating of each converter is also
low. Because of the large number of the series
converters, they can be manufactured in series
production. If the power system is already equipped
with the STATCOM, the system can be updated to
the DPFC with only low additional costs. However,
there is a drawback to using the DPFC.
Extra currents:
Because the exchange of power between the
converters takes place through the same transmission
line as the main power, extra currents at the 3rd
harmonic frequency are introduced. These currents
reduce the capacity of the transmission line and result
in extra losses within the line and the two star-delta
transformers. However, because this extra current is
at the 3rd harmonic frequency, the increase in the
RMS value of the line current is not large and through
the design process can be limited to less than 5% of
the nominal current.


V.SIMULATION AND RESULTS OF DPFC

A) Modelling Of DPFC Shunt Converter:

The modeling of this converter is done by using
MATLAB software and the modeling diagram is
shown in the fig 6 Simulation circuit for the modeling
of Shunt converter.



Fig 6. Simulation circuit for the modeling of Shunt
converter


Fig 7. Shunt converter Input voltage


Fig 8. Shunt converter Output voltage


Fig 9. Shunt converter Input current

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Fig 10. Shunt converter output current

When fault is applied between 0.5 to 2 second,
current is increased to 150 A, thereby voltage reduced
to 8 times the normal value. When the shunt
compensator is connected at 0.6 second, current is
increased and thereby simultaneously the voltage
value is reduced. Analysis of shunt converter shown
in table 1. In order to compensate the voltage, a series
compensator is used.

Table 1 Analysis Of Shunt Converter

Supply
current(A)
100
A
Fault
Occurring
period(Sec)
0.5-
2 S
Current
during fault
period(A)
150
A
Compensated
current
200
A

B)Modelling of DPFC Series Converter
The modeling of this converter is done by
using MATLAB software and the modeling
diagram is shown in the figure 8 Simulation
circuit for the modeling of Series converter.


Fig. 11 Simulation circuit for the modeling of Series
converter


Fig. 12 Series Compensated Output Voltage and Current

When fault is applied between 0.5 to 2
second, voltage is reduced to 180v, thereby
current increased to 8 times the normal value.
When the series compensator is connected at 0.6
second, voltage is increased and thereby
simultaneously the current value is reduced.
Analysis of series converter shown in table 2. In
order to compensate the current, a shunt
compensator is used.

Table 2 Analysis Of Series Converter









C) DPFC Modelling

The modeling of this converter is done by
using MATLAB software and the modeling
diagram is shown in the figure 10 Simulation
circuit for the DPFC modeling.

Supply Voltage(V) 400 V
Fault Occurring
period(Sec)
0.5-2 S
Voltage during fault
period(V)
180 V
Compensated voltage 390 V
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Fig 13 simulation circuit for the DPFC modelin


Fig 14 DPFC modelling Output

VI. CONCLUSION

This paper investigates the capability of the
DPFC to balance a network. It is found that the DPFC
can compensate both negative and zero sequence
components, consequently the DPFC is more
powerful than other FACTS device for compensation
of unbalanced currents. Additional controllers are
supplemented to existing DPFC controller, and their
principle is to monitor the negative and
zerosequences of the current through the transmission
line, and to force them to be zero by applying an
opposing voltage. As a side effect, the DPFC
generates non-zero sequence 3rd current during the
unbalance situation, which can not be blocked by the
Y- transformer. However the magnitude of the
nonzero sequence 3rd current is much smaller than
the nominal current at the fundamental frequency,
less than 4% typically.

REFERENCES


[1] L. Gyugyi, Unified power-flow control concept for
flexible ac transmission systems, Generation,
Transmission and Distribution [see also IEE Proceedings-
Generation, Transmission and Distribution], IEE
Proceedings C, vol. 139, no. 4, pp. 323331, 1992.

[2] Y. Ikeda and T. Kataoka, A upfc-based voltage
compensator with current and voltage balancing function,
in Applied Power Electronics Conference and Exposition,
2005. APEC 2005. Twentieth Annual IEEE, vol. 3, 2005,
pp. 18381844 Vol. 3.

[3] Z. Yuan, S. W. H. de Haan, and B. Ferreira, A new
facts component: Distributed power flow controller (dpfc),
in Power Electronics and Applications, 2007 European
Conference on, 2007, pp. 14.

[4] D. Divan and H. Johal, Distributed facts - a new
concept for realizing grid power flow control, in Power
Electronics Specialists Conference, 2005. PESC 05. IEEE
36th, 2005, pp. 814.

[5] M. Milosevic, G. Andersson, and S. Grabic,
Decoupling current control and maximum power point
control in small power network with photovoltaic source,
in Power Systems Conference and Exposition, 2006. PSCE
06. 2006 IEEE PES, 2006, pp. 10051011.

[6] H. Namho, J. Jinhwan, and N. Kwanghee, A fast
dynamic dc-link power-balancing scheme for a pwm
converter-inverter system, Industrial Electronics, IEEE
Transactions on, vol. 48, no. 4, pp. 794803, 2001.



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Power System Restoration in Transmission Network Using
Dijkstras Algorithm
Naveen.G
1
, Arther Jain.A
2
, Vimal Raj.A
3
Electrical and Electronics Engineering,Thangavelu Engineering College,Chennai,India

ABSTRACT
A graph theory based methodology called
dijkstras algorithm is used to find the
energizing path of power to flow for a given
network after a complete blackout is proposed
here. Whenever a blackout occurs in the
transmission network, the power system
operators are under immense pressure to
restore the network. The main aim of the power
system restoration is to restore as much load as
possible & as quickly as possible. After a
blackout occurs first all the generators has to be
energized and then synchronized. After
synchronization of generators only all the loads
can be supplied. For energizing the generators a
sequential procedure has to be followed. If the
sequence used is wrong then it may lead to
cascaded outages.The Dijkstra's algorithm helps
in finding the sequence to energize the
generators based on least impedance path called
minimum spanning tree. Newton Raphson based
load flow technique is applied to this resultant
minimum spanning tree(power flow path).
Based on the results (voltage, current and power
flow) obtained from the load flow solutions,
other constraints of the restoration problem are
applied.
Keywords: Black out, graph theory, minimum
spanning tree, load flow solution.
I. INTRODUCTION
Power system is a complex network involving the
flow of power, which is generated using various
techniques to meet the need of the industries or
domestic consumers [1-3]. In normal mode of
operation all the constraints are satisfied. Reserve
margin is sufficiently high too make the system
well secure by the system security level falls below
certain level or the probability of disturbances
increases the system may be in alert state [4-6].
II. BROWN OUT
A brownout is an intentional drop in
voltage in an electrical power supply system used
for load reduction in an emergency. The reduction
lasts for minutes or hours, as opposed to short-term
voltage sag or dip [7]. The term brownout comes
from the dimming experienced by lighting when
the voltage sags. A voltage reduction may be an
effect of disruption of an electrical grid, or may



occasionally be imposed in an effort to reduce load
and prevent a blackout.

Fig 1 : Power System Operating States
III LOAD FLOW ANALYSIS
Power flow studies are of great
importance in planning & designing the future
expansion of power system as well as in
determining the best operation of existing systems.
The principle information obtained from power
flow study is the magnitude & phase angle of
voltage at each bus the real & reactive power
following in each line. Power flow calculations
usually employ iterative techniques such as
Newton-Raphson method solves the polar form of
power flow equations until P & Q mismatches at
all buses fall within specified tolerances.
IV GRAPH THEORY
Graph theory is a branch of data structures
concerned about how the networks can be encoded
& their properties measured. A graph (G) is a set of
points called vertices & the lines connecting the
points called Edges. The graphs are broadly
classified into two types. One type of classification
is Directed Graph & Undirected Graphs.An
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Methods Enriching Power and Energy Development


undirected graph G= (V, E) consist of finite set of
vertices V & set of edges E.
Fig 2 : Example Problem

V DIJKSTRAS ALGORITHM
Dijkstra's algorithm, conceived by
Dutch computer scientist Edsger Dijkstra in
1959, is a graph search algorithm that solves
the single-source shortest path problem for a
graph with nonnegative edge path costs,
producing a shortest path tree. This algorith
is often used in routing.
Fig 3 : Minimum Spanning Tree by Dijkstras
Algorithm
Table 1 : Comparison of results of various Algorithm
ALGORITHM DISTANCE CALCULATED
FROM MINIMUM
TREE
Prims Algorithm 1.03
Dijkstras
Algorithm
0.83
Kruskals
Algorithm
1.03
Reverse Delete
Algorithm
1.03

VI RECOVERY PROCESS
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Methods Enriching Power and Energy Development (MEPED) 2014
undirected graph G= (V, E) consist of finite set of

Problem

Dijkstra's algorithm, conceived by
Dutch computer scientist Edsger Dijkstra in
1959, is a graph search algorithm that solves
source shortest path problem for a
graph with nonnegative edge path costs,
producing a shortest path tree. This algorithm

Minimum Spanning Tree by Dijkstras
Table 1 : Comparison of results of various Algorithm
DISTANCE CALCULATED
SPANNING
The whole recovery process is divided into 3
stages.
(A) BLACK START:
Due to any critical fault or transient in the
network a complete blackout will be occurring.
(B) SYSTEM RECONSTRUCTION
The generator (Slack bus) started first &
based on the sequence of starting & starting time
the generators on the network are started.
(C) LOAD RECOVERY:
Initially the critical loads are fed & later
after stabilization of the critical loads all other
loads are connected.
Fig 4 : Initial Network

Table 2 : Bus Data Of Initial Network
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178 | P a g e
The whole recovery process is divided into 3
Due to any critical fault or transient in the
network a complete blackout will be occurring.
RECONSTRUCTION:
The generator (Slack bus) started first &
based on the sequence of starting & starting time
the generators on the network are started.
Initially the critical loads are fed & later
ical loads all other

Fig 4 : Initial Network
Table 2 : Bus Data Of Initial Network
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Fig 5 : System Reconstruction Stage
VII OUTPUT OF INITIAL NETWORK
Power Flow Solution by Newton-Raphson
Method
Maximum Power Mismatch = 3.83432e-005
No. of Iterations = 4

Table 3 : Output Of Initial Network
Bus
No
Bus
Code Voltage
Load Generator
MW Mvar MW Mvar
1 0 1 0 0 0 0
2 0 1 0 0 0 0
3 0 1 322 2.4 0 0
4 0 1 500 184 0 0
5 0 1 0 0 0 0
6 0 1 0 0 0 0
7 0 1 233.8 84 0 0
8 0 1 522 176 0 0
9 0 1 0 0 0 0
10 0 1 0 0 0 0
11 0 1 0 0 0 0
12 0 1 7.5 88 0 0
13 0 1 0 0 0 0
14 0 1 0 0 0 0
15 0 1 320 153 0 0
16 0 1 329 32.3 0 0
17 0 1 0 0 0 0
18 0 1 158 30 0 0
19 0 1 0 0 0 0
20 0 1 628 103 0 0
21 0 1 274 115 0 0
22 0 1 0 0 0 0
23 0 1 247.5 84.6 0 0
24 0 1 308.6 -92 0 0
25 0 1 224 47.2 0 0
26 0 1 139 17 0 0
27 0 1 281 75.5 0 0
28 0 1 206 27.6 0 0
29 0 1 283.5 26.9 0 0
30 2 1 0 0 250 0
31 1 1 9.2 4.6 0 0
32 2 1 0 0 650 0
33 2 1 0 0 632 0
34 2 1 0 0 508 0
35 2 1 0 0 650 0
36 2 1 0 0 560 0
37 2 1 0 0 540 0
38 2 1 0 0 830 0
39 2 1 1104 250 1000 0
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Total 6097
1409 6145 1445.9 0

Fig 6 : Load Recovery Stage

VIII Results Of Newton-Raphson
Method
--Line-- Power at bus & line flow
--Line loss--
From To MW Mvar MVA
MW Mvar
1 0.000 0.000 0.000
2 -125.392 24.820 127.824 0.671 -
61.246
39 125.392 -24.820 127.824 0.158 -
71.359

2 0.000 0.000 0.000
1 126.063 -86.066 152.640 0.671 -
61.246
3 363.659 94.209 375.664 1.924 -
2.131
25 -239.722 66.443 248.759
4.534 -8.760
Bus
no Voltage Angle Load Generation Injected
MW Mvar MW Mvar Mvar
1 1.004 -8.408 0 0 0 0 0
2 0.985 -5.3 0 0 0 0 0
3 0.966 -8.525 322 2.4 0 0 0
4 0.944 -9.657 500 184 0 0 0
5 0.95 -8.525 0 0 0 0 0
6 0.953 -7.782 0 0 0 0 0
7 0.942 -10.22 233.8 84 0 0 0
8 0.942 -10.77 522 176 0 0 0
9 0.988 -10.47 0 0 0 0 0
10 0.962 -4.966 0 0 0 0 0
11 0.958 -5.922 0 0 0 0 0
12 0.937 -5.876 7.5 88 0 0 0
13 0.957 -5.712 0 0 0 0 0
14 0.951 -7.457 0 0 0 0 0
15 0.947 -7.538 320 153 0 0 0
16 0.961 -7.538 329 32.3 0 0 0
17 0.965 -5.752 0 0 0 0 0
18 0.964 -8.098 158 30 0 0 0
19 0.979 0.195 0 0 0 0 0
20 0.976 -0.81 628 103 0 0 0
21 0.959 -2.97 274 115 0 0 0
22 0.976 2.178 0 0 0 0 0
23 0.973 1.939 247.5 84.6 0 0 0
24 0.967 -5.612 308 -92 0 0 0
25 0.996 -3.796 224 47.2 0 0 0
26 0.987 -5.072 139 17 0 0 0
27 0.97 -7.291 281 75.5 0 0 0
28 0.989 -1.128 206 27.6 0 0 0
29 0.992 1.96 283 26.9 0 0 0
30 1 -2.668 0 0 250 87.276 0
31 1 0 9.2 4.6 525.41 227.41 0
32 1 2.801 0 0 650 234.37 0
33 1 5.394 0 0 632 141.95 0
34 1 4.497 0 0 508 133.09 0
35 1 7.64 0 0 650 195.64 0
36 1 10.907 0 0 560 133.3 0
37 1 3.416 0 0 540 336.39 0
38 1 9.433 0 0 830 65.866 0
39 1 -10.19 1104 250 1000 190.66 0
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30 -250.000 -74.586 260.889 0.000
12.691

3 -322.000 -2.400 322.009
2 -361.736 -96.340 374.345 1.924 -2.131
4 90.339 85.188 124.170 0.241 -16.229
18 -50.603 8.752 51.355 0.034
-19.479

4 -500.000 -184.000 532.781
3 -90.098 -101.416 135.657 0.241 -16.229
5 -140.702 -43.228 147.193 0.190 -8.983
14 -269.200 -39.356 272.062 0.661
-1.741

5 0.000 0.000 0.000
4 140.892 34.245 144.995 0.190 -8.983
6 -457.407 -77.875 463.988 0.476 2.265
8 316.514 43.629 319.507 0.911 -0.462

6 0.000 0.000 0.000
5 457.883 80.139 464.843 0.476 2.265
7 420.738 84.670 429.173 1.223 8.594
11 -362.412 -21.029 363.021 1.014 -0.800
31 -516.210 -143.780 535.859 0.000 79.029

7 -233.800 -84.000 248.432
6 -419.516 -76.076 426.358 1.223 8.594
8 185.716 -7.924 185.885 0.155 -5.140

8 -522.000 -176.000 550.872
5 -315.604 -44.092 318.669 0.911 -0.462
7 -185.560 2.784 185.581 0.155
-5.140
9 -20.836 -134.692 136.294 0.371 -29.592

9 0.000 0.000 0.000
8 21.207 105.100 107.218 0.371 -29.592
39 -21.207 -105.100 107.218 0.027
-117.899

10 0.000 0.000 0.000
11 364.020 65.127 369.800 0.593
-0.339
13 285.980 73.760 295.339 0.379
-2.637
32 -650.000 -138.887 664.673 0.000
95.486

11 0.000 0.000 0.000
6 363.425 20.229 363.988 1.014 -0.800
10 -363.427 -65.466 369.276 0.593
-0.339
12 0.001 45.237 45.237 0.036
0.971

12 -7.500 -88.000 88.319
11 0.034 -44.266 44.266 0.036
0.971
13 -7.534 -43.734 44.379 0.036
0.976

13 0.000 0.000 0.000
10 -285.601 -76.397 295.642 0.379
-2.637
14 278.031 31.687 279.830 0.774
-6.998
12 7.570 44.710 45.347 0.036
0.976

14 0.000 0.000 0.000
4 269.861 37.615 272.470 0.661 -1.741
13 -277.256 -38.685 279.942 0.774
-6.998
15 7.395 1.070 7.472 0.007
-32.872
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15 -320.000 -153.000 354.696
14 -7.388 -33.942 34.737 0.007
-32.872
16 -312.612 -119.058 334.516 1.106
-4.022

16 -329.000 -32.300 330.582
15 313.718 115.036 334.144 1.106
-4.022
17 230.494 -60.279 238.246 0.425
-7.052
19 -502.095 -35.931 503.379 4.372
24.659
21 -328.465 35.266 330.353 0.953
-7.401
24 -42.651 -86.392 96.347 0.028
-5.761

17 0.000 0.000 0.000
16 -230.070 53.226 236.147 0.425
-7.052
18 208.966 -6.651 209.072 0.328
-8.420
27 21.104 -46.575 51.134 0.020
-29.845

18 -158.000 -30.000 160.823
3 50.638 -28.231 57.976 0.034 -19.479
17 -208.638 -1.769 208.645 0.328
-8.420

19 0.000 0.000 0.000
16 506.468 60.590 510.079 4.372
24.659
33 -629.063 -82.369 634.433 2.937
59.579
20 122.595 21.779 124.515 0.113
2.230

20 -628.000 -103.000 636.391
34 -505.518 -83.451 512.360 2.482
49.640
19 -122.482 -19.549 124.032 0.113
2.230

21 -274.000 -115.000 297.155
16 329.418 -42.667 332.170 0.953
-7.401
22 -603.418 -72.333 607.738 3.202
32.014

22 0.000 0.000 0.000
21 606.620 104.347 615.529 3.202
32.014
23 43.380 25.408 50.273 0.019
-17.229
35 -650.000 -129.755 662.825 0.000 65.891
23 -247.500 -84.600 261.560
22 -43.361 -42.636 60.811 0.019 -17.229
24 354.204 1.205 354.206 2.924 12.573
36 -558.343 -43.168 560.009 1.657 90.132

24 -308.600 92.000 322.022
16 42.680 80.631 91.230 0.028 -5.761
23 -351.280 11.369 351.464 2.924 12.573

25 -224.000 -47.200 228.919
2 244.256 -75.204 255.571 4.534 -8.760
26 69.987 -3.567 70.078 0.173 -48.698
37 -538.242 31.571 539.168 1.758 67.958

26 -139.000 -17.000 140.036
25 -69.813 -45.131 83.131 0.173 -48.698
27 261.018 80.848 273.252 1.102
-11.383
28 -140.507 -24.706 142.663 0.879
-66.490
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29 -189.697 -28.011 191.754 2.134
-77.314

27 -281.000 -75.500 290.966
17 -21.084 16.731 26.915 0.020
-29.845
26 -259.916 -92.231 275.795 1.102
-11.383

28 -206.000 -27.600 207.841
26 141.386 -41.784 147.431 0.879
-66.490
29 -347.386 14.184 347.676 1.737
-5.691

29 -283.500 -26.900 284.773
26 191.831 -49.304 198.066 2.134
-77.314
28 349.123 -19.874 349.688 1.737
-5.691
38 -824.454 42.278 825.537 5.546
108.145

30 250.000 87.276 264.796
2 250.000 87.277 264.797 0.000 12.691

31 516.208 222.807 562.239
6 516.210 222.809 562.242 0.000 79.029

32 650.000 234.370 690.963
10 650.000 234.373 690.964 0.000 95.486

33 632.000 141.947 647.745
19 632.000 141.948 647.745 2.937
59.579

34 508.000 133.091 525.145
20 508.000 133.091 525.145 2.482
49.640

35 650.000 195.644 678.805
22 650.000 195.646 678.806 0.000
65.891

36 560.000 133.300 575.646
23 560.000 133.301 575.647 1.657
90.132

37 540.000 36.387 541.225
25 540.000 36.388 541.225 1.758
67.958

38 830.000 65.866 832.609
29 830.000 65.867 832.609 5.546
108.145

39 -104.000 -59.340 119.738
1 -125.234 -46.539 133.602 0.158 -71.359
9 21.234 -12.799 24.793 0.027
-117.899

Total loss 48.310 36.862

IX.CONCLUSION
This paper presents the use of
Dijkstras Algorithm for service restoration
plan after a complete blackout. The large
number of possible outage conditions & the
need to provide a restoration plan in minimum
time are argument in favor of this technique.
By application of graph theory the process had
been made simple and user friendly. In order
to demonstrate the efficiency of dijkstras
algorithm it has been applied to IEEE 10
Generator 39 Bus System. We carry out three
stages of recovery process by using dijkstras
algorithm. Newton-Raphson method is used to
carry out load flow analysis. The simulation
results show that Newton-Raphson method is
effective and promising. It has been found that
by application of dijkstras algorithm the
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Methods Enriching Power and Energy Development (MEPED) 2014 184 | P a g e



transmission losses can be reduced to
significant extent.The advantages are (1)
solution procedure leads to the optimum
solution & (2) avoid combinational explosion
of the number of the number of configurations
to be tested. This it is believed that the results
from Dijkstras algorithm in power system
restoration results in better plan, so it can be
considered for real time application.Since the
simulation implementation is done only for 39
bus system it can be extended to networks
with more number of buses.
REFERENCES
[1] M.M. Adibi, R.J. Kafka, and D.P. Milanicz, Expert
System Requirements For Power System
Restoration, IEEE Transactions on Power
Systems, vol. 9, no. 3, pp. 15921598, 1994.
[2] M.M. Adibi, P. Clelland, and L. Fink et al., Power
System Restoration- A Task Force Report, IEEE
Transactions on PowerSystems, vol. 2, no. 2, pp.
271277, 1987.
[3] M.M. Adibi, J.N. Borkoski, and R.J. Kafka, Power
System Restoration -- The Second Task Force
Report, IEEE Transactions on Power Systems, vol.
2, no. 4, pp. 927933, 1987.
[4] M.M.Abidi & R.J.Kafka, Power System Restoration
Issues, 1990.
[5] Ancona J.J,A framework for power system
restoration following major power failure ,IEEE
Transactions on power systems, Vol 9,pp.1480-
1485,August 1995.
[6] Black-Start Network Partitioning Considering Time
limits & Subsystem Restoration Sequences Liang
Hai-ping, Ma Hui-yuan, Gu Xue-ping IEEE
transactions on Power System,2011.
[7] Development of an Interactive rule based system
for bulk power system restoration ,C.Y.Teo &
Weishen,IEEE transaction on Power System, Vol-
15, Num-2, May 2000.
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Methods Enriching Power and Energy Development (MEPED) 2014 185 |P a g e

Fuzzy Logic Controller with Maximum Power Point
Tracking for Three-Phase Grid-Connected
PV System
V.Bala
1
, G.Rajeswari
2

Department Of EEE, Valliammai Engineering College, Chennai


ABSTRACT
A simple closed loop controller has been developed
for interfacing PV array with utility grid through a
three-phase line-commutated inverter. The closed
loop controller has been employed to track and
feed maximum power to the grid. A PIC
microcontroller together with a multiplier and op
amp signal conditioning circuit has been used for
the generation of firing pulses to the thyristors in
the inverter. The firing angle is automatically
adjusted by the closed loop controller to extract
maximum power from the solar PV array, which is
fed to the utility grid. The simulink model of the
proposed scheme employing Fuzzy Logic
Controller has been developed using
MATLAB/PSB. The results obtained from the
experimental investigation and simulation studies
of the proposed scheme are compared and the value
of firing angle at which maximum power is fed to
the grid is found to be in close agreement. To
reduce the current harmonics introduced by the
line-commutated inverter on the grid side, a
capacitor bank is connected across the utility grid.

Keywords: Fuzzy systems, Inverters,
Maximum power point tracking, Photovoltaic
I. INTRODUCTION
With the industrial development, the problem of
energy shortage is more and more aggravating. The
Photovoltaic (PV) system technologies are rapidly
expanding and have increasing roles in electric
power technology and regarded as the green energy
of the new century [1]. The solar cell has an
optimum point corresponding to the maximum
power. The output power of a PV array varies
according to the sunlight conditions, atmospheric
conditions including cloud cover, local surface
reflectivity, and temperature. To obtain maximum
power from photovoltaic array, photovoltaic power
system usually requires maximum power point
tracking (MPPT) controller [2]. Various
approaches have been reported to implement
MPPT. The Perturb and Observe (P&O) method
needs to calculate dP/dV to determine the
maximum power point (MPP) [3],[4]. Though it is
relatively simple to implement, it cant track the
MPP when the irradiance changes rapidly; and it
oscillates around the MPP instead of directly
tracking it. The Incremental Conductance method
can track MPP rapidly but increases the complexity
of the algorithm, which employs the calculation of
dI/dV [5]. The Constant Voltage method [6], which
uses 76% open circuit voltage as the MPP voltage,
and the Short- Circuit Current method [7] are
simple, but they do not always accurately track
MPPs. A single-stage PV generation system was
presented by Liang et al. [8], but it needs nontrivial
calculations for MPPT and the control loop is
complex. MPPT for grid-connected PV system
have been proposed using three-arm rectifier-
inverter [9]. This describes a single-phase system
and employs line-frequency switching only for
common arm of the inverter, in order to reduce the
switching loss. MPPT using fuzzy logic have also
been reported [10], [11]. These studies show that
the fuzzy control algorithm is capable of improving
the tracking performance as compared with the
conventional methods for both linear and non-
linear loads. However, these schemes supply only
an isolated load. In this paper, a fuzzy logic
controller is proposed for maximum solar power
tracking of the PV array with a line-commutated
inverter for a three-phase grid-connected system.
This method requires only the linguistic control
rules for maximum power point; the mathematical
model is not required.
II. PROPOSED SCHEME

The block diagram of the proposed scheme is
shown in Fig.1. This scheme of power generation
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Methods Enriching Power and Energy Development (MEPED) 2014 186 |P a g e

consists of PV array, a line-commutated SCR
inverter, a step-up transformer and the fuzzy logic
controller. The PV array converts the solar into
electrical power.
Fig.1 Basic PV system integrated with three phase
utility grid
This is fed to the 6-pulse Thyristor Bridge, which
acts as line-commutated inverter through dc link
inductance. This inductance is used to obtain a
steady direct current from the PV panels. The line-
commutated inverter transfers the power from the
PV panels to the utility grid via the step-up
transformer.
The FLC takes two inputs, namely the actual
power output P
o
at the output of the transformer
and the maximum reference power which is
calculated based on V
oc
and I
sc
of the PV array as
explained in section III. It is to be noted that the
V
oc
of the array will vary with temperature and I
sc

will vary with irradiation. The error between the
actual power and the reference power is used for
modulating the firing angle delay for the line-
commutated inverter, so that maximum power is
fed to the grid. The FLC produces an output which
is used for varying the firing angle of the inverter
till the actual power equals the maximum power.
The transformer is used to adjust the voltage level
of the inverter output to match that of utility for
proper operation of the system.

A. PV Array Model
The classical equation of a PV cell describes the
relationship between current and voltage of the cell
(neglecting the current in the shunt resistance of the
equivalent circuit of the cell) as [12]


I
pv
- Iph- Io[

1
which is written as

(2)
where,

10

(3)
since,


The above equations can be used to determine the
characteristics of a panel or an array, as it is evident
that the characteristics of a panel made up of
identical cells can be obtained by appropriately
scaling the I-V characteristics of the individual
cells.
Neglecting the effect of the recombination losses
in the i-layer, the analytical model yields the
following expression:

ln

(4)
The PV model developed using the above
equation is used for simulation in the proposed
scheme.
B. Line - Commutated Inverter
It is well known that a fully controlled SCR
converter shown in Fig. 2 can operate both as
rectifier and inverter depending upon the range of
firing angle. In the proposed scheme, the converter
operates as an inverter. The dc output voltage and
the current in phase-a, of the three-phase full
converter, for a firing angle = 150
o
are shown in
Fig. 3. If the thyristors are numbered as shown in
Fig. 2, the normal firing sequence is 12, 23, 34, 45,
56 and 61. So, if the load is capable of supplying
power, then the direction of power flow can be
reversed by reversal of the dc voltage, the current
direction being unchanged. The delay angle must
be greater than 90
o
. In the present case, no extra
effort is required to synchronize the inverter output
with grid supply. This of course is possible only
with SCR converters.
Line-
commutat
ed inverter
a
V
R L
Three
-
phase
Firing
pulse

P
V
+
_

V
I
Fuzzy
Logic

V

I
b
Filter
P
Pr
Three
-
phase
c
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Fig 2: Circuit of three-phase fully controlled bridge
converter



Fig 3: Voltage and current waveforms of three phase full
converter
(i) Harmonics:
The rms value of n
th
harmonic current in phase-a is
given by,

sin



(5)
The rms value of the fundamental current is

= 0.7797

(6)
The total rms current in phase a is given by,

()

= 0.8165



(7)
Now, harmonic factor (HF) or total harmonic
distortion (THD) is given by,
HF=

= 0.3108 i.e THD = 31.08%


(8)
The active and reactive powers in three-phase full
converters at the fundamental frequency
respectively are given by,
=

cos() (9)
=

sin() =

sin() (10)
III. FUZZY LOGIC CONTROLLER
The classical (P, PI, PID) control technique has
been the basis in simple control systems. Since
classical controllers are fixed-gain feedback
controllers, they cannot compensate the parameter
variations in the plant and cannot adapt changes in
the environment. In classical conventional
techniques, mathematical modeling of the plants
and parameter tuning of the controller have to be
done before implementing the controller.
Therefore, a classical controller is not suitable for
nonlinear control application. The need to
overcome such problems and to have a controller
well-tuned not only for one operating point but also
for a whole range of operating points has motivated
the other control techniques and the idea of an
adaptive controller. In a fuzzy logic control system,
there is no necessity for a plant model. The plant
can be single input single output (SISO) or multi
input multi output (MIMO) in nature. The block
diagram of fuzzy logic control scheme is shown in
Fig. 4. Fuzzy logic controller is composed of 3
parts: fuzzification, inference engine and
defuzzification as described below.
A. Fuzzification
The values of membership function are assigned to the
linguistic variables using seven fuzzy subsets called
negative big (nb), negative medium (nm), negative small
(ns), zero (zr), positive small (ps), positive medium (pm),
positive big (pb). Variables e and de are selected as input
variables, where e is the error between the reference
power (P
ref
) and the actual power (P
act
) of system; de is
the change in error in the sampling interval. The output
variable is the change in firing angle, dalpha. Triangular
membership functions (trimf) are selected for all these
singletons. The membership functions of the variables
error, change in error and change in firing angle are
Pact
e
d
e

FLC

Plant
Pref
+

-
-
v
bc

v
ab
-v
ca
v
bc
-
v
ab

v
ca


PV
L
Three-
phase
R
T4 T T
T T
Step -
up
T
+
-
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Methods Enriching Power and Energy Development (MEPED) 2014 188 |P a g e

D
e
g
r
e
e

o
f

m
e
m
b
e
r
s
h
i
p


dalpha
D
e
g
r
e
e

o
f

m
e
m
b
e
r
s
h
i
p


de
shown in Figs. 5, 6 respectively. The range of each
membership function is decided by the previous
knowledge of the proposed scheme parameters. Error is
limited between -50 and 50 watts since the change in
actual power fed to the grid and the reference maximum
power has been found to be within this limit from the
open loop scheme of the proposed model.

Fig. 4. Fuzzy Logic Control Scheme

and change in firing angle is set between -45 to 45
degrees because the range of firing angle of an
inverter is 90. The reference power, variable e and
de are expressed as follows:
The peak voltage, V
mp
and peak current, I
mp
of
Fig. 6. Membership function plots de the PV
array are obtained by
V
mp
= k
1
V
oc
(11)
I
mp
= k
2
I
sc
(12)

Fig. 5. Membership function plots e



Fig.6.Membership functions for dalpha

where, k
1
, k
2
are proportional constants [13],[14].
Thus, the peak power of the PV array can be
obtained from (11) and (12). The error and change
in error during the sampling instant k are given as

e(k) = P
ref
P
act
(13)
de (k) = e(k) e(k-1) (14)
Therefore, e(k) is zero at the maximum power
point of a PV array.
B. Inference Engine
Inference engine mainly consists of two sub
blocks namely, fuzzy rule base and fuzzy
implication. The inputs which are now fuzzified are
fed to the inference engine and the rule base is then
applied; the output fuzzy sets are then identified
using fuzzy implication method. Table I shows the
rule base of fuzzy logic controller, where all the
entries of the matrix are fuzzy sets of error (e),
change in error (de) and change in firing angle
(dalpha) to the line-commutated inverter. The
consequent fuzzy region is restricted to the
minimum (MIN) of the predicate truth while
selecting output fuzzy set. The output fuzzy region
is updated by taking the maximum (MAX) of these
minimized fuzzy sets during shaping of output
fuzzy space.
C. Defuzzification
After fuzzy implication, output fuzzy region is located.
As the final desired output is a non-fuzzy value of
control, a defuzzification stage is needed. Bisector
defuzzification method is used for defuzzification in the
proposed scheme. Here, the actual value of the change in
firing angle is calculated by (15), which partitioned the
area under the aggregate fuzzy set into two equal parts as
shown in the Fig. 8.
Fig. 7. Bisector Defuzzification Method.

( ) ( )

d d
d
d d d
d
d =
0
0

(15)

TABLE I: Fuzzy associative memory for the proposed

e
nb Nm ns Zr ps pm pb
nb nb Nb nb Nb nm ns zr
nm nb Nb nb Nm ns zr ps
ns nb Nb nm Ns zr ps pm
zr nb Nm ns Zr ps pm pb
ps nm ns zr Ps pm pb pb
pm ns zr ps Pm pb pb pb
pb zr ps pm Pb pb pb pb
de
d
(d)
d
o



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Methods Enriching Power and Energy Development (MEPED) 2014 189 |P a g e

system .


IV. COMPUTER SIMULATION
The PV array in the proposed scheme consists of
solar PV array of 54V, 12A (three panels of 18V,
4A in series and three such cascaded arrangements
connected in parallel). The actual power fed to the
grid is compared with the reference maximum
power that can be obtained at the grid for a given
V
oc
and I
sc
. The error is calculated and accordingly
the firing angle delay to the inverter is changed in
order to deliver maximum power to the grid. Every
time the change in firing angle is added to the
previous firing angle, the thyristors will be fired
accordingly.
The model of PV array has been implemented in
PSB using an independent current source (I
sc
), a
controlled current source (I
d
), measurement blocks
and arithmetic blocks. The three-phase converter
circuit has been modeled using the power
electronic switches available in PSB. The PV
model developed is appropriately connected to the
inverter through the dc link and the output is
connected to the three-phase utility grid. The PV
array in the proposed scheme consists of three
panels each rated for 18V, 4A connected in series
and three such strings connected in parallel. The
closed loop model of the proposed scheme is
obtained. The simulation results of the controller
showing the variation of error, firing angle delay
and the active power fed to the grid with time are
shown.
It is seen that the error decreases with time and
finally reaches zero, ensuring that the error
between the maximum reference power and the
actual power fed to the grid is zero. The variation
of firing angle delay, shows that the delay angle
is increased to reach the maximum power point,
and once the error reaches zero, the delay angle
remains constant. It is seen that the time delay in
the firing of thyristor 1 after the zero crossing
detection is 6.1 ms. Hence the firing angle delay at
which the maximum power is fed to the grid is
6.4*(360/20) = 115.2.

V. CONCLUSIONS AND FURTHER RESEARCH
A simple power electronic controller for
interfacing photovoltaic arrays with the three-phase
grid through a line-commutated inverter and step-
up transformer has been developed. Simulation
studies of the closed loop scheme with Fuzzy Logic
Controller have been carried out. The fuzzy control
is an effective tool in feed back systems to track
and extract maximum power to the grid. There are
no difficulties like proportional and integral gain
adjustments. The use of SCR converter in inverter
mode has resulted in less complicated power
circuit. Further, it has the advantage of lesser
switching power loss over forced commutated
inverter with self-commutating devices such as
IGBTs and power MOSFETs. However, due to the
inverter used in the proposed scheme, certain
harmonics have been introduced in the grid current.
A three-phase capacitor bank is kept across the grid
to reduce the current harmonics induced by the
line-commutated inverter. This has improved the
grid-current waveform and hence reduced
harmonics in the three-phase grid current, thereby
decreasing the THD. The harmonic spectrum for
the grid current waveforms with and without filter
have been obtained to prove that the introduction of
capacitor filter across the grid has eliminated the
lower order harmonics to a great extent, thus
bringing down the THD to within 10%.
REFERENCES
[1] Takashi Hiyama, Shinichi Kouzuma, Tomofui
Imakubo, Evaluation of Neural Network Based
Real Time Maximum Power Tracking Controller
For PV system, IEEE Transactions on Energy
Conversion, Vol. 10, No.3, September 1995.
Table II: Comparative simulation results
Parameters Simulation Results
Firing angle at which
maximum power
occurs,
115.6
DC link voltage, V
dc
(
V)
-31.3
DC link current, I
dc
( A) 6.4
Grid current, I
rms
( A) 4.44
Active power fed to the
grid, P
grid
( W)
-128.4
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Methods Enriching Power and Energy Development (MEPED) 2014 190 |P a g e

[2] T. Ohnishi, S. Takata, Comparisons of Maximum
Power Tracking Strategy of Solar Cell Output and
Control Characteristics Using Step Up/Down
Chopper Circuit, Trans. IEEJ, 112-D, 3, 250/257
(1992).
[3] O. Wasynczuk, Dynamic behavior of a class of
photovoltaic power systems, IEEE Trans. Power
App. Syst.., Vol. PAS-102, pp. 30313037,
Sept. 1983.
[4] E. Koutroulis, K. Kalaitzakis, N.C.
Voulgaris,Development of a Microcontroller
Based, Photovoltaic Maximum Power Point
Tracking Control System, IEEE Transactions on
Power Electronics, Vol. 16, No.1, pp. 46-54,
January 2001.
[5] K.H. Hussein, I. Muta, Maximum Photovoltaic
Power Tracking: An Algorithm for Rapidly
Changing Atmospheric Conditions, IEEE
Proceedings on Generation, Transmission, and
Distribution, Vol. 142, No.1, pp. 59-64, January
1995.
[6] T. Noguchi, S. Togashi, R. Nakamoto, Short-
Current Pulse-Based Adaptive Maximum-Power-
Point Tracking for a Photovoltaic Power Generation
System, Electrical Engineering in Japan, Vol. 139,
No.1, pp. 65-72, 2002.
[7] J.H.R .Enslin, M.S. Wolf, D.B. Snyman, W.
Swiegers, Integrated Photovoltaic Maximum
Power Point Tracking Converter, IEEE
Transactions on Industrial Electronics, Vol.44,
No.6, pp. 769-773, December 1997.
[8] T.J. Liang, Y.C. Kou, J.R. Chen, Single-Stage
Photovoltaic Energy Conversion System, IEE
Proceedings on Electrical Power Application,
Vol.148, No.4, pp. 339-344, July 2001.
[9] J. M. Chang, W. N. Chang, S. J. Chiang, Single-
Phase Grid- Connected using Three-Arm
Rectifier-Inverter, IEEE Transactions on
Aerospace and Electronic Systems, Vol. 42, No. 1,
pp. 211-219, January 2006.
[10] M. Veerachary, T. Senjyu, K. Uezato,
Feedforward Maximum Power Point Tracking of
PV Systems using Fuzzy Controller, IEEE
Transactions on Aerospace and Electronic Systems,
Vol. 38, No. 3, pp. 969981,July 2002.
[11] C.Y. Won, D.H. Kim, S.C. Kim, W.S. Kim, H.S.
Kim, A new maximum power point tracker of
photovoltaic arrays using fuzzy controller,
Proceedings of PESC, pp. 396-403, 1994.
[12] S. Arul Daniel, N. Ammasai Gounden, A Novel
Hybrid Isolated Generating System Based on PV
Fed Inverter-Assisted Wind-Driven Induction
Generators, IEEE Transactions on energy
conversion, Vol. 19, No. 2, pp. 416-422, June
2004.
[13] Dong-Yun Lee, Hyeong-Ju Noh, Dong-Seok Hyun,
Ick Choy, An Improved MPPT converter Using
Current Compensation Method for Small Scaled
PV-Applications, IEEE Conference, 2003, Vol. 3,
pp. 540-545.
[14] S. Yuvarajan, Shanguang Xu, Photo-Voltaic Power
Converter with a Simple Maximum-Power-Point-
Tracker, IEEE conference, 2003, Vol. 3, pp. 399-
402.


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Enhancement of Managing Load of PV System with Grid
Tied Inverter Using MPPT Estimate PERTURB
PERTURB Method

VIVEK.A
1
,JENSEN FERNANDO
2
1,2
St. Josephs college of engineering,Chennai,INDIA


ABSTRACT
The present energy scenario needs to be
developed using renewable energy sources to
avoid pollution free air and to keep the natural
resources for some more extend. According to
our scheme, an optimized design of grid-tied PV
system without storage is proposed which is
suitable for Industries as it requires less
installment cost. Higher PV system power
output can be withdrawn with the help of
implementing MPPT estimate perturb perturb
algorithm. This project is trying to propose an
optimized scheme which would be suitable to
demonstrate how the grid-tied PV systems can
be organized with an efficient use of solar
energy. One of the main objectives of the project
is to reduce the Electricity Tariff and to reduce
the usage of fuel for power production in order
to avoid the future demand, this project
proposes an optimized design of grid-tied PV
system without storage. Use of solar energy in
industries is never been tried widely due to
technical inconvenience, and high installment
cost and this project is that to mitigate these
problems (mainly for heavy load areas).

I. INTRODUCTION TO THE
ENERGY SCENARIO

Solar energy is the real and unpolluted energy
forever. Demand of electrical energy and less
availability of present resources. In our project, we
would like to improve the present solar collector
system to produce more electrical power.
According to our system, our time investment will
lead good payback. Before investigating the solar
power, we would like to look the energy scenario
of India till 2006

1.1 MAJOR POWER GENERATION

a) Thermal-64.4% b) Atomic-2.7% c)
Renewable-4.9% d) Hydro -26%
In the power production scenario, solar power
doesnt play any role and not contributing even

1%.But India is the country, where sunlight
intensity is very high and thats the main natural
resource also [1]. To keep the above in mind, we
would like to develop an efficient power collection
and advanced intelligent charging system for solar
based power generation. The main drawbacks of
PV systems are high fabrication cost and low
conversion efficiency, which are partly caused by
their nonlinear and temperature dependent V-I and
P-I characteristics. To overcome these problems,
the maximum power operating point of the PV
system is tracked using online or offline algorithms
and the system operating point is forced toward this
optimal condition.

2. MAXIMUM POWER POINT
TRACKING

Maximum Power Point Tracking (MPPT) is used
in photovoltaic (PV) systems to continuously tune
the system, so that it draws maximum power from
the solar array irrespective of weather or load
conditions [2-3]. The problem of nonlinear and
temperature dependent V-I and P-I characteristics
are solved with the help of MPPT is depicted in fig
1. Many maximum power point tracking techniques
have been proposed and implemented [4]. They are
categorized as follows
Perturbation & Observation (P&O)
method
Modified Perturbation & Observation
method
Estimate perturbation & perturbation
(EPP) method


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Fig 1 - Typical PV module I-V and P-V characteristics
A MPPT tracks the maximum power
point, which is going to be different from the STC
(Standard Test Conditions) rating under almost all
situations. Under very cold conditions a 75 watt
panel is actually capable of putting over 80 watts
because the output goes up as temperature goes
down. On the other hand under very hot conditions,
the power drops and the power lost as the
temperature goes up. MPPT are most effective
under these conditions: Winter, and/or cloudy or
hazy days - when the extra power is needed. Cold
weather - solar panels work better at cold
temperatures, but without a maximum power
tracker you are losing most of that. Cold weather is
most likely in winter - the time when sun hours are
low and you need the power the most.

2.1 MPPT TECHNIQUE
PERTURBATION & OBSERVATION
(P&O) METHOD

The P&O algorithm is also called hill-climbing,
but both names refer to the same algorithm
depending on how it is implemented. Hill-climbing
involves a perturbation on the duty cycle of the
power converter and P&O a perturbation in the
operating voltage of the DC link between the PV
array and the power converter .Based on this, EPP
has been developed.
2.2 PROPOSED SYSTEM ESTIMATE
PERTURBATION & PERTURBATION (EPP)
METHOD
A MPPT system has been developed, consisting
of a boost type Dc - Dc converter, which is
controlled by a microcontroller-based unit. The
main difference between the method used in the
proposed MAXIMUM PPT system and other
techniques used in the past is that the PV array
output power is used to directly control the dc/dc
Converter, thus reducing the complexity of the
system. The resulting system has high-efficiency,
lower-cost. The results show that the use of the
proposed MPPT control increases the PV output
power by as much as 15%.A microcontroller is
used to measure the PV array output power and to
change the duty cycle of the dc/dc converter control
signal. By measuring the array voltage and current,
the PV array output power is calculated and
compared to the previous PV array output power.
Comparing with the MP&O algorithm, the EPP
algorithm has a tracking speed of 1.5 times faster
but has the same delay time

Fig-2: EPP method

Between the estimate process and the perturb
process. In each iteration, the dc/dc converter input
voltage and current are measured and the input
power is calculated. The input power is compared
to its value calculated in the previous iteration and
according to the result of the comparison; the duty
cycle of PWM is either incremented, decremented
or remains unchanged. The MPPT process is shown
in fig-2 the starting points vary, depending on the
atmospheric conditions, while the duty cycle is
changed continuously, according to the above-
mentioned algorithm, resulting in the system steady
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state operation around the maximum power point.
The main supply voltage is monitored continuously
and, if it exceeds or decrease certain level, the
synchronizing operation is stopped in orde
prevent damage to the grid. The PV array output
fed to the inverter can be maximized using MPPT
control system. This EPP method is more reliable
than the systems in which the converter duty
cycle is arranged such that the maximum
power is supplied to load.

3 .BASIC BLOCK DIAGRAM FOR THE
WHOLE SYSTEM


fig -3: Block diagram

3.1 GRID TIED INVERTER:
A grid-tie inverter (GTI) or
inverter is a special type of power inverter
converts direct
current (DC) electricity into alternating
current (AC) and feeds it into an existing electrical
grid. GTIs are often used to convert direct current
produced by many renewable energy sources, such
as solar panels or small wind turbines,
alternating current used to power homes and
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Methods Enriching Power and Energy Development (MEPED) 2014
state operation around the maximum power point.
The main supply voltage is monitored continuously
and, if it exceeds or decrease certain level, the
stopped in order to
The PV array output
fed to the inverter can be maximized using MPPT
control system. This EPP method is more reliable
converter duty
cycle is arranged such that the maximum
FOR THE
synchronous
power inverter that
alternating
(AC) and feeds it into an existing electrical
grid. GTIs are often used to convert direct current
produced by many renewable energy sources, such
wind turbines, into the
d to power homes and
businesses. Fig 3- denotes the block diagram for
GTI. The technical name for a grid
"grid-interactive inverter". Grid
inverters typically cannot be used in standalone
applications where utility power is
During a period of overproduction from
the generating source, power is routed into the
power grid, thereby being sold to the local power
company. During insufficient power production, it
allows for power to be purchased from the power
company. The circuit for proposed system is shown
in fig 4
fig-4 : circuit for the proposed system

3.2 SYNCHRONIZATION IN GRID TIED
INVERTER
Synchronization is the process of
the produced power with the grid power
be done by changing the voltage, frequency
and phase angle of the produced power
according to the grid power. This can be done
by writing coding in the PIC controller
are two types of synchronization.
Normal synchronization and accu
synchronization.

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denotes the block diagram for
The technical name for a grid-tie inverter is
interactive inverter". Grid-interactive
inverters typically cannot be used in standalone
applications where utility power is not available.
During a period of overproduction from
source, power is routed into the
power grid, thereby being sold to the local power
company. During insufficient power production, it
allows for power to be purchased from the power
The circuit for proposed system is shown

circuit for the proposed system
ONIZATION IN GRID TIED
Synchronization is the process of combining
produced power with the grid power. It can
be done by changing the voltage, frequency
and phase angle of the produced power
according to the grid power. This can be done
by writing coding in the PIC controller. There
synchronization. They are
Normal synchronization and accurate
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fig-5 : synchronization representation
3.2.1 NORMAL SYNCHRONIZATION
It is the easy way of synchronizing the grid power
with the produced power. It will treat the grid
voltage, frequency are constant and changes can be
done to the produced power according to the
constant value. This type of open loop
synchronization is only of small load systems
alone.

3.2.2 ACCURATE SYNCHRONIZATION
It is a tedious way of synchronizing the grid
power with the produced power. It is the closed
loop system which checks the voltage, frequency
and phase angle and changes can be done to the
produced power frequently. This can be included
for both large as well as small systems Frequency F
1, voltage V 1, Phase angle P 1 (PV) &
Frequency F 2, voltage V 2, Phase angle P 2
(Grid) Microcontroller collects the data from the
grid and the PV systems and give the signal to the
inverter. Inverter will change the voltage,
frequency, phase angle of the produced energy in
the PV system according to the grids voltage,
frequency, phase angle
If V 1 = V 2, F 1 = F 2, P 1 = P 2, then
synchronization will occur and the produced power
can easily mingle with the grid power.

4. OPERATION

There are three separate sections. They are
4.1 PV SECTION:
Solar energy is converted into electrical energy
using solar cells in PV array. The produced voltage
depends on the PV array sizing and rating.
Generated energy is send to a collection of boost
converters which are connected in series. This
boost converter is operated at different levels which
are controlled by a microcontroller. This comprises
the MPPT EPP function. The coding of the MPPT
EPP algorithm is dumped into the microcontroller
which gets the PV voltage data and switches the
boost converter correspondingly. The output of the
boost converter will be a DC voltage of 24 V. The
output of the DC to DC converter and the flow
shown in fig 6.

fig-6 : PV section

4.2 LOCAL GRID
The generated AC voltage from the inverter is
given to the synchronizing circuit which also
receives the supply voltage from the local grid. If
the voltage, frequency, phase angle are equal, the
synchronizing circuit syncs the energy of both PV
and grid. If there is any change in the phase angle
and frequency in the grid, the microcontroller give
signal to the inverter to change the phase angle,
frequency of the produced energy according to the
Grid energy. If suppose the Grid voltage falls
below certain level or zero, the total system shuts
down automatically. This is a safety measure
because there is a possibility of power exporting
from the PV system to the grid, this may affect the
line workers working in the grid. Thus this inverter
provides a safety islanding scheme. The connection
to the local grid is shown in the fig 7


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fig-7: connection to local grid

4.3 DIESEL GENERATOR:
The main disadvantage of the system is that
if there is a power cut, total system does not
work and the energy is being generated is
wasted. In order to overcome this
disadvantage, a diesel generator is connected
to a system. Since many industries already
have a diesel generator, it requires a bus bar to
tie DG with PV system either manually or
automatically. This also have an advantage
that, since the grid is disconnected from the
PV system and Diesel generator there will be
no exporting of power to the grid.

5. SIMULATION CIRCUIT

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to local grid
The main disadvantage of the system is that
if there is a power cut, total system does not
work and the energy is being generated is
wasted. In order to overcome this
a diesel generator is connected
Since many industries already
have a diesel generator, it requires a bus bar to
with PV system either manually or
also have an advantage
disconnected from the
PV system and Diesel generator there will be
SIMULATION CIRCUITS
Fig 8:Circuit of PV system
6. SIMULATION RESULTS:
Fig 9: PV Voltage

Fig 10: Grid Voltage

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Fig 8:Circuit of PV system
6. SIMULATION RESULTS:

Fig 10: Grid Voltage
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The variation of V ,I ,P,T, Light in the PV system
is shown below: (using VB)


Fig 11: PV data graph

CONCLUSION
This grid-tied system enables a home owner to
use an alternative generation from solar energy. If
the alternative power being produced is inadequate,
the deficit will be sourced from the electricity grid.
If the grid power is not available, still the system
will continue to supply critical on-site loads. A
typical solar system would require a large bank of
batteries to store the energy. This represented a
huge investment for the industries before they
could build a functional alternative energy system.
By removing the need for an expensive battery
pack and replacing the large, expensive grid-tied
inverters with smaller, cheaper units that dont need
batteries .Also a new MPPT algorithm called
Estimate Perturb Perturb is proposed in order to
achieve effective tracking of solar energy.

FUTURE SCOPE
Space Based Solar Power Generation is the
latest research topic and if the project is properly
worked out, this project may help to synchronize
the produced energy with the grid energy which
may satisfy the load demand. If the system is
implemented in residential areas, this will reduce
the present Load demand and there is a possibility
of sending the extra generated energy to the grid
and thereby reducing the usage of nonrenewable
resources in order to save that for future generation

REFERENCE:
[1] Bangladesh Energy Crisis: Soul Searching, Energy
Bangladesh, June, 2009.
[2] Islam Sharif Renewable energy development in
Bangladesh, Executive Exchange on the use and
integration of Renewable Energy in the Power Sector,
Madrid, Spain, October 19-23, 2003
[3] Bangladesh Renewable Energy Report, APCTT-
UNESCAP
[4] Islam Sharif Renewable energy development in
Bangladesh, Executive Exchange on the use and
integration of Renewable Energy in the Power Sector,
Madrid, Spain, October 19-23, 2009



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Harmonic Reduction in Wind Energy by Using Multi
Pulse Converter
1
G.Selvalakshmi,
2
D.Ramya Devi,
3
V.Chitra,
4
P.Manikandan

1,2,3
UG EEE FINAL YEAR,
4
Assistant Professor & Head of EEE
Sree Sowdambika College Of Engineering Chettikurichi 626115,Virudhunagar Dist, Tamilnadu, India.


ABSTRACT
Todays world carries many power quality
problems in power system areas. Especially, wind
power plants introduce a great number of non-
linear power electronic devices. A large number of
non-linear power electronic devices can have
significant effect on the harmonic emissions. These
harmonics can become serious threat to the power
quality. So this paper handles the reduction of
harmonics in wind energy. For that, many
techniques are used. Here, multi pulse technique is
used to decrease the Total Harmonic Distortion
(THD) level from both converter and wind energy.
6 and 12 pulse converter have been designed and
simulated in MATLAB/SIMULINK software. By
increasing the number of pulses, the level of
harmonic is reduced. Only one set of controlled
converter has been employed for generating multi
pulses. Switching losses also get reduced through
this operation.

I. INTRODUCTION
The number of wind power plants (WPP) increases
world widely and the nominal power of an average
wind power plant increases. In many countries
wind power has already taken an important part in
the electrical energy production mix. Due to the
importance of wind power, the manufacturers and
transmission system operators (TSO) cannot ignore
the effects of wind power plants on the power
quality and power system stability. Wind power
plants introduce a great number of non-linear
power electronic devices. A large number of non-
linear power electronic devices include an effect of
harmonic emissions [5]. For that, the reduction of
harmonics there are many techniques are used like
filtering and cancellation [3],[4]. So it becomes
harmful to the power quality. That is why harmonic
analysis is developed and taken as an integrated
part of wind power plant design. Because every
power network is unique and has different
characteristics, the effect of the harmonics on every
power system varies. Even if the percentage of the
harmonics seemed small, the harmonic emission
becomes a significant issue when the capacity of a
wind power plant is hundreds of megawatts.
Harmonics are sinusoidal voltages and currents
with frequency multiply integer of the fundamental
frequency that is 50 or 60 Hz in a typical power
system. This can be expressed mathematically as

f
h
= h.f
Where,
h= order of the harmonic (h=1, 2, 3,n),
f= fundamental frequency (harmonic of the
order 1 refers to the fundamental frequency)
f
h
= frequency of the harmonic

In harmonic free power systems currents and
voltages always maintain sinusoidal form. Usually
this is not the case as there are many non-linear
power electronic devices and loads that do not
consume power in a sinusoidal form but for
example consume only some parts of the sinusoidal
current and voltage. This causes distortion in the
current and might distort the voltage waveform and
the result can be seen as harmonic currents. Non-
linear apparatus can be seen as sources of
harmonics that inject harmonic currents or voltages
into the power system. The majority of the
harmonic sources are treated as harmonic current
sources.
The performance improvement of multi-pulse
converter is achieved for Total Harmonics
Distortion (THD) in supply current, DC voltage
ripples and form factor. Pulse number is defined as
the number of pulses in the dc output voltage
within one time period of the ac source voltage. In
high-power applications, AC-DC converters based
on the concept of multi pulse, namely, 12, 18 pulses
are used to reduce the harmonics in ac supply
currents. These are named as multi pulse
converters. They use either a diode bridge or
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thyristor bridge, which is connected with special
arrangement of zigzag transformer. This zigzag
transformer also reduces second harmonics. All the
simulations have been done for similar ratings of
RL Load, for all the multi-pulse converters
configurations, so as to represent a fair comparison
among controlled continuations of multi-pulse
converters. The presented simulation results show
the reduced THD at supply side.

MULTI PULSE METHODS
Multi-pulse methods involve multiple converters
connected so that the harmonics generated by one
converter are cancelled by harmonics produced by
other converters. By this means, certain harmonics
related to number of converters are eliminated from
the power source. In multi-pulse converters,
reduction of AC input line current harmonics is
important as regards to the impact the converter has
on the power system[6].
The Multi pulse Converter theory deals with the
reduction of harmonics present on the source side.
This theory involves with the phase shifting of the
input voltage and thereby breaking the input
voltage into number of pulses [1]. As the pulse
number increases, the harmonics present in the
input decreases and the Total Harmonic Distortion
(THD) reduces.
Multi pulse methods are characterized
by the use of multiple converters or
multiple semiconductor devices with a
common load. Fig 1 show various
techniques used widely for the reduction
of harmonics [8].

Harmonic reduction
Technique



Multi pulse

Filters

PWM
rectifier


converter



Active Passive




Six Twelve Eighteen
Twenty
four Thirty


Figure 1. Various Harmonic Reduction Techniques

The term multi-pulse method is not
defined precisely. In principle, it could be
imagined to be simply more than one pulse.
However, by proper usage in the power
electronics industry, it has come to mean
converters operating in a three phase system
providing more than six pulse of DC per cycle.
Multi-pulse systems result in two major
accomplishments namely,
1. Reduction of ac input line
current harmonics.

2. Reduction of DC output voltage ripple.
Reduction of ac input line current
harmonics is important as regards the
impact the converter has on the power
system[7].
Multi-pulse methods are characterized by the use of
multiple converters or multiple semiconductor
devices with a common load [2].
Phase shifting transformers are an essential
ingredient and provide the mechanism for
cancellation of harmonic current pairs, e.g. the 5th
and 7th harmonics or the 11th and 13th so on. Thus
for harmonic current reduction the multi- pulse
converters are fed from phase shifting transformers.
The phase shift has to be appropriate.

THREE PHASE CIRCUIT BREAKER:
The Three-Phase Breaker block implements a
three-phase circuit breaker where the opening and
closing times can be controlled either from an
external Simulink signal (external control mode), or
from an internal control timer (internal control
mode).
The Three-Phase Breaker block uses three Breaker
blocks connected between the inputs and the
outputs of the block. You can use this block in
series with the three-phase element you want to
switch. See the Breaker block reference pages for
details on the modeling of the single-phase
breakers.
If the Three-Phase Breaker block is set in external
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control mode, a control input appears in the block
icon. The control signal connected to this input
must be either 0 or 1, 0 to open the breakers, 1 to
close them. If the Three-Phase Breaker block is set
in internal control mode, the switching times are
specified in the dialog box of the block. The three
individual breakers are controlled with the same
signal.




Figure 2: Three phase breaker
CIRCUIT DIAGRAM OF CONTROLLED
TWELVE PULSE CONVERTER








Figure 3: Circuit diagram for 12 pulse

SIMULATION OF CONTROLLED MULTI
PULSE CONVERTERS:

Three-phase twelve-pulse converter twelve
thyristors are connected in a bridge manner. A
three-phase supply is connected across the input
terminal of the converter. The output of this
converter is connected to the dc load. Because
thyristor are unidirectional, dc current flows only in
one direction. For generating 12 pulses per
fundamental ac cycle synchronized 12
generator is used.

Simulation Diagram














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control mode, a control input appears in the block
The control signal connected to this input
must be either 0 or 1, 0 to open the breakers, 1 to
Phase Breaker block is set
in internal control mode, the switching times are
specified in the dialog box of the block. The three
ual breakers are controlled with the same
Three phase breaker
CIRCUIT DIAGRAM OF CONTROLLED
TWELVE PULSE CONVERTER
converter
SIMULATION OF CONTROLLED MULTI
pulse converter twelve
thyristors are connected in a bridge manner. A
phase supply is connected across the input
terminal of the converter. The output of this
converter is connected to the dc load. Because
nal, dc current flows only in
one direction. For generating 12 pulses per
fundamental ac cycle synchronized 12-pulse




Figure 4: Simulation of 12 pulse










Figure 5: THD Waveform















Figure 6: Voltage and current

SIMULATION DIAGRAM FOR
CONVERTER UNIT:













Figure 7: Converter unit











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Simulation of 12 pulse converter
THD Waveform Distortion
Voltage and current waveform
SIMULATION DIAGRAM FOR
Converter unit
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Figure 8: Output voltage waveform

PULSE GENERATOR UNIT:

The Pulse Generator block generates square wave
pulses at regular intervals. The block's waveform
parameters, Amplitude, Pulse Width, Period, and
Phase delay, determine the shape of the output
waveform.The Pulse Generator (Thyristor) block
generates two pulse trains. These control a twelve-
pulse thyristor converter made of two three-phase
full-wave thyristor bridges (also called Graetz
bridges). In steady-state condition, each pulse train
consists of six equidistant square pulses with 60
degrees shift between them.





















Figure 9: Pulse generator unit

CONCLUSION
The objective of the present work is to investigate
the performance of controlled multi-pulse
converters. These converters are studied in terms of
harmonic spectrum of AC supply current, Total
Harmonic Distortion, Ripple Content in AC mains.
The harmonic reduction for 12 pulse is done. Best
result of ripple factor, a harmonics reduction and
regulated output voltage is obtained using multi
pulse converter. It is concluded therefore that in
general with increase in number of pulses in multi-
pulse case the performance parameters of these
converters are remarkably improved.

REFERENCE

[1] N. Mohan, T. M. Undeland, W. P. Robbins, Power
Electronics: Converters, Applications, and Design, 3rd
Edition, 2002

[2] J. Arrillaga, Y. H. Liu, L. B. Perera, and N.

R. Watson, A current rein- jection scheme that adds
self- commutation and pulse multiplication to the
thyristor converter, IEEE Trans. Power Del., vol. 21,
no. 3, pp. 1593 1599, Jul. 2006.

[3] L. Weilin, Design and Realization of Star
Connected Autotransformer Based 24-Pulse AC-DC
Converter, International Conference on Power System
Technology, 978-1-4244-5940-7 IEEE, 2010.

[4] P. Srivastava, K. Sanjiv, Simulation of

Multi pulse AC-DC Converters for Medium Voltage
ASDs, VSRD International Journal of Electrical,
Electronics & Communications Engineering. Vol. 1,
No.10, pp. 542-554, Dec. 2011.

[5] Kalle Rauma, School of Electrical
Engineering, Aalto University, Electrical
Resonances and Harmonics in a Wind Power Plant
Thesis submitted for examination for the degree of
Master of Science in Technology Espoo, Finland 17th
February 2012.

[5] K.Srinivas, Assistant Professor, JNTUH College of
Engineering, Andhrapradesh, India. Analysis and
Implementation of Multi Pulse Converters for HVDC
System International Journal of Emerging Technology
and Advanced Engineering, (ISSN 2250-2459, Volume
2, Issue 4, April 2012).

[6].Deependra Singh, Prof. Hemant Mahala,
Prof.Paramjeet Kaur, Modeling & Simulationof
Multi-Pulse Converters for Harmonic Reduction
International Journal of Advanced Computer Research
(ISSN).Volume-2 Number-3 Issue-5 September-2012.

[7]Madhuri Saxena, Sanjeev Gupta,
Simulation of Multi pulse Converter for Harmonic
Reduction using Controlled Rectifier International
Journal of Science and Research (IJSR), India Online
ISSN: 2319-7064, Volume 2 Issue 4, April 2013.

[8] Ms.Shruti Gour, Mr.Saurabh Gupta,
Comparative Analysis of Multipulse AC-DC Converter
Using Zig- Zag Transformer IOSR Journal of
Engineering (IOSRJEN) e-ISSN: 2250-3021, p-ISSN:
2278-8719 Vol. 3, Issue 7 July, 2013.
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MODELLING OF CUSTOM DEVICES FOR
REDUCING VOLTAGE SAG PROBLEMS
P.Banukutti
1
,A.R.Jothisri
2
, U.Vishnupriya
3
, P.Manikandan
4

Student
1, 2, 3,
Assistant Professor
4

Sree Sowdambika College of Engineering, Aruppukottai, TamilNadu
banu5.eee@gmail.com, jothisree014@gmail.com, vishnupriya772@gmail.com,


ABSTRACT
Power quality of gains their importances with the
introduction of sophisticated electrical gadgets .The
performances of these devices are sensitive to the
quality of input power supply. Various power quality
problems results in failure or mal operation of end
user equipments. One of major problems is voltage
sag. To solve this problem, capacitors and voltage
regulator are conventionally used .These techniques
involve inherent drawback. With the advancement of
power electronic devices these drawbacks overcome
easily .The invention of various custom power
devices such as static compensator (STATCOM)
and DVR and unified power quality conditioner
(UPQC) can be used to mitigate voltage sag. In this
work, it is proposed to mitigate voltage sag and
improve the reactive power support at the user level
by using the custom power device of DVR. Custom
power devices are the most efficient and effective
modern devices used in power distribution network.
By this we can reduce the voltage sag in the power
system.
Keywords: Dynamic Voltage Restorer (DVR),
Power Quality Problem, PI controller, voltage sag,
Voltage Source Converter.
I. INTRODUCTION
In the power sector compatible with the power
quality standards in becoming major issue for the
endeavor power distribution utilities [1]. But now a
day power quality problem is impact of the power
system. Voltage sag is one of the major power
quality problems. A voltage sag is a momentary
decrease in rms ac voltage (0.1-0.9 p.u. of the
nominal voltage), at the power frequency, of duration
from cycles to a few seconds. Voltage sag is an
eccentric issue for system performance. Voltage sag
occurred by using sensitive load, programmable logic
control and variable speed drives in the load side.
Voltage sags are most often caused by fuse, breaker
operation, motor starting and capacitor switching.
[7], [8].
This paper introduced a new approach of a FACTS
device for overcome the Voltage sag problem.
Voltage sags are one of the most occurring power
quality problems. Of course, for an industry an
outage is worse, but voltage dips occur more often
and cause severe problems and economical losses.
The most efficient mitigating device for Voltage sag
has the Dynamic Voltage Restorer (DVR). In order to
properly evaluate the contribution of FACTS devices
to system sag performance two points should be
considered: First, the installation of FACTS device
will influence the voltage sag performance of the
whole network even though the primary reason for its
installation might have been to maintain the voltage
at one particular bus. So from a system point of view,
proper evaluation of the benefits resulting from the
installation of the device could reveal a way to solve
a common problem. Second, due to often prohibitive
costs of these devices the full economic benefits
might be derived only if a larger part of the network
is considered therefore, it is important to take new
and comprehensive approach to assessment of
benefits that FACTS devices could bring to the
system in terms of voltage sag reduction [6]











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Fig1.Block diagram of DVR
2. FACTS CONTROLLER
FACTs controller is a power electronic device to be
used for power flow controllability and power
transfer capability. FACTs controller is known as
custom device because it is to improve power flow
controllability and power transfer capability in the
customer side [2].
2.1. VOLTAGE SOURCE CONVERTERS (VSC)
A voltage-source converter is a power electronic
device which can generate a sinusoidal voltage with
any necessary magnitude, frequency and phase angle.
Voltage source converters are widely used in
variable-speed drives, but can also be used to
mitigate voltage dips. The VSC is used to either
totally replace the voltage or to inject the missing
voltage. The missing voltage is the difference
between the nominal voltage and the actual. The
converter is usually based on some kind of energy
storage, which supplies the converter with a DC
voltage. The solid-state electronics in converter is
then switched to get the desired output voltage.
Generally the VSC is not only used for voltage sag
mitigation, but also for other power quality issues,
e.g. flicker, fluctuation and harmonics.

3. SERIES VOLTAGE CONTROLLER
DYNAMIC VOLTAGE RESTORER, (DVR)
DVR is the series voltage control device; the primary
side is connected through the coupling transformer to
power transmission. And secondary side is connected
to the Voltage Source Converter with DC energy
storage. A voltage-source converter is power
electronic devices it can be generate a sinusoidal
voltage with any required magnitude, frequency and
phase angle [3]. The resulting voltages at the load
side are equal to the sum of the source voltage and
injected voltage from the DVR. A DC to AC inverter
regulates this voltage by sinusoidal PWM techniques.
All through normal operating condition, the DVR
injected only a small voltage to compensate for the
voltage drop of the injection transformer and device
losses. However when voltage sag occurs in
transmission system DVR to inject the voltage for
required magnitude and phase angle through injection
transformer. It is linked in series between a power
grid and a load the block diagram of DVR as shown
in fig1.The dc voltage provided by an energy storage
capacitor.



Where,

- Load Voltage.
Vse - DVR voltage.
Vs - Source Voltage.

3. DVR CONTROLLER

Voltage Sag is created by increasing load in the load
terminals as shown in fig.3. The magnitude is
compared with reference voltage (). Pulse width
modulated (PWM) control technique is applied for
inverter switching so as to produce a three phase 50
Hz sinusoidal voltage at the load terminals. [4]
Chopping frequency is in the range of a few KHz
.The MOSFET inverter is controlled with PI
controller in order to maintained in 1 p.u. voltage at
the load terminals i.e. considered as Base voltage
=1p.u.
A proportional-integral (PI) controller [5] (shown in
Fig. 2) drives the plant to be controlled with a
weighted sum of the error (difference between the
actual sensed output and desired set-point) and the
integral of that value. An advantage of a proportional
to plus integral controller is that its integral term
causes the steady-state error to be zero for a step
input. Output of the PI controller block is of the form
of an angle , which introduces additional phase-
lag/lead in the three-phase voltages. The output of
error detector is as following,

........ (2)
Where,

= + (1)
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Vref equal to 1 p.u. voltage
Voltage in p.u. at the load terminals

The controller output when compared at PWM signal
Generator Results in the desired firing sequence.


Fig.2. Schematic of a typical PI Controller
The modulated angle is applied to the PWM
generators in phase A as shown in (2). The angles for
phases B and C are shifted by 120
0
and 240
0

respectively as shown in (3) and (4). In this PI
controller only voltage magnitude is taken as a
feedback parameter in the control scheme [4]. The
sinusoidal signal V control is phase-modulated by
means of the angle and the modulated three-phase
voltages are given by

Va = sin (t +) (2)

Vb= sin (t++2/3) (3)

Vc= sin (t ++4/3) (4)

4. PARAMETERS OF DVR TEST SYSTEM
Table 1. System Parameters
Electrical circuit model of DVR test system is shown
in Fig.3. System parameters are listed in Table 1.
Voltage sag is created at load terminals via a three-
phase fault as shown in Fig.3. Load voltage is sensed
and passed through a sequence analyzer. The
Magnitude is compared with reference voltage (Vref).
The testing of system Parameters are lists in Table 1.
MATLAB Simulation diagram of the test system
comprises of 230 kV, 50 Hz generator, feeding
transmission lines through a coupling transformer
connected in Y/, 120/120 kV.



Fig 5.Simulation diagram for DVR

5. SIMULATION RESULTS

Detailed simulations are performed on the DVR test
System using MATLAB/SIMULINK System
performance is analyzed for compensating voltage
sag to give with or without load. Transition time for
the fault is considered from 0.1 sec to 0.2 sec as
shown in Fig. 5. In this cases are discussed below:

Case1: In normal load condition voltage sag is not
present in the transmission network. Transition time
for the fault is considered from 0.1 sec to 0.2 sec as
S.No System
Quantities
Standards
1. Inverter
Specifications
MOSFET based,3 arms
6 Pulse,
Carrier Frequency =1050
Hz,
Sample Time= 5 s
2. Transmission
Line
Parameter
R=0.001 ohms ,L=0.005 H
3. PI Controller KP=0.5
Ki=0.0003
Sample time=10 s
4. Load-1 Active power = 2 Mw
Inductive Reactive Power
=0.2 Mvar
5. Load-2 Active power = 4 Mw
Inductive Reactive Power
=0.2 Mvar
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shown in Fig 5.1. And the FFT analysis output as
shown in Fig 5.2.



Fig 5.1 Three phase voltage wave form in Normal
condition

Fig 5.2 FFT analysis in Normal condition
Case2: In adding double load in the transmission
network that condition voltage sag is present without
DVR. Transition time for the fault is considered from
0.1 sec to 0.2 sec as shown in Fig 5.3. And the FFT
analysis output as shown in Fig 5.4.

Fig 5.3 Three phase voltage wave form without DVR



Fig 5.4 FFT analysis without DVR
Case3: In adding double load in the transmission
network that condition voltage sag is present without
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DVR. Transition time for the fault is considered from
0.1 sec to 0.2 sec as shown in Fig 5.5.And the FFT
analysis output as shown in Fig 5.6.

Fig 5.5 Three phase voltage waveform with DVR

Fig 5.6 FFT analysis with DVR
6. THD COMPARISON

By increasing the no of cycles but harmonics will get
reduced. Instead of using more number of cycles only
three cycles are used here as following Table 5.1

TABLE 2. THD COMPARISION UNDER
DIFFERENT CYCLE

7. CONCLUSION

In this paper presented the power quality problems
such as voltage sag mitigated by using DVR. DVR is
proposed to eliminate voltage sag Problems. DVR
effectively improves the power quality in
transmission network. It has lower cost, smaller size,
and fast dynamic response to the disturbance. The
objective of this work is to study the performance of
DVR and improve the power quality in transmission
network. THD comparisons of different cycles are
also carried out during normal condition and voltage
condition. So it can be concluded that DVR
effectively improve the power quality in transmission
network.

REFERENCES

S.NO NO OF
CYCLES
THD WITH
OUT DVR
THD WITH
DVR
1. 3 3.12% 0.92%
2. 4 2.75% 0.82%
3 5 2.49% 0.75%
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[1] R.Mohan Mathur, Rajiv K.Varma, "Thyristor-
Based FACTS controllers For electrical Transmission
system. New Delhi Widely student EditionIEEE press
on P ower Engineering (2013).

[2] A.Elnady Magdy M.A.salama,fellow, unified
apporach For mitigation Voltage sag and voltage
flicker Using the D-STATCOM. vol.20,no.2, April 2005.

[3] S. V. Ravi Kumar, S. Siva Nagaraju, Simulation
of D-Statcom and DVR In Power system ARPN journal
of Engineering for Applied science vol.2, No.2, June 2007

[4] H.P.Tiwari and Sunil Kumar kuptar DVR
against voltage sag, International journal of innovation,
Management and Technology, vol.1, No.3, Aug 2010.

[5] S.Ezhilarasan, G.Balasubramani, DVR for
voltage sag Mitigation Using pi with fuzzy logic controller
Internal Journal of Engineering Research Application
(IJERA) Vol.3,issue1,January,2013.

[6] Jovica V.Milanovic, fellow, IEEE And
Yanzhang, modeling of facts Devices for voltage sag
mitigation Studies in large power systems IEEE
Transaction power delivery Vol.25, No.4, October 2010

-[7] E. E. El-Araby, N. Yorino and H. Sasaki,A
comprehensive approach FACTs devices optimal
allocation For to mitigate voltage collapse, presented
at the IEEE Power Eng. Soc. Transmission and
Distribution conf. Exhibit: Asia Pacific Yokohama,
Japan, Oct. 6-10-2002, CD-ROM.

[8] M. H. Haque, Compensation of Distribution
voltage sag by DVR And D-STATCOM, presented at
the EEE Porto Power Tech, Porto, Portugal, Sep. 10-13-
2001, CD- ROM.

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MICROCONTROLLER BASED ECONOMIC ROOM
ACCESS SYSTEM
1
Bhuvana.K,
2
Jeevitha.D,
3
Umasankari.R,
4
Sasithar.J
1, 2, 3
Dept. of EEE, Ganadipathy Tulsis Jain Engineering College, Kaniyambadi, Vellore

ABSTRACT
Security is gaining awareness and importance in
recent years. And the access control system form
a vital link in the security chain at present there
are many security system available in the
market but the paper proposed here is an
economical electronic system. The consumption
of low operating power, flexible and user
friendly mechanical designs are the merits of
this project the paper presents the technology of
authorized access system by using 89c51
microcontroller and it has an added advantage
of having more than one passwords for entering
into the building.
KEYWORDS- DC Motor, Keypad, LCD
Display, 89c51 Microcontroller, Relay,
Security system
1. INTRODUCTION
Security includes several areas such as personal
security, organizational security and among others.
Security access control is an important aspect of
any system.it is act of ensuring that an
authenticated user accesses only what they are
authorized to and no more. Nearly all application
that deal with financial, privacy, or defence include
some form of access control .Access control is
concerned with determining the allowed activities
of legitimate uses mediating every attempt by a
user to access a resource in the system [1-6].
Nowadays, locks and key are not enough to keep an
environment secure against unwanted or
uncontrolled visitors. To have access mechanical
security system are widely used such system purely
mechanical can be easily defrauded. This paper
presents an access control system that uses keypad
technology.
These functionalities of the design are being able
to:
Give the facility multiple access system an
administrator and 5 users. (user s number can
be extended depending on the size of the used
EEPROM)
The user is able to access only the system
Visualized all functionalities provided using
LCD
2. CIRCUIT DIAGRAM
The system uses a compact circuitry built around
microcontroller ATmel89C51 is low power C-
MOS 8 bit microcontroller it provides following
feature: compatible with MCS-51 product 4k byte
of in system reprogrammable flash memory 32
programmable input output lines working register,
two 16bit timer and counter with compare modes
and internal and external interrupts.
The 89C51 reset pin receive a resister to
ground and an electrolytic capacitors connected to
VCC .at the power up the capacitor discharge ,so
current flows from ground to VCC via the resister
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and the capacitor, until it charge the capacitor [7-8].
The CMOS version doesnt need the resistor. If you
want to install reset button, just install the switch
in parallel to the capacitor, so when pressing the
key it will apply VCC to the reset pin also
discharging the capacitor. When reading the code
memory in case of EPROM the 89C51 breaks the
16bit address in twobytes of 8bit each higher order
bits are posted at pore P2 bits while lower order
8bits rae posted at port P0 bits.the 8051 then pulses
up the pin ALE (30)to signal the external circuit
that the address us available at the output of P0 and
P2.
The 8051 pulses down PSEN pin 29 to get the
program byte stored at the EPROM. this PSEN low
level pulse goes directly in to the/ CE. EPROM pin
20 selects the EPROM chip. The output enable(OE
pin22) allows the EPROM to output byte addressed
at pin 11-19. The 8051 reads external code memory
whenever the EA (pin 31)is connected to ground,
even if the 8051 memory has internal
ROM/EPROM. To execute the code stored into the
internal ROM/EPROM the EA pin must be
connected to +5Vdc(high level)
EEPROM: the memory is an electrically erasable
programmable read only memory fabricated with
high endurance single polysilicon CMOS
technology which guarantees an endurance
typically well above one million erase/write cycles
with data .the single supply voltage 4.5v to 5.5v .
The variable resistor connected at LCD pin 3 and
ground, controls LCD display contrast. LCD with
extended temperature range can need a negative
voltage at the VD pin3. When you apply a resistor
or variable resistor to VD a small current flows
through and a voltage develops over a resistor,
normally this voltages small during 0 and 1 volt.
The crystal connected at 89c51 pins 18 &19 need
the capacitor (33pf) connected to ground. Several
89c51 works well without capacitors but some of
them have intermittent no START or STOP
oscillation problem to avoid problems just install a
capacitors.
The 230v,50Hz AC mains step down by
transformer to deliver secondary output of 12v
,500MA.the transformer output is rectified by a full
wave bridge rectifier comprising diodeD1 through
D4 filtered by capacitor and regulated by IC 7805
used to maintain constant output voltage. LED
glows when the power is ON and the resistor act as
current limiter. A numeric keypad for password
entry is connected to the microcontroller. The
keypad is also used for password change and
application of master password when required [9-
11]. Due to the high speed of microcontroller, the
states of different keys is checked in less than
100ms and a key are pressed manually by the users,
this delay of 100 ms is not noticeable. The net
result is that you save I/O pins of the
microcontroller.
Relay is an electrical switch that uses an
electromagnet to move the switch from the OFF
and ON position instead of person moving the
switch. Relay come in different configuration
SPST, SPDT, DPST, DPDT here we are using
SPDT switch. Single pole double through has three
contact common (com) normally open (NO)
normally close (NC).the normally closed contact
will be connected to a common contact when no
power is applied to the coil. The normally open
contact will be open(not connect).when no power is
applied to the coil.
When a persons wants to enters the room, he
enters the password if the password matches
successfully the relay will operate gate is unlocked,
if the password is wrong means the relay will not
operate.
OUTPUT RESULTS:
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During execution of the proposed circuit at first it
displays welcome and in further asks the user to
enter the password as shown in fig3.



Fig3.Password Entry screen
Once the user entered the password if matched it
allows the user to enter into the room if not LCD
displays it as Invalid password and it is tested with
the compiler. Those results have been shown in
Fig4. & Fig 5.



Fig4.Entering The Password


Fig 5. Door opening Authenticated

CONCLUSION
This paper has successfully presented a
functional, low cost and low complexity
microcontroller based room access control system.
A real-life equivalent of the prototype can be
developed with minimal development costs and
with relatively low operational costs for
environment where high degrees of security are
required like banks, military research areas, and big
private investment companies. It has the special
feature of keeping more than one entry passwords.
So for more than one reliable authorities can access
the system with their personalized passwords.
REFERENCES
[1]. E. Yavuz, B. Hasan, I. Serkan and K. Duygu. Safe
and Secure PIC Based Remote Control Application
for Intelligent Home. International Journal of
Computer Science and Network Security, Vol. 7,
No. 5, May 20.
[2]. http://research.microsoft.com/enus/
projects/homeos/
[3]. David Ritter, Bernhard Isler, Hans-Joachim Mundt
and Stephen Treado, Access Control In BACnet,
American Society of Heating, Refrigerating and
Air-Conditioning Engineers(ASHRAE), Journal
Vol. 48, Nov. 2006.
[4] Popa, M.; Popa, A.S.; Marcu, M.; A distributed
smart card based access control system, 8
th

International Symposium on Intelligent Systems
and Informatics (SISY), 2010, pp: 341 346.
[5] LCD MODULE 4x20 - 3.73mm, 21 January 2012,
[online]. Available: http://www.lcdmodule.
de/eng/pdf/doma/dip204-4e.pdf
[6] Inderpreet Kaur, Microcontroller Based Home
Automation System With Security, International
Journal of Advanced Computer Science and
Applications (IJACSA), Vol. 1, No. 6, December
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Methods Enriching Power and Energy Development (MEPED) 2014 210 | P a g e



2010, pp: 60-65.
[7] Shiwani Saini,C.R.Suri, Design and Development
of Microcontroller Based Auto-Flow Assembly for
Biosensor Application, International Journal of
Computer Applications (0975 8887) Volume 6
No.1, September 2010.
[8] S. A. Hari Prasadi, B. S. Kariyappa, R. Nagaraj, S.
K.Thakur, Micro Controller Based Ac Power
Controller, Wireless Sensor Network, 2009, 2, 61-
121 by Scientific Research, pp:76-81.
[9] Magnetic locks, 24 March 2012, [online] Available:
http://www.doorentryonline.co.uk/acatalog/Magnet
ic_locks.html
[10] White papers: Magnetic locks, 20 March, 2012,
[online]
Available:http://www.sdcsecurity.com/docs/eblasts
/whitepapers_emlo ks.pdf
[11] Magnetic Locks Holding Force Security &
Application,
[online],Available:http://sdcsecurity.wordpress.co
m/2009/04/05/magnetic-locks-holding-
forcesecurity- application/
[12] Bart Huyskens, An Introduction To
Microcontroller Programming V1.0.


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Reducing Power in Reconfigurable Processors
Using Dual V
DD

1
S.A.Raja Ram,
2
Mr.D.Jerish Solomon,

1
PG Student, Nehru Institute of Technology, Coimbatore.
2
Assis.Prof.of ECE Department, Nehru Institute of Technology, Coimbatore.


ABSTRACT
Power optimization is very important for
FPGAs in nanometer technologies. The dual V
DD

technique has already been implemented in
reconfigurable processors to improve energy
efficiency. In dual V
DD
technique configurable
power supply is required to obtain a satisfactory
performance and power tradeoff. In this paper,
a flexible or variable dual V
DD
method is used to
reduce the power consumption by varying the
level of lower V
DDL
according to the applications
on a processor. This method finds out the
optimum V
DDL
based on the utilization times of
all arithmetic and logic unit operations. In this
method we use storage elements as latches
instead of registers. This will again reduce some
amount of power. Compared to single V
DD

FPGAs, configurable dual V
DD
FPGAs will
achieve more power reduction.

Index Terms Low power, power gating,
programmable dual V
DD
, reconfigurable
processor (RP), variable dual V
DD
.
I. INTRODUCTION
A Reconfigurable Processor is a microprocessor
with erasable hardware that can rewire itself
dynamically. This allows the chip to adapt
successfully to the programming tasks demanded
by the particular software they are interfacing with
at any given time. Power consumption is an
important factor in embedded system design. Now
a days power consumption becomes more
important for integrated circuit (IC) design. Since
the threshold voltage is restricted by leakage, the
power needed to switch each transistor has not
decreased. FPGAs have a much lower power
efficiency than ASICs since they use more number
of transistors.
Reconfigurable processors are more energy
efficient when compared to general purpose
processors. However its energy efficiency is still lower
than the application -specified IC implementing the
same function [2] since some runtime redundant
circuits are designed to make it flexible. The dual V
DD

technique was already been implemented to increase
the energy efficiency of RP. This technique examine
the slack time between different operations to reduce
power consumption by executing the faster operations
on lower voltage [3], [4]. The supply voltage levels are
fixed, heedless of software. Though, the optimum
level of V
DDL
varies with different applications.








Fig. 1. Architecture of RPU
This paper proposes a power optimization
method called flexible dual V
DD
for the
conventional dual V
DD
RP [3], [4].This method
adapts its V
DDL
for the current application based on
the ALU operations used by it. If the faster
operations are used more oftenly, the optimum
V
DDL
could be lowered. In this varying dual V
DD

method, we use latches as storage elements instead
of the registers which again lead to the power
reduction. In this scheme we apply V
DDH
to logic
on critical paths and V
DDL
to logic on non-critical
paths. A higher supply voltage leads to a higher
performance but larger power.
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The rest of this paper is ordered as
follows. Section 2 describes the architecture of the
RPU. Section 3 examines the power and delay of
all its components. Section 4 analyzes the proposed
method in detail. The result of the experiment is
discussed in section 5. Section 6 concludes this
method.
II. ARCHITECTURAL DESCRIPTION
The study of this method is based on the RPU
as shown in fig. 1. Alike to many previous RPs [5],
[6], it contains three main components: an 8 x 8
coarse grained RCA, a 9 k bit data FIFO whose
data width is 256 bits, and a 160 kb configuration
memories whose data width is 1024 bits. The
configuration of the RC is depicted in the right part
of fig.1, containing three-input two-output 16-bit
ALU, the input and output registers and some local
registers.
A. Coarse Grained Reconfigurable Cell:
While the initial systems for reconfigurable
computation featured fine grained FPGAs, it was
soon revealed, that FPGAs stand different
disadvantages for computational tasks. Initially,
due to the bit-level operations, operators for wide
data paths have to be collected of several (bit-level)
processing units. This includes classically a large
routing overhead for the interconnect between
these units and leads to a low silicon area
efficiency of FPGA computing solutions. In
addition, the switched routing wires use more
power than hardwired connections. A second
shortcoming of the fine granularity is the high
volume of configuration data wanted for the large
number of both processing units and routing
switches. This shows the need for a high
configuration memory, with according power
dissipation. The long configuration time, that is
implied by this problem, makes execution models
depending on a steady change of the configuration
impossible.
As a third disadvantage, application
development for FPGAs is very similar to VLSI
design owing to the programmability at logic level.
The mapping of applications from common high-
level languages is difficult compared to the
compilation onto a standard microprocessor, as the
granularity of the target FPGA does not match that
of the operations in the source code. The standard
way of application specification is still a hardware
description language, which requires a hardware
expert. In the following design process, the large
number of processing units leads to a complex
synthesis, which uses up much computation time.
Coarse grained reconfigurable architectures try to
overcome the disadvantages of FPGA-based
computing solutions by providing multiple-bit wide
data paths and complex operators instead of bit-
level configurability. In contrast to FPGAs, the
wide data path allows the efficient implementation
of complex operators in silicon. Thus, the routing
overhead generated by having to compose complex
operators from bit-level processing units is
avoided. Regarding the interconnects between
processing elements, coarse grain architectures also
differ in several ways to FPGAs. The connections
are multiple bits wide, which implies a higher area
usage for a single line. On the other hand, the
number of processing elements is typically several
orders of magnitude lower than in an FPGA. Thus,
much fewer lines are needed, resulting in a globally
lower area usage for routing. The lower number
and higher granularity of communication lines
allows also for communication resources, which
would be quite inefficient for fine grained
architectures. Examples for such resources are
time-multiplexed buses or global buses, which
connect every processing element. In the past
years, several approaches for coarse grained
reconfigurable architectures have been published.
In this chapter, several example architectures will
be presented to give an overview over the
developments in the area of coarse grain
reconfigurable computing.
III. EXPERIMENTAL ANALYSIS
This division describes the features of the RPU
including power and delay distributions. The RPU
is modeled in VHDL. One aim is to find out the
most power efficient circuit parts so that slack time
could be traded for more power reduction. The
application benchmarks include H.264 decoder,
audio video coding standard (AVS) decoder,
MPEG2 decoder, and GPS receiver.

Table I
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Methods Enriching Power and Energy Development


Normalized delay of ALU with different configurations


Table II
Delays of the different paths in RCA
Table III
Utilization Times of Operation Codes

Table IV
Power analysis of RPU giving out H.264 decoder
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Methods Enriching Power and Energy Development (MEPED) 2014
configurations

the different paths in RCA

Utilization Times of Operation Codes

H.264 decoder
Table V
Power of ALU and Interconnect of RCA

A. Static Timing Analysis:
Initially a static timing analysis of the ALU
performed. The normalized ALU delays with
respect to different configurations are shown in
table I. The average slack time is about 50% of the
critical operation delay.
Table II shows the static timing analysis of the
RCA. The critical path and non
through different ALU components are listed. The
path delay changes from 0.67 to 7.39 ns and the
ALU delay increases from 0.42 to 5.70 ns The
leading conclusion is that the ALU delay occupies
about 75% of the critical path delay and 64% o
minimal path delay.
B. Power Analysis:
The power of the RPU depends on its
configuration as revealed in table IV. All
configurations given in the table IV are the sub
algorithms of H.264 decoder. The data on the static
row are calculated when the RPU is not working
but its clock is still on. Table V gives the thorough
power consumption of the RCA module,
ALU power and interconnect power are listed
individually. The RCA module contributes about
70% of the RPUs working power and the
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Power of ALU and Interconnect of RCA


Initially a static timing analysis of the ALU is
The normalized ALU delays with
respect to different configurations are shown in
. The average slack time is about 50% of the
Table II shows the static timing analysis of the
non-critical path
through different ALU components are listed. The
path delay changes from 0.67 to 7.39 ns and the
ALU delay increases from 0.42 to 5.70 ns The
leading conclusion is that the ALU delay occupies
about 75% of the critical path delay and 64% of the
The power of the RPU depends on its
configuration as revealed in table IV. All the
configurations given in the table IV are the sub
algorithms of H.264 decoder. The data on the static
U is not working
but its clock is still on. Table V gives the thorough
power consumption of the RCA module, where the
ALU power and interconnect power are listed
The RCA module contributes about
70% of the RPUs working power and the
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interconnect part contributes nearly 90% of the
RCAs power. From the above details, interconnect
is the critical part concerning power.
C. Basic Interconnect Structure:
The basic interconnect structure is determined
by the global of the processing elements. This
inturn is often motivated by the targeted
applications for the architecture or by
implementation considerations. Obviously, the type
of the communication architecture has a direct
impact on the complexity of architectures
application mapping. The predominating structures
of the architectures presented here is a two-
dimensional network. In extra architectures, the
processing elements are arranged in one or more
linear arrays. The third interconnect structure found
is a crossbar switch being used to connect
processing elements. This allows basically
orbitrary connections.


IV. FLEXIBLE DUAL V
DD

The analysis of previous section leads to
various outcomes.The RPU normally has large
slack time and it differs with the software.ALU is
the most critical part concerning delay.The
interconnect is the critical part concerning power.

Fig. 2 (a): Flexible dual-V
DD
RCA
A. Reconfiguration Model:
The reconfiguration model determines when a
new reconfiguration is to be loaded in to the
architecture. For architectures containing static
reconfiguration, a configuration is loaded at the
opening of the execution and stays for the period of
the computation phase. When a new arrangement
has to be loaded, the execution must stop. The
dynamic reconfiguration model allows a new
configuration to be loaded while the application is
executing. This includes the case that the execution
relies on steady reconfiguration of the processing
elements.
B. ALU:
The Arithmetic and Logic Unit is the section
of the processor that is implicated with executing
operations of an arithmetic or logical nature. It
works in combination with the register array for
many of these, in specific, the accumulator and flag
registers. The accumulator holds the outcome of
the operations, while the flag register contains a
number of seperate bits that are used to store
information about the last operation carried out by
the ALU. More of these registers can be originate
in the register array section. In the proposed
method we use latches instead of registers.
C. Latch:
Latch is an electronic device that can be worn
to store one bit of information. The D latch is used
to confine, or latch the logic level which is there on
the data line when the clock input is high. If the
data present on the D line changes state though the
clock pulse is high, then the output follows the
input. When the clock input falls to logic 0, the
final state of the D input is fascinated and held in
the latch.
D. Latch Up:
In CMOS fabrication, latch-up is a
malfunction which can occur as a result of
improper design. Latch-up in a CMOS integrated
circuit, causes unintended currents will possibly
resulting with the destruction of the entire circuit,
thus, it must be prevented.
E. Explanation of the Phenomena:
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Methods Enriching Power and Energy Development


The cross segment of a two
CMOS integrated circuit where the nMOS is on the
left hand area and the pMOS on the right han
As it can be seen as of the figure, we can
about a parasitic pnp transistor from source of the
pMOS to the p-substrate. In addition a parasitic npn
transistor is formed from source of the nMOS, p
substrate and the n-well. These parasitic transistors
and finite resistances of n-well and p-substrate
Fig 2 (b) Latch up phenomenon
As it can be clearly seen from the
equivalent circuit, there is a positive fee
around Q1 and Q2. If a parasitic current flows
through the node X and raise V
x
, Q2 turns on an
I
C2
increases resulting V
Y
decrease. This increases
I
C1
and consequently V
x
increases much more. If
the loop gain is equal to or greater than unity, this
situation continues until an enormous current flow
through the circuit in other words, until the circuit
is latched up.It should be lesser then unity in or
to prevent latch-ups. Consequently, both of process
and design engineers should take steps for latch
prevention. Doping levels, and the other
aspects should be arranged properly in or
have low parasitic resistances and current gain of
bipolar transistors. There are specific
to prevent latch-ups in different technologies. As
its results may be fatal for the circuit, preventing
latch-up in CMOS integrated circuit
essential for a proper operation.
F. Proposed Method:
A variable or flexible V
DD
proposed to reduce power consumption. This is
based on a configurable dual V
DD
technique, which
was implemented for FPGA [7]-[9] and after
International Journal for Research and Development in Engineering (IJRDE)
ISSN: 2279-0500 Special Iss
Methods Enriching Power and Energy Development (MEPED) 2014
of a two-transistor
circuit where the nMOS is on the
the pMOS on the right hand side.
the figure, we can converse
about a parasitic pnp transistor from source of the
a parasitic npn
from source of the nMOS, p-
well. These parasitic transistors
substrate.

Fig 2 (b) Latch up phenomenon
As it can be clearly seen from the
equivalent circuit, there is a positive feedback loop
Q2. If a parasitic current flows
, Q2 turns on and
This increases
increases much more. If
the loop gain is equal to or greater than unity, this
ntinues until an enormous current flow
s, until the circuit
then unity in order
nsequently, both of process
take steps for latch-up
the other design
properly in order to
current gain of
bipolar transistors. There are specific design rules
ifferent technologies. As
its results may be fatal for the circuit, preventing
circuit design is
DD
method is
proposed to reduce power consumption. This is
technique, which
[9] and after that
applied to RP [3], [4], but an adjustable V
used in the place of the fixed V
DDL
that the application dependent optimum V
increase power reduction rate further.
Since ALU is much more power efficient
than ALU, the granularity of dual V
to be the interconnect. The power or
is tens of times larger than that of ALU, so it is
favoured to design configurable dual V
interconnect rather than that of ALU. Two
selecting transistors and two bit configurations are
needed to elect power supply from V
Level shifters are needed at the boundary
the V
DDL
signals are transmitted to the V
domain.
The extra cost of this method is an
adjustable dc to dc converter. The control circuit
and buck converter used in [10]
generate the flexible V
DDL
. The input is given by
the compiler, so the output V
DDL
can be varied by
software control.
G. Variable V
DDL
:


The key point of the projected
variable V
DDL
since the optimum V
with applications. Initially, choose
whose delays under a specified V
DDL
than the target delay. Then, determine
utilization times by a given application by the use
of table III. Finally, the overall section
functioning under this given V
DDL

optimized power consumption can be
accordingly.
V. DISCUSSIONS AND SUMMARY
A. PVT Analysis:
Process voltage temperature (PVT)
variations after fabrication impact the optim
V
DDL
. Considering the impacts on D
are similar, so the optimum V
determined by u(I, V
DDL
).The u(i, V
different process corners and temperatures was
simulated to obtain the corresponding optimum
V
DDL
For GPS application, the PVT variation leads
to a deviation of -0.08- + 0.01 V for the optimum
V
DDL
level. To overcome this problem, a detector
circuitry measuring post silicon delays could be
International Journal for Research and Development in Engineering (IJRDE)
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215 | P a g e
applied to RP [3], [4], but an adjustable V
DDL
is
DDL
. The cause is
that the application dependent optimum V
DDL
can
increase power reduction rate further.
Since ALU is much more power efficient
than ALU, the granularity of dual V
DD
is selected
to be the interconnect. The power or delay of ALU
than that of ALU, so it is
red to design configurable dual V
DD
to the
interconnect rather than that of ALU. Two
selecting transistors and two bit configurations are
needed to elect power supply from V
DDH
and V
DDL
.
Level shifters are needed at the boundary by which
signals are transmitted to the V
DDH

The extra cost of this method is an
adjustable dc to dc converter. The control circuit
and buck converter used in [10] are used to
. The input is given by
can be varied by
projected method is a
e the optimum V
DDL
changes
those operations
DDL
are not larger
delay. Then, determine their
on times by a given application by the use
section of the RCs
is obtained. The
optimized power consumption can be determined
DISCUSSIONS AND SUMMARY
Process voltage temperature (PVT)
variations after fabrication impact the optimum
on D
A
, D
I
, and D
C

are similar, so the optimum V
DDL
is mainly
).The u(i, V
DDL
) at
different process corners and temperatures was
simulated to obtain the corresponding optimum
For GPS application, the PVT variation leads
0.01 V for the optimum
. To overcome this problem, a detector
circuitry measuring post silicon delays could be
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Methods Enriching Power and Energy Development (MEPED) 2014 216 | P a g e



designed to calibrate the parameters used in our
method, such as u, and also to direct the assignment
of power supplies. However, the detail is out of the
scope of this brief and could be our future topic.
VI. CONCLUSION
This paper has presented the Variable dual
V
DD
method to reduce the power consumption of
RP. This is based on the conventional dual -V
DD

method but has a variable application-dependent
V
DDL
.The main change in this paper is that the
proposed method uses latches instead of the
register, which leads to a power reduction in the
Variable dual V
DD
method. The Reconfigurable
processor can always achieve higher power
optimized performance with this method. This can
be used for the applications of GPS, MPEG2,
H.264, and AVS. The proposed method reduces
power of RPU by about 20%. Compared with the
other techniques, more improvement is achieved in
this technique. The PVT variation causes a slight
deviation in the power,which will be be overcome
in our future work by designing a detector circuitry.

REFERENCES

[1] Jianfeng Zhu, Leibo Liu, Shouyi Yin, and Shaojun
Wei, Low-Power Reconfigurable Processor Utilizing
Variable Dual VDD,IEEE Trans. Circuits and
systems,April 2013.
[2] T. Yamamoto, K. Hironaka, Y. Hayakawa, M.
Kimura, H. Amano, and K. Usami, Dynamic VDD
switching technique and mapping optimization in
dynamically reconfigurable processor for efficient
energy reduction, in Proc. 7th Int. Symp. Reconfig.
Comput.Architect., Tools, Appl., Mar. 2011, pp. 230
241.
[3] C. Tzu-Der, T. Pei-Kuei, L. Pin-Chih, C. Lo-Mei, M.
Tsung-Chuan,C. Yi-Hau, and C. Liang-Gee, A 59.5
mW scalable/multi-view video decoder chip for Quad/3D
full HDTV and video streaming applications, in Proc.
ISSCC Dig. Tech. Papers, Feb. 2010, pp. 330331.
[4] D. Rossi, F. Campi, A. Deledda, S. Spolzino, and S.
Pucillo, A heterogeneous digital signal processor
implementation for dynamically reconfigurable
computing, in Proc. Custom Integr. Circuits Conf., Sep.
2009,pp. 641644.
[5] S. Bijansky and A. Aziz, TuneFPGA: Post-silicon
tuning of dual-Vdd FPGAs, in Proc. Des. Autom. Conf.,
Jun. 2008, pp. 796799.
[6] Y. Lin and L. He, Statistical dual-Vdd assignment
for FPGA interconnect power reduction, in Proc. Des.,
Autom. Test Eur. Conf. Exhib., Apr. 2007,pp. 16.
[7] T. Schweizer, T. Oppold, J. Oliveira Filho, S.
Eisenhardt, K. Blocher, and W. Rosenstiel, Exploiting
slack time in dynamically reconfigurable processor
architectures, in Proc. Int. Conf. Field-Programm.
Technol., Dec. 2007, pp. 381384.
[8] F. Li, Y. Lin, L. He, and J. Cong, Low power FPGA
using pre-defined dual-Vdd/dual-Vt fabrics, in Proc.
ACM Int. Symp. Field-Programm.Gate Arrays, 2004, pp.
4250.
[9] A. Gayasen, Y. Tsai, N. Vijaykrishnan, M. Kandemir,
M. J.Irwin, and T. Tuan, Reducing leakage energy in
FPGAsusing region-constrained placement: in PTOC.
ACM Intl. Symp. Field-Programmable Gate Arrays,
February 2004.
[10] J. H. Anderson, F. N. Najm, and T. Tuan, Active
leakage power optimization for FPGAs, in Proc. ACM
Intl. Symp. Field-Programmable Cote Arrays, Februray
2004.
[11] F. Li, Y. Lin, L. He, and J. Cong, FPGA power
reduction using configurable dual-Vdd, in Proc. Des.
Autom. Conf., Jul. 2004, pp. 735740.
[12] F. Li, Y. Lin, L. He, and J. Cong, Vdd
programmability to reduce FPGA interconnect power,
in Proc. Int. Conf. Comput.-Aided Des., Nov. 2004,pp.
760765.
[13] H. Singh, M. H. Lee, G. Lu, F. Kurdahi, N.
Bagherzadeh, and E. Chaves,MorphoSys: An integrated
reconfigurable system for data-parallel and computation-
intensive applications, IEEE Trans. Comput., vol. 49,
no. 5,pp. 465481, May 2000.
[14] T. Kuroda, K. Suzuki, S. Mita, T. Fujita, F. Yamane,
F. Sano, A. Chiba, Y. Watanabe, K. Matsuda, T. Maeda,
T. Sakurai, and T. Furuyama, Variable-supply voltage
scheme for low-power high-speed CMOS digital
design, IEEE J. Solid-State Circuits, vol. 33, no. 3, pp.
454462,Mar. 1998.
[15] E. Kusse and J. Rabaey, "Low-energy embedded
FPGA structures," in ISLPED, pp. 155-160, August
1998.
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Methods Enriching Power and Energy Development (MEPED) 2014 217 | P a g e

Microcontroller Based Wheel Run Out Measurement System
for Commercial Vehicles
N.Gayathri
1
, V.Priyanka
2
, Swasini sudarsan
3
, Mr.M.Subramanian
4
1,2,3
Electronics and Instrumentation Engineering, Sri Sairam Engineering College, Chennai, Tamil Nadu
4
Assistant Professor, Dept. of EIE, Sri Sairam Engineering College, Chennai

ABSTRACT
Quality check is a big Challenge, due to high
volume manufacturing. Out of Several Quality
checks, one of the Quality Measurements is Wheel
Run out Measurement. Existing method of
measurement is using displacement strain gauge.
Because of wear and tear of strain gauge, operation
and maintenance expenses per month is high. Our
proposed solution is Micro controller based wheel
run out measurement system. As part of this, a
rectilinear position sensor is fixed at a point on the
wheel around the circumference. The sensed analog
output is proportional to the displacement value.
Microcontroller senses the Displacement value
through ADC and compares with allowed Wheel
Runout value in mm. Microcontroller based system
will pass the wheel which is having allowed runout
value otherwise wheel will be rejected. This system
will ensure proper checking of wheels with required
quality aspects.

Keywords: Hitech-C-compiler, MP lab IDE, PIC
16F886, PICkit 3
I. INTRODUCTION
A. Objective:
Quality check is a big Challenge. Out of
Several Quality checks, one of the Quality Measurement
is Wheel Run out Measurement.
The main objective of wheel run out test is to
check the deformities like
a) welding cracks
b) welding joint unevenness
c) welding abnormalities
B. Current scenario:
Run out tests were performed based on strain
gauge principles of detecting cracks, breaks and
abnormalities. Existing method of measurement is using
displacement strain gauge. Because of wear and tear of
strain gauge, operation and maintenance expenses per
month is high. In order to overcome it, an alternative
solution naming MICROCONTROLLER BASED
WHEEL RUN OUT MEASUREMENT SYSTEM FOR
COMMERCIAL VEHICLES has been introduced. This
system will ensure proper checking of wheels with
required quality aspects [1-3]. The scope of our project
is designing hardware and programming PIC
Microcontroller for Wheel Runout application.
II. DESCRIPTION
A. Existing system
Existing method of measurement is using
displacement strain gauge. Because of wear and tear of
strain gauge, operation and maintenance expenses per
month is high.

Figure.1. Wheel run out test using strain gauge

Optimal replacement of strain gauge due to
wear and tear induced larger cost to the industry. An
intense study was done on the type of sensor to be used
for the process [3-4]. It was decided experimentally to
use rectilinear positional sensor instead of strain gauges.

B. Proposed system
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Methods Enriching Power and Energy Development (MEPED) 2014 218 | P a g e

Figure.2. Block diagram for proposed system

III. HARDWARE COMPONENTS

The major hardware components in this system are
a) Rectilinear positional sensor
b) PIC microcontroller
c) LCD display
d) Voltage regulator
e) MAX 232

A. Rectilinear positional sensor (PY-2-F-010-
S01M)
a) 10 to 100 mm stroke
b) Double support of the control rod and return
spring
c) Tip with M2.5 thread and stainless steel ball

Table 1: Technical Data of sensor

d) Independent linearity up to 0.1% and infinite
resolution
e) Working temperature: -30...+100C
f) Displacement speed up to 10 m/s and force
4N
g) Maximum cursor current:- 10mA

h) Case material:- Ionized Aluminium Nylon 66 G
25
i) Control rod material:- Stainless steel material
AISI 303
j) Electrical connections:
PY2 F 3 wire 1m screened cable and PY2 C 5-
pole connector DIN43322 Figure.3. Rectilinear
positional sensor
k) Life duration: > 100x10
6
operations (within
C.E.U.)
l) Suitable for use in explosive environments with
presence of gas (groups IIA, IIB, IIC) and
combustible powders.

B. PIC Microcontroller(PIC 16F886)
PIC is a family of modified Harvard
architecture microcontrollers made by Microchip
Technology, derived from the PIC1650 originally
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Methods Enriching Power and Energy Development (MEPED) 2014 219 | P a g e
developed by General Instrument's Microelectronics
Division. The name PIC initially referred to
"Peripheral Interface Controller'". PIC
microcontrollers are electronic circuits that can be
programmed to carry out a vast range of tasks [5-6].
They are found in most electronic devices such as
alarm systems, computer controllers etc. PICs are
popular with both industrial developers and hobbyists
alike due to their low cost, wide availability, large user
base, extensive collection of application notes,
availability of low cost or free development tools, and
serial programming capability.


Figure.4. PIC 16F886-PIN Description

Port A and TRISA Register: Port A is an 8-bit wide,
bidirectional port. Bits of the TRISA control the PORTA
pins. All Port A pins act as digital inputs/outputs.
Port B and TRISB Register: Port B is an 8-bit wide,
bidirectional port. Bits of the TRISB register determine
the function of its pins.
Port C and TRISC Register: Port C is an 8-bit wide,
bidirectional port. Bits of the TRISC Register determine
the function of its pins. Similar to other ports, a logic one
(1) in the TRISC Register configures the appropriate
port pin as an input.



C. LCD Display
A liquid-crystal display (LCD) is a flat panel
display, electronic visual display, or video display that
uses the light modulating properties of liquid crystals.
Liquid crystals do not emit light directly. LCDs are used
in a wide range of applications including computer
monitors, televisions, instrument panels, aircraft cockpit
displays, and signage. They are common in consumer
devices such as video players, gaming
devices, clocks, watches, calculators, and telephones,
and have replaced cathode ray tube (CRT) displays in
most applications. They are available in a wider range of
screen sizes than CRT and plasma displays, and since
they do not use phosphors, they do not suffer image
burn-in. LCDs are, however, susceptible to image
persistence.
Table 2: LCD Pin Description

D. MAX 232
The MAX232 is an IC, first created in 1987
by Maxim Integrated Products, that converts signals
from an RS-232 serial port to signals suitable for use
in TTL compatible digital logic circuits.





Figure.7. MAX 232-PIN Diagram
The intermediate link is provided through
MAX232. It is a dual driver/receiver that includes a
capacitive voltage generator to supply RS232 voltage
levels from a single 5V supply. Each receiver converts
RS232 inputs to 5V TTL/CMOS levels. These receivers
(R1& R2) can accept 30V inputs. The drivers (T1&
T2), also called transmitters, convert the TTL/CMOS
input level into RS232 level.
The transmitters take input from controllers
serial transmission pin and send the output to RS232s
receiver. The receivers, on the other hand, take input
from transmission pin of RS232 serial port and give
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Methods Enriching Power and Energy Development
serial output to microcontrollers receiver pin. MAX232
needs four external capacitors whose value ranges from
1F to 22F.

E. Voltage Regulator
The 78xx (sometimes L78xx, LM78xx
x...) is a family of self-contained fixed linear voltage
regulator integrated circuits. The 78xx family is
commonly used in electronic circuits requiring a
regulated power supply due to their ease-of-
cost. For ICs within the family, the xx is replaced with
two digits, indicating the output voltage (for example,
the 7805 has a 5 volt output, while the 7812 produces
12 volts). The 78xx lines are positive voltage regulators;
they produce a voltage that is positive relative to a
common ground.






Figure.8. LM7805
Features: LM7805
a) Output Current up to 1A
A. CONNECTIONS OF PIC
Port A
RA0 to RA5, RA6 and RA7 - To LCD display with pull
up resistors and also connected to supply with pull down
resistors.
Port B
RB6 and RB7 - To program pin
RB3- To push button
RB0 - To 3 pin connector
Port C
RC0, RC1 and RC2 - To LCD display
RC4 and RC5 - To LED with pull up resistors
RC6 and RC7 - To MAX232 (for serial
communications)

V. WORKING
A rectilinear positional sensor is fixed at a point
on the wheel around the circumference. This senses the
deformities in the wheel and the sensed analog output is
proportional to the displacement value. Microcontroller
receives the Displacement value through ADC and
compares with allowed Wheel Runout value in mm. The
respective values will be displayed in LCD. The allowed
run out value is set at first using push button.
International Journal for Research and Development in Engineering (IJRDE)
ISSN: 2279-0500 Special Issue:
Methods Enriching Power and Energy Development (MEPED) 2014
serial output to microcontrollers receiver pin. MAX232
e value ranges from
LM78xx, MC78x
linear voltage
. The 78xx family is
commonly used in electronic circuits requiring a
-use and low
is replaced with
(for example,
volt output, while the 7812 produces
volts). The 78xx lines are positive voltage regulators;
they produce a voltage that is positive relative to a
b) Output Voltages of 5
c) Thermal Overload Protection
d) Short Circuit Protection
e) Output Transistor Safe Operating Area
Protection

IV. CIRCUIT DIAGRAM AND
CONNECTION
Figure.9. Circuit diagram


To LCD display with pull
up resistors and also connected to supply with pull down
To LED with pull up resistors
To MAX232 (for serial
Other pins
MCLR- To program pin and supply
Vss- To ground
VDD- To program pin
B. OTHER PINS OF LCD
Vss - To ground
VDD - connected to supply
VEE - connected to a variable resistor for lcd contrast
adjustment
Negative (-): BACKLIGHT - connected to ground
Positive (+): BACKLIGHT - connected to supply via a
pull up resistor
A power supply is connected to the voltage re
A rectilinear positional sensor is fixed at a point
on the wheel around the circumference. This senses the
deformities in the wheel and the sensed analog output is
proportional to the displacement value. Microcontroller
ugh ADC and
compares with allowed Wheel Runout value in mm. The
respective values will be displayed in LCD. The allowed
run out value is set at first using push button.
Microcontroller based system will pass the
wheel which is having allowed runout value
the wheel will be rejected. This is indicated using the
LEDs where if green LED glows, the wheel will be
passed and if red LED glows, the wheel will be rejected.
Besides, Wheel runout value can be transferred through
RS232 to the PC for quality audit.

VI. SOFTWARE
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220 | P a g e
Thermal Overload Protection
Output Transistor Safe Operating Area
DIAGRAM AND

diagram
To program pin and supply
connected to a variable resistor for lcd contrast
connected to ground
connected to supply via a
A power supply is connected to the voltage regulator.
Microcontroller based system will pass the
wheel which is having allowed runout value otherwise
the wheel will be rejected. This is indicated using the
LEDs where if green LED glows, the wheel will be
passed and if red LED glows, the wheel will be rejected.
Besides, Wheel runout value can be transferred through

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The software requirement for this system is
EMBEDDED C CODING for programming the PIC
microcontroller. Programming code can be performed
using MP lab IDE (Integrated Development
Environment) with Hitech-C-compiler. PICkit 3 is for
programming on PIC microcontroller.
PICkit is a family of programmers for PIC
microcontrollers made by Microchip Technology. They
are used to program and debug microcontrollers, as well
as program EEPROM. Some models also feature logic
analyzer and serial communications (UART) tool.
Validation will be done in Lab Level for
different wheel models. Based on programming, the
microcontroller based system will pass the wheel which
is having allowed runout value otherwise wheel will be
rejected.

Figure.10. PICkit 3

VII. CONCLUSION

Based on programming, the microcontroller
based system will pass the wheel which is having
allowed runout value otherwise wheel will be rejected.
This system will ensure proper checking of wheels with
required quality aspects. The future extension of this
idea may be done on a larger and more efficient scale by
using three rectilinear positional sensors at three fixed
points that are placed at 120
0
angle on the wheel to be
tested. The entire run out measurement could be
obtained by a single rotation of the wheel about its axis.
This increases the efficiency of the operation largely.

REFERENCES

[1] Jinyi Lee, Myoungki Choi, Jongwoo Jun, Seokjin Kwon,
Joo-Hyung Kim; Jungmin Kim, Minhhuy Le;
Nondestructive Testing of Train Wheels Using Vertical
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Array; Instrumentation and Measurement, IEEE
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between analytical approaches and field tests, Iran
University of Science and Technology, School of
Railway Engineering, Rolling Stock Dept, Tehran
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USA,JRC2006-94054
[3] Rainer Hohmann, Dieter Lomparski, Hans-Joachim
Krause, Marc v. Kreutzbruck, and Willi Becker;
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Technique using a HTS SQUID Magnetometer, IEEE
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rail/wheel contact points of running railway
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Constructeurs/Werther/Attrezzature/Allineamento/W
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056)_MAN_GB.PDF





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Methods Enriching Power and Energy Development (MEPED) 2014 222 | P a g e

Geographic Image Retrieval Using Local Invariant
Features with Euclidean Distance
R.Nandhini
1
, T.Joel
2
1,2
Electronics and Communication, R.M.K.Engineering College, Chennai, India


ABSTRACT:-
An image retrieval system is a computer
system for browsing, searching and retrieving
images from a large database of digital images.
A robust natural and geographic image retrieval
using a supervised classifier which concentrates
on extracted features is proposed. Gray level co-
occurrence matrix (GLCM), Scale invariant
feature technique(SIFT) and moment invariant
features are implemented to extract the features
from natural images. Then these features are
passed through SVM classifier. SVM classifies
whether the input is Geographic or natural
image. Based on the SVM result, the retrieval
process is done with Euclidean distance. The
performance comparison is done with standard
features such as colour and texture.

Keywords- GLCM, moment invariant, SIFT,
SVM.

I. INTRODUCTION
Content-based image retrieval is a technique,
which uses visual contents to search images from
large scale image databases according to users
interests and it has been an active and fast
advancing research area since the 1990s[1-7] . A
necessity for developing a successful CBIR system
is the extraction of discriminant features to describe
the images in the database. As such, the
development of feature extraction algorithms has
dominated the literature in this field, where the
ultimate goal is to retrieve visually similar images.
In this paper, retrieval is done for natural
and geographic images using SIFT, GLCM and
moment invariant techniques. Advantages of using
these feature extraction algorithms are better error
tolerance with fewer matches, reliability, efficient
and best image matching task.
II. PROPOSED SYSTEM
A robust natural scene and Geographic
image retrieval using a supervised classifier which
concentrates on extracted features is proposed.
Gray level co-occurrence matrix and invariant
Features are implemented to extract the features
from images. First, the input image undergoes pre-
processing step, in which the noise occurred in it
are removed with the help of median filter. In
second step, features (SIFT, GLCM, invariant) are
extracted from the images. Then these features are
passed through SVM classifier which classifies
whether the input is Geographic image or Natural
image. Based on the SVM result, retrieval process
is done with Euclidean distance. The performance
comparison is done with standard features such as
colour and texture.
Scale-invariant feature transform (SIFT): It is an
algorithm in computer vision to detect and describe
local features in images. For any object in an
image, interesting points on the object can be
extracted to provide a "feature description" of the
object. This description, extracted from a training
image, can then be used to identify the object when
attempting to locate the object in a test image
containing many other objects.
To perform reliable recognition, it is
important that the features extracted from the
training image be detectable even under changes in
image scale, noise and illumination. Such points
usually lie on high-contrast regions of the image,
such as object edges. SIFT descriptors are extracted
from an image in two steps [8-10]. First, a
detection step locates points that are identifiable
from different views. This process ideally locates
the same regions in an object or scene regardless of
viewpoint or illumination. Second, these locations
are described by a descriptor that is distinctive yet
invariant to viewpoint and illumination.
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Gray Level Co-occurrence Matrix
(GLCM):
A co-occurrence matrix or co-occurrence
distribution is a matrix or distribution that is
defined over an image to be the distribution of co-
occurring values at a given offset.
Moment Invariant:
Moments are projections of the image
function into a polynomial basis. Invariants are
functional defined on the image space such that,
I(f) = I(D(f)) for all admissible D and I(f
1
), I(f
2
)
different enough for different f
1
, f
2
.The features
drawn by invariants moment technique are used to
evaluate the distributed parameter of a character
image [9-12]. They are measures of the pixel
distribution around the centre of gravity of the
character and allow capturing the global character
shape information.
III. PROBLEM ANALYSIS
Though many feature extraction
techniques are proposed, they have disadvantages
like complexity in probabilistic network, time
consuming in bit mapping and segmentation and
hence this paper is proposed to overcome it.
IV. SYSTEM ARCHITECTURE
In pre-processing method, median filter is
used to remove noise from the input test images.
Then, the pre-processed image undergoes feature
extraction process. The texture features of the
dataset are already calculated. Then, the features of
the input image is also calculated which is then
compared and retrieved using Euclidean distance.
Feature Extraction
SIFT-Detector: The SIFT detection step is
designed to find image regions that are salient not
only spatially but also across different scales.
Candidate locations are initially selected from local
extrema in difference of Gaussian (DoG) filtered
images in scale space. The DoG images are derived
by subtracting two Gaussian blurred images with
different .
D(x, y, ) = L(x, y, k) L(x, y, )


Fig 1 Block diagram for geographic image retrieval
Where L(x, y, ) is the image convolved with a
Gaussian kernel with standard deviation , and k
represents the different sampling intervals in scale
space.
Descriptor: A SIFT descriptor is extracted from
the image patch centered at each interest point. The
size of this patch is determined by the scale of the
corresponding extremum in the DoG scale space.
This makes the descriptor scale invariant.
GLCM-The first step in GLCM is to count all pairs
of pixels in which the first pixel has a value i, and
its matching pair displaced from the first pixel
by d which has a value of j. Then, this count is
entered in the i
th
row and j
th
column of the matrix
P
d
[i,j]. Note that P
d
[i,j] is not symmetric, since the
number of pairs of pixels having gray levels [i,j]
does not necessarily equal the number of pixel pairs
having gray levels [j,i].
Moment invariant: The moment invariants are
evaluated using central moments of the image
function f(x,y) ) up to third order. The image
matrix f(x,y) is processed to obtain the character
with white color on black background. The
expressions given by Equations are used to
evaluate the central invariants moment, which are
used as features. Further, mean and standard
deviation are determined for each feature using
samples [12-14]. To increase the success rate, the
new features need to be extracted based on
perturbation and divisions of the images.
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Retrieval: The Euclidean distance or Euclidean
metric is the "ordinary" distance between two
points that one would measure with a ruler, and is
given by the Pythagorean formula. Relevant
Images are retrieved using Euclidean distance.
Texture Features
The below mentioned texture features of
the dataset are calculated and compared against
input image features.

1) Local Homogeneity, Inverse Difference
Moment (IDM) :

IDM= P(i,j)
IDM is also influenced by the homogeneity of
the image. Because of the weighting factor
IDM will get small contributions from
inhomogeneous areas. The result is a low IDM
value for inhomogeneous images, and a
relatively higher value for homogeneous
images.

2) Sum of Squares, Variance

This feature puts relatively high
weights on the elements that differ from the
average values of p[i,j]
3) Cluster Prominence
PROM=
P(i,j)

4) Dissimilarity
D= |i-j|

5) Autocorrelation
Other statistical approaches include an
autocorrelation function, which has been used for
analyzing the regularity and coarseness of texture
by Kaizer. This function evaluates the linear
spatial relationships between primitives. The set
of autocorrelation coefficients shown below are
used as texture features:
C(p,q)=

Where p, q is the positional difference in
the i, j direction, and M, N are image
dimensions.
V. RESULTS AND DISCUSSION

Fig 1(a) and Fig (b)
Fig 1(a) and (b) shows the location of interest
points in the input image using SIFT and the
retrieved image from the dataset.


Fig 2

Fig 2 shows the priority of the input image retrieval
among given dataset.
V. CONCLUSION AND FUTURE
WORK
In this project, a robust natural, Geographic
image retrieval using a supervised classifier which
concentrates on extracted features is developed.
Gray level co-occurrence matrix, moment
invariant features, scale invariant feature
technique are implemented to extract the features
from images. Thus, we found that local invariant
features are more effective than standard features
such as colour and texture for image retrieval of
LULC classes on comparison.
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In future, we can apply this technique
for detection and classification. Also, we can
implement some other SIFT techniques for
retrieval process. For further improvement, we can
extend this technique for detecting buildings in
aerial and satellite images.

REFERENCES
[1] Aisen A.M , L. S. Broderick Brodley C.E, C.
Kak, A. Kosak(2010), Assert: A physician-in-
the-loop content-based retrieval system for
HRCT image databases, Comput. Vis. Image
Understand., vol. 75, no. 12, pp. 111132.
[2] Bandon D , A. Geissbuhler , N.
Michoux,(2009), A review of content-based
image retrieval systems in medical applications
clinical benefits and future directions, Int. J.
Med. Informat., vol. 73, no. 1, pp. 123.
[3] Belongie S, Malik J, and Puzicha J (2004),
Shape matching and object recognition using
shape contexts, IEEE Trans. Pattern Anal.
Mach. Intell, vol. 24, no. 4, pp. 509522.
[4] Beaulieu F, S. A. Napel C. Rodriguez, J. Xu
(2009), Rubin, Automated retrieval of ct
images of liver lesions on the basis of image
similarity: Method and preliminary results.,
Radiology, vol. 256, pp. 243252
[5] Brady M and Kadir Z.T (2004), An affine
invariant salient region detector, in Proc. Eur.
Conf. Comput. Vis., pp. 404416.
[6] L hen, D. Foran L. Goodell, O. Tuzel L. Yang
(2009), Pathminer:Aweb-based tool for
computer-assisted diagnostics in pathology,
IEEE Trans. Inf. Technol. Biomed., vol. 13, no.
3, pp. 291299.
[7] Davis C, Klaric M, Scott G and Shyu C.R
(2011), Entropy-balanced bitmap tree for
shape-based object retrieval from large-scale
satellite imagery databases, IEEE Trans.
Geosci. Remote Sens., vol. 49, no. 5a pp.
16031616.
[8] Ebadi H, Mokhtarzade M and Sedaghat (2011),
Uniform robust scale invariant feature
matching for optical remote sensing images,
IEEE Trans. Geosci. Remote Sens., vol. 49, no.
11, pp. 45164527.
[9] Fang T, Xu S and Wang S (2010), Object
classification of aerial images with bag-of-
visual words, IEEE Geosci. Remote Sens.
Lett, vol. 7, no. 2, pp. 366370.
[10] Goncalves J and Goncalves H
(2011),Automatic image registration through
image segmentation and SIFT, IEEE Trans.
Geosci.Remote Sens., vol. 49, no. 7, pp. 2589
2600.
[11] Gool L.J, Moons T and Ungureanu D
(2000),Affine/photometric invariants for
planar intensity patterns, in Proc. Eur. Conf.
Comput. Vis., pp. 642651.
[12] Hongyu Y and Wen C (2004), Remote sensing
imagery retrieval based- on Gabor texture
feature classification, in Proc. Int. Conf. Signal
Process., pp. 733736.
[13] Lindeberg T (1998), Feature detection with
automatic scale selection, Int. J. Comput. Vis.,
vol. 30, no. 2, pp. 79116.
[14] H.Lang, R. Hanka, and H. H. S. Ip(2003),
Histological image retrieval based on
semantic content analysis, IEEE Trans. Inf.
Technol. Biomed., vol. 7, no. 1, pp. 2636.










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VIDEO MULTICAST USING LBP AND QDM
IN WIRELESS NETWORK

Ayyappan B
1
Jagan P
2
, Rajasekar K
3
, Thenpandian S
4
1,
Asst Prof,Information Technology,Jeppiaar Engineering College,Chennai,India

2,3,4
information Technology,Jeppiaar Engineering College,Chennai,India



ABSTRACT
Adaptation of transmission bit-rate for
video multicasting is a challenging problem
because of heterogeneous client speed and
variable bit-rates.Prior approach based on leader
based schemes to achieve the video multicasting
for the node that experiences the worst channel
condition .However ,this could affect the other
nodes that can receive a higher throughput. Our
goal is to provide clients heterogeneous visual
quality matching their channel conditions .we
providing differentiated video quality for various
clients to match their heterogeneous channel
conditions and guaranteeing minimum visual
quality for each client. Specifically, our goal is to
develop a software-based rate scheduling protocol
in order to produce the maximal total visual
quality for quality-differentiated video multicast
under the constraint of ensuring at least minimum
visual quality for each member.

Keywords: modulation, multicast, Quality
Differentiated Multicasting(QDM),transmission bit-
rates ,leader based protocol

I. INTRODUCTION
In this paper we have found a way to
transmit the video to different multirate system in a
wireless network connection such that every client node
gets the video streaming with a effective quality
without any data loss using a technology called
QDM(Quality differentiated multicast) and LBP(Leader
Based Protocol) [1].

II. SYSTEM ANALYSIS
Due to the heterogeneity among multicast members,
different multicast recipients may observe dissimilar
link qualities. Recently, several works have focused
on how to allocate bandwidth efficiently for
broadcasting video streams to clients either with
heterogeneous resources, e.g., screen resolution or
decoding capability, or with multiple access
technologies. Our goal is to provide clients
heterogeneous visual quality matching their channel
conditions. Most work on rate selection for wireless
multicast focuses on achieving multicast reliability
by selecting the rate that can deliver data reliably to
the member with the worst channel condition. In the
Leader-Based Protocol (LBP) is the first leader-based
approach proposed to overcome the problem of
feedback collision. It selects the worst node as the
leader to acknowledge multicast packets. Other
members can issue negative acknowledgements to
collide the acknowledgement sent by the leader and,
thus, trigger the sender to retransmit the lost packets.
The goal of LBP is to support reliability by a single
feedback [2].
However, it does not adapt the transmission bit rate
to dynamic channel conditions, but only sends data at
the base rate. Thus, the rate adaptation algorithms,
such as RAM and ARSM, are proposed for the
leader-based multicast protocol. They estimate link
quality of the leader and determine a proper rate that
can better reach the leader. Both of these techniques
let each receiver embed the information about it
receiving SNR value in the CTS frame. The sender
can infer the leaders SNR upon receiving the CTS
frames, and predict a suitable rate accordingly.

A. PROBLEM FORMULATION
However, this approach may not be efficient for
video multicast because it merely selects the rate that
maximizes the throughput of the worst node. In doing
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so, it penalizes those nodes who can receive data at a
higher bit rate [3].To avoid this effect, some
multicast rate adaptation schemes select the member
who experiences the worst channel condition as the
leader of the multicast group, and predict a bit
rate that can reach this leader.

III. PROPOSED ARCHITECTURE
In this project, we providing differentiated
video quality for various clients to match their
heterogeneous channel conditions and guaranteeing
minimum visual quality for each client. Specifically,
our goal is to develop a software-based rate
scheduling protocol in order to produce the maximal
total visual quality for quality-differentiated video
multicast under the constraint of ensuring at least
minimum visual quality for each member.
We model the rate scheduling problem as a
variation of the Knapsack problem, and propose a
dynamic programming solution to solve it optimally.
We propose a practical protocol, called Quality-
Differentiated Multicast (QDM), which exploits a
sample-based technique to adapt the transmission bit-
rate of each video frame to variable video bitrates and
client mobility without the need of any preprocess.

Fig 4.1.System Architecture Diagram

A. PEAK SIGNAL-TO-NOISE RATIO
(PSNR)
The different transmission bit-rate for each
video frame according to its importance (defined as
the rate scheduling problem), so that members can
receive differentiated video quality that best takes
advantage of their channel conditions. An intuitive
solution of the rate scheduling problem is to select
the rates that can achieve the maximal peak signal-to-
noise ratio (PSNR) value (a metric standardized by
ITU and used to evaluate video quality.
B. WIRELESS MULTICAST
Most work on rate selection for wireless
multicast focuses on achieving multicast reliability
by selecting the rate that can deliver data reliably to
the member with the worst channel condition. In the
Leader-Based Protocol (LBP) is the first leader-based
approach proposed to overcome the problem of
feedback collision [3-4]. It selects the worst node as
the leader to acknowledge multicast packets. Other
members can issue negative acknowledgements to
collide the acknowledgement sent by the leader and,
thus, trigger the sender to retransmit the lost packets.
The goal of LBP is to support reliability by a single
feedback.

C. QUALITY DIFFERENTIATED MULTICAST
(QDM)
The propose a practical protocol, called
Quality Differentiated Multicast (QDM), which
exploits a sample-based technique to adapt the
transmission bit-rate of each video frame to variable
video bitrates and client mobility without the need of
any preprocess. Thus, it can be applied to real-time
video streaming.

D. RATE SCHEDULING MODEL
A theoretical optimization model, and utilize
a dynamic programming algorithm to compute the
solution using oracle information. This model needs a
high computational complexity and complete
information about the packet loss probability of each
wireless link. Our motivation is to use the model as a
reference to assess the performance of our new
technique, called QDM, introduced in the next
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section. We will discuss their performance
comparison.

E. MULTIPLE DESCRIPTIONS CODING
(MDC):

The MDC encodes a media stream into
multiple independent sub streams any part of which
can be decoded independently. Receivers can get
minimum quality by decoding one arbitrary
description, and achieve incremental improvement by
receiving additional descriptions.


F. QDM FRAMEWORK:

The model in the last section is proposed to
find the most efficient solution, which needs
complete information about the loss probability To
cope with the above practical issues, we propose DM,
a practical video multicast framework including three
components: 1) cluster construction: it clusters clients
according to their channel conditions in order to
characterize the heterogeneity of clients; 2) sample-
based rate scheduling: it predicts the rate schedule by
real-time sampling, and, thus, can estimate visual
quality even if information.
V. EXPERIMENTAL RESULTS



Fig V.(a) .Server


Fig V.(b).Proxy


Fig.V.(c) Video Transmission
VI. CONCLUSION & FUTURE WORK

The performance evaluation shows that QDM can
produce a gain of 2-5 dB in terms of the average
video quality as compared to the leader-based
scheme, while also guarantee that each client
perceives at least a minimum video quality. In
addition, the two-state rate-adaptation scheme in
QDM can adapt the rate to network dynamics and
variable video bit rates with a reduced sampling
overhead.
REFERENCES

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[1] K.A. Hua and F. Xie, A Dynamic Stream
Merging Technique for Video-on-Demand Services over
Wireless Mesh Access Networks, Proc. IEEE CS
Seventh Ann. Conf. Sensor Mesh and Ad Hoc Comm.
and Networks (SECON), 2010.
[2] A. Kamerman and L. Monteban, WaveLAN-II:
A High-Performance Wireless LAN for the Unlicensed
Band, Bell Labs Technical J., vol. 2, no. 3, pp. 118-133,
1997.
[3] G. Holland, N. Vaidya, and P. Bahl, A Rate-
Adaptive MAC Protocol for Multi-Hop Wireless
Networks, Proc. ACM MobiCom, 2001.
[4] B. Sadeghi, V. Kanodia, A. Sabharwal, and E.
Knightly, OAR: An Opportunistic Auto-Rate Media
Access Protocol for Ad Hoc Networks, Proc. ACM
MobiCom,2002

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IMPLEMENTATION OF TEMPERATURE
COMPENSATION TECHNIQUE WITH ULTRASONIC
RANGING FOR OBSTACLE IDENTIFICATION
B.Nalini
1
, B.Nandhini
2
, E.Kavitha
3
, Mrs R.Chandralekha
4
1,2,3
EEE, Veltech multi tech Dr.RR Dr.SR Engg. College, Chennai, India
4
Assistant professor EEE, Veltech multi tech Dr.RR Dr.SR Engg. College, Chennai, India


ABSTRACT
The main aim of the model proposed in this
project is to reduce the error in the distance
measured by ultrasonic sensor using
temperature compensation. With the help of this
we are implementing a system to give alarm
once an obstacle is identified within a specified
distance. The applications may vary according
to the field such as in industries, self-propelling
vehicles, robots or for differently abled person
to detect the obstacle. The model contains an
ultrasonic sensor for distance measurement. A
temperature sensor is also provided for
measuring the temperature of the surrounding
environment. An error is caused in the distance
measured by the ultrasonic sensor due to the
temperature variation. This can be overcome
with the help of the technique of temperature
compensation proposed in this paper. The
sensors are interfaced with a PIC
microcontroller. Based on the calculated
distance, an alarm or LED indication is given
when the obstacle is near. Using ZigBee
transmitter and receiver, the measured values
are sent to a computer. Then a MATLAB based
calculation and analysis is carried out to obtain
the correct distance of the obstacle and to bring
out the difference in the measured value with
compensation and that without temperature
compensation. The main advantage of this
project is its simplicity and feasibility. In future
the analysis can be done for different materials
so that effect of all material can be analysed.
Other factors such as humidity and pressure can
also be included so that the combined
compensation can reduce more error.
Keywords: MATLAB analysis, obstacle,
temperature compensation, ultrasonic, ZigBee.

I. INTRODUCTION
There are various techniques to locate a moving
target in real-time. These can be IR based,
Ultrasonic based or RFID based technology. In [1]
an obstacle detection system using ultrasonic
sensors and USB camera based visual navigation
was considered .In [2] a smart phone based
ultrasonic wireless ranging and collision warning
system was proposed. Many obstacle detection
techniques also use IR sensors. But the sensor
cannot be used in sunlight. Some techniques use
RFID but it is costly. Hence the proposed system is
very effective. In the system proposed we are using
ultrasonic sensor which is more accurate and can be
used outside also.
II.PROPOSED SYSTEM
The general block diagram of the proposed system
is shown in figure 1. Distance is measured with the
help of ultrasonic sensor. Temperature sensor
measures the environment temperature. The
PIC16F887 microcontroller computes the distance
with temperature compensation.
The computer receives serial data (temperature and
distance) from the controller using ZigBee
technology and MATLAB based compensation is
done and displayed. If the distance is below
particular value (say 5 or 10 cm), buzzer alarm is
given to indicate the presence of an obstacle.
A. Ultrasonic sensor:
The audible sound frequency for ultrasonic sound
waves greater than 20kHz.Thus it is greater than
human audible frequency.
With the ultrasonic advance, and the electronic
technology development, especially as high-power
semiconductor device technology matures, the
application of ultrasonic has become increasingly
widespread. Some of the applications are given
below.
Ultrasonic measurement of distance, depth
and thickness
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Ultrasonic testing
Ultrasound imaging
Ultrasonic machining, such as polishing,
drilling
Ultrasonic cleaning
Ultrasonic welding

Figure 1: Block diagram of proposed system

The ultrasonic sensor used in this project is HC
SR04. It has four pins: vcc, trig, echo, and ground.
The pin diagram is shown below.
.
Figure 2: Pin diagram of ultrasonic sensor
Electrical Parameters of HC-SR04 Ultrasonic
Module are given the table 1.

Table 1: HC-SR04 electrical parameters
Operating
Voltage
DC 5V
Operating
Current
0.015A
Operating
Frequency
40kHz
Farthest Range 4m
Nearest Range 0.02m
Measuring
Angle
15 degrees
Input trigger 10s TTL pulse
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ning, such as polishing,

ure 1: Block diagram of proposed system
The ultrasonic sensor used in this project is HC-
It has four pins: vcc, trig, echo, and ground.

Figure 2: Pin diagram of ultrasonic sensor
SR04 Ultrasonic
SR04 electrical parameters
5V
A
40kHz

15 degrees
s TTL pulse
signal
Output echo
signal
Output TTL level signal
proportional with range
Dimensions 45*20*15 mm

Ultrasonic transmitter emits an ultrasonic wav
one direction, and starts timing when it launched.
Ultrasonic spreads in the air
immediately when it encounters obstacles on the
way. At last, the ultrasonic receiver
when it receives the reflected wave. As U
spread velocity is 340m / s in the air, based on the
timer record t, we can calculate the distance (d
between the obstacle and transmitter, namely:

d =340t / 2

This is called as the time difference distance
measurement principle.

The sound wave spreading velocity for the sensor
used here is 340m/s. The following steps are to be
followed for measuring distance with the help of
ultrasonic sensor. The Trig and Echo port
low when the module initializes. Then at
high level pulse is transmitted to the Trig pin.
the module automatically sends eight 40K square
wave. Then we wait to capture the rising edge
output by echo port at the same time,
opened to start timing. The falling edge output by
echo port is captured, at the same time;
the counter is read. Then the test distance is
calculated as below:

Test distance = (high level time*sound waves
spreading velocity in air)/2.

B. Temperature sensor:
The temperature sensor used in this project
DS18B20. The DS18B20 provides 9
Celsius temperature measurements. The DS18B20
communicates over a 1-Wire bus that by definition
requires only one data line (and ground) for
communication with a central microcontroller. It
has three pins: VDD, DQ, and ground.
diagram is shown in figure 3.
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Output TTL level signal
proportional with range
45*20*15 mm
an ultrasonic wave in
timing when it launched.
air and returns
obstacles on the
receiver stops timing
the reflected wave. As Ultrasonic
spread velocity is 340m / s in the air, based on the
calculate the distance (d)
and transmitter, namely:
time difference distance
The sound wave spreading velocity for the sensor
The following steps are to be
followed for measuring distance with the help of
he Trig and Echo port are set as
Then at least 10s
to the Trig pin. Now
ly sends eight 40K square
wait to capture the rising edge
at the same time, the timer is
he falling edge output by
at the same time; the time of
the test distance is
Test distance = (high level time*sound waves
The temperature sensor used in this project is
DS18B20. The DS18B20 provides 9-bit to 12-bit
Celsius temperature measurements. The DS18B20
Wire bus that by definition
requires only one data line (and ground) for
communication with a central microcontroller. It
DD, DQ, and ground. The pin
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Figure 3: Pin diagram of temperature sensor
The core functionality of the DS18B20 is its direct
to-digital temperature sensor. The resolution of the
temperature sensor is user-configurable to 9, 1
11, or 12 bits, corresponding to increments of
0.5C, 0.25C, 0.125C, and 0.0625C,
respectively. The default resolution at power
12-bit. The DS18B20 powers up in a low
idle state.
Some of the features of the temperature sensor are:
The operating temperature of the sensor is
-55
0
C to +125
0
C.
It can be powered from Data Line; the
power Supply Range is 3.0V to 5.5V.
It has a 0.5C Accuracy from
+85C.
Resolution of the sensor is user selectable
from 9 to 12 bits.
It converts temperature to 12 b
word in 750ms (max)

C. PIC microcontroller:

The microcontroller used in this project is
PIC16F887.
The PIC16F887 is one of the latest products from
Microchip. It features all the components which
modern microcontrollers normally have. For its low
price, wide range of application, high quality and
easy availability, it is an ideal solution in
applications such as: the control of different
processes in industry, machine control devices,
measurement of different values etc. Som
main features are listed below.

Operating frequency of the controller is 0
20 MHz
It has a precision internal oscillator which
is factory calibrated.
Power supply voltage is 2.0-5.5V.
International Journal for Research and Development in Engineering (IJRDE)
ISSN: 2279-0500 Special Issue
Methods Enriching Power and Energy Development (MEPED) 2014
Figure 3: Pin diagram of temperature sensor
The core functionality of the DS18B20 is its direct-
digital temperature sensor. The resolution of the
configurable to 9, 10,
11, or 12 bits, corresponding to increments of
0.5C, 0.25C, 0.125C, and 0.0625C,
respectively. The default resolution at power-up is
bit. The DS18B20 powers up in a low-power
Some of the features of the temperature sensor are:
operating temperature of the sensor is
It can be powered from Data Line; the
power Supply Range is 3.0V to 5.5V.
It has a 0.5C Accuracy from -10C to
Resolution of the sensor is user selectable
temperature to 12 bits digital
The microcontroller used in this project is
The PIC16F887 is one of the latest products from
Microchip. It features all the components which
mally have. For its low
price, wide range of application, high quality and
easy availability, it is an ideal solution in
applications such as: the control of different
processes in industry, machine control devices,
measurement of different values etc. Some of its
Operating frequency of the controller is 0-
It has a precision internal oscillator which
5.5V.
The power consumption is
4MHz), 11A (2.0 V, 32 K
(stand-by mode).
Power-Saving Sleep Mode is available.
35 input/output pins are available.
D. ZigBee:

ZigBee is based on an IEEE 802.15 standard.
Though low-powered, ZigBee devices can transmit
data over long distances by passing data through
intermediate devices to reach more distant ones.
Because ZigBee nodes can go from sleep to active
mode in 30 ms or less, the latency can be low and
devices can be responsive, particularly compared to
Bluetooth wake-up delays, which are typically
around three seconds. Because ZigBee nodes can
sleep most of the time, average power consumption
can be low, resulting in long battery life.
driver has to be installed in the computer in order to
connect the ZigBee receiver to it.
In this project ZigBee is used to transmit the data
from the various sensors interfaced with the
PIC16F887 microcontroller to the PC in which
MATLAB based calculation and analysis is done.

E. MATLAB based analysis:

A MATLAB based GUI is developed. The actual
distance measured by the ultrasonic sensor and the
temperature measured by the temperature sensor
received through ZigBee are displayed. Then the
compensation is done and the new distance
calculated is also displayed in the GUI. Thus the
amount of error reduction can be analys

F. Implementation:

The sensors are interfaced with the microcontroller.
Then the LED and Buzzer alarm are also interfaced
to the PIC controller. A configuration switch can
also be provided to select the range of proximity of
the obstacle for which the alarm has to be given.
The ZigBee transmitter is also connected to the
microcontroller.
The ZigBee receiver is connected to the computer
through USB port. The required software is
downloaded. MATLAB based GUI is developed
and used for analysis.

International Journal for Research and Development in Engineering (IJRDE)
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232 | P a g e
The power consumption is 220A (2.0V,
A (2.0 V, 32 KHz) 50nA
Saving Sleep Mode is available.
35 input/output pins are available.
ZigBee is based on an IEEE 802.15 standard.
powered, ZigBee devices can transmit
data over long distances by passing data through
intermediate devices to reach more distant ones.
Because ZigBee nodes can go from sleep to active
mode in 30 ms or less, the latency can be low and
devices can be responsive, particularly compared to
up delays, which are typically
ee seconds. Because ZigBee nodes can
sleep most of the time, average power consumption
can be low, resulting in long battery life. FTDI
driver has to be installed in the computer in order to
d to transmit the data
from the various sensors interfaced with the
PIC16F887 microcontroller to the PC in which
MATLAB based calculation and analysis is done.
A MATLAB based GUI is developed. The actual
the ultrasonic sensor and the
temperature measured by the temperature sensor
received through ZigBee are displayed. Then the
compensation is done and the new distance
calculated is also displayed in the GUI. Thus the
amount of error reduction can be analysed.
The sensors are interfaced with the microcontroller.
Then the LED and Buzzer alarm are also interfaced
to the PIC controller. A configuration switch can
to select the range of proximity of
the alarm has to be given.
The ZigBee transmitter is also connected to the
The ZigBee receiver is connected to the computer
The required software is
MATLAB based GUI is developed
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III. TEMPERATURE COMPENSATION

The speed of sound at 0 degree Celsius is
331.46m/s. In dry air at 20 C (68 F), the speed of
sound is 343 metres per second. It is because the
speed of sound waves is affected by various factors
like temperature, pressure and other factors.

A. Speed of sound in ideal gas:
The speed of sound in an ideal gas is independent
of frequency. It is proportional to the square root of
the absolute temperature, but is independent of
pressure or density for a given ideal gas. It is also
independent of pressure in an ideal gas.
B. Speed of sound in real gas:
The speed of sound does vary slightly with
frequency in a real gas. Sound speed in air varies
slightly with pressure. In addition, for different
gases, the speed of sound is inversely proportional
to the mean molecular weight of the gas [4].
Thus various factors affect the speed of sound
waves. In this paper we are trying to reduce the
effect of temperature.

C. Distance calculation:
Generally the distance is measured by the
ultrasonic sensor is given as:

= /2
C is the speed of sound waves. t is the time
interval between the transmission and reception of
the ultrasonic waves. It is known as the round trip
delay. Hence to find the distance of the obstacle
half the value of t is taken.
Now since the value of C is dependent on
temperature, the value of the distance measured by
the ultrasonic sensor is also affected.
The formula without temperature compensation is:

Dcm=34000*
(t*10
-6
)
2

Here since the round trip delay is in s, it is
converted to seconds and the distance in
centimetres is obtained from the above equation.
It is observed that the speed increases by 0.607 m/s
for an increase of 10 degree Celsius in air
temperature and also decrease for decrease in
temperature [1]. The reported distance will be
comparably less in hot weather and large in cold
weather. To overcome this problem we are using
temperature compensation. The speed of ultrasonic
waves in air is 340m/s. Thus the new formula is
obtained with the help of this information.

The formula with temperature compensation is:
Dcm=(34000+60.7T)*
(t*10
-6
)
2

Where t = round trip delay from ultrasonic sensor
and T= temperature of the surrounding.
So this formula is used to obtain the corrected
distance based on which the obstacle will be
detected and if found to be very near, an alarm will
be raised.

IV. APPLICATIONS
This system can be used in automatic robots, self-
propelling vehicles in automated production
factories etc. This distance measurement and
obstacle detection system can be used in places
where accurate distance measurement is required.
This system if reduced in size can also be
implemented for helping blind people.
V. CONCLUSION

The accuracy of the distance measurement is thus
improved by using this module along with
temperature compensation. This project effectively
reduces the error in the distance measured due to
the effect of temperature. In future various other
factors influencing the distance measurement can
be taken into account. The proposed method is
highly effective and efficient.


REFERENCES

[1] Rahul Kumar Rastogi, Rajesh Mehra Efficient
Error Reduction in Ultrasonic Distance
Measurement Using Temperature compensation.
[2] Amit Kumar, Rusha Patra, M. Manjunatha, J.
Mukhopadhyay and A. K. Majumdar, IIT,
Kharagpur An Electronic Travel Aid for
Navigation of Visually Impaired Persons
International Conference on Communication
Systems and Networks (COMSNETS), PP-1-5,
IEEE 2011.
[3] Bruno Ando, and Salvatore Graziani,
Multisensor Strategies to Assist Blind People: A
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Methods Enriching Power and Energy Development (MEPED) 2014 234 | P a g e



Clear-Path Indicator, Transactions on
Instrumentation and Measurement, Vol. 58, Issue
no. 8, PP- 2488-2494, IEEE.
[4] http://en.wikipedia.org/wiki/Speed_of_sound.
[5]http://www.elecfreaks.com/store/download/prod
uct/Sensor/HC-SR04/HC-
SR04_Ultrasonic_Module_Guide.pdf

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Hardware mapping for Graphics Geometric Intersections

R.Karthika
1
,K.Kayalvizhi
1
,P.Meera
1
and Dr.M.P.Chitra
2

1
student, Electronics and communication, Panimalar Institute Of Technology, Chennai-123,
2
Professor and head, Electronics and communication, Panimalar Institute of Technology, Chennai-123.



ABSTRACT
Most consumer electronic devices employ graphic
applications which vector graphics equations to model
various object shapes. These mathematical representations
of data are computationally intense giving ample scope for
hardware oriented accelerating ways. This paper explains
the hardware mapping of ray tracing algorithm which is
used for three dimension object rendering. First, the
matlab simulation model for various object rendering is
demonstrated. Based on this model, architecture is
proposed using fast arithmetic units like divider,
multipliers and square root. The proposed computational
element computes the box-cube intersections. The
synthesis result shows that it can run at 20 MHz
frequency.
Keywords Vector graphics, Ray Tracing, rendering,
data path.

I.INTRODUCTION

Computer graphics are graphics created using
computers and the representation of image data by a computer
with the help of graphics hardware and software. It is used to
understand and interpretation of data in an easier manner.
Vector graphics is used to create more complex image. If a
vector graphic image is made very big on the monitor, it will
still be as good as its regular size.
3D graphics is the three dimensional representation
of data. Some of the algorithm used in 3D graphics are ray
tracing, cone tracing, beam tracing, path tracing, photon
mapping, scan-line renderer. Ray tracing is the one of the
method to render the 3D image. It is the most straightforward
method compared to other algorithms [7], [1]. There are many
techniques to improve the performance of 3D graphics. In this,
graphics accelerator is one of the techniques. It is hardware
used to perform functions faster than the software. In shading,
secondary and tertiary reflections are not considered. It will
consider only primary reflection.

II.RAY TRACING

Ray tracing is a technique for generating an image by
tracing the path of light through pixels in an image plane. This
technique is capable of producing a very high degree of
photorealism. There are two types of ray tracing are forward
and reverse ray tracing. In forward ray tracing, it traces the
light path from light source to object and from object to
viewer. Many photons will come from the light source to find
only one photon that would strike the viewer. This is the main
drawback of the forward ray tracing. To overcome this
drawback, reverse ray tracing is used. In reverse ray tracing
[8], it traces light from viewer to object and from object to
light source. If the ray hits an object from viewer, it is used to
find how much light it receives by throwing another ray from
object to light source.


Figure 1: Image plane Formation

Ray tracing includes three steps of process to trace the image.
i) Intersection tests
ii) Grid traversal
iii) Shading

In intersection tests, each ray is tested for intersection
against the surface in the rays current pixel in the grid.
Intersection testing is done with ray tracing algorithm. If the
intersection is found within the pixel, the surface index and
information about the point of intersection are stored alone to
be used in future for tracing image in the final process of
algorithm. In grid traversal, if an intersection is not found in
the previous process the ray will be traversed through the grid
Viewer origin
(x0, y0, z0)
Image plane
Object
X axis
Y axis
Z axis
Max, Min
bound
International Journal for Research and Development in Engineering (IJRDE)
www.ijrde.com ISSN: 2279-0500 Special Issue: pp- 235-239


to the next pixel which intersects in the grid. If an intersection
has been found, no tracing will be done either a new ray will
be created with its beginning point in the pixel. This created
ray is named as shadow. If there is an intersection, then the
pixel is shaded using the point of intersection, position of light
and material, color and normal of the hit surface.







(a) (b) (c) (d) (e)
Figure 2: Various Graphics Geometric in 3D with varied orientation (a) and (b) representing Cube, (c) and (d) representing Sphere, (e)
Representing Tetrahedron

The following pseudo code techniques the computation of
every pixel value of the image plane is taken

For every pixel value {
Generate Viewing Rays r(x, y, and z)
Calculate the intersection I(x0, y0, z0)
Determine suitable shading f(x, y, z)
Find the Pixel value}



Figure 3: Viewing Rays
To view the ray direction,

/| | (1)
Where, X = ray direction, R = image center,
S = focal point, r (t) = viewing ray can be represented as

(2)

RAY-SPHERE INTERSECTION

To find the point on the ray,
(3)
To find the point on sphere,

. (4)
Substitute the equation (3) in (4)

. (5)
To find the solution for the above equation, use quadratic
solution. The suitable coefficients shall decide the point of
intersection of generated rays and the object surface using
equation (6).
The equation is in the form of

0. (6)
Where

, 2. ,


Let

4
If d < 0 no solution
Otherwise
_ / 2 , Check t_ 0

RAY-BOX INTERSECTION

Equation (7), (8) (9) (10) explains the method of
intersection finding for axis aligned cube - box which involves
solving simultaneous equations as shown in figure 4.

To find where the ray intersects with this line is
(7)
Re-ordering the above expression
/.. (8)
If the value of t is negative then box is behind the ray.
Similarly, the ray intersects the box plane parallel to the y and
z axis.
0 0/... (8)

0 0 0/.. (10)



Figure 4: Ray-Box Intersection

The results of the matlab model constructed for sphere,
cubical and tetrahedron intersection is shown in the figure (2).
International Journal for Research and Development in Engineering (IJRDE)
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Methods Enriching Power and Energy Development (MEPED) 2014 237 | P a g e



The point of origin (camera viewing) and light throwing
direction, focal length, focal point, material properties,
viewing direction are considered parameter. To keep it simple,
the considered material surface is opaque so the reflection and
refraction phenomenon and multiple reflections are avoided.
The model object rendering for various orientation is also
illustrated. The basic unidirectional lighting and shading [6]
for the rendered object is considered.

III. DATA PATH ARCHTIECTURE

As computational 3D geometry its origin, the vector
graphics equation dictates these tasks are highly
computationally intensive. The hardware mapped to these
corresponding iterations is the suitable solution to these
demands [2]. The data path synthesis is alone considered from
the entire architecture.
However, at the coarse level of this architecture include
adders, subtractor, multipliers, dividers, square roots only. The
efficient methods of these individual units combined with
proper data driven arrangement will make the computational
overhead at ease. The increased pipelined registers in between
these hardware units can effect easy processing with little
compromise on area utilized by these registers. This data path
is explained here is novel architecture of one computational
element, basic unit of computation. The architecture reuse is
made in use through this method as this repeatedly accessed
for every pixel value in the image plane.
The computational element takes the coordinates of the
origin view point and the image plane points to calculate the
viewing ray direction. Having direction computed the ray
extension R (t) is done for varying values of t. Next, to find
the intersection with specific geometry i.e. cube or box like
structure is taken as consideration. The Vmin and Vmax
bound limits the cube with axis aligned as {Xmin, Xmax}
{Ymin, Ymax} and {Zmin, Zmax}.
Figure 6 shows the architecture of a computational element
which is the basis for computing value of a pixel in the image
plane. First the input co ordinates (x1, y1, z1) with the
considered origin (x0, y0, z0) the unit direction vector is
calculated for ray generation. After generation, the intersection
for cube-box object is by solving the equation using the
suitable integer value. The arithmetic multiplier employs
modified booth algorithm which computed is n/2 iteration
limit. The arithmetic divider unit has restoring method of
division. The hardware unit for square root gives only integer
results with little compromise on accuracy.

In box intersection the respective axis intercept with
magnitude value is computed and compared with the each
other to calculate the intersection points. The minimum and
maximum value of those intercept within the bound Vmin and


Vmax values are inferred to confirm the intersection with the
rendered object boundary.




X1-X0

Y1-Y0 Z1-Z0
(.)
2
(.)
2
(.)
2
(+)/ (.)
*
+ y=x0+ t*r
x
min
-x
0

x
max
-x
0
y
min
-y
0
y
max
-y
0

z
min
-z
0

z
max
-z
0
xmin
ymin
zmin

Any
integer t
xmax
ymax
zmax
Ra Ry Rz
X0
x0 z0 y0
t0z>t0y t1x>t1y
> t
0z,
t
1z

t0x
t1x
t0y
t1y
t0z
t1z
t
min
t
max
t
0x
>t
1y

or
t
0y
>t
1y
No intersection

t
max
t
min
Yes
Creating
ray trace
Intersection
mapping to
cube-box
structure
no
International Journal for Research and Development in Engineering (IJRDE)
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Methods Enriching Power and Energy Development (MEPED) 2014 238 | P a g e




Figure 5: Hardware architecture of ray generation and
Cube-box Intersection
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Methods Enriching Power and Energy Development


IV. RESULTS AND DISCUSSION

The proposed architecture RTL level net list
inferred is shown in figure6. The results shows
with the critical path delay fixing the maxim
operating frequency up to 20
arithmetic unit with inherent pixel level parallelism
can be achieved with array of
elements. This computation with respect to a single
pixel is what that is iteratively repeated for
entire pixels in the image plane.
this architecture with parallel mapping pixel will
enable it for other geometric i
Using the sc105u technology, this architecture use
the clock frequency of 20
is 7000. It uses some of the gates are AN2T0,
AO1A0, FA2A0, HA1A0, IVIN0, etc.

REFERENCES

[1]Efficient Vector Graphics Rasterization Accelerator
Using Optimized Scan-line Buffer
vol.21, No.7, July 2013

[2]Ray Tracing On Graphics Hardware
Hachisuka, University of California, San Diego.

[3]Ray Tracing On Programmable
by Timothy, T.J. Purcell, I. Buck
P.Hanrahan Stanford University.
Trans.Graph.21,3,703-712,2002

[4]A 2.05 Gvertices/S 151 mw
3D Graphics Vertex And Pixel Shading
in IEEE journal of solid-state circuits,vol.48,No.1,Jan
2013.
International Journal for Research and Development in Engineering (IJRDE)
ISSN: 2279-0500


Methods Enriching Power and Energy Development (MEPED) 201



Figure 6: Synthesized Structure Of Computational Element
IV. RESULTS AND DISCUSSION
architecture RTL level net list
inferred is shown in figure6. The results shows
with the critical path delay fixing the maximum
operating frequency up to 20 MHz. The faster
with inherent pixel level parallelism
can be achieved with array of such computational
This computation with respect to a single
pixel is what that is iteratively repeated for the
in the image plane. The extension of
with parallel mapping pixel will
other geometric intersections too.
Using the sc105u technology, this architecture use
MHz and the total gates
. It uses some of the gates are AN2T0,
AO1A0, FA2A0, HA1A0, IVIN0, etc.
Efficient Vector Graphics Rasterization Accelerator
line Buffer in IEEE Transaction
Graphics Hardware by Toshiya
Hachisuka, University of California, San Diego.
Programmable Graphics Hardware
I. Buck William R.Mark,
Hanrahan Stanford University.ACM
,2002.
w Lighting Accelerator For
Pixel Shading In 32 Nm CMOS
state circuits,vol.48,No.1,Jan

[5]3D Graphics Acceleration Development
VLSI and Computer Grap

[6]An Improved Illumination Model
by Tuner Whitted, Bell laboratories, Holmdel, New
Jersey.

[7]Hardware
Y.O.Kim, H.J.Woo and C.H.Kim U.S.Patent 0 045 683
Feb 25 2010.

[8]Parker.S, Martin.W, Sloan.P, Shriley.P,
Hansen.C.1999.
Symposium on Ineractive 3D Graphics,

[9]B.G.Nam et al.,
Rendering Engine With Lighting Acceleration For
Handheld Multimedia Systems
Trans.Consum.Electron., vol.51,no.3, pp.1020
Aug 2005.

[10]Karlsson.F and Ljungstedt.C.J.2004.
Fully Implemented On Programmable Graphics
Hardware. Masters thesis, Chalmers University Of
Technology.

[11]Wald.I, Slusallek.P, Benthin.C, and Wagner.M.2001.
Interactive Rendering With Coherent Ray
Computer Graphics Forum 20,3,

[12]Deering, Michael and S.Nelson, Leo:
Cost Effective
SIGGARAPH,

[13]B.T.Phong,
Pictures, Commun. ACM,
1975.

International Journal for Research and Development in Engineering (IJRDE)
Special Issue: pp- 235-239
MEPED) 2014 239 | P a g e

Figure 6: Synthesized Structure Of Computational Element

3D Graphics Acceleration Development by centre for
VLSI and Computer Graphics, University of Sussex, UK.
An Improved Illumination Model For Shaded Display
by Tuner Whitted, Bell laboratories, Holmdel, New
Hardware Type Vector Graphics Accelerator by
Y.O.Kim, H.J.Woo and C.H.Kim U.S.Patent 0 045 683
Feb 25 2010.
[8]Parker.S, Martin.W, Sloan.P, Shriley.P, Smits Band
Hansen.C.1999. Interactive Ray Tracing. In 1999 ACM
Symposium on Ineractive 3D Graphics, 119-12.
9]B.G.Nam et al.,Development Of 3D Graphics
Rendering Engine With Lighting Acceleration For
Handheld Multimedia Systems, IEEE
Trans.Consum.Electron., vol.51,no.3, pp.1020-1027,
]Karlsson.F and Ljungstedt.C.J.2004.Ray Tracing
Fully Implemented On Programmable Graphics
. Masters thesis, Chalmers University Of
Technology.
Wald.I, Slusallek.P, Benthin.C, and Wagner.M.2001.
Interactive Rendering With Coherent Ray Tracing.
Computer Graphics Forum 20,3, 153-164.
[12]Deering, Michael and S.Nelson, Leo: A System For
Cost Effective 3D Shaded Graphics. Proceedings of
SIGGARAPH, 1993, pp.101-108.
[13]B.T.Phong, Illumination For Computer Generated
, Commun. ACM, vol.18, no.6.pp, 311-317, Jun
9
P a g e
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Performance Analysis for the Automatic Detection and
Grading of Macular Edema Stages
M.Ramya
1
, S.Vijayprasath
2
1
M.E Communication Systems, M.Kumarasamy College of Engineering, Tamilnadu, India
2
Assistant Professor, M.Kumarasamy College of Engineering, Tamilnadu, India



ABSTRACT
Recently, we have many researches on the fundus
image for the detection of abnormality. Diabetic
retinopathy is the damage of retina caused by
complication of diabetes which results complete
vision loss. Macula is responsible for our pinpoint
vision. Diabetic macular edema is the major
problem for the diabetic patients. Several
techniques have been reported about an automated
solution for the diabetic macular edema detection.
In this paper, we propose a new method for the
detection and severity classification of abnormality.
Proposed method has five steps which comprises of
localization and masking of optic disk and macula,
motion pattern generation, feature selection,
exudate detection by PCA DD, feature extraction
of possible exudate region for classification using
Naive Bayes Classifier. The normal retinal images
in the MESSIDOR database are taken for training
and testing. By finding the exudate, the
performance of the proposed methodology
provides better accuracy classification compare to
the existing method. In addition, the severity for
the abnormal images is graded as three stages.
Experimental result shows the superior nature of
proposed method in terms of performance
measures.

Keywords: Diabetic macular edema, Diabetic
retinopathy, Fundus, Hard exudates, Retina
I. INTRODUCTION
Retinopathy is the group of noninflammatory eye
disease. Diabetic retinopathy (DR) is a disorder of the
eyes which occurs in patients having diabetes. Early
detection and treatment is essential to prevent the DR
from its severe stage. Hypoalbuminemia is often
found in diabetic patients, as a major retinal disease
and subsequent loss of protein in the proteinuria.The
decreased plasma protein deliberation decreases the
intravascular oncotic pressure. This in turn results in
net fluid movement into the retinal tissues. The person
who has diabetics with longer year there is a chances
of developing diabetic retinopathy. This systemic
disease can degenerate DME and their treatment and
control can help to resolve DME. The patients with
retinopathy on premature stage, have no symptoms,
but at the mature stage, symptoms such as cloudy
vision or blind spots may develop in [1]-[3].
Eventually it will develop blindness if it is untreated.
Complete eye exam is the only way to know whether
the person have diabetic retinopathy or not. Macula is
found at the centre of the retina where the incoming
rays of lights are focused. The macula is very
important and it is responsible for what we see straight
in front of us, the vision needed for full activities and
for our ability to see colour.


(a) (b)
Figure 1: (a) A Normal retina, (b) A retina showing
signs of diabetic retinopathy
Macular edema is often complication of diabetic
retinopathy. The fluid and protein deposits collect on
or under the macula of the eye, cause it to thicken the
macula portion. Fig. 1 differentiates 1(a) the normal
retinal image and 1(b) abnormal retinal image by
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showing signs of diabetic retinopathy in the fundus
system. The symptom of DME was based on the HE
location with respect to the macula region. Hard
exudates have been used to grade the risk of macular
edema. In the retina, the yellow spots near the macula
are called hard exudates. The substances like lipid
break-down from the blood vessels. Usually Diabetic
macular edema (DME) can be evaluated directly or
indirectly. The manual examination (direct) is by
using Stereoscopy or optical computed tomography
images [6]. And in the other way of indirect
examination is done by the presence of hard exudates
in the retina. This indirect way is taken into an account
for the automatic assessment of the disease and the
severity level measurement in [7], [8], and [9]. The
remainder part of this paper prepared as follows. The
section II gives the literature review for the
abnormality detection. In section III, gives the brief
explanation with different algorithms and classifiers
for the processing steps. Finally, the paper is
concluded in section IV.
II. PAST DETECTION METHOD
Many techniques have been proposed for the detection
of abnormality in colour fundus images. Different
filters and classifiers have been used for the automatic
detection of exudates. These techniques help the
doctor to diagnose the disease as earlier as possible.
A. Case for automatic detection:
Silberman et al. [1] briefly discuss about a case for
automatic detection of diabetic retinopathy. In
addition it also discuss about the potential force on
early detection of DR. For the preprocessing the
global colour-balancing operation is performed. For
the SIFT feature extraction the segmentation mask is
created during preprocessing because the optic disk
and the exudates have the same intensity. They mask
the optic disk and subsequently mask the non-retinal
background component in the feature extraction.
Finally the images were trained using 2000 negative
and 1309 positive patches by the Gaussian SVM
classifier [10]. The classification score is greater than
93%. From the SIFT feature extraction of 1000
images, the SVM classifier detect that 87 images
having exudates.
B. CAD Scheme:
Hatanaka et al. [2] determine the both Hemorrhages
and exudate in ocular images. The detection of
Hemorrhages and exudates is done by the length-to-
width ratio analysis. It avoids the fluorescein
angiograms. In the detection process the blood vessels
were eliminated by examining the structure of blood
vessels. In this, the vessels in the centrelines are
extracted and eliminated to avoid the incorrectly
detected vessels. Finally, the funicular shapes were
eliminated to enhance the detection of hemorrhage. By
evaluating the lengthto-with ratio [11], the remaining
false positives are eliminated accurately. Normally the
ratio value was small when the candidate is incorrectly
detected as vessels. The detection of exudates is same
as the hemorrhage detection. Since the exudates are
segmented by thresholding technique. The only
difference is that the false positives are eliminated by
the contrast. For 109 fundus images, the detection of
exudates results with a sensitivity of 77% when the
specificity was 83%.
C. Computation intelligence based approach:
Osareh et al. [3] combines the computational
intelligence and pattern recognition with machine
learning techniques to analyse the diabetic
retinopathy. Two steps have been performed for the
pre-processing. In the first step, the colour retinal
images are normalized by using histogram
specification [12]. In the second step the local contrast
enhancement is performed to increase the contrast
level of exudates in [13]. The segmentation of retinal
image is done by using two-stage colour segmentation
algorithm based on Gaussian-smoothed histogram
analysis and FCMs clustering [14]. After segmentation
the feature is extracted by using Gabor filters based on
iris recognition. For selecting the best subset from the
input images, the genetic-based algorithm (GA) is
used for the result of better classification. The Neural
network classifier classifies the segmented regions
[15]. Over 150 images this scheme achieves
sensitivity of 96% and specificity of 94.6%.
D. Model based approach:
Li et al. [4] make use of the prior knowledge of the
retinal images. For the detection purpose first the optic
disk is localized by PCA which make use of the top-
down strategy for extract the common characteristics
among the training images. Boundary of the optic disk
is detected by Modified ASM. Then the fovea is
estimated at the centre of candidate region. A polar
coordinate system centred on the fovea is selected in
this work. The radii of the three fovea-centred circles
from the innermost to the outermost correspond to
(1/3) DD, 1DD and 2DD respectively. Finally the
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exudates are detected by region growing [17]. In this
the retinal image is subdivided into 64 subimages.
Exudate detection is performed in each subimage. The
resultant sensitivity and specificity is 100% and 71%
respectively.
III. PROPOSED DETECTION METHOD
In the proposed work, the HE detection and severity
classification is done by using Naive Bayes classifier.
The proposed method has two divisions. In the first
division the exudate detection is done by using single
class classifier called Principle Component analysis
data description (PCA DD) which is one of the
existing methods. In the second division the exudate
detected lesions in the process of PCA DD are taken
as input for the clear classification of exudates and
nonexudates using Naive Bayes classifier. The reason
for migrating to second division is because of
incorrect exudate detection. Before exudate detection
some steps of operation is done on images, which is
same for both divisions. The operations on the images
are explained in step by step manner given below with
flow diagram. Here the operations need not have
preprocessing operation because the images were
taken in the database. The database images have high
resolution, high contrast and no noise. So there is no
need of preprocessing. The preprocessing is taken into
an account only for enhancing the image and prior to
computational processing. It involves removing low-
frequency surroundings noise, normalizing the
strength of the individual unit of an image and
removing reflections. The detection and severity
classification steps are shown in Fig. 2. For both
classifiers the processing steps is same. The only
difference is in the detection process.























Figure 2: Flow diagram for the detection and assessment of
DME
A. Locating and masking of optic disk and macular
region:
The images in the database are in the form of RGB
colour combination. In the RGB colour images, only
the green channel is selected for input images. The
selection of green channel as
=

()
(1)
The green channel interest denoted as I gives a clear
contrast and high intensity compared to Red and Blue
colour component. The green channel interest I forms
the input for all upcoming processing. Next the Optic
disk and macular region were detected by the intensity
variation in the pixels. The optic disc is noticeable and
brightest region, where the macular region is the
darkest region in the fundus image. The macula is the
central region of the given input image. Their
centroids are detected using [19] and superimpose
those centroid locations on the input image. The large
and bright region is located as optic disc that consist
of pixels with the highest gray levels in [20] and [21].
In the fundus image the large lesions are similar to
optic disc lead to false detection. The optic disc is
detected and masked using [22]. Subsequently the
macular region also masked same as optic disc. The
detection and masking is shown in Fig.3.
Performance Comparison
Severity Classification
Nave Bayes PCA
Detection based
Feature Selection
Motion Pattern Generation
Locating and masking of OD
and macula
Green channel
Retinal images from database
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(a) (b)
Figure 3: Result of macula and OD detection (a)
Detection of OD and macula (b) Mask of OD in rectangle
and macula in circle

B. Motion pattern Generation:
The given image is transformed to an intermediate
representation called motion pattern that spatially look
up the HE presence regardless of their size. This is
followed by foundation of global features on motion
pattern for detection of HE. The images are rotated by
angle degrees in a counterclockwise direction around
its center point to induce the motion pattern. The
rotation step is -1 and maximum angle is -90.
Motion pattern I
MP
is obtained by using the union
operation as the coalescing function f. Let the given
input image I is denoted as ()

. A motion pattern I
MP

for I is derived as follows:

()

() (2)

where vector r denote the pixel location. G
N
is a
transformation representing the induced motion. Let N
be the transformed images generated by G
N
combined
using f to coalesce the sampled intensities at each
pixel location in (2). G
N
(I) is expressed as follows:
G
N
(I) = {R
n
(I)} (3)

where R is a rotation matrix. The rotation angle
n
=
n
0
with n=0,1,....N;
0
denotes the rotation step. For
the discriminability between normal and abnormal
retinal image the mean and maximum were consider
in this work. These are defined as follows:

()

(()

) (4)


(())

()

(5)

From the above two equations the mean tries to
achieve the averaging effect observed in motion blur
and the maximum tries to exploit the fact that HE
usually appear brighter than any other structures in the
background at the same radial distance. Here the
Shannons entropy is calculated for the motion pattern
I
MP
is defined as H(Y) at every point Y in the
magnitude of imageI

. The entropy is computed


over a local neighbourhood of Y to create an
entropy map. The total entropy is computed by
summing the entropy at every point Y as follows:
H

= H(I

(Y)) (6)
The discriminability d of normal and abnormal retinal
images is the difference between the entropy values
for normal and abnormal images
d = H


HMPnormal (7)
C. Feature selection:
In model construction, feature selection is the process
of selecting a subset of relevant features. Motion
pattern is well defined by using descriptor derived
from the Radon space. The radon transform method is
used for the feature selection in [9]. This provides the
rotation pattern for the mean values of the given
image. Then these mean vectors are passed to the
radon transform method to extract the rotation pattern
estimation and in the next step we extract the feature
values of the image. The radon function computes the
line integrals from multiple sources along parallel
paths in a certain direction. A projection of a two-
dimensional function f(x, y) is a set of line integrals.
The beams are spaced 1 pixel unit apart. To represent
an image, the radon function takes multiple parallel-
beam projections of the image from different angles
by rotating the source around the center of the image.
Since the transformation transform two dimensional
images with lines into a domain of possible line
parameters, where each line in the image will give a
peak positioned at the corresponding line parameters.
The radon transform of f(x, y) is computed as
P

(r) = f(x, y)(r xcos

y sin)dxdy (8)
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where r is the distance from a line to the origin and
is the angle formed by the distance vector. First a
vector response for every angle is obtained by
projecting the image I
MP
and then concatenates the
responses P

for different orientations to derive the


desired feature vector. The motion pattern I
MP

enhances the spatial extent of any HE that may be
present. Due to the intensity variation of HE the
normal retina feature vector have uniform values and
the abnormal retina feature vector have several peaks
in its profile. Thus the feature vectors are used for
learning the subspace corresponding to normal
images.
D. Detection of macular edema:
For the abnormality detection two classifiers are used
in this classification work: Principle component
Analysis Data Description (PCA DD) and Naive
Bayes Classifier.
1) PCA DD: By learning normal cases, the detection
of macular edema is achieved using this type of
classification. A classification boundary is formed in
the feature space around the subspace corresponding
to normal cases. Then the new image is projected to
this feature space for the classification. If that new
image is lies within this boundary, then it is classified
as normal otherwise it is abnormal. In the PCD DD the
linear subspace is defined for the normal images. The
subspace is described by the Eigen values
corresponding to the covariance matrix of the
training set. The new case is again reconstructed as
(I
MP
)
proj
by projecting that new case to the subspace.
Based on the reconstruction error the new image is
classified to be normal. The feature vectors (I
MP
)
were projected on to six dimensions to compute the
reconstruction error. For the classification, the
reconstruction error is computed as
(

) = ((

) (

(9)

In data description of classification between normal
and abnormal images, the threshold ranging from 0 to
1 was applied on the parameter (

). In Fig.4
shows the result of PCA DD. Fig.4 (a) is the detected
lesions and Fig.4 (b) is the detected exudates of colour
fundus image.

(a) (b)
Figure 1: Result of PCA DD (a) Detected lesions (b)
Detected exudate

By using this PCA DD method we met some problems
in the detection. Those are the exudate detection gives
more false positive values, smaller exudates detection
is less, raw data is not the best form for running a PCA
and normalization needs to be applied to the data
before running PCA.
2) Nave Bayes Classifier: It involves feature
extraction and classification. Naive Bayes classifier is
a simple probabilistic classifier based on applying
Bayes theorem with strong independence
assumptions. An advantage of naive Bayes is that it
only requires a small amount of training data to
estimate the parameters (means and variances of the
variables) necessary for classification [18]. Because
independent variables are assumed, only the variances
of the variables for each class need to be
determined and not the entire covariance matrix.
In the feature extraction step, the detected lesion
region from the PCA DD is considered as possible
exudate region which is taken as input. To increase the
possibility of detecting smaller exudates, the threshold
value for filtering is kept low by design. Pixels not
lying in the exudate category are detached in
classification phase. The appearance of exudates can
be viewed as bright yellow spots which can have
different sizes and shapes having strong and sharp
edges. If there are n possible regions for image x, in
which presence of exudates can be viewed, the set of
exudates can be represented as follows X = v1; v2; v3;
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_ _ _; vn. This whole set has to be processed for
detecting each exudate and non-exudate region. Every
potential candidate exudate is considered as a sample
vector input for the classification algorithm. The
classification algorithm uses certain features for
making the decisions. The feature vector includes of
area, compactness, mean intensity, mean HSV values,
mean gradient magnitude, energy, entropy and third
moment.
In the lesion identifying process, we have used the low
value of threshold by choice so that we can get most
out of the image in forms of possible exudates. The
unsure detections are eliminated in the phase of
classification. In the proposed scheme, we have used
Naive Bayes classifier [5]. Two classes are used for
classification those are R
1
= Exudate region and R
2
=
Non exudate region. The final decision of classifying
regions is made by using a supervised classification
method. The input data set is divided into subsets for
training. The classifier is trained using the earlier
created sample dataset. Bayes decision rule is used to
obtain a decision rule based on estimation from the
training set. Bayes decision rule is stated as [5].

Choose R
1
if; p (v|R
1
) P (R
1
) > p (v|R
2
) P (R
2
)
Otherwise Choose R
2
(1)

Here p (v
j
|R
i
) can be defined as the class conditional
probability Density Function and P (R
i
) is the prior
probability of class R
i
which is calculated as the ratio
of class R
i
samples in the training set.
E. Severity case of macular edema:
Considering 1 optic disk diameter from the center, is
the key interest to detect the risk of severity. The
classification is divided into three types of cases.
Those are normal case, moderate case and severe case.
If there is no HE present in the fundus image, that
image is classified as normal image otherwise it is
classified as affected image. The location of HE is not
inside macula, hence it is stated as a moderate case.
On the other hand the HE is within the macula, hence
the case is deemed severe. The severity classification
is characterized using rotational asymmetry metric by
studying the rotational symmetry of macular edema
[9].
IV. EXPERIMENTS AND RESULTS
A. Retinal images from database:
The image database is a collection of images. The
databases are publicly available with high contrast
compressed (jpeg) images [23]. The images from
these databases are taken for the evaluation purpose.
For the assessment of macular edema the training and
testing is performed on the MESSIDOR database.
MESSIDOR database consists of retinal images which
has macula as a centered on that fundus images. Over
200 images were taken for normal and abnormal
classification.

B. Detection results:
For the detection of macular edema and severity
classification the performance comparison parameters
are as follows: Sensitivity, Specificity, Precision, and
Accuracy. All the parameters are calculated by using
confusion matrix. The confusion matrix have the
following meaning in the context of our study: TP is
defined as sick people correctly diagnosed as sick and
FP is defined as Healthy people incorrectly identified
as sick. Then TN is defined as Healthy people
correctly identified as healthy and FN is defined as
Sick people incorrectly identified as healthy.
Sensitivity measures the proportion of actual positives
which are correctly identified as such that is the
proportion of a positive test, given that the patient is
ill. This can be written as Sensitivity = TP/(TP+FN).
Then Specificity measures the proportion of negatives
which are correctly identified as such that is the
proportion of negative test, that the patient is well. It
can also be written as, Specificity = TN/(TN+FP). The
Precision is the proportion of the predicted positive
cases that were correct, as calculated using the
equation: TP/(TP+FP). Finally, the Accuracy is the
proportion of the total number of predictions that were
correct. It is determined using the equation:
Accuracy(AC) = (TP+TN)/(TP+FP+FN+TN).

In Table I shows the calculation result for the
performance parameter. Table II shows the severity
classification for all three type of cases. Here the
threshold value is in percentage (p) as 10% for the S
value for normals and for the moderate case 30%.

Table 1: Performance classification for normal and
abnormal cases in MESSIDOR database
Parameters PCA DD Nave Bayes classifier
Sensitivity (%) 100 100
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Specificity (%) 92 94
Precision (%) 80 84
Accuracy (%) 94 95

Table 2: Performance classification for normal and
abnormal cases in MESSIDOR database

Parameters PCA
DD
Nave Bayes
classifier
Overall
Accuracy (%)
92 95
Normal
Accuracy (%)
89.83 94.91
Moderate
Accuracy (%)
94.73 94.73
Severe
Accuracy (%)
95.45 95.45
V. CONCLUSION
In this paper, we examine towards the development of
an existing automated methods for the detection and
severity classification of diabetic retinopathy. Diabetic
retinopathy is the new cause of blindness at the age
from 20 to 74. The macular edema disease affects 10
percentages of all patients who had diabetics for 10
years or more. This paper also describes the automatic
assessment technique for the diabetic retinopathy with
new method, which helps the diabetics to diagnosis
the disease at the early stage for the prevention from
vision loss. An aggregate performance of 92%
specificity with 100% sensitivity is observed for PCA
DD. For the Nave Bayes classification 94%
specificity with 100% sensitivity is observed. Then the
accuracy for the detection is 94% and 95% for PCA
DD and Nave Bayes classifier respectively. The
Overall Accuracy for severity classification forPCA
DD is 92% and for Nave Bayes is 95%. The proposed
method reduces the effort of building CAD scheme by
removing the need for annotated abnormal images.
Moreover there is no need for either preprocessing the
original images or postprocessing the results, to
handle the false alarms. Even though the proposed
method is quite complicated but the detection is
accurate. In future, by using this motion pattern
generation and radon transformation we can apply for
the abnormal indicators such as microaneurysms,
hemorrhages, and cotton wool spots for the better
performance.
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ACKNOWLEDGEMENT
We would like to thank the person for providing the
MESSIDOR dataset: Mr.XiweiZHANG, PhD student,
Centre for Mathematical Morphology Mines ParisTech.
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CONGESTION CONTROL AND RATE BASED
SCHEDULING ALGORITHM FOR MULTIHOP
WIRELESS NETWORKS WITH ORDER OPTIMAL PER
FLOW DELAY
S.SHAHANA
1
,
Ms.K.L.NISHA
2
1,2
Department of ECE, Arunachala college of engineering for women,Nagercoil,India


ABSTRACT
Quantifying the end-to-end delay performance in
multihop wireless networks is a well-known
challenging problem. This project uses a window
based flow control and rate based scheduling
algorithm for multihop wireless networks with
fixed-route flows operated under a general
interference model with interference degree. The
proposed algorithm not only achieves a provable
throughput guarantee but also leads to explicit
upper bounds on the end-to-end delay of every
flow. The end-to-end delay and throughput
bounds are in simple and closed forms, and they
explicitly quantify the tradeoff between
throughput and delay of every flow. The proposed
algorithm is fully distributed and requires a low
per-node complexity that does not increase with
the network size. Hence, it can be easily
implemented in practice.

Keywords: multihop wireless networks , rate
based scheduling, throughput, window based flow
control
I.INTRODUCTION
The joint congestion control and scheduling
problem in multihop wireless networks has been
extensively studied in the literature. Often, each user
is associated with a non decreasing and concave
utility function of its rate, and a cross-layer utility
maximization important as well because, practical
congestion control protocols need to set
retransmission timeout values based on the packet
delay, and such parameters could significantly impact
the speed of recovery when packet loss occurs [1-6].
Packet delay is also important for multimedia traffic,
some of which have been carried on congestion-
controlled sessions.There are two major issues on the
delay-performance of the back-pressure algorithm.
First, for long flows, the end-to-end delay may grow
quadratically with the number of hops. Under the
back-pressure algorithm, if a link schedules the long
flow, the queue difference of the long flow must be
larger than the queue length q of the competing short
flow. Therefore, when the joint congestion and
scheduling algorithm converges, the queue length of
the long flow at each hop must be around H
q
,(H-
1)q,..,q and the total end-to-end backlog is of order
O(H
2
) [7-9]. By Littles law, the end-to-end delay
will also be of order O(H
2
). Note that a packet needs
at least H time-slots to reach the destination. Hence,
the optimal order should have been O(H). This
implies that the back-pressure algorithm may have
significantly larger end-to-end delay for long flows.
Second, under the back-pressure algorithm, it is
difficult to control the end-to-end delay of each flow.
The main parameter to tune a joint congestion control
and scheduling algorithm based on the back-pressure
algorithm is the step size in the queue update. A
larger step size may lead to smaller queue length.
However, a smaller step size is needed to ensure that
the joint congestion control and scheduling algorithm
converges to close-to-optimal system throughput.
Although one may use the step sizes to tune the
throughputdelay tradeoff, a change of the step size
on one node will likely affect all flows passing
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through the node. Hence, it is difficult to tune the
throughputdelay tradeoff on a per-flow basis [9-15].

This project provides a new class of joint congestion
control and scheduling algorithms that can achieve
both provable throughput and provable per- flow
delay. Consider flows in a multihop network shown
in fig.1.1operating under a general interference
model with the interference degree , and each flow
is given a fixed route with H
m
hops.

Fig 1. Multihop network
A.COMPONENTS:
Algorithm consists of three main components:
window-based flow control, virtual-rate computation,
and scheduling. The main ideas of the proposed
algorithm, is to improve the end-to-end delay are as
follows. First, by using window-based flow control, it
can tightly control the number of packets inside the
network. Second, by using a rate-based scheduling
algorithm with the computed virtual rate as input to
schedule packets and do not need to wait for the
packets to accumulate before making scheduling
decisions. However, the key difficulty in analyzing
the end-to-end throughput and delay under this
algorithm is that the services at different links are
correlated. Hence, a Markov chain analysis will no
longer provide a closed-form solution. Specifically,
for any ,
m
(0,1) by appropriately choosing the
number of backoff mini-slots for the scheduling
algorithm and the window size of flow m, algorithm
can guarantee that each flow m will achieve a
throughput where the total utility of the virtual rate
allocation vector is no smaller than the total utility of
any rate h,hvector within /, where is the
capacity region. Further-more, the end-to-end
expected delay of flow m can be upper-bounded by
H
m
. Therefore, with a reasonable choice of the
parameters of the algorithm, and this scheme can
utilize a provable fraction of the total system utility
with per- flow expected delay that increases line arly
with the number of hops.
Since a flow- packet requires at least H
m
time-slots to
reach the destination, the order of the per-flow delay
upper bound is optimal with respect to the number of
hops. This proposed algorithm is fully distributed and
can be easily implemented in practice. Furthermore,
the delaythroughput tradeoff of each flow can be
individually controlled [16-18]. This is the first fully
distributed cross-layer control solution that can both
guarantee order-optimal per- flow delay and a
minimum throughput utilization close to1/ of the
system capacity under a general interference
model.Recently, there have been a number of papers
that quantify the delay performance of wireless
networks with or without congestion control. The
authors proposed methods to reduce the delay of the
back-pressure algorithm [19]. The algorithm
proposed by the authors is a shadow back-pressure
algorithm, which maintains a single first-in first-out
(FIFO) queue at each link and uses multiple shadow
queues to schedule the transmissions. This method
decouples the control information from the real
queues and hence reduces the delay. In simulation,
this algorithm seems to achieve linear delay after the
algorithm con-verges. However, at the transient
period, the real queues will still follow the shadow
queues, which leads to a large queue backlog.
B. NETWORKING
A computer network, or simply a network, is a
collection of computers and other hardware
interconnected by communication channels that
allow sharing of resources and information. Where at
least one process in one device is able to send/receive
data to/from at least one process residing in a remote
device, then the two devices are said to be in a
network. Simply, more than one computer
interconnected through a communication medium for
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information interchange is called a computer
network.
Networks may be classified according to a
wide variety of characteristics, such as the medium
used to transport the data, communications
protocol used, scale, topology, benefit, and
organizational scope. Communication protocols
define the rules and data formats for exchanging
information in a computer network, and provide the
basis for network programming. Well-known
communications protocols include Ethernet, a
hardware and link layer standard that is ubiquitous
in local area networks, and the Internet protocol suite,
which defines a set of protocols for internetworking,
i.e. for data communication between multiple
networks, as well as host-to-host data transfer, and
application-specific data transmission formats.
A communication protocol is a set of rules
for exchanging information over a network. It is
typically a protocol stack , which is a "stack" of
protocols. This stack is used between the wireless
router and the home user's personal computer when
the user is surfing the web. Communication protocols
have various properties, such as whether they are
connectionoriented or connectionless, whether they
use circuit mode or packet switching, or whether they
use hierarchical or flat addressing.
C.NETWORK PROGRAMMING
Computernetwork programming involves writing
computer programs that communicate with each
other across a computer network. Different programs
must be written for the client process, which initiates
the communication, and for the server process, which
waits for the communication to be initiated. Both
endpoints of the communication flow are
implemented as network sockets; hence network
programming is basically socket programming.

D.MULTI HOP NETWORKING
Multi-hop or ad hoc, wireless networks use two or
more wireless hops to convey information from a
source to a destination. There are two distinct
applications of multi-hop communication, with
common features, but different applications.
MOBILE AD HOC NETWORKS (MANETS): A
mobile ad hoc network consists of a group of mobile
nodes that communicate without requiring a fixed
wireless infrastructure. In contrast to conventional
cellular systems, there is no master-slave relationship
between nodes such as base station to mobile users in
ad hoc networks. Communication between nodes is
performed by direct connection or through multiple
hop relays. Mobile ad hoc networks have several
practical applications including battlefield
communication, emergency first response, and
public safety systems. Despite extensive research in
networking, many challenges remain in the study of
mobile ad hoc networks including development of
multiple access protocols that exploit advanced
physical layer technologies like MIMO, OFDM, and
interference cancellation, analysis of the fundamental
limits of mobile ad hoc network capacity, practical
characterization of achievable throughputs taking into
account network overheads.Multi-hop cellular
networks: Cellular systems conventionally employ
single hops between mobile units and the base
station. As cellular systems evolve from voice centric
to data centric communication, edge-of-cell
throughput is becoming a significant concern. This
problem is accentuated in systems with higher carrier
frequencies (more path loss) and larger bandwidth
(larger noise power). A promising solution to the
problem of improving coverage and throughput is the
use of relays. Several different relay technologies are
under intensive investigation including fixed relays
(powered infrastructure equipment that is not
connected to the network backbone), mobile relays
(other users opportunistically agree to relay each
others' packets), as well as mobile fixed relays (fixed
relays that are mounted on buses or trains and thus
moving). There has been extensive research on multi-
hop cellular networks the last few years under the
guise of relay networks or cooperative diversity. The
use of relays, though, impacts almost every aspect of
cellular system design and optimization including:
scheduling, handoff, adaptive modulation, ARQ, and
interference management.
II.ALGORITHMS
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A. JOINT CONGESTION CONTROL AND
SCHEDULING ALGORITHM
There are many approaches available in the literature
to solve, and most of them do not consider delay
performance. A typical optimal solution can be
obtained by a duality approach that results into the
back-pressure algorithm and a congestion-control
component at the source node. Furthermore, a
considerable amount of effort has focused on
developing low-complexity and distributed
scheduling algorithms that can replace the centralized
back-pressure algorithm and yet still achieve
provably good throughput performance. Like the
back-pressure algorithm, these low-complexity
scheduling algorithms are usually also queue-length-
based. The drawback of these approaches, however,
is that the end-to-end delay of the resulting queue-
length-based scheduling algorithm is very difficult to
quantify, under certain cases the back-pressure
algorithm can have poor delay performance. This
paper uses a window-based flow control algorithm
and a rate-based scheduling algorithm that are very
different from the back-pressure algorithm. The
solution strategy is to first approximately solve and
compute the decision vector [r
m
]. However, the
decision variables are not directly used as the rates to
inject flow- packets. For this reason, these variables
r
m
are referred as virtual rates. These virtual rates
are the control variables in a new class of rate-based
scheduling algorithms. The actual end-to-end
throughput under this algorithm will be denoted as
R
m
. For each flow, this new joint congestion control
and scheduling algorithm will guarantee both
provable throughput and provably low delay. Also,
they are fully distributed and easy to implement in
real systems.
B.VIRTUAL-RATE COMPUTATION
The equations are solved. Since the true capacity
region is of a complex form, instead of solving
directly, precise the relationship between
optimization problems
0 ,


Note that the eqn is very similar to the standard
convex-optimization problem in wire line network
with linear constraints. Therefore, it is easy to apply
the approaches. Instead of elaborating on all the
possible approaches to solve problem, it is possible to
present one well-known distributed solution.
Specifically, associate a Lagrange multiplier (the dual
variable) to each constraint.
C.virtual-Rate Computation Algorithm:
At each time t:
1) The source node of flow m updates r
m
by equation
r
m
(t)=


2) Each link updates the dual variables by equation
(t+1)=
k
(t) +
k

m
r
m
1
The variables r
m
are virtual rates, and they
are not directly used to inject flow-m packets under
proposed algorithm.The virtual rates used by the real
injection rates due to the following reasons. First,
optimization problems are formulated as if the rates
are immediately passed to all links at the same time.
In reality, a packet must traverse the links in a hop-
by-hop fashion. In order to control the end-to-end
delay, an additional flow-control algorithm is needed
to regulate this hop-by-hop packet flow. Second, the
low-complexity virtual-rate computation algorithm
did not produce the schedule for link transmission.
The scheduling algorithm is needed to compute the
schedule that can support the virtual rate vector [r
m
].
The end-to-end delay of the back-pressure
algorithm is difficult to quantify and may be poor.
Hence, in the sequel, will use very different
scheduling and flow-control components, for which
quantify both the throughput and the end-to-end
delay on a per- flow basis.
D. SCHEDULING ALGORITHM
The scheduling algorithm, which is a
modification of the low-complexity distributed
scheduling algorithm. Each time-slot consists of an
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initial scheduling slot, which is further divided into F
mini-slots. The links that are to be scheduled are
selected in the scheduling slot, and the selected links
transmit their packets in the rest of the time-slot.
RATE-BASEDSCHEDULING ALGORITHM
At each time-slot t:
1) Each link L first computes Power
2) In the scheduling slot, each link then randomly
picks a backoff mini-slot (B)
3) When the backoff timer for a link expires in the
scheduling slot, it begins transmission unless it has
already heard a transmission from one of its
interfering links. If two or more links that interfere
begin transmissions simultaneously, a collision
occurs, and both transmissions fail.
4) When a link begins transmission, it will randomly
choose a passing flow m to serve with probability.
Note that this scheduling algorithm only uses virtual
rates to compute P
L
, which is different from the
queue-length-based algorithm. For simplicity, the
performance analysis will be based on this scheduling
algorithm.
WINDOW-BASED FLOW CONTROL
It is the process of managing the rate of data
transmission between two nodes to prevent a fast
sender from overwhelming a slow receiver. It
provides a mechanism for the receiver to control the
transmission speed, so that the receiving node is not
overwhelmed with data from transmitting node. Flow
control should be distinguished from congestion
control, which is used for controlling the flow of data
when congestion has actually occurred. Flow control
mechanisms can be classified by whether or not the
receiving node sends feedback to the sending
node.Flow control is important because it is possible
for a sending computer to transmit information at a
faster rate than the destination computer can receive
and process it. This can happen if the receiving
computers have a heavy traffic load in comparison to
the sending computer, or if the receiving computer
has less processing power than the sending computer.
F.WINDOW-BASEDFLOW CONTROL
ALGORITHM
It is the congestion control component. For each
flow, maintain a window W
m
at the source node, and
inject new packets to the queue at the source node
when the total number of packets for this flow inside
the network is smaller than the window size. This can
be achieved by letting the destination node send an
acknowledgement (ACK) back to the source node
whenever it receives a packet. There are two
advantages for this approach. First, for each flow,
tightly control the maximum number of packets in
each intermediate node along the route. This will
prevent buffer over flows, which is an important
issue as addressed. Second, each flows tradeoff
between