VLSI Design Flow

The system prototyping methodology is a natural outgrowth of recent developments in

software and hardware facilities intended to make it simple for designers with an idea for
a particular application to turn that idea into a working system based on very large scale
integrated chips. Today VLSI CMS technologies deliver individual integrated circuits
!ICs" and containing millions of gates# sufficient to implement substantial systems$on$a
chip or ma%or subsystems$on$a chip. System$on$chip design may involve the e&pertise
from many fields of electronics such as signal processing# communication# device physics
etc. and so on. It is unreasonable to e&pect the architect of a speech recognition system#
for e&ample# to be an e&pert in device physics as well as in signal processing. The Mead$
Conway methodology for integrated$circuit design makes VLSI technology available to
such an application designers.
The problem encountered designing very large scale integrated circuits are fundamentally
different from the problems encountered in the design of small scale integrated circuits.
The differences re'uire a different methodology of design and the new methodology
re'uires a new set of tools. (t one time design automation was attempted# but the effort
later was shifted to Computer$aided design# it was under$stood that fully automation
without human intervention is a formidable task. So the effort was on to use of computers
with human intervention for obtaining a critical decision is more meaningful approach.
The procedures for design# simulation# verification or test involve C() tools.
( ma%or goal of computer$aided design is to produce correct designs without the need for
checking. This goal of correctness by construction permeates the design methodology
and tools. These tools can be very specific to the design methodology. The mating of the
tools to the design style allows more powerful tools to be constructed and leads to much
greater productivity from the designers.
The structured design methodology of Mead and Conway is an approach to VLSI system
design that attacks the problems of comple& chip designs. The structured design
methodology is similar in concept to structured programming* the design proceeds in a
top$down manner in which the problem is decomposed and refined. The structured
design methodology has two ma%or parts* hierarchy and regularity. +ierarchial
techni'ues have long been used to design comple& systems. +ierarchies are used to
partition designs and common parts of a design can be factored out and specified only
once. ,y introducing regularity into a system# the design problem is reduced in
comple&ity as subunits are replicated many times and connections between units are
simplified.
-egularity means that the hierarchical decomposition of a large system should result in
not only simple# but also similar blocks# as much as possible. ( good e&ample of
regularity is the design of array structures consisting of identical cells . such as a parallel
multiplication array. -egularity can e&ist at all levels of abstraction* If the designer has
a small library of well$defined and well$characteri/ed basic building blocks# a number of
different functions can be constructed by using this principle. -egularity usually reduces
the number of different modules that need to be designed and verified# at all levels of
abstraction.
Design description:
VLSI design style mainly uses three domains of design description# vi/. the behavioral#
the description of the function of the design0 the structural# the description of the form of
the implementation0 and the physical# the description of the physical implementation of
the design. There are many possible representations of a circuit in each description# and
%udicious choice of representations is important in tool design.
( simplified view of design flow is shown in 1ig. 2. -egardless of the actual si/e of the
pro%ect# the basic principles of structured design will improve the prospects of success.
System Specification
1unctional
!(rchitecture" )esign
,ehavioral
-epresentatio
1unctional
Verification
Logic
!3ate$level"
-epresentati
Logic )esign
Logic Verification
Circuit
-epresentatio
Circuit )esign
Circuit Verification
)evice Modeling
4hysical )esign
Layout
-epresentation
Layout Verification
1abrication 5 Testing
1igure* 2
(t the beginning of a design it is important to specify the re'uirements without unduly
restricting the design. The ob%ect is to describe the purpose of the design including all
aspects# such as the functions to the realised# timing constraints# and power dissipation
re'uirements# etc. )escriptions in block level may show either data flow# control flow# or
both. The individual blocks generally correspond to hardware modules.
1unctional design specifies the functional relationships among subunits or registers. In
general# a description of the IC in either the functional or the block diagram domain
consists both of the input$output description# and the way that this behavior is to be
realised in terms of subordinate modules. In turn each of these modules is described both
in terms of input$output behaviors and as an interconnection of other modules. These
hierarchical ideas apply to all the domains. The internal description of a module any be
given in another domain. If a module has no internal description then the design is
incomplete. 6ltimately this hierarchy stops when the internal description is in terms of
mask geometry# which is primitive. +ierarchy and modularity are used in block diagrams
or computer programs. In these domains hierarchy suppresses unnecessary details#
simplifies system design through a 7divide$and$con'uer8 strategy and leads to more
easily understood designs that are more readily debugged and documented.
It can be summari/ed in a way that when we want to design a digital system# we need to
specify the system performance which is called 7system specification8. Then the system
must be broken down into subunits or registers. So we have a functional design which
specifies the functional relationships among subunits or registers. 7(rchitecture8 usually
means the functional design# system specification and often including part of the
subse'uent logic design.
To plan the Architecture of a VLSI chip# it is always easier to conceive the system in a
similar line to Mead 5 Conway approach# which they described as M pro%ect at
C(LT9C+. 1igure : illustrates the block diagram of that system. It consists of basically
;$sub blocks e.g.
2. Manager chip
:. )ata path chip
<. Memory chip
=. Controller chip
>. I? )evices and
;. Clock chip
The data path chip performs mainly the data computations. The se'uence of
computations are mainly controlled either by the controller or by the instructions fetched
from the microcode instructions unit. The main subsystems of the data path unit are
(rithmetic logic 6nit !(L6"# shifter# register arrays# and different type of processing
elements !49s" which perform some definite %obs.
The memory manager chip contains the addresses of the data memory and provides
the link to communicate between the sub blocks. It supports the different data structures.
It takes the decision to push or pop data.
The clock generation block supplies the two clock signals for the chip. (ccording to
the need in some chip a single clock is available# which can generate two clock phases on$
chip.
The controller part is generally having the microprogram counter that stores the
microcode memory address and its structure is very similar controller of computer
system.
The system bus interface sub block provides synchronous? asynchronous communication
with the outer systems.
Microcode
)ata bus
Microcode
9&ternal
flags
Microcode
Microcode
address
Microcode
enables
9&ternal
data
9&ternal
)ata
chip
1lag
Controller
1lags and
enables
)ata chip enables
Interface
Interface
System
bus
,us
enables
enable
9&ternal
hold
Clock
Clock
Clock
+old
Manager
enables
Memory
address
Memory
Manager
address
Manager
microcode
-M
1igure :* ,lock diagram of an M system
The design of VLSI processor may be subdivided in for ma%or sections.
2. +igh level design
:. perative part design
<. Control part design
=. Memory design
>. )esign of miscellaneous parts !interrupt mechanism# clock system#
pads# etc@".
The ne&t step is the Logic design of networks which constitutes subunits or registers.
Ahen a system architecture or logic networks are designed# performance and errors are
checked by C() programs# called as 7logic simulation8. The sub%ect of the logic design
is to decide overall structure of blocks# their interconnection pattern# to specify the
structure of data path and to control se'uences of data path. Logic simulator does the
logic verification considering the propagation delays of interconnection signals and the
element delay. Simulator also checks whether the network contains ha/ards analysis.
Logic design and simulation is a key issue in VLSI C(). The flow of logic design
process is determined by the level at which the design can begin$system level# behavioral
level or functional level. Logic design consists of a series of design steps leading from a
higher level to a circuit description at the logic level.
The three design process i.e behavioral level# structural level and physical level can be
represented as shown in 1igure < and 1igure = shows different possible refinement for the
three main levels of design representations including the different synthesis steps at each
level.
1igure <* 9&amples for the design levels
1igure =* Levels of representation and design
Today# the following design phases of digital circuits have become widely recogni/ed.
1igure > shows the relationship between these design phases.
!2" (rchitecture design
!:" -egister transfer level design
!<" 3ate level design
!=" Cell design
!>" Layout design
!;" Test program design
Simulators are used in every design phase e&cept for the layout design phase# and play
important roles for the evaluation of system performance# the functional verification and
the timing verification.
1igure >* )esign flow for VLSI logic circuits
There are the following four types of logic simulators according to the levels of
abstraction of simulated elements as shown in Table 2.
Simulation
primitive
9&ample Signal
value
SAITC+
3(T9
16BCTIB
-TL
T-(BSIST-
(B) gata
())9- etc.
user coded primitive
C?2# strength
C?2
C?2
C?2# vector
Table 2* Simulation primitive
!2" Switch level simulators
!:" Gate level simulators
!<" Functional level simulators
!=" Register transfer level simulators
!>" Simulators used in the logic design
Logic networks have to be converted into electronic circuits. Ahen designers specify
electronic circuit re'uirements such as speed# power supply voltage# types of logic
operations# and signal level tolerances# it is desirable to have C() programs which
automatically design electronic circuits meeting all re'uirements# and specify parameters
such as dimensions of transistors and magnitudes of currents.
1or this electronic circuit design and simulation# C() programs perform comple&
numerical analysis calculations of nonlinear differential e'uations which characteri/e
electronic circuits. Since we need to finish calculation within a reasonable time limit#
keeping the re'uired accuracy# many advanced numerical analysis techni'ues are used.
The C() programs usually yield the analysis of transient behavior# direct$current
performance# stationary alternating$current performance# temperature# signal distortion#
noise interference# sensitivity and parameter optimi/ation of the electronic circuits.
The layout system is used to convert block?cell placement data into actual locations# and
to construct a routing ma/e containing all spacing rules. The format used for relative cell
placement data is the same for automatic as for manual placements in order to simplify
their interchange. In fact# the output of the automatic placement program can be
modified by hand before input into the chip building step as manual placement data.
The layout for random$logic networks in the most time$consuming stage throughout the
entire se'uence of LSI?VLSI chip design. (fter having finished the layout# designers
usually check by C() programs whether the layout conforms to the layout rules. (s the
integration si/e of LSI?VLSI chips becomes larger# design verification and testing at each
design stage is vitally important# because any errors which sneak in from the previous
design stages are more difficult to find and more e&pensive# since once found# we need to
redo the previous design stages. (s the integration si/e increases# the test time increases
very rapidly# so it is crucial to find a good way to test within as short a time as possible#
though it appears very difficult to find good solutions. Complete test and design
verification with software or hardware !i.e.# computers speciali/ed in testing" is usually
done to find a design mistake.
The last domain in which the design of an IC can e&ist include the mask set# and of
course# the final fabricated chip followed by prototype testing.
In the summary# the following domains of description have been used in the design.
D (rchitectural level !including functional and block diagram"
D Logic and network level.
D 9lectronic circuit level
D Layout * 4lacement 5 -outing
D 4rototype testing