Left

ADC
DRC
tpl
Left
DAC
AGC
´
+
+
+
+
ADC
Signal
Proc.
DAC
Signal
Proc.
Right
ADC
DRC
tpr
Right
DAC
AGC
ADC
Signal
Proc.
DAC
Signal
Proc.
+
+
+
+
CM
CM
Vol. Ctrl
Vol. Ctrl
Gain Adj .
Gain Adj .
0…
+47.5 dB
0.5 dB steps
0…+47.5 dB
0.5 dB
steps
-6...+29dB
1dB steps
-6...+29dB
1dB steps
-6...+29dB
1dB steps
-6...+29dB
1dB steps
SPI / I2C
Control Block
Pin Muxing/ Clock Routing
Secondary
I
2
S IF
Primary
I
2
S Interface
Digital
Mic.
Interrupt
Ctrl
ALDO
DLDO
PLL
Mic
Bias
Ref
SPI_Select
MicBias
Ref
L
D
O
S
e
le
c
t
Supplies
L
D
O
in
HPVdd
D
V
d
d
A
V
d
d
IO
V
d
d
A
V
s
s
D
V
s
s
IO
V
s
s
S
C
L
/
S
S
Z
S
D
A
/
M
O
S
I
M
IS
O
S
C
L
K
M
C
L
K
G
P
I
O
D
O
U
T
D
IN
B
C
L
K
W
C
L
K
HPL
LOL
HPR
LOR
IN1_R
IN2_R
IN3_R
IN3_L
IN2_L
IN1_L
Reset
-30...0 dB
-30...0 dB
Data Interface
-72...0dB
-72...0dB
´
´ ´

––









•™




––


×

LDOIN
HPR
DV
SS
DV
DD
LDO_SELECT
GPIO/MFP5 (32)
SDA/MOSI
MISO/MFP4
SPI_SELECT
IN1_L
IN1_R
IN2_L
IN2_R
I
O
V
S
S
O
V
I
D
D
D
O
U
T
/
M
F
P
2
D
I
N
/
M
F
P
1
W
C
L
K
B
C
L
K
M
C
L
K
(
1
)
L
O
R
L
O
L
I
N
3
_
R
I
N
3
_
L
M
I
C
B
I
A
S
R
E
F
A
V
S
S
RESET
S
C
L
K
/
M
F
P
3
SCL/SSZ
A
V
D
D
HPL
1 8
9
16
17 24
25
32

––

–°°

––

––

––







–°
–°

°

–θ

θ

°
“”



–°

––
°

µ


–––


––

µ

––

°

µ

––

°

µ

µ

µ

µ

µ

––

°

µ


–––



––

–––

––

°

µ


––


––

±

µ
µ

±

µ
µ


WCLK
BCLK
DOUT
DIN
t (WS)
d
t (DO-WS)
d
t (DO-BCLK)
d
t (DI)
S
t (DI)
h
I2S/LJF Timing in Master Mode

––

°

µ

µ

µ
µ
µ

µ
µ
µ

°

µ×

µ≤×

µ

µ–×

µ≤×

µ

×

×

ts
(DI)
th
(DI)
td(DO-BCLK)
td
(DO-WS)
WCLK
BCLK
DOUT
DIN
I2S/LJF/RJF Timing in Master Mode
td
(WS)

––

°

°

WCLK
BCLK
DOUT
DIN
t (WS)
d t (WS)
d
t (DO-BCLK)
d
t (DI)
s
t (DI)
h

WCLK
BCLK
DOUT
DIN
t (BCLK)
H
t (BCLK)
P
t (ws)
h
t (BCLK)
L
t (ws)
s
t (ws)
h
t (DO-BCLK)
d
t (ws)
h
t (DI)
s
t (DI)
h

––

°

––
°

µ

µ

µ

µ

µ

µ

µ

t
td
S
t
a
MSB OUT BIT 6 . . . 1 LSB OUT
t
sck
t
Lead
t
Lag
t
wsck
t
wsck
t
r
t
f
t
v
t
ho
t
dis
MSB IN BIT 6 . . . 1 LSB IN
t
hi
t
su
SSZ
SCLK
MISO
MOSI

––

°

0 20 40 60 80 100
Headphone Output Power - mW
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
T
H
D

-

T
o
t
a
l

H
a
r
m
o
n
i
c

D
i
s
t
o
r
t
i
o
n

-

d
B
CM=0.9 V,
R = 16
L
W
CM=0.9 V,
R = 32
L
W
CM=1.65 V,
R = 16
L
W
CM=1.65 V,
R = 32
L
W
-20 0 20 40 60
Channel Gain - dB
100
90
80
70
60
50
40
30
20
10
0
S
N
R

-

S
i
g
n
a
l
-
t
o
-
N
o
i
s
e

R
a
t
i
o

-

d
B
R = 10 k , Differential
IN
W
R = 20 k , Differential
IN
W
R = 10 k , Single Ended
IN
W
R = 20 k , Single Ended
IN
W
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
0 50 100 150 200
Headphone output Power - mW
T
H
D

-

T
o
t
a
l

H
a
r
m
o
n
i
c

D
i
s
t
o
r
t
i
o
n

-

d
B
Load = 32 BTL W
CM=1.5 V
CM=1.65 V
60
65
70
75
80
85
90
95
100
105
0.75
0.9 1.25 1.5
1.65
Output Common Mode Setting - V
S
N
R

-

S
i
g
n
a
l
-
t
o
-
N
o
i
s
e

R
a
t
i
o

-

d
B
0
10
20
30
40
50
60
70
SNR
OUTPUT POWER

––

0
50
100
150
200
250
300
350
0 10 20 30 40 50
Load - mA
D
r
o
p
o
u
t

V
o
l
t
a
g
e

-

m
V
AV LDO
DD
DV LDO
DD
-20
-15
-10
-5
0
5
10
15
20
0 10 20 30 40 50
Load - mA
C
h
a
n
g
e

I
n

O
u
t
p
u
t

V
o
l
t
a
g
e

-

m
V
AV LDO
DD
DV LDO
DD
2.4
2.45
2.5
2.55
2.6
0 0.5 1 1.5 2 2.5 3
MicBIAS Load - mA
M
i
c
B
I
A
S

V
o
l
t
a
g
e

-

m
V

––

-120
-100
-80
-60
-40
-20
0
0 5000 10000 15000 20000
f - Frequency - Hz
P
o
w
e
r

-

d
B
r
DAC
-140
-120
-100
-80
-60
-40
-20
0
0 5000 10000 15000
20000
f - Frequency - Hz
P
o
w
e
r

-

d
B
F
s
ADC
-140
-120
-100
-80
-60
-40
-20
0
0 5000 10000 15000 20000
f - Frequency - Hz
P
o
w
e
r

-

d
B
r
-120
-100
-80
-60
-40
-20
0
0 5000 10000 15000 20000
f - Frequency - Hz
P
o
w
e
r

-

d
B
r
DAC

––

-140
-120
-100
-80
-60
-40
-20
0
0 5000 10000 15000
20000
f - Frequency - Hz
P
o
w
e
r

-

d
B
r

––

IN1_L
IN1_R
HPL HPR
LOL
LOR
LDOIN
DVDD
IOVDD
1.9...3.6V
MICBIAS
AVDD
LDO_SELECT
10 uF
TLV320AIC3204
0.1uF 1.0uF 10uF
IN2_L
IN2_R
MFP3/SCLK
IN3_R
AVSS DVSS IOVSS
1.1...3.6V
REF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
2. 7k 1k 1k
1k
47uF
1K
4700p
0.1u
1K
4700p
0.1u
0.1u
0.1u
TPA2012
Class D Amp
10 uF 10 uF
1k
47uF
Reset DIN WCLK SCL SDA BCLK DOUT
SPI_Select
MCLK
Headset_Mic
Headset_Spkr_R
Headset_Spkr_L
Headset_Gnd
Earjack
microphone
and headset
speakers
Host Processor

––

––

––

––

-
+
CM
LADC
IN3_R
IN2_R
IN1_R
HPL
CM HP
MAR
LDAC
MAL
IN1L
IN1_L
IN2_L
IN3_L
LOL
MAL
HPR
CM HP
MAR
RDAC
HPL
IN1R
LOR
MAR
RDAC
LDAC
Left ADC Left DAC
Right DAC
IN1_R
IN2_R
IN3_R
IN1_L
IN3_L
IN2_L
Left Channel, Input Options:
Single Ended: IN1_L or IN2_L or IN3_L or IN1_R
Differential: IN2_L and IN2_R or
IN3_L and IN3_R
Right Channel, Input Options:
Single Ended: IN1_R or IN2_R or IN3_R or IN2_L
Differential: IN1_R and IN1_L or
IN3_R and IN3_L
Vol Ctrl 0… -72dB
Headphone
Amplifier
-6dB … + 29 dB
CM LO
Line Out
Amplifier
-6dB … + 29 dB
RDAC
Line Out
Amplifier
-6dB … + 29 dB
LDAC
LADC Left ADC
Mixer Amp
0..-30dB
LDOIN
AVDD
LOR
1,10,6
CM2L
CM1L
CM1R
CM2R
Headphone
Amplifier
-6dB … + 29 dB
Mic PGA
0...47.5 dB
-
+
Mic PGA
0...47.5 dB
N
P
P
N
P
N
N
P
Vol Ctrl 0… -72dB
Mixer Amp
0..-30dB

––

––

––

––

‘’

––

––

––

––

––

––

––

––

‘’

––

––

––

––

––

ΩΩΩ

ΩΩ

Analog
Gain
Analog
In
Input
Selection
ADC
Filtering
Digital
Volume
Control
Digital
Gain
Adjust
0...47.5 dB
Step =0.5 dB
0, -6, -12 dB -12... 20 dB
Step =0.5 dB
0…-0.4 dB
Step=0.1 dB
Frequency
Response/
Gain
Fully
Programmable
Coefficients
Audio
Interface
ADC
PGA

––

ΩΩΩ

––
––
–––
…………………

––



––

––

–––

1
1
23
1
1 0
z D 2
z N N
) z ( H
-
-
-
+
=

––

Decay Time
Target
Level
Input
Signal
Output
Signal
AGC
Gain
Attack
Time

––

––




To Audio
Interface
1
st
Order
IIR
´
AGC
Gain
Compen
Sation
AGC
To Analog PGA
Filter A
From Delta-Sigma
Modulator or
Digital Microphone
From
Digital Vol. Ctrl

1
st
Order
IIR
AGC
Gain
Compen
sation
AGC
Filter A HE
HD HC HB HA
To Audio
Interface
To Analog PGA
From Delta-Sigma
Modulator or
Digital Microphone
From
Digital Vol. Ctrl
´

1
st
Order
IIR
AGC
Gain
Compen
sation
AGC
Filter A
25-Tap FIR
From Delta-Sigma
Modulator or
Digital Microphone
From
Digital Vol. Ctrl
To Analog PGA
To Audio
Interface
´

To Audio
Interface
1
st
Order
IIR
AGC
Gain
Compen
sation
AGC
Filter B
From
Digital Vol. Ctrl
To Audio
Interface
To Analog PGA
From Delta-Sigma
Modulator or
Digital Microphone
´

––

1
st
Order
IIR
AGC
Gain
Compen
sation
AGC
Filter B H
C
H
B
H
A
From Delta-Sigma
Modulator or
Digital Microphone
From
Digital Vol. Ctrl
To Analog PGA
To Audio
Interface
´

1
st
Order
IIR
AGC
Gain
Compen
sation
AGC
Filter B 20-Tap FIR
From Delta-Sigma
Modulator or
Digital Microphone
From
Digital Vol. Ctrl
To Analog PGA
To Audio
Interface
´

1
st
Order
IIR
AGC
Gain
Compen
sation
AGC
Filter C
From Delta-Sigma
Modulator or
Digital Microphone
From
Digital Vol. Ctrl
To Analog PGA
To Audio
Interface
´

––

1
st
Order
IIR
AGC
Gain
Compen
sation
AGC
Filter C HE
HD HC HB HA
From Delta-Sigma
Modulator or
Digital Microphone
From
Digital Vol. Ctrl
To Analog PGA
To Audio
Interface
´

1
st
Order
IIR
AGC
Gain
Compen
sation
AGC
Filter C 25-Tap FIR
From Delta-Sigma
Modulator or
Digital Microphone
From
Digital Vol. Ctrl
To Analog PGA
To Audio
Interface
´

1
1
23
1
1 0
z D 2
z N N
) z ( H
-
-
-
+
=

––

2
2
1
1
23
2
2
1
1 0
z D z D * 2 2
z N z N * 2 N
) z ( H
- -
- -
- -
+ +
=

––

PRB_R12 and PRB_R9 for , 19 M
PRB_R18 and PRB_R15 PRB_R6, PRB_R3, for , 24 M
z Fir ) z ( H
M
0 n
n
n
=
=
=
å
=
-

––

0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
Frequency Normalized w.r.t. F
S
M
a
g
n
i
t
u
d
e

-

d
B
ADC Channel Response for Decimation Filter A
(Red line corresponds to -73 dB)

––


…–




…–




0
-10
-20
-30
-40
-50
-60
-70
-80
-90
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
M
a
g
n
i
t
u
d
e

-

d
B
Frequency Normalized w.r.t. F
S
ADC Channel Response for Decimation Filter A
(Red line corresponds to -44 dB)

––

…±
…–




0
-20
-40
-60
-80
-100
-120
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
M
a
g
n
i
t
u
d
e

-

d
B
Frequency Normalized w.r.t. F
S
ADC Channel Response for Decimation Filter C
(Red line corresponds to -60 dB)

––

…±
…–





LEFT ADC
CIC FILTER
RIGHT ADC
CIC FILTER
Signal
Processing
Blocks
GPIO MISO DIN SCLK
Σ-Δ
Σ-Δ
ADC_MOD_CLK
D
I
G
_
M
I
C
_
I
N

––

LEFT RIGHT LEFT RIGHT LEFT RIGHT
ADC_MOD_CLK
DIG_MIC_IN

) t t ( OUT _ ADC _ RIGHT ) t ( COMP _ PHASE _ ADC _ RIGHT
pr
- =

( )
FS _ ADC * AOSR
k * AOSR * ) 5 : 6 ( Delay ) 0 : 4 ( Delay
t
f
pr
+
=
) t t ( OUT _ ADC _ LEFT ) t ( COMP _ PHASE _ ADC _ LEFT
pl
- =

FS _ ADC * AOSR
) 7 ( Delay
t
pl
=

––

––

––

‘’

––

µµ

––


––

––

––



•–

Interp.
Filter A
BiQuad
C
BiQuad
B
BiQuad
A
to
Modulator
Digital
Volume
Ctrl
from
Interface
´

Interp.
Filter
A,B
DRC HPF
BiQuad
F
BiQuad
E
BiQuad
D
BiQuad
C
BiQuad
B
BiQuad
A
IIR
to
Modulator
Digital
Volume
Ctrl
from
Interface
´

Interp.
Filter
A,B
BiQuad
F
BiQuad
E
BiQuad
D
BiQuad
C
BiQuad
B
BiQuad
A
IIR
to
Modulator
Digital
Volume
Ctrl
from
Interface
´

Interp.
Filter
B,C
IIR
to
Modulator
Digital
Volume
Ctrl
from
Interface
´

Interp.
Filter B
DRC HPF
to
Modulator
Digital
Volume
Ctrl
BiQuad
D
BiQuad
C
BiQuad
B
BiQuad
A
from
Interface
´

––

Interp.
Filter B
BiQuad
D
BiQuad
C
BiQuad
B
BiQuad
A
to
Modulator
Digital
Volume
Ctrl
from
Interface
´

Interp.
Filter C
DRC HPF
IIR
to
Modulator
Digital
Volume
Ctrl
BiQuad
D
BiQuad
C
BiQuad
B
BiQuad
A
from
Interface
´

Interp.
Filter C
BiQuad
D
BiQuad
C
BiQuad
B
BiQuad
A
IIR
to
modulator
Digital
Volume
Ctrl
from
Interface
´

BiQuad
A
L
Interp.
Filter A
BiQuad
A
R
IIR
Left
3D
PGA
+
+
BiQuad
C
R
BiQuad
B
R
IIR
Right
+
+
-
+
-
+
+
from
Left
Channel
Interface
to
Modulator
Digital
Volume
Ctrl
from
Right
Channel
Interface
BiQuad
B
L
BiQuad
C
L
Interp.
Filter A
to
Modulator
Digital
Volume
Ctrl
´
´

––

BiQuad
A
L
Interp.
Filter A
DRC
HPF
BiQuad
F
L
BiQuad
E
L
BiQuad
A
R
IIR
Left
3D
PGA
+
+
Interp.
Filter A
DRC
HPF
BiQuad
F
R
BiQuad
E
R
BiQuad
D
R
BiQuad
C
R
BiQuad
B
R
IIR
Right
+
+
-
+
-
+
+
from
Left
Channel
Interface
to
Modulator
to
Modulator
Digital
Volume
Ctrl
Digital
Volume
Ctrl
from
Right
Channel
Interface
BiQuad
B
L
BiQuad
C
L
BiQuad
D
L
´
´

BiQuad
AL
Interp.
Filter
+
DRC
HPF
BiQuad
F
L
BiQuad
E
L
BiQuad
AR
IIR
left
3D
PGA
+
+
Interp.
Filter
+
DRC
*
Beep
Gen.
HPF
BiQuad
F
R
BiQuad
E
R
BiQuad
D
R
BiQuad
C
R
BiQuad
B
R
IIR
right
+
+
-
+
-
+
+
from
left
channel
interface
to
modulator
to
modulator
Digital
Volume
Ctrl
Digital
Volume
Ctrl
Beep
Volume
Ctrl
from
right
channel
interface
BiQuad
B
L
BiQuad
C
L
BiQuad
D
L
*
´
´

––

1
1
23
1
1 0
z D 2
z N N
) z ( H
-
-
-
+
=

2
2
1
1
23
2
2
1
1 0
z D z D * 2 2
z N z N * 2 N
) z ( H
- -
- -
- -
+ +
=

––

0
-10
-20
-30
-40
-50
-60
-70
-80
-90
1 3 4 5 6 7 2
M
a
g
n
i
t
u
d
e

-

d
B
Frequency Normalized w.r.t. F
S
DAC Channel Response for Interpolation Filter A
(Red line corresponds to -65 dB)

––

…±
…–

0
-10
-20
-30
-40
-50
-60
-70
-80
M
a
g
n
i
t
u
d
e

-

d
B
DAC Channel Response for Interpolation Filter B
(Red line corresponds to -58 dB)
0.5 1 1.5 2 2.5 3 3.5
Frequency Normalized w.r.t. F
S

0
-10
-20
-30
-40
-50
-60
-70
M
a
g
n
i
t
u
d
e

-

d
B
0 0.2 0.4 0.6 0.8 1 1.2 1.4
Frequency Normalized w.r.t. F
S
DAC Channel Response for Interpolation Filter C
(Red line corresponds to -43 dB)

––

…±
…–

HPL
HPR

––

…±
…–


––

HPL
HPR
LEFT
DAC AFIR
HPL
HPR
LEFT_DACP
LEFT_DACM
Rload
Rpop
Cc
Output
Driver
PAD

––

cm
pop load
load
load
V
R R
R
V ´
+
=

––



ΩΩ

µ

µ

µ

––

L = 82 H m
C = 47 F
C
m
C = 1 F m
Rload = 32 W

––

×

ΩΩ

‘’

LOL
LOR
LEFT
DAC AFIR
Output +
LOR
RIGHT_DACP
RIGHT_DACM
LOL
Output -

––

1
1
23
1
1 0
HPF
z D 2
z N N
) z ( H
-
-
-
+
=

1
1
23
1
1 0
LPF
z D 2
z N N
) z ( H
-
-
-
+
=

––

––

––






––

––

––

PLL_CLKIN
MCLK
BCLK
GPIO
DIN/MFP1
MCLK
BCLK
GPIO
÷NDAC
÷MDAC
÷DOSR
PLL
x(RxJ·D)/P
PLL_CLK
CODEC_CLKIN
÷NADC
NDAC = 1,2,....,127,128
NADC = 1,2,....,127,128
DAC_CLK
ADC_CLK
MDAC = 1,2,...,127,128 ÷MADC MADC = 1,2,...,127,128
ADC_MOD_CLK DAC_MOD_CLK
÷AOSR
DOSR = 1,2,...,1023,1024 AOSR = 1,2,...,255,256
DAC_FS ADC_FS
AOSR MADC NADC
CLKIN _ CODEC
FS _ ADC
´ ´
=

MADC NADC
CLKIN _ CODEC
CLK _ MOD _ ADC
´
=

DOSR MDAC NDAC
CLKIN _ CODEC
FS _ DAC
´ ´
=

MDAC NDAC
CLKIN _ CODEC
CLK _ MOD _ DAC
´
=

––

÷N
BCLK
DAC_CLK
ADC_MOD_CLK
DAC_MOD_CLK
ADC_CLK
BDIV_CLKIN
N = 1,2,...,127,128

––

÷M
CLKOUT
CDIV_CLKIN
MCLK BCLK DIN
GPIO MISO DOUT
PLL_CLK
DAC_CLK ADC_CLK
DAC_MOD_CLK ADC_MOD_CLK
M = 1,2,...,127,128

––
’’

P
D . J R CLKIN _ PLL
CLK _ PLL
´ ´
=

MHz 20
P
CLKIN _ PLL
kHz 512 £ £

MHz 20
P
CLKIN _ PLL
MHz 10 £ £

––

≥≥

……


•≠

––

––

BCLK
WCLK
DIN/
DOUT
n-1 n-2 1 0 0 n-1 n-2 1 0
LSB MSB
Left Channel Right Channel
n-3 2 2 n-3
LSB MSB
1/fs

LD(n) LD(n+1)
WORD
CLOCK
BIT
CLOCK
DATA -
1
-
2
-
3
2 1 0 3 -
1
-
2
-
3
2 1 0 3 -
1
-
2
N N N N N N N N N
-
3
RD(n)
LEFT CHANNEL RIGHT CHANNEL
LD(n) = n'th sample of left channel data RD(n) = n'th sample of right channel data
LD(n) LD(n+1)
WORD
CLOCK
BIT
CLOCK
DATA -
1
-
2
-
3
2 1 0 3 -
1
-
2
-
3
2 1 0 3 -
1
-
2
N N N N N N N N N
-
3
RD(n)
LEFT CHANNEL RIGHT CHANNEL
LD(n) = n'th sample of left channel data RD(n) = n'th sample of right channel data

––

LD(n) LD(n+1)
WORD
CLOCK
BIT
CLOCK
DATA 3
N
-
1
N
-
2
N
-
3
2 1 0 3
N
-
1
N
-
2
N
-
3
2 1 0 3
N
-
1
N
-
2
N
-
3
RD(n)
LEFT CHANNEL RIGHT CHANNEL
LD(n) = n'th sample of left channel data RD(n) = n'th sample of right channel data

LD(n) LD(n+1)
WORD
CLOCK
BIT
CLOCK
DATA -
1
-
2
-
3
2 1 0 3 -
1
-
2
-
3
2 1 0 3 -
1
-
2
N N N N N N N N N
-
3
3
RD(n)
LEFT CHANNEL RIGHT CHANNEL
LD(n) = n'th sample of left channel data RD(n) = n'th sample of right channel data
LD(n) LD(n+1)
WORD
CLOCK
BIT
CLOCK
DATA
-
1
4 3 2 5 1 0 -
1
4 3 2 5 1 0
N N N
-
1
5
RD(n)
LEFT CHANNEL RIGHT CHANNEL
LD(n) = n'th sample of left channel data RD(n) = n'th sample of right channel data

––

LD(n) LD(n+1)
WORD
CLOCK
BIT
CLOCK
DATA -
1
-
2
-
3
2 1 0 3 -
1
-
2
-
3
2 1 0 3 -
1
-
2
N N N N N N N N N
-
3
3
RD(n)
LEFT CHANNEL RIGHT CHANNEL
LD(n) = n'th sample of left channel data RD(n) = n'th sample of right channel data

LD(n) LD(n+1)
BIT
CLOCK
DATA -
1
-
2
-
3
2 1 0 3 -
1
-
2
-
3
0 3 2 1 -
1
-
2
N N N N N N N N N
-
3
3
RD(n)
WORD
CLOCK
LEFT CHANNEL RIGHT CHANNEL
LD(n) = n'th sample of left channel data RD(n) = n'th sample of right channel data
LD(n) LD(n+1)
BIT
CLOCK
DATA -
1
-
2
-
3
2 1 0 3 -
1
-
2
-
3
0 3 2 1 -
1
-
2
N N N N N N N N N
-
3
RD(n)
WORD
CLOCK
LEFT CHANNEL RIGHT CHANNEL
LD(n) = n'th sample of left channel data RD(n) = n'th sample of right channel data

––

LD(n) LD(n+1)
BIT
CLOCK
DATA
N
-
1
N
-
2
N
-
3
2 1 0 3
N
-
1
N
-
2
N
-
3
0 3 2 1
N
-
1
N
-
2
N
-
3
3
RD(n)
WORD
CLOCK
LEFT CHANNEL RIGHT CHANNEL

––

BCLK
WCLK
DOUT
DOUT_int
S_DIN
BCLK
DIN
WCLK
DIN
DOUT
Primary
Audio
Processor
S_WCLK
DAC_FS
ADC_FS
S_BCLK
BCLK_OUT
BCLK
S_BCLK
WCLK
S_WCLK
DIN
S_DIN
WCLK
ADC_WCLK
Audio
Digital
Serial
Interface
BCLK_INT
DAC_WCLK_INT
ADC_WCLK_INT
DIN_INT
GPIO
SCLK
MISO
S_BCLK
DOUT
BCLK
BCLK_OUT
GPIO
SCLK
MISO
S_WCLK
DOUT
WCLK
DAC_FS
ADC_FS
GPIO
SCLK
S_DIN
DOUT_int
DIN
MISO
(S_DOUT)
Clock
Generation
BCLK_OUT
DAC_FS
ADC_FS WCLK
DIN
DOUT
Secondary
Audio
Processor
BCLK
GPIO
SCLK
MISO
ADC_FS
ADC_WCLK
BCLK2
WCLK2

––

––

DA(6) DA(0) RA(7) RA(0) D(7) D(0)
Start
(M)
7-bit Device Address
(M)
Write
(M)
Slave
Ack
(S)
8-bit Register Address
(M)
Slave
Ack
(S)
8-bit Register Data
(M)
Stop
(M)
Slave
Ack
(S)
SDA
SCL
(M) => SDA Controlled by Master
(S) => SDA Controlled by Slave
Start
(M)
7-bit Device Address
(M)
Write
(M)
Slave
Ack
(S)
8-bit Register Address
(M)
Slave
Ack
(S)
SDA
SCL
7-bit Device Address
(M)
Read
(M)
Slave
Ack
(S)
DA(6) DA(0) RA(7) RA(0) DA(6) DA(0) D(7) D(0)
8-bit Register Data
(S)
Stop
(M)
Master
No Ack
(M)
Repeat
Start
(M)
(M) => SDA Controlled by Master
(S) => SDA Controlled by Slave

––

SSZ
SCLK
MOSI
MISO
A6 A5 A0 D7 D6 D1 D0
SSZ
SCLK
MOSI
MISO
A6 A5 A0 D7 D6 D1 D0
D7 D6 D1 D0

––

––

µ
µ

µ

µ

µ

––

µ

µ




µ

µ

µ
µ

s
g
s
m
1 3
Micbias
m
s
g
s
MICBIAS
HPR
HPL
SCLK
Micpga

––

––

µ







––

“”

“”

µ

––

“”

“”

––

––

––

––

“”

––





––

––


––

––

––

––


––

––

––

––

––


––




––



––

––

––

––

––

––

––

––



––


––

––


––

––

––

––

––

––

––

––

––

––

––

––


––

––

––

––

––


––


––

––


––

––


––

––

PACKAGING INFORMATION
Orderable Device Status
(1)
Package
Type
Package
Drawing
Pins Package
Qty
Eco Plan
(2)
Lead/Ball Finish MSL Peak Temp
(3)
TLV320A3204IRHBRG4 ACTIVE QFN RHB 32 3000 Green (RoHS &
no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
TLV320AIC3204IRHBR ACTIVE QFN RHB 32 3000 Green (RoHS &
no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
TLV320AIC3204IRHBT ACTIVE QFN RHB 32 250 Green (RoHS &
no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 26-Jan-2009
Addendum-Page 1
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type
Package
Drawing
Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0 (mm) B0 (mm) K0 (mm) P1
(mm)
W
(mm)
Pin1
Quadrant
TLV320AIC3204IRHBR QFN RHB 32 3000 330.0 12.4 5.3 5.3 1.5 8.0 12.0 Q2
TLV320AIC3204IRHBT QFN RHB 32 250 180.0 12.4 5.3 5.3 1.5 8.0 12.0 Q2
PACKAGE MATERIALS INFORMATION
www.ti.com 5-Feb-2009
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TLV320AIC3204IRHBR QFN RHB 32 3000 346.0 346.0 29.0
TLV320AIC3204IRHBT QFN RHB 32 250 190.5 212.7 31.8
PACKAGE MATERIALS INFORMATION
www.ti.com 5-Feb-2009
Pack Materials-Page 2
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