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SEMESTER I, 2012/2013 SESSION

KULLIYYAH OF ENGINEERING

Programme : ENGINEERING Level of Study : UG 2

Time : 9:00 am- 12:00 pm Date : 28-12-2012

Duration : 3 Hrs

Course Code : ECE 2111 Section(s) : 1

Course Title : Digital Logic Design

This question paper consists of five (5) printed pages (including cover page) with six (6)

questions.

INSTRUCTION(S) TO CANDIDATES

DO NOT OPEN UNTIL YOU ARE ASKED TO DO SO

Total mark of this examination is 100.

This examination is worth 50% of the total assessment.

Answer all questions in Section (1). Answer only (1) question in Section (2).

Any form of cheating or attempt to cheat is a serious

offence which may lead to dismissal.

Digital Logic Design ECE 2111

2

Section One (answer ALL questions)

Q.1 [20 marks]

(a) Answer the following: (6 marks)

i. What is meant by Synthesis and what are its steps?

ii. Under which library does std_logic package exist? Explain why it is

recommended use std_logic instead of bit.

(b) What is the Binary equivalent of the Gray number (11110010)? Attach an odd

parity for the Binary number. (4 marks)

(c) Find the equivalent Binary number for the Decimal number 83.1875. Show all the

steps. (5 marks)

(d) Using Boolean algebra, reduce the following terms: (5 marks)

i. F = ( (A . B C + (A/ . C + B)/ C)/

ii. F = ((A( B. C)) ( A+ B/) + ( A/. B/))/

Q.2 [20 marks]

(a) Describe the internal architecture of a ROM that stores 1024 X 4 and uses a

square register array. (6 marks)

(b) Draw the circuit shown in fig. 2(b) using ONLY NOR gates.

(6 marks)

fig. 2(b)

(c) Find the canonical sum and product for the following logic function: (4 marks)

F

(A,B,C)

=

A,B,C

(1,2,4)

(d) Using K-map, find a minimal sum of products expression for the following

logic function, indicate the distinguished 1-cells: (4 marks)

F

(A,B,C,D)

A,B,C,D

(0,1,2,7,8,9,10,15)

Digital Logic Design ECE 2111

3

Q.3 [20 marks]

(a) A decoder takes a valid BCD input code to be displayed on a common anode 7-

segment HEX display as shown in Fig. 3(a). The 4-bit input codes are A

0

, A

1

, A

2

and A

3

with A

0

as the least significant bit. In order to ensure that the 7-segment

only display the correct decimal values, an enable signal, E, will be connected to

the Vcc input of the 7-segment HEX display. Design the enable circuit which will

give a LOW at signal E for invalid BCD input code and HIGH if otherwise. In

other words the 7-segment HEX display will not light up for invalid BCD input

code. (7 marks)

Fig. 3(a)

(b) There are three students A, B and C all tied in a chain form as shown in Fig. 3(b).

Student A is tied to student B while student B is tied to student C. The length of

the two ropes is the same. The three students are required to climb over a tall

vertical wallon their own with student C to lead the climb. There is ONLY one

rope suspended over the wall to assist the three students as shown in Fig. 3(b).

This means that at any level of the vertical wall, there could only be one student.

Let the input is 1 when a student is climbing while 0 otherwise. Design the

circuit that will give HIGH when the sequence of the students climbing the wall is

valid. Make use of the dont care conditions to simplify your design. Draw your

circuit using ONLY NAND gates. (8 marks)

Fig. 3(b)

Signal E

Digital Logic Design ECE 2111

4

(c) In computer systems it is often necessary to choose data from exactly one of a

number of sources. Design a circuit that has an output (F) that is exactly the same

as one of two data inputs (X,Y) based on the value of a control input (s):

(5 marks)

If S=0 then F=X

If S=1 then F=Y

The function f is really a function of three variables (S,X,Y)

Describe the function in a three variable truth table

Q.4 [20 marks]

(a) Derive the characteristic equation of the T flip flop and draw its state diagram.

(6 marks)

(b) Analyze the clocked synchronous state machine shown in Fig. 4(b). Write the

excitation equations, excitation/transition table, the state/output table and state

diagram (use state names A-D for Q

A

Q

B

= 00 11). (14 marks)

Fig. 4(b)

Digital Logic Design ECE 2111

5

Section Two (answer ONLY one question)

Q.5 [20 marks]

(a) Construct MOD 32 synchronous counter. (6 marks)

(b) Construct the state output table equivalent to the state diagram shown in fig. 5 (b).

(8 marks)

Fig. 5 (b)

(c) Using diagram, discuss the limitations of asynchronous counter. (6 marks)

Q.6 [20 marks]

(a) Consider MOD-16 Asynchronous down counter: (6 marks)

i. Construct the state transition diagram for this counter.

ii. If the counter is initially in the 0110 state, what state will it be in after 37

clock pulses?

(b) Construct the state output table equivalent to the state diagram shown in fig. 6 (b).

(8 marks)

Fig. 6 (b)

(c) Construct MOD 32 up/down counter. (6 marks)

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