Professional Documents
Culture Documents
Data Sheet
High Performance, Enhanced FLASH
Microcontrollers with 10-Bit A/D
Advance Information
DS39564A
Note the following details of the code protection feature on PICmicro MCUs.
The PICmicro family meets the specifications contained in the Microchip Data Sheet.
Microchip believes that its family of PICmicro microcontrollers is one of the most secure products of its kind on the market today,
when used in the intended manner and under normal conditions.
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the PICmicro microcontroller in a manner outside the operating specifications contained in the data sheet.
The person doing so may be engaged in theft of intellectual property.
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as unbreakable.
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of
our product.
If you have any further questions about this matter, please contact the local sales office nearest to you.
Trademarks
The Microchip name and logo, the Microchip logo, PIC, PICmicro,
PICMASTER, PICSTART, PRO MATE, KEELOQ, SEEVAL,
MPLAB and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
Total Endurance, ICSP, In-Circuit Serial Programming, FilterLab, MXDEV, microID, FlexROM, fuzzyLAB, MPASM,
MPLINK, MPLIB, PICC, PICDEM, PICDEM.net, ICEPIC,
Migratable Memory, FanSense, ECONOMONITOR, Select
Mode and microPort are trademarks of Microchip Technology
Incorporated in the U.S.A.
Serialized Quick Term Programming (SQTP) is a service mark
of Microchip Technology Incorporated in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
2001, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
DS39564A - page ii
Advance Information
PIC18FXX2
28/40-pin High Performance, Enhanced FLASH
Microcontrollers with 10-Bit A/D
High Performance RISC CPU:
On-Chip Program
Memory
Device
FLASH
(bytes)
On-Chip
Data
RAM EEPROM
# Single Word (bytes)
(bytes)
Instructions
PIC18F242
16K
8192
768
256
PIC18F252
32K
16384
1536
256
PIC18F442
16K
8192
768
256
PIC18F452
32K
16384
1536
256
Up to 10 MIPs operation:
- DC - 40 MHz osc./clock input
- 4 MHz - 10 MHz osc./clock input with PLL active
16-bit wide instructions, 8-bit wide data path
Priority levels for interrupts
8 x 8 Single Cycle Hardware Multiplier
Peripheral Features:
High current sink/source 25 mA/25 mA
Three external interrupt pins
Timer0 module: 8-bit/16-bit timer/counter with
8-bit programmable prescaler
Timer1 module: 16-bit timer/counter
Timer2 module: 8-bit timer/counter with 8-bit
period register (time-base for PWM)
Timer3 module: 16-bit timer/counter
Secondary oscillator clock option - Timer1/Timer3
Two Capture/Compare/PWM (CCP) modules.
CCP pins that can be configured as:
- Capture input: capture is 16-bit,
max. resolution 6.25 ns (TCY/16)
- Compare is 16-bit, max. resolution 100 ns (TCY)
- PWM output: PWM resolution is 1- to 10-bit,
Max. PWM freq. @: 8-bit resolution = 156 kHz
10-bit resolution = 39 kHz
Analog Features:
Compatible 10-bit Analog-to-Digital Converter
module (A/D) with:
- Fast sampling rate
- Conversion available during SLEEP
- DNL = 1 LSb, INL = 1 LSb
Programmable Low Voltage Detection (PLVD)
- Supports interrupt on-Low Voltage Detection
Programmable Brown-out Reset (BOR)
CMOS Technology:
Low power, high speed FLASH/EEPROM
technology
Fully static design
Wide operating voltage range (2.0V to 5.5V)
Industrial and Extended temperature ranges
Advance Information
DS39564A-page 1
PIC18FXX2
RA3/AN3/VREF+
RA2/AN2/VREFRA1/AN1
RA0/AN0
MCLR/VPP
NC
RB7/PGD
RB6/PGC
RB5/PGM
RB4
NC
Pin Diagrams
6
5
4
3
2
1
44
43
42
41
40
PLCC
RA4/T0CKI
RA5/AN4/SS/LVDIN
RE0/RD/AN5
RE1/WR/AN6
RE2/CS/AN7
VDD
VSS
OSC1/CLKI
OSC2/CLKO/RA6
RC0/T1OSO/T1CKI
NC
PIC18F442
PIC18F452
28
27
26
25
24
23
22
21
20
19
8
7
8
9
10
11
12
13
14
15
16
171
39
38
37
36
35
34
33
32
31
30
29
RB3/CCP2*
RB2/INT2
RB1/INT1
RB0/INT0
VDD
VSS
RD7/PSP7
RD6/PSP6
RD5/PSP5
RD4/PSP4
RC7/RX/DT
RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
RD3/PSP3
RD2/PSP2
RD1/PSP1
RD0/PSP0
RC3/SCK/SCL
RC2/CCP1
RC1/T1OSI/CCP2*
NC
NC
RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
RD3/PSP3
RD2/PSP2
RD1/PSP1
RD0/PSP0
RC3/SCK/SCL
RC2/CCP1
RC1/T1OSI/CCP2*
44
43
42
41
40
39
38
37
36
35
34
TQFP
1
2
3
4
5
6
7
8
9
10
11
PIC18F452
NC
RC0/T1OSO/T1CKI
OSC2/CLKO/RA6
OSC1/CLKI
VSS
VDD
RE2/AN7/CS
RE1/AN6/WR
RE0/AN5/RD
RA5/AN4/SS/LVDIN
RA4/T0CKI
RA3/AN3/VREF+
RA2/AN2/VREFRA1/AN1
RA0/AN0
MCLR/VPP
RB7/PGD
RB6/PGC
RB5/PGM
RB4
NC
NC
DS39564A-page 2
PIC18F442
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
RC7/RX/DT
RD4/PSP4
RD5/PSP5
RD6/PSP6
RD7/PSP7
VSS
VDD
RB0/INT0
RB1/INT1
RB2/INT2
RB3/CCP2*
Advance Information
PIC18FXX2
Pin Diagrams (Cont.d)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
PIC18F452
MCLR/VPP
RA0/AN0
RA1/AN1
RA2/AN2/VREFRA3/AN3/VREF+
RA4/T0CKI
RA5/AN4/SS/LVDIN
RE0/RD/AN5
RE1/WR/AN6
RE2/CS/AN7
VDD
VSS
OSC1/CLKI
OSC2/CLKO/RA6
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2*
RC2/CCP1
RC3/SCK/SCL
RD0/PSP0
RD1/PSP1
PIC18F442
DIP
RB7/PGD
RB6/PGC
RB5/PGM
RB4
RB3/CCP2*
RB2/INT2
RB1/INT1
RB0/INT0
VDD
VSS
RD7/PSP7
RD6/PSP6
RD5/PSP5
RD4/PSP4
RC7/RX/DT
RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
RD3/PSP3
RD2/PSP2
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
1
2
3
4
5
6
7
8
9
10
11
12
13
14
PIC18F252
MCLR/VPP
RA0/AN0
RA1/AN1
RA2/AN2/VREFRA3/AN3/VREF+
RA4/T0CKI
RA5/AN4/SS/LVDIN
VSS
OSC1/CLKI
OSC2/CLKO/RA6
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2*
RC2/CCP1
RC3/SCK/SCL
PIC18F242
DIP, SOIC
28
27
26
25
24
23
22
21
20
19
18
17
16
15
RB7/PGD
RB6/PGC
RB5/PGM
RB4
RB3/CCP2*
RB2/INT2
RB1/INT1
RB0/INT0
VDD
VSS
RC7/RX/DT
RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
Advance Information
DS39564A-page 3
PIC18FXX2
Table of Contents
1.0 Device Overview .......................................................................................................................................................................... 7
2.0 Oscillator Configurations ............................................................................................................................................................ 17
3.0 Reset .......................................................................................................................................................................................... 25
4.0 Memory Organization ................................................................................................................................................................. 35
5.0 FLASH Program Memory ........................................................................................................................................................... 55
6.0 Data EEPROM Memory ............................................................................................................................................................. 65
7.0 8 X 8 Hardware Multiplier ........................................................................................................................................................... 69
8.0 Interrupts .................................................................................................................................................................................... 71
9.0 I/O Ports ..................................................................................................................................................................................... 85
10.0 Timer0 Module ......................................................................................................................................................................... 101
11.0 Timer1 Module ......................................................................................................................................................................... 105
12.0 Timer2 Module ......................................................................................................................................................................... 109
13.0 Timer3 Module ......................................................................................................................................................................... 111
14.0 Capture/Compare/PWM (CCP) Modules ................................................................................................................................. 115
15.0 Master Synchronous Serial Port (MSSP) Module .................................................................................................................... 123
16.0 Addressable Universal Synchronous Asynchronous Receiver Transmitter (USART).............................................................. 163
17.0 Compatible 10-bit Analog-to-Digital Converter (A/D) Module................................................................................................... 179
18.0 Low Voltage Detect .................................................................................................................................................................. 187
19.0 Special Features of the CPU .................................................................................................................................................... 193
20.0 Instruction Set Summary .......................................................................................................................................................... 209
21.0 Development Support............................................................................................................................................................... 251
22.0 Electrical Characteristics .......................................................................................................................................................... 257
23.0 DC and AC Characteristics Graphs and Tables ....................................................................................................................... 287
24.0 Packaging Information.............................................................................................................................................................. 289
Appendix A: Revision History............................................................................................................................................................. 297
Appendix B: Device Differences......................................................................................................................................................... 297
Appendix C: Conversion Considerations ........................................................................................................................................... 298
Appendix D: Migration from Baseline to Enhanced Devices.............................................................................................................. 298
Appendix E: Migration from Mid-Range to Enhanced Devices .......................................................................................................... 299
Appendix F: Migration from High-End to Enhanced Devices ............................................................................................................. 299
Index .................................................................................................................................................................................................. 301
On-Line Support................................................................................................................................................................................. 311
Reader Response .............................................................................................................................................................................. 312
PIC18FXX2 Product Identification System......................................................................................................................................... 313
DS39564A-page 4
Advance Information
PIC18FXX2
TO OUR VALUED CUSTOMERS
It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and
enhanced as new volumes and updates are introduced.
If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via
E-mail at docerrors@mail.microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150.
We welcome your feedback.
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision
of silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
Microchips Worldwide Web site; http://www.microchip.com
Your local Microchip sales office (see last page)
The Microchip Corporate Literature Center; U.S. FAX: (480) 792-7277
When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include literature number) you are using.
Advance Information
DS39564A-page 5
PIC18FXX2
NOTES:
DS39564A-page 6
Advance Information
PIC18FXX2
1.0
DEVICE OVERVIEW
PIC18F242
PIC18F252
PIC18F442
PIC18F452
TABLE 1-1:
DEVICE FEATURES
Features
Operating Frequency
PIC18F242
PIC18F252
PIC18F442
PIC18F452
DC - 40 MHz
DC - 40 MHz
DC - 40 MHz
DC - 40 MHz
16K
32K
16K
32K
8192
16384
8192
16384
768
1536
768
1536
256
256
256
256
Interrupt Sources
17
17
18
18
Ports A, B, C
Ports A, B, C
I/O Ports
Timers
Capture/Compare/PWM Modules
Serial Communications
Parallel Communications
10-bit Analog-to-Digital Module
Ports A, B, C, D, E Ports A, B, C, D, E
4
MSSP,
Addressable
USART
MSSP,
Addressable
USART
MSSP,
Addressable
USART
MSSP,
Addressable
USART
PSP
PSP
5 input channels
5 input channels
8 input channels
8 input channels
POR, BOR,
RESET Instruction,
Stack Full,
Stack Underflow
(PWRT, OST)
POR, BOR,
RESET Instruction,
Stack Full,
Stack Underflow
(PWRT, OST)
Yes
Yes
POR, BOR,
POR, BOR,
RESET Instruction, RESET Instruction,
Stack Full,
Stack Full,
Stack Underflow
Stack Underflow
(PWRT, OST)
(PWRT, OST)
Yes
Yes
Yes
Yes
Yes
Yes
75 Instructions
75 Instructions
75 Instructions
75 Instructions
28-pin DIP
28-pin SOIC
28-pin DIP
28-pin SOIC
40-pin DIP
44-pin PLCC
44-pin TQFP
40-pin DIP
44-pin PLCC
44-pin TQFP
Advance Information
DS39564A-page 7
PIC18FXX2
FIGURE 1-1:
21
8
21
PORTA
Data Latch
RA0/AN0
RA1/AN1
RA2/AN2/VREFRA3/AN3/VREF+
RA4/T0CKI
RA5/AN4/SS/LVDIN
RA6
Data RAM
inc/dec logic
21
Address Latch
20
Address Latch
Program Memory
(up to 2 Mbytes)
PCLATU PCLATH
Data Latch
12
Address<12>
12
4
BSR
31 Level Stack
16
(2)
Decode
Table Latch
4
Bank0, F
FSR0
FSR1
FSR2
12
inc/dec
logic
PORTB
8
ROM Latch
RB0/INT0
RB1/INT1
RB2/INT2
RB3/CCP2(1)
RB4
RB5/PGM
RB6/PCG
RB7/PGD
Instruction
Register
Instruction
Decode &
Control
OSC2/CLKO
OSC1/CLKI
Timing
Generation
T1OSCI
T1OSCO
PRODH PRODL
3
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
4X PLL
Precision
Voltage
Reference
MCLR
8
BIT OP
WREG
8
8
Watchdog
Timer
ALU<8>
Brown-out
Reset
PORTC
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2(1)
RC2/CCP1
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
RC6/TX/CK
RC7/RX/DT
Low Voltage
Programming
In-Circuit
Debugger
VDD, VSS
Timer0
Timer1
CCP1
Note
8 x 8 Multiply
CCP2
Timer2
Master
Synchronous
Serial Port
Timer3
Addressable
USART
A/D Converter
Data EEPROM
1: Optional multiplexing of CCP2 input/output with RB3 is enabled by selection of configuration bit.
2: The high order bits of the Direct Address for the RAM are from the BSR register (except for the MOVFF instruction).
3: Many of the general purpose I/O pins are multiplexed with one or more peripheral module functions. The multiplexing combinations
are device dependent.
DS39564A-page 8
Advance Information
PIC18FXX2
FIGURE 1-2:
8
21
Data RAM
(up to 4K
address reach)
inc/dec logic
21
Address Latch
RA0/AN0
RA1/AN1
RA2/AN2/VREFRA3/AN3/VREF+
RA4/T0CKI
RA5/AN4/SS/LVDIN
RA6
Data Latch
Address Latch
20
Program Memory
(up to 2 Mbytes)
(2)
PCLATU PCLATH
Data Latch
12
Address<12>
PORTB
12
4
BSR
31 Level Stack
16
Decode
Table Latch
RB0/INT0
RB1/INT1
RB2/INT2
RB3/CCP2(1)
RB4
RB5/PGM
RB6/PCG
RB7/PGD
Bank0, F
FSR0
FSR1
FSR2
12
inc/dec
logic
8
PORTC
ROM Latch
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2(1)
RC2/CCP1
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
RC6/TX/CK
RC7/RX/DT
Instruction
Register
Instruction
Decode &
Control
OSC2/CLKO
OSC1/CLKI
Timing
Generation
T1OSCI
T1OSCO
PRODH PRODL
3
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
4X PLL
Precision
Voltage
Reference
MCLR
Watchdog
Timer
8 x 8 Multiply
8
BIT OP
8
WREG
8
PORTD
RD0/PSP0
RD1/PSP1
RD2/PSP2
RD3/PSP3
RD4/PSP4
RD5/PSP5
RD6/PSP6
RD7/PSP7
8
ALU<8>
Brown-out
Reset
8
PORTE
Low Voltage
Programming
RE0/AN5/RD
In-Circuit
Debugger
VDD, VSS
RE1/AN6/WR
RE2/AN7/CS
Timer0
CCP1
Note
Timer1
CCP2
Timer2
Master
Synchronous
Serial Port
A/D Converter
Timer3
Addressable
USART
Data EEPROM
1: Optional multiplexing of CCP2 input/output with RB3 is enabled by selection of configuration bit.
2: The high order bits of the Direct Address for the RAM are from the BSR register (except for the MOVFF instruction).
3: Many of the general purpose I/O pins are multiplexed with one or more peripheral module functions. The multiplexing combinations
are device dependent.
Advance Information
DS39564A-page 9
PIC18FXX2
TABLE 1-2:
Pin Name
DIP
MCLR/VPP
MCLR
Pin
SOIC Type
Buffer
Type
1
I
ST
ST
CMOS
CLKO
RA6
I/O
TTL
VPP
NC
OSC1/CLKI
OSC1
CLKI
OSC2/CLKO/RA6
OSC2
10
10
RA0/AN0
2
2
RA0
I/O
TTL
AN0
I
Analog
RA1/AN1
3
3
RA1
I/O
TTL
AN1
I
Analog
4
4
RA2/AN2/VREFI/O
TTL
RA2
I
Analog
AN2
I
Analog
VREFRA3/AN3/VREF+
5
5
I/O
RA3
TTL
I
AN3
Analog
I
VREF+
Analog
RA4/T0CKI
6
6
RA4
I/O
ST/OD
T0CKI
I
ST
7
7
RA5/AN4/SS/LVDIN
I/O
TTL
RA5
AN4
I
Analog
I
ST
SS
LVDIN
I
Analog
RA6
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
O = Output
OD = Open Drain (no P diode to VDD)
DS39564A-page 10
Description
Master Clear (input) or programming voltage (input).
Master Clear (Reset) input. This pin is an active low
RESET to the device.
Programming voltage input.
These pins should be left unconnected.
Oscillator crystal or external clock input.
Oscillator crystal input or external clock source input.
ST buffer when configured in RC mode, CMOS otherwise.
External clock source input. Always associated with
pin function OSC1. (See related OSC1/CLKIN,
OSC2/CLKOUT pins.)
Oscillator crystal or clock output.
Oscillator crystal output. Connects to crystal or
resonator in Crystal Oscillator mode.
In RC mode, OSC2 pin outputs CLKOUT which has 1/4
the frequency of OSC1, and denotes the instruction
cycle rate.
General Purpose I/O pin.
PORTA is a bi-directional I/O port.
Digital I/O.
Analog input 0.
Digital I/O.
Analog input 1.
Digital I/O.
Analog input 2.
A/D Reference Voltage (Low) input.
Digital I/O.
Analog input 3.
A/D Reference Voltage (High) input.
Digital I/O. Open drain when configured as output.
Timer0 external clock input.
Digital I/O.
Analog input 4.
SPI Slave Select input.
Low Voltage Detect Input.
See the OSC2/CLKO/RA6 pin.
CMOS = CMOS compatible input or output
I = Input
P = Power
Advance Information
PIC18FXX2
TABLE 1-2:
Pin Name
DIP
Pin
Type
SOIC
Buffer
Type
Description
PORTB is a bi-directional I/O port. PORTB can be software
programmed for internal weak pull-ups on all inputs.
RB0/INT0
RB0
INT0
RB1/INT1
RB1
INT1
RB2/INT2
RB2
INT2
RB3/CCP2
RB3
CCP2
RB4
21
21
I/O
I
24
25
TTL
ST
External Interrupt 1.
I/O
I
23
Digital I/O.
External Interrupt 0.
I/O
I
22
TTL
ST
TTL
ST
Digital I/O.
External Interrupt 2.
I/O
I/O
I/O
TTL
ST
TTL
Digital I/O.
Capture2 input, Compare2 output, PWM2 output.
Digital I/O.
Interrupt-on-change pin.
22
23
24
25
RB5/PGM
26
26
RB5
I/O
TTL
PGM
I/O
ST
RB6/PGC
27
27
RB6
I/O
TTL
PGC
I/O
ST
RB7/PGD
28
28
RB7
I/O
TTL
PGD
I/O
ST
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
O = Output
OD = Open Drain (no P diode to VDD)
Advance Information
DS39564A-page 11
PIC18FXX2
TABLE 1-2:
Pin Name
DIP
Pin
Type
SOIC
Buffer
Type
Description
DS39564A-page 12
Advance Information
PIC18FXX2
TABLE 1-3:
Pin Name
DIP
MCLR/VPP
MCLR
Pin
Type
PLCC TQFP
Buffer
Type
18
I
ST
ST
CMOS
CLKO
RA6
I/O
TTL
VPP
NC
OSC1/CLKI
OSC1
13
14
14
15
31
RA0/AN0
2
3
19
RA0
I/O
TTL
AN0
I
Analog
RA1/AN1
3
4
20
RA1
I/O
TTL
AN1
I
Analog
4
5
21
RA2/AN2/VREFI/O
RA2
TTL
I
AN2
Analog
I
VREFAnalog
5
6
22
RA3/AN3/VREF+
I/O
TTL
RA3
I
Analog
AN3
I
Analog
VREF+
RA4/T0CKI
6
7
23
RA4
I/O
ST/OD
T0CKI
I
ST
7
8
24
RA5/AN4/SS/LVDIN
RA5
I/O
TTL
AN4
I
Analog
SS
I
ST
LVDIN
I
Analog
RA6
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
O = Output
OD = Open Drain (no P diode to VDD)
30
CLKI
OSC2/CLKO/RA6
OSC2
Description
Advance Information
DS39564A-page 13
PIC18FXX2
TABLE 1-3:
Pin Name
DIP
Pin
Type
PLCC TQFP
Buffer
Type
Description
PORTB is a bi-directional I/O port. PORTB can be
software programmed for internal weak pull-ups on all
inputs.
RB0/INT0
RB0
INT0
RB1/INT1
RB1
INT1
RB2/INT2
RB2
INT2
RB3/CCP2
RB3
CCP2
RB4
RB5/PGM
RB5
PGM
RB6/PGC
RB6
PGC
RB7/PGD
RB7
PGD
33
36
8
I/O
I
39
40
41
42
43
44
TTL
ST
Digital I/O.
External Interrupt 2.
I/O
I/O
I/O
TTL
ST
TTL
Digital I/O.
Capture2 input, Compare2 output, PWM2 output.
Digital I/O. Interrupt-on-change pin.
TTL
ST
I/O
I/O
37
38
39
External Interrupt 1.
I/O
I/O
36
38
TTL
ST
I/O
I
35
37
Digital I/O.
External Interrupt 0.
I/O
I
34
TTL
ST
TTL
ST
I/O
I/O
TTL
ST
10
11
14
15
16
17
DS39564A-page 14
Advance Information
PIC18FXX2
TABLE 1-3:
Pin Name
DIP
Pin
Type
PLCC TQFP
Buffer
Type
Description
PORTC is a bi-directional I/O port.
RC0/T1OSO/T1CKI
RC0
T1OSO
T1CKI
RC1/T1OSI/CCP2
RC1
T1OSI
CCP2
RC2/CCP1
RC2
CCP1
RC3/SCK/SCL
RC3
SCK
15
16
32
I/O
O
I
I/O
I
I/O
17
18
SCL
18
19
20
ST
CMOS
ST
Digital I/O.
Timer1 oscillator input.
Capture2 input, Compare2 output, PWM2 output.
I/O
I/O
16
ST
ST
ST
ST
Digital I/O.
Capture1 input/Compare1 output/PWM1 output.
I/O
I/O
ST
ST
I/O
ST
Digital I/O.
Synchronous serial clock input/output for
SPI mode.
Synchronous serial clock input/output for
I2C mode.
35
36
37
RC4/SDI/SDA
23
25
42
RC4
I/O
SDI
I
SDA
I/O
RC5/SDO
24
26
43
RC5
I/O
SDO
O
RC6/TX/CK
25
27
44
RC6
I/O
TX
O
CK
I/O
RC7/RX/DT
26
29
1
I/O
RC7
RX
I
DT
I/O
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
O = Output
OD = Open Drain (no P diode to VDD)
Digital I/O.
Timer1 oscillator output.
Timer1/Timer3 external clock input.
ST
ST
ST
Digital I/O.
SPI Data In.
I2C Data I/O.
ST
Digital I/O.
SPI Data Out.
ST
ST
Digital I/O.
USART Asynchronous Transmit.
USART Synchronous Clock (see related RX/DT).
ST
ST
ST
Digital I/O.
USART Asynchronous Receive.
USART Synchronous Data (see related TX/CK).
CMOS = CMOS compatible input or output
I = Input
P = Power
Advance Information
DS39564A-page 15
PIC18FXX2
TABLE 1-3:
Pin Name
DIP
Pin
Type
PLCC TQFP
RD0/PSP0
19
21
38
I/O
RD1/PSP1
20
22
39
I/O
RD2/PSP2
21
23
40
I/O
RD3/PSP3
22
24
41
I/O
RD4/PSP4
27
30
I/O
RD5/PSP5
28
31
I/O
RD6/PSP6
29
32
I/O
RD7/PSP7
30
33
I/O
RE0/RD/AN5
RE0
RD
25
Buffer
Type
ST
TTL
ST
TTL
ST
TTL
ST
TTL
ST
TTL
ST
TTL
ST
TTL
ST
TTL
Description
PORTD is a bi-directional I/O port, or a Parallel Slave
Port (PSP) for interfacing to a microprocessor port.
These pins have TTL input buffers when PSP module
is enabled.
Digital I/O.
Parallel Slave Port Data.
Digital I/O.
Parallel Slave Port Data.
Digital I/O.
Parallel Slave Port Data.
Digital I/O.
Parallel Slave Port Data.
Digital I/O.
Parallel Slave Port Data.
Digital I/O.
Parallel Slave Port Data.
Digital I/O.
Parallel Slave Port Data.
Digital I/O.
Parallel Slave Port Data.
PORTE is a bi-directional I/O port.
I/O
ST
TTL
AN5
RE1/WR/AN6
RE1
WR
Analog
9
AN6
RE2/CS/AN7
RE2
CS
10
10
26
I/O
ST
TTL
Analog
11
27
Digital I/O.
Write control for parallel slave port
(see CS and RD pins).
Analog input 6.
I/O
ST
TTL
AN7
Analog
Vss
12, 31 13, 34 6, 29 P
Vdd
11, 32 12, 35 7, 28 P
DS39564A-page 16
Digital I/O.
Read control for parallel slave port
(see also WR and CS pins).
Analog input 5.
Digital I/O.
Chip Select control for parallel slave port
(see related RD and WR).
Analog input 7.
Ground reference for logic and I/O pins.
Positive supply for logic and I/O pins.
CMOS = CMOS compatible input or output
I = Input
P = Power
Advance Information
PIC18FXX2
2.0
OSCILLATOR
CONFIGURATIONS
2.1
Oscillator Types
TABLE 2-1:
Ranges Tested:
LP
XT
HS
HS + PLL
5.
6.
RC
RCIO
7.
8.
EC
ECIO
2.2
Crystal Oscillator/Ceramic
Resonators
Use of a series cut crystal may give a frequency out of the crystal manufacturers
specifications.
FIGURE 2-1:
C1(1)
CRYSTAL/CERAMIC
RESONATOR OPERATION
(HS, XT OR LP
CONFIGURATION)
Mode
Freq
C1
C2
XT
455 kHz
68 - 100 pF 68 - 100 pF
2.0 MHz
15 - 68 pF
15 - 68 pF
4.0 MHz
15 - 68 pF
15 - 68 pF
HS
8.0 MHz
10 - 68 pF
10 - 68 pF
16.0 MHz
10 - 22 pF
10 - 22 pF
These values are for design guidance only.
See notes following this table.
Resonators Used:
455 kHz Panasonic EFO-A455K04B
0.3%
2.0 MHz Murata Erie CSA2.00MG
0.5%
4.0 MHz Murata Erie CSA4.00MG
0.5%
8.0 MHz Murata Erie CSA8.00MT
0.5%
16.0 MHz Murata Erie CSA16.00MX
0.5%
All resonators used did not have built-in capacitors.
OSC1
XTAL
RS(2)
C2(1)
OSC2
RF(3)
To
Internal
Logic
SLEEP
PIC18FXXX
Note 1: See Table 2-1 and Table 2-2 for recommended values of C1 and C2.
2: A series resistor (RS) may be required for AT
strip cut crystals.
3: RF varies with the oscillator mode chosen.
Advance Information
DS39564A-page 17
PIC18FXX2
TABLE 2-2:
FIGURE 2-2:
Ranges Tested:
Mode
Freq
LP
32.0 kHz
33 pF
33 pF
200 kHz
15 pF
15 pF
XT
C1
C2
200 kHz
47-68 pF
15 pF
15 pF
4.0 MHz
15 pF
15 pF
4.0 MHz
15 pF
15 pF
8.0 MHz
15-33 pF
15-33 pF
20.0
MHz
15-33 pF
15-33 pF
25.0
MHz
HS
PIC18FXXX
OSC2
Open
47-68 pF
1.0 MHz
OSC1
Clock from
Ext. System
TBD
TBD
Epson C-001R32.768K-A
20 PPM
200 kHz
20 PPM
1.0 MHz
ECS ECS-10-13-1
50 PPM
4.0 MHz
ECS ECS-40-20-1
50 PPM
8.0 MHz
30 PPM
20.0 MHz
2.3
RC Oscillator
FIGURE 2-3:
Note 1: Higher capacitance increases the stability
of the oscillator, but also increases the
start-up time.
2: Rs may be required in HS mode, as well
as XT mode, to avoid overdriving crystals
with low drive level specification.
3: Since each resonator/crystal has its own
characteristics, the user should consult
the resonator/crystal manufacturer for
appropriate values of external components., or verify oscillator performance.
RC OSCILLATOR MODE
VDD
REXT
Internal
Clock
OSC1
CEXT
PIC18FXXX
VSS
FOSC/4
OSC2/CLKO
DS39564A-page 18
Advance Information
PIC18FXX2
2.4
FIGURE 2-5:
2.5
HS/PLL
The PLL can only be enabled when the oscillator configuration bits are programmed for HS mode. If they are
programmed for any other mode, the PLL is not
enabled and the system clock will come directly from
OSC1.
OSC2
FIGURE 2-6:
I/O (OSC2)
A Phase Locked Loop circuit is provided as a programmable option for users that want to multiply the frequency of the incoming crystal oscillator signal by 4.
For an input clock frequency of 10 MHz, the internal
clock frequency will be multiplied to 40 MHz. This is
useful for customers who are concerned with EMI due
to high frequency crystals.
PIC18FXXX
FOSC/4
PIC18FXXX
RA6
OSC1
Clock from
Ext. System
OSC1
Clock from
Ext. System
FIGURE 2-4:
The PLL is one of the modes of the FOSC<2:0> configuration bits. The oscillator mode is specified during
device programming.
A PLL lock timer is used to ensure that the PLL has
locked before device execution starts. The PLL lock
timer has a time-out that is called TPLL.
Loop
Filter
Crystal
Osc
VCO
FOUT
OSC1
Divide by 4
Advance Information
MUX
OSC2
SYSCLK
DS39564A-page 19
PIC18FXX2
2.6
FIGURE 2-7:
Tosc/4
Timer1 Oscillator
T1OSO
MUX
TOSC
OSC1
T1OSI
4 x PLL
TSCLK
TT1P
T1OSCEN
Enable
Oscillator
Clock
Source
Clock Source option
for other modules
DS39564A-page 20
Advance Information
PIC18FXX2
2.6.1
REGISTER 2-1:
OSCCON REGISTER
U-0
bit 7
U-0
U-0
bit 7-1
U-0
U-0
U-0
R/W-1
SCS
bit 0
bit 0
U-0
W = Writable bit
1 = Bit is set
0 = Bit is cleared
Advance Information
x = Bit is unknown
DS39564A-page 21
PIC18FXX2
2.6.2
OSCILLATOR TRANSITIONS
FIGURE 2-8:
Q1 Q2
Q3 Q4
Q1
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
TT1P
1
T1OSI
Tscs
OSC1
TOSC
Internal
System
Clock
SCS
(OSCCON<0>)
Program
Counter
TDLY
PC
PC + 2
PC + 4
Note 1: Delay on internal system clock is eight oscillator cycles for synchronization.
The sequence of events that takes place when switching from the Timer1 oscillator to the main oscillator will
depend on the mode of the main oscillator. In addition
to eight clock cycles of the main oscillator, additional
delays may take place.
FIGURE 2-9:
If the main oscillator is configured for an external crystal (HS, XT, LP), then the transition will take place after
an oscillator start-up time (TOST) has occurred. A timing
diagram, indicating the transition from the Timer1 oscillator to the main oscillator for HS, XT and LP modes, is
shown in Figure 2-9.
TIMING FOR TRANSITION BETWEEN TIMER1 AND OSC1 (HS, XT, LP)
Q3
Q4
Q1
Q1
TT1P
Q2 Q3
Q4
Q1
Q2
Q3
T1OSI
1
OSC1
TOST
TSCS
OSC2
TOSC
Internal System
Clock
SCS
(OSCCON<0>)
Program Counter
PC
PC + 2
PC + 6
DS39564A-page 22
Advance Information
PIC18FXX2
If the main oscillator is configured for HS-PLL mode, an
oscillator start-up time (TOST) plus an additional PLL
time-out (TPLL) will occur. The PLL time-out is typically
2 ms and allows the PLL to lock to the main oscillator
frequency. A timing diagram indicating the transition
from the Timer1 oscillator to the main oscillator for
HS-PLL mode is shown in Figure 2-10.
FIGURE 2-10:
TIMING FOR TRANSITION BETWEEN TIMER1 AND OSC1 (HS WITH PLL)
Q4
Q1 Q2 Q3 Q4
TT1P
Q1
Q1 Q2 Q3 Q4
T1OSI
OSC1
TOST
TPLL
OSC2
TSCS
TOSC
PLL Clock
Input
Internal System
Clock
SCS
(OSCCON<0>)
Program Counter
PC
PC + 2
PC + 4
FIGURE 2-11:
Q4
T1OSI
Q1
Q1 Q2 Q3
TT1P
Q4 Q1 Q2
Q3 Q4
TOSC
OSC1
OSC2
Internal System
Clock
SCS
(OSCCON<0>)
TSCS
Program Counter
PC
PC + 2
PC + 4
Advance Information
DS39564A-page 23
PIC18FXX2
2.7
TABLE 2-3:
OSC Mode
OSC1 Pin
OSC2 Pin
RC
At logic low
RCIO
ECIO
EC
LP, XT, and HS
See Table 3-1, in the Reset section, for time-outs due to SLEEP and MCLR Reset.
2.8
Power-up Delays
DS39564A-page 24
Advance Information
PIC18FXX2
3.0
RESET
FIGURE 3-1:
RESET
Instruction
Stack
Pointer
MCLR
WDT
Module
SLEEP
WDT
Time-out
Reset
VDD Rise
Detect
Power-on Reset
VDD
Brown-out
Reset
BOREN
OST/PWRT
OST
Chip_Reset
OSC1
PWRT
On-chip
RC OSC(1)
Enable PWRT
Enable OST(2)
Note 1: This is a separate oscillator from the RC oscillator of the CLKIN pin.
2: See Table 3-1 for time-out situations.
Advance Information
DS39564A-page 25
PIC18FXX2
3.1
3.3
FIGURE 3-2:
EXTERNAL POWER-ON
RESET CIRCUIT (FOR
SLOW VDD POWER-UP)
R
R1
MCLR
C
PIC18FXXX
3.2
DS39564A-page 26
3.4
3.5
VDD
3.6
Time-out Sequence
Advance Information
PIC18FXX2
TABLE 3-1:
Oscillator
Configuration
Brown-out
Wake-up from
SLEEP or
Oscillator Switch
PWRTE = 0
PWRTE = 1
72 ms + 1024TOSC
+ 2ms
1024TOSC
+ 2 ms
72 ms(2) + 1024TOSC
+ 2 ms
1024TOSC + 2 ms
HS, XT, LP
72 ms + 1024TOSC
1024TOSC
72 ms(2) + 1024TOSC
1024TOSC
EC
72 ms
72 ms(2)
(2)
External RC
72 ms
REGISTER 3-1:
72 ms
U-0
U-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
IPEN
RI
TO
PD
POR
BOR
bit 7
bit 0
TABLE 3-2:
RCON
Register
RI
TO
PD
POR
BOR
STKFUL
STKUNF
Power-on Reset
0000h
0--1 1100
0000h
0--u uuuu
0000h
0--0 uuuu
0000h
0--u uu11
0000h
0--u uu11
0000h
0--u 10uu
WDT Reset
0000h
0--u 01uu
WDT Wake-up
PC + 2
u--u 00uu
Brown-out Reset
0000h
0--1 11u0
u--u 00uu
Condition
PC + 2
(1)
Advance Information
DS39564A-page 27
PIC18FXX2
TABLE 3-3:
Register
Applicable Devices
Power-on Reset,
Brown-out Reset
MCLR Resets
WDT Reset
RESET Instruction
Stack Resets
TOSU
242 442 252 452
---0 0000
---0 0000
---0 uuuu(3)
TOSH
242 442 252 452
0000 0000
0000 0000
uuuu uuuu(3)
TOSL
242 442 252 452
0000 0000
0000 0000
uuuu uuuu(3)
STKPTR
242 442 252 452
00-0 0000
00-0 0000
uu-u uuuu(3)
PCLATU
242 442 252 452
---0 0000
---0 0000
---u uuuu
PCLATH
242 442 252 452
0000 0000
0000 0000
uuuu uuuu
PCL
242 442 252 452
0000 0000
0000 0000
PC + 2(2)
TBLPTRU
242 442 252 452
--00 0000
--00 0000
--uu uuuu
TBLPTRH
242 442 252 452
0000 0000
0000 0000
uuuu uuuu
TBLPTRL
242 442 252 452
0000 0000
0000 0000
uuuu uuuu
TABLAT
242 442 252 452
0000 0000
0000 0000
uuuu uuuu
PRODH
242 442 252 452
xxxx xxxx
uuuu uuuu
uuuu uuuu
PRODL
242 442 252 452
xxxx xxxx
uuuu uuuu
uuuu uuuu
INTCON
242 442 252 452
0000 000x
0000 000u
uuuu uuuu(1)
INTCON2
242 442 252 452
1111 -1-1
1111 -1-1
uuuu -u-u(1)
INTCON3
242 442 252 452
11-0 0-00
11-0 0-00
uu-u u-uu(1)
INDF0
242 442 252 452
N/A
N/A
N/A
POSTINC0 242 442 252 452
N/A
N/A
N/A
POSTDEC0 242 442 252 452
N/A
N/A
N/A
PREINC0
242 442 252 452
N/A
N/A
N/A
PLUSW0
242 442 252 452
N/A
N/A
N/A
FSR0H
242 442 252 452
---- xxxx
---- uuuu
---- uuuu
FSR0L
242 442 252 452
xxxx xxxx
uuuu uuuu
uuuu uuuu
WREG
242 442 252 452
xxxx xxxx
uuuu uuuu
uuuu uuuu
INDF1
242 442 252 452
N/A
N/A
N/A
POSTINC1 242 442 252 452
N/A
N/A
N/A
POSTDEC1 242 442 252 452
N/A
N/A
N/A
PREINC1
242 442 252 452
N/A
N/A
N/A
PLUSW1
242 442 252 452
N/A
N/A
N/A
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as 0, q = value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack.
4: See Table 3-2 for RESET value for specific condition.
5: Bit 6 of PORTA, LATA, and TRISA are enabled in ECIO and RCIO oscillator modes only. In all other
oscillator modes, they are disabled and read 0.
6: Bit 6 of PORTA, LATA and TRISA are not available on all devices. When unimplemented, they are read 0.
DS39564A-page 28
Advance Information
PIC18FXX2
TABLE 3-3:
Register
Applicable Devices
Power-on Reset,
Brown-out Reset
MCLR Resets
WDT Reset
RESET Instruction
Stack Resets
FSR1H
242 442 252 452
---- xxxx
---- uuuu
---- uuuu
FSR1L
242 442 252 452
xxxx xxxx
uuuu uuuu
uuuu uuuu
BSR
242 442 252 452
---- 0000
---- 0000
---- uuuu
INDF2
242 442 252 452
N/A
N/A
N/A
POSTINC2 242 442 252 452
N/A
N/A
N/A
POSTDEC2 242 442 252 452
N/A
N/A
N/A
PREINC2
242 442 252 452
N/A
N/A
N/A
PLUSW2
242 442 252 452
N/A
N/A
N/A
FSR2H
242 442 252 452
---- xxxx
---- uuuu
---- uuuu
FSR2L
242 442 252 452
xxxx xxxx
uuuu uuuu
uuuu uuuu
STATUS
242 442 252 452
---x xxxx
---u uuuu
---u uuuu
TMR0H
242 442 252 452
0000 0000
uuuu uuuu
uuuu uuuu
TMR0L
242 442 252 452
xxxx xxxx
uuuu uuuu
uuuu uuuu
T0CON
242 442 252 452
1111 1111
1111 1111
uuuu uuuu
OSCCON
242 442 252 452
---- ---0
---- ---0
---- ---u
LVDCON
242 442 252 452
--00 0101
--00 0101
--uu uuuu
WDTCON
242 442 252 452
---- ---0
---- ---0
---- ---u
RCON(4)
242 442 252 452
0--q 11qq
0--q qquu
u--u qquu
TMR1H
242 442 252 452
xxxx xxxx
uuuu uuuu
uuuu uuuu
TMR1L
242 442 252 452
xxxx xxxx
uuuu uuuu
uuuu uuuu
T1CON
242 442 252 452
0-00 0000
u-uu uuuu
u-uu uuuu
TMR2
242 442 252 452
0000 0000
0000 0000
uuuu uuuu
PR2
242 442 252 452
1111 1111
1111 1111
1111 1111
T2CON
242 442 252 452
-000 0000
-000 0000
-uuu uuuu
SSPBUF
242 442 252 452
xxxx xxxx
uuuu uuuu
uuuu uuuu
SSPADD
242 442 252 452
0000 0000
0000 0000
uuuu uuuu
SSPSTAT
242 442 252 452
0000 0000
0000 0000
uuuu uuuu
SSPCON1 242 442 252 452
0000 0000
0000 0000
uuuu uuuu
SSPCON2 242 442 252 452
0000 0000
0000 0000
uuuu uuuu
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as 0, q = value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack.
4: See Table 3-2 for RESET value for specific condition.
5: Bit 6 of PORTA, LATA, and TRISA are enabled in ECIO and RCIO oscillator modes only. In all other
oscillator modes, they are disabled and read 0.
6: Bit 6 of PORTA, LATA and TRISA are not available on all devices. When unimplemented, they are read 0.
Advance Information
DS39564A-page 29
PIC18FXX2
TABLE 3-3:
Register
Applicable Devices
Power-on Reset,
Brown-out Reset
MCLR Resets
WDT Reset
RESET Instruction
Stack Resets
ADRESH
242 442 252 452
xxxx xxxx
uuuu uuuu
uuuu uuuu
ADRESL
242 442 252 452
xxxx xxxx
uuuu uuuu
uuuu uuuu
ADCON0
242 442 252 452
0000 00-0
0000 00-0
uuuu uu-u
ADCON1
242 442 252 452
00-- 0000
00-- 0000
uu-- uuuu
CCPR1H
242 442 252 452
xxxx xxxx
uuuu uuuu
uuuu uuuu
CCPR1L
242 442 252 452
xxxx xxxx
uuuu uuuu
uuuu uuuu
CCP1CON 242 442 252 452
--00 0000
--00 0000
--uu uuuu
CCPR2H
242 442 252 452
xxxx xxxx
uuuu uuuu
uuuu uuuu
CCPR2L
242 442 252 452
xxxx xxxx
uuuu uuuu
uuuu uuuu
CCP2CON 242 442 252 452
--00 0000
--00 0000
--uu uuuu
TMR3H
242 442 252 452
xxxx xxxx
uuuu uuuu
uuuu uuuu
TMR3L
242 442 252 452
xxxx xxxx
uuuu uuuu
uuuu uuuu
T3CON
242 442 252 452
0000 0000
uuuu uuuu
uuuu uuuu
SPBRG
242 442 252 452
0000 0000
0000 0000
uuuu uuuu
RCREG
242 442 252 452
0000 0000
0000 0000
uuuu uuuu
TXREG
242 442 252 452
0000 0000
0000 0000
uuuu uuuu
TXSTA
242 442 252 452
0000 -010
0000 -010
uuuu -uuu
RCSTA
242 442 252 452
0000 000x
0000 000x
uuuu uuuu
EEADR
242 442 252 452
0000 0000
0000 0000
uuuu uuuu
EEDATA
242 442 252 452
0000 0000
0000 0000
uuuu uuuu
EECON1
242 442 252 452
xx-0 x000
uu-0 u000
uu-0 u000
EECON2
242 442 252 452
---- ------- ------- ---Legend: u = unchanged, x = unknown, - = unimplemented bit, read as 0, q = value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack.
4: See Table 3-2 for RESET value for specific condition.
5: Bit 6 of PORTA, LATA, and TRISA are enabled in ECIO and RCIO oscillator modes only. In all other
oscillator modes, they are disabled and read 0.
6: Bit 6 of PORTA, LATA and TRISA are not available on all devices. When unimplemented, they are read 0.
DS39564A-page 30
Advance Information
PIC18FXX2
TABLE 3-3:
Register
Applicable Devices
Power-on Reset,
Brown-out Reset
MCLR Resets
WDT Reset
RESET Instruction
Stack Resets
IPR2
PIR2
PIE2
Advance Information
DS39564A-page 31
PIC18FXX2
FIGURE 3-3:
INTERNAL POR
TPWRT
PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
FIGURE 3-4:
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
FIGURE 3-5:
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
DS39564A-page 32
Advance Information
PIC18FXX2
FIGURE 3-6:
1V
0V
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
FIGURE 3-7:
VDD
MCLR
IINTERNAL POR
TPWRT
PWRT TIME-OUT
TOST
TPLL
OST TIME-OUT
PLL TIME-OUT
INTERNAL RESET
Note:
Advance Information
DS39564A-page 33
PIC18FXX2
NOTES:
DS39564A-page 34
Advance Information
PIC18FXX2
4.0
MEMORY ORGANIZATION
4.1
Advance Information
DS39564A-page 35
PIC18FXX2
FIGURE 4-1:
PC<20:0>
21
CALL,RCALL,RETURN
RETFIE,RETLW
Stack Level 1
FIGURE 4-2:
PC<20:0>
21
CALL,RCALL,RETURN
RETFIE,RETLW
Stack Level 1
Stack Level 31
Stack Level 31
RESET Vector
0000h
RESET Vector
0000h
On-chip
Program Memory
Read 0
On-chip
Program Memory
7FFFh
8000h
3FFFh
4000h
Read 0
1FFFFFh
200000h
DS39564A-page 36
Advance Information
1FFFFFh
200000h
PIC18FXX2
4.2
4.2.2
4.2.1
TOP-OF-STACK ACCESS
Advance Information
DS39564A-page 37
PIC18FXX2
REGISTER 4-1:
STKPTR REGISTER
R/C-0
R/C-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
STKFUL
STKUNF
SP4
SP3
SP2
SP1
SP0
bit 7
bit 0
bit 7(1)
bit 6(1)
bit 5
bit 4-0
- n = Value at POR
FIGURE 4-3:
W = Writable bit
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
TOSH
0x1A
Top of Stack
4.2.3
STKPTR<4:0>
00010
TOSL
0x34
00011
0x001A34 00010
0x000D58 00001
00000
4.2.4
The ability to pull the TOS value off of the stack and
replace it with the value that was previously pushed
onto the stack, without disturbing normal execution, is
achieved by using the POP instruction. The POP instruction discards the current TOS by decrementing the
stack pointer. The previous value pushed onto the
stack then becomes the TOS value.
DS39564A-page 38
Advance Information
PIC18FXX2
4.3
4.4
If high priority interrupts are not disabled during low priority interrupts, users must save the key registers in
software during a low priority interrupt.
The contents of PCLATH and PCLATU will be transferred to the program counter by an operation that
writes PCL. Similarly, the upper two bytes of the program counter will be transferred to PCLATH and
PCLATU by an operation that reads PCL. This is useful
for computed offsets to the PC (see Section 4.8.1).
EXAMPLE 4-1:
CALL SUB1, FAST
4.5
SUB1
FIGURE 4-4:
Clocking Scheme/Instruction
Cycle
RETURN FAST
CLOCK/INSTRUCTION CYCLE
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
OSC1
Q1
Q2
Internal
Phase
Clock
Q3
Q4
PC
OSC2/CLKOUT
(RC mode)
PC
PC+2
Advance Information
PC+4
DS39564A-page 39
PIC18FXX2
4.6
Instruction Flow/Pipelining
EXAMPLE 4-2:
TCY1
Fetch 1
1. MOVLW 55h
Execute 1
Fetch 2
2. MOVWF PORTB
3. BRA
4. BSF
TCY2
TCY4
TCY5
Execute 2
Fetch 3
SUB_1
TCY3
Execute 3
Fetch 4
Flush (NOP)
Fetch SUB_1 Execute SUB_1
All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction
is flushed from the pipeline while the new instruction is being fetched and then executed.
4.7
The program memory is addressed in bytes. Instructions are stored as two bytes or four bytes in program
memory. The Least Significant Byte of an instruction
word is always stored in a program memory location
with an even address (LSB =0). Figure 4-5 shows an
example of how instruction words are stored in the program memory. To maintain alignment with instruction
boundaries, the PC increments in steps of 2 and the
LSB will always read 0 (see Section 4.4).
The CALL and GOTO instructions have an absolute program memory address embedded into the instruction.
Since instructions are always stored on word bound-
FIGURE 4-5:
LSB = 0
0Fh
EFh
F0h
C1h
F4h
55h
03h
00h
23h
56h
Program Memory
Byte Locations
Instruction 1:
Instruction 2:
MOVLW
GOTO
055h
000006h
Instruction 3:
MOVFF
123h, 456h
DS39564A-page 40
Advance Information
Word Address
000000h
000002h
000004h
000006h
000008h
00000Ah
00000Ch
00000Eh
000010h
000012h
000014h
PIC18FXX2
4.7.1
TWO-WORD INSTRUCTIONS
The PIC18FXX2 devices have four two-word instructions: MOVFF, CALL, GOTO and LFSR. The second
word of these instructions has the 4 MSBs set to 1s
and is a special kind of NOP instruction. The lower 12
bits of the second word contain data to be used by the
instruction. If the first word of the instruction is executed, the data in the second word is accessed. If the
EXAMPLE 4-3:
TWO-WORD INSTRUCTIONS
CASE 1:
Object Code
0110 0110
1100 0001
1111 0100
0010 0100
0000
0011
0110
0000
Source Code
TSTFSZ
REG1
; is RAM location 0?
MOVFF
REG1, REG2 ; No, execute 2-word instruction
; 2nd operand holds address of REG2
ADDWF
REG3
; continue code
0000
0011
0110
0000
Source Code
TSTFSZ
REG1
; is RAM location 0?
MOVFF
REG1, REG2 ; Yes
; 2nd operand becomes NOP
ADDWF
REG3
; continue code
CASE 2:
Object Code
0110 0110
1100 0001
1111 0100
0010 0100
4.8
0000
0010
0101
0000
0000
0010
0101
0000
Lookup Tables
4.8.2
4.8.1
COMPUTED GOTO
Advance Information
DS39564A-page 41
PIC18FXX2
4.9
4.9.1
The register file can be accessed either directly or indirectly. Indirect addressing operates using a File Select
Register and corresponding Indirect File Operand. The
operation of indirect addressing is shown in
Section 4.12.
Enhanced MCU devices may have banked memory in
the GPR area. GPRs are not initialized by a Power-on
Reset and are unchanged on all other RESETS.
Data RAM is available for use as GPR registers by all
instructions. The top half of Bank 15 (0xF80 to 0xFFF)
contains SFRs. All other banks of data memory contain
GPR registers, starting with Bank 0.
4.9.2
DS39564A-page 42
Advance Information
PIC18FXX2
FIGURE 4-6:
BSR<3:0>
= 0000
= 0001
Access RAM
FFh
00h
GPR
Bank 0
000h
07Fh
080h
0FFh
100h
GPR
Bank 1
1FFh
200h
FFh
GPR
2FFh
300h
Access Bank
Access RAM low
= 0010
= 1110
Bank 2
to
Bank 14
Unused
FFh
= 1111
7Fh
Access RAM high 80h
(SFRs)
FFh
Unused
Read 00h
00h
SFR
Bank 15
00h
EFFh
F00h
F7Fh
F80h
FFFh
When a = 0,
the BSR is ignored and the
Access Bank is used.
The first 128 bytes are General
Purpose RAM (from Bank 0).
The second 128 bytes are
Special Function Registers
(from Bank 15).
When a = 1,
the BSR is used to specify the
RAM location that the instruction uses.
Advance Information
DS39564A-page 43
PIC18FXX2
FIGURE 4-7:
BSR<3:0>
= 0000
= 0001
= 0010
= 0011
Access RAM
FFh
00h
GPR
Bank 0
GPR
Bank 1
FFh
00h
Bank 2
1FFh
200h
GPR
2FFh
300h
FFh
00h
Bank 3
GPR
FFh
= 0100
= 0101
Bank 4
3FFh
400h
GPR
= 1110
00h
GPR
Bank 5
Bank 6
to
Bank 14
5FFh
600h
Unused
Read 00h
00h
Unused
FFh
= 1111
Access Bank
4FFh
500h
FFh
= 0110
000h
07Fh
080h
0FFh
100h
SFR
Bank 15
EFFh
F00h
F7Fh
F80h
FFFh
00h
7Fh
Access RAM high 80h
(SFRs)
FFh
When a = 0,
the BSR is ignored and the
Access Bank is used.
The first 128 bytes are General
Purpose RAM (from Bank 0).
The second 128 bytes are
Special Function Registers
(from Bank 15).
When a = 1,
the BSR is used to specify the
RAM location that the instruction uses.
DS39564A-page 44
Advance Information
PIC18FXX2
TABLE 4-1:
Address
Address
Name
Address
(3)
Name
Address
Name
FFFh
TOSU
FDFh
FBFh
CCPR1H
F9Fh
IPR1
FFEh
TOSH
FDEh
POSTINC2(3)
FBEh
CCPR1L
F9Eh
PIR1
FBDh
CCP1CON
F9Dh
PIE1
FBCh
CCPR2H
F9Ch
INDF2
FFDh
TOSL
FDDh
POSTDEC2(3)
FFCh
STKPTR
FDCh
PREINC2(3)
(3)
FFBh
PCLATU
FDBh
PLUSW2
FBBh
CCPR2L
F9Bh
FFAh
PCLATH
FDAh
FSR2H
FBAh
CCP2CON
F9Ah
FF9h
PCL
FD9h
FSR2L
FB9h
F99h
FF8h
TBLPTRU
FD8h
STATUS
FB8h
F98h
FF7h
TBLPTRH
FD7h
TMR0H
FB7h
F97h
FF6h
TBLPTRL
FD6h
TMR0L
FB6h
F96h
TRISE(2)
FF5h
TABLAT
FD5h
T0CON
FB5h
F95h
TRISD(2)
FF4h
PRODH
FD4h
FB4h
F94h
TRISC
FF3h
PRODL
FD3h
OSCCON
FB3h
TMR3H
F93h
TRISB
FF2h
INTCON
FD2h
LVDCON
FB2h
TMR3L
F92h
TRISA
FF1h
INTCON2
FD1h
WDTCON
FB1h
T3CON
F91h
FF0h
INTCON3
FD0h
RCON
FB0h
F90h
(3)
FCFh
TMR1H
FAFh
SPBRG
F8Fh
FEEh
POSTINC0(3)
FCEh
TMR1L
FAEh
RCREG
F8Eh
FEDh
(3)
FCDh
T1CON
FADh
TXREG
F8Dh
LATE(2)
FCCh
TMR2
FACh
TXSTA
F8Ch
LATD(2)
FEFh
INDF0
POSTDEC0
FECh
PREINC0(3)
FEBh
PLUSW0(3)
FCBh
PR2
FABh
RCSTA
F8Bh
LATC
FEAh
FSR0H
FCAh
T2CON
FAAh
F8Ah
LATB
FE9h
FSR0L
FC9h
SSPBUF
FA9h
EEADR
F89h
LATA
FE8h
WREG
FC8h
SSPADD
FA8h
EEDATA
F88h
(3)
FC7h
SSPSTAT
FA7h
EECON2
F87h
FE6h
POSTINC1(3)
FC6h
SSPCON1
FA6h
EECON1
F86h
FE5h
POSTDEC1(3)
FC5h
SSPCON2
FA5h
F85h
FE4h
PREINC1(3)
FC4h
ADRESH
FA4h
F84h
PORTE(2)
FE3h
PLUSW1(3)
FC3h
ADRESL
FA3h
F83h
PORTD(2)
FE2h
FSR1H
FC2h
ADCON0
FA2h
IPR2
F82h
PORTC
FE1h
FSR1L
FC1h
ADCON1
FA1h
PIR2
F81h
PORTB
FE0h
BSR
FC0h
FA0h
PIE2
F80h
PORTA
FE7h
INDF1
Advance Information
DS39564A-page 45
PIC18FXX2
TABLE 4-2:
File Name
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Details
on page:
---0 0000
37
TOSH
0000 0000
37
TOSL
0000 0000
37
TOSU
Value on
POR,
BOR
STKPTR
STKFUL
STKUNF
00-0 0000
38
PCLATU
---0 0000
39
PCLATH
0000 0000
39
PCL
0000 0000
39
--00 0000
58
TBLPTRU
bit21(2)
TBLPTRH
0000 0000
58
TBLPTRL
0000 0000
58
TABLAT
0000 0000
58
PRODH
xxxx xxxx
69
PRODL
xxxx xxxx
69
INTCON
GIE/GIEH
PEIE/GIEL
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
0000 000x
73
INTCON2
RBPU
INTEDG0
INTEDG1
INTEDG2
TMR0IP
RBIP
1111 -1-1
74
INTCON3
INT2IP
INT1IP
INT2IE
INT1IE
INT2IF
INT1IF
11-0 0-00
75
INDF0
Uses contents of FSR0 to address data memory - value of FSR0 not changed (not a physical register)
n/a
50
POSTINC0
Uses contents of FSR0 to address data memory - value of FSR0 post-incremented (not a physical register)
n/a
50
POSTDEC0
Uses contents of FSR0 to address data memory - value of FSR0 post-decremented (not a physical register)
n/a
50
PREINC0
Uses contents of FSR0 to address data memory - value of FSR0 pre-incremented (not a physical register)
n/a
50
PLUSW0
Uses contents of FSR0 to address data memory - value of FSR0 pre-incremented (not a physical register) value of FSR0 offset by value in WREG
n/a
50
---- xxxx
50
FSR0H
FSR0L
xxxx xxxx
50
WREG
Working Register
xxxx xxxx
n/a
INDF1
Uses contents of FSR1 to address data memory - value of FSR1 not changed (not a physical register)
n/a
50
POSTINC1
Uses contents of FSR1 to address data memory - value of FSR1 post-incremented (not a physical register)
n/a
50
POSTDEC1
Uses contents of FSR1 to address data memory - value of FSR1 post-decremented (not a physical register)
n/a
50
PREINC1
Uses contents of FSR1 to address data memory - value of FSR1 pre-incremented (not a physical register)
n/a
50
PLUSW1
Uses contents of FSR1 to address data memory - value of FSR1 pre-incremented (not a physical register) value of FSR1 offset by value in WREG
n/a
50
---- xxxx
50
xxxx xxxx
50
---- 0000
49
FSR1H
FSR1L
BSR
INDF2
Uses contents of FSR2 to address data memory - value of FSR2 not changed (not a physical register)
n/a
50
POSTINC2
Uses contents of FSR2 to address data memory - value of FSR2 post-incremented (not a physical register)
n/a
50
POSTDEC2
Uses contents of FSR2 to address data memory - value of FSR2 post-decremented (not a physical register)
n/a
50
PREINC2
Uses contents of FSR2 to address data memory - value of FSR2 pre-incremented (not a physical register)
n/a
50
PLUSW2
Uses contents of FSR2 to address data memory - value of FSR2 pre-incremented (not a physical register) value of FSR2 offset by value in WREG
n/a
50
---- xxxx
50
xxxx xxxx
50
FSR2H
FSR2L
STATUS
TMR0H
TMR0ON
OV
DC
T08BIT
T0SE
PSA
T0PS2
T0PS1
T0PS0
52
103
xxxx xxxx
T0CS
---x xxxx
0000 0000
T0CON
TMR0L
103
1111 1111
101
Legend:
x = unknown, u = unchanged, - = unimplemented, q = value depends on condition
Note 1: RA6 and associated bits are configured as port pins in RCIO and ECIO oscillator mode only and read '0' in all other oscillator modes.
2: Bit 21 of the TBLPTRU allows access to the device configuration bits.
3: These registers and bits are reserved on the PIC18F2X2 devices; always maintain these clear.
DS39564A-page 46
Advance Information
PIC18FXX2
TABLE 4-2:
File Name
Bit 6
OSCCON
LVDCON
IRVST
LVDEN
LVDL3
LVDL2
IPEN
RI
TO
PD
WDTCON
RCON
Bit 5
Bit 4
Bit 3
Bit 2
Bit 0
Value on
POR,
BOR
SCS
---- ---0
21
LVDL1
LVDL0
--00 0101
189
SWDTE
---- ---0
201
POR
BOR
0--1 11qq
53, 28,
82
Bit 1
Details
on page:
TMR1H
xxxx xxxx
105
TMR1L
xxxx xxxx
105
0-00 0000
105
109
T1CON
RD16
T1CKPS1
T1CKPS0
T1OSCEN
T1SYNC
TMR1CS
TMR1ON
TMR2
Timer2 Register
0000 0000
PR2
1111 1111
110
-000 0000
109
T2CON
TOUTPS3
TOUTPS2
TOUTPS1
TOUTPS0
TMR2ON
T2CKPS1
T2CKPS0
SSPBUF
xxxx xxxx
123
SSPADD
SSP Address Register in I2C Slave Mode. SSP Baud Rate Reload Register in I2C Master Mode.
0000 0000
132
SSPSTAT
SMP
CKE
D/A
R/W
UA
BF
0000 0000
124
SSPCON1
WCOL
SSPOV
SSPEN
CKP
SSPM3
SSPM2
SSPM1
SSPM0
0000 0000
125
SSPCON2
GCEN
ACKSTAT
ACKDT
ACKEN
RCEN
PEN
RSEN
SEN
0000 0000
135
xxxx xxxx
185,186
ADRESH
ADRESL
xxxx xxxx
185,186
ADCON0
ADCS1
ADCS0
CHS2
CHS1
CHS0
GO/DONE
ADON
0000 00-0
179
ADCON1
ADFM
ADCS2
PCFG3
PCFG2
PCFG1
PCFG0
00-- 0000
180
xxxx xxxx
119, 121
xxxx xxxx
119, 121
CCPR1H
CCPR1L
CCP1CON
DC1B1
DC1B0
CCPR2H
CCP1M2
CCP1M1
CCP1M0
DC2B1
DC2B0
CCP2M3
CCP2M2
CCP2M1
CCP2M0
115
119, 121
xxxx xxxx
CCP2CON
--00 0000
xxxx xxxx
CCPR2L
CCP1M3
119, 121
--00 0000
115
TMR3H
xxxx xxxx
111
TMR3L
xxxx xxxx
111
T3CON
RD16
T3CCP2
T3CKPS1
T3CKPS0
T3CCP1
T3SYNC
TMR3CS
TMR3ON
0000 0000
111
SPBRG
0000 0000
166
RCREG
0000 0000
172, 175,
177
TXREG
0000 0000
170, 173,
176
164
TXSTA
CSRC
TX9
TXEN
SYNC
BRGH
TRMT
TX9D
0000 -010
RCSTA
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
0000 000x
165
0000 0000
65, 68
EEDATA
0000 0000
68
EECON2
---- ----
65, 68
xx-0 x000
66
EEADR
EECON1
EEPGD
CFGS
FREE
WRERR
WREN
WR
RD
Advance Information
DS39564A-page 47
PIC18FXX2
TABLE 4-2:
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR,
BOR
Details
on page:
IPR2
EEIP
BCLIP
LVDIP
TMR3IP
CCP2IP
---1 1111
81
PIR2
EEIF
BCLIF
LVDIF
TMR3IF
CCP2IF
---0 0000
77
PIE2
EEIE
BCLIE
LVDIE
TMR3IE
CCP2IE
---0 0000
79
IPR1
PSPIP(3)
ADIP
RCIP
TXIP
SSPIP
CCP1IP
TMR2IP
TMR1IP
1111 1111
80
PIR1
PSPIF(3)
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
0000 0000
76
PIE1
PSPIE(3)
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
0000 0000
78
IBF
OBF
IBOV
PSPMODE
0000 -111
96
TRISE(3)
TRISD(3)
1111 1111
94
TRISC
1111 1111
91
TRISB
1111 1111
88
-111 1111
85
---- -xxx
97
TRISA
TRISA6(1)
LATE(3)
LATD(3)
xxxx xxxx
93
LATC
xxxx xxxx
91
LATB
xxxx xxxx
88
-xxx xxxx
85
LATA
LATA6(1)
PORTE(3)
---- -000
97
PORTD(3)
xxxx xxxx
93
PORTC
xxxx xxxx
91
PORTB
xxxx xxxx
88
-x0x 0000
85
PORTA
RA6(1)
DS39564A-page 48
Advance Information
PIC18FXX2
4.10
Access Bank
4.11
A MOVLB instruction has been provided in the instruction set to assist in selecting banks.
If the currently selected bank is not implemented, any
read will return all '0's and all writes are ignored. The
STATUS register bits will be set/cleared as appropriate
for the instruction performed.
FIGURE 4-8:
DIRECT ADDRESSING
Direct Addressing
BSR<3:0>
Bank Select(2)
From Opcode(3)
Location Select(3)
00h
01h
0Eh
0Fh
000h
100h
E00h
F00h
0FFh
1FFh
EFFh
FFFh
Bank 14
Bank 15
Data
Memory(1)
Bank 0
Bank 1
Advance Information
DS39564A-page 49
PIC18FXX2
4.12
Indirect addressing is a mode of addressing data memory, where the data memory address in the instruction
is not fixed. An FSR register is used as a pointer to the
data memory location that is to be read or written. Since
this pointer is in RAM, the contents can be modified by
the program. This can be useful for data tables in the
data memory and for software stacks. Figure 4-9
shows the operation of indirect addressing. This shows
the moving of the value to the data memory address
specified by the value of the FSR register.
Indirect addressing is possible by using one of the
INDF registers. Any instruction using the INDF register
actually accesses the register pointed to by the File
Select Register, FSR. Reading the INDF register itself,
indirectly (FSR = 0), will read 00h. Writing to the INDF
register indirectly, results in a no operation. The FSR
register contains a 12-bit address, which is shown in
Figure 4-10.
The INDFn register is not a physical register. Addressing INDFn actually addresses the register whose
address is contained in the FSRn register (FSRn is a
pointer). This is indirect addressing.
Example 4-4 shows a simple use of indirect addressing
to clear the RAM in Bank1 (locations 100h-1FFh) in a
minimum number of instructions.
EXAMPLE 4-4:
FSR0 ,0x100 ;
POSTINC0
; Clear INDF
; register and
; inc pointer
BTFSS FSR0H, 1
; All done with
; Bank1?
GOTO NEXT
; NO, clear next
CONTINUE
; YES, continue
NEXT
LFSR
CLRF
DS39564A-page 50
4.12.1
INDIRECT ADDRESSING
OPERATION
Advance Information
PIC18FXX2
FIGURE 4-9:
0h
Instruction
Executed
Opcode
Address
FFFh
12
File Address = access of an indirect addressing register
BSR<3:0>
Instruction
Fetched
Opcode
FIGURE 4-10:
12
12
8
File
FSR
INDIRECT ADDRESSING
Indirect Addressing
11
FSR Register
Location Select
0000h
Data
Memory(1)
0FFFh
Note 1: For register file map detail, see Table 4-1.
Advance Information
DS39564A-page 51
PIC18FXX2
4.13
STATUS Register
REGISTER 4-2:
STATUS REGISTER
U-0
U-0
U-0
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
OV
DC
bit 7
bit 0
bit 7-5
bit 4
N: Negative bit
This bit is used for signed arithmetic (2s complement). It indicates whether the result was
negative (ALU MSB = 1).
1 = Result was negative
0 = Result was positive
bit 3
bit 2
Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit 1
bit 0
For borrow, the polarity is reversed. A subtraction is executed by adding the twos
complement of the second operand. For rotate (RRF, RLF) instructions, this bit is
loaded with either the bit 4 or bit 3 of the source register.
C: Carry/borrow bit
For ADDWF, ADDLW, SUBLW, and SUBWF instructions
1 = A carry-out from the Most Significant bit of the result occurred
0 = No carry-out from the Most Significant bit of the result occurred
Note:
For borrow, the polarity is reversed. A subtraction is executed by adding the twos
complement of the second operand. For rotate (RRF, RLF) instructions, this bit is
loaded with either the high or low order bit of the source register.
Legend:
R = Readable bit
DS39564A-page 52
W = Writable bit
1 = Bit is set
0 = Bit is cleared
Advance Information
x = Bit is unknown
PIC18FXX2
4.14
RCON Register
REGISTER 4-3:
RCON REGISTER
R/W-0
U-0
U-0
R/W-1
R/W-1
R/W-1
R/W-0
R/W-0
IPEN
RI
TO
PD
POR
BOR
bit 7
bit 0
bit 7
bit 6-5
bit 4
bit 3
bit 2
bit 1
bit 0
W = Writable bit
1 = Bit is set
0 = Bit is cleared
Advance Information
x = Bit is unknown
DS39564A-page 53
PIC18FXX2
NOTES:
DS39564A-page 54
Advance Information
PIC18FXX2
5.0
Table Write operations store data from the data memory space into holding registers in program memory.
The procedure to write the contents of the holding registers into program memory is detailed in Section 5.5,
'Writing to FLASH Program Memory. Figure 5-2
shows the operation of a Table Write with program
memory and data RAM.
Writing or erasing program memory will cease instruction fetches until the operation is complete. The program memory cannot be accessed during the write or
erase, therefore, code cannot execute. An internal programming timer terminates program memory writes
and erases.
5.1
FIGURE 5-1:
Program Memory
Table Pointer(1)
TBLPTRU
TBLPTRH
Program Memory
(TBLPTR)
Advance Information
DS39564A-page 55
PIC18FXX2
FIGURE 5-2:
Program Memory
Holding Registers
Table Pointer(1)
TBLPTRU
TBLPTRH
TABLAT
Program Memory
(TBLPTR)
Note 1: Table Pointer actually points to one of eight holding registers, the address of which is determined by
TBLPTRL<2:0>. The process for physically writing data to the Program Memory Array is discussed in
Section 5.5.
5.2
Control Registers
EECON1 register
EECON2 register
TABLAT register
TBLPTR registers
5.2.1
DS39564A-page 56
Note:
Advance Information
PIC18FXX2
REGISTER 5-1:
R/W-x
U-0
R/W-0
R/W-x
R/W-0
R/S-0
R/S-0
EEPGD
CFGS
FREE
WRERR
WREN
WR
RD
bit 7
bit 0
bit 7
bit 6
bit 5
bit 4
bit 3
When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows
tracing of the error condition.
bit 2
bit 1
bit 0
W = Writable bit
- n = Value at POR
1 = Bit is set
0 = Bit is cleared
Advance Information
x = Bit is unknown
DS39564A-page 57
PIC18FXX2
5.2.2
5.2.4
5.2.3
TABLE 5-1:
TBLRD*
TBLWT*
TBLRD*+
TBLWT*+
TBLRD*TBLWT*TBLRD+*
TBLWT+*
21
Example
FIGURE 5-3:
16
15
TBLPTRH
TBLPTRL
ERASE - TBLPTR<21:6>
WRITE - TBLPTR<21:3>
READ - TBLPTR<21:0>
DS39564A-page 58
Advance Information
PIC18FXX2
5.3
The TBLRD instruction is used to retrieve data from program memory and place into data RAM. Table Reads
from program memory are performed one byte at a
time.
FIGURE 5-4:
Program Memory
TBLPTR = xxxxx1
Instruction Register
(IR)
EXAMPLE 5-1:
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
FETCH
TBLRD
TBLPTR = xxxxx0
TABLAT
Read Register
READ_WORD
TBLRD*+
MOVFW TABLAT
MOVWF WORD_EVEN
TBLRD*+
MOVFW TABLAT
MOVWF WORD_ODD
Advance Information
DS39564A-page 59
PIC18FXX2
5.4
5.4.1
When initiating an erase sequence from the microcontroller itself, a block of 64 bytes of program memory
is erased. The Most Significant 16 bits of the
TBLPTR<21:6> point to the block being erased.
TBLPTR<5:0> are ignored.
2.
3.
4.
5.
6.
7.
8.
9.
EXAMPLE 5-2:
CODE_ADDR_UPPER
TBLPTRU
CODE_ADDR_HIGH
TBLPTRH
CODE_ADDR_LOW
TBLPTRL
BSF
BSF
BSF
BCF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
NOP
BSF
EECON1,EEPGD
EECON1,WREN
EECON1,FREE
INTCON,GIE
55h
EECON2
AAh
EECON2
EECON2,WR
;
;
;
;
INTCON,GIE
; re-enable interrupts
ERASE_ROW
Required
Sequence
DS39564A-page 60
; write 55H
; write AAH
; start erase (CPU stall)
Advance Information
PIC18FXX2
5.5
FIGURE 5-5:
8
TBLPTR = xxxxx0
8
TBLPTR = xxxxx2
TBLPTR = xxxxx1
Holding Register
Holding Register
Holding Register
8
TBLPTR = xxxxx7
Holding Register
Program Memory
5.5.1
8.
9.
10.
11.
12.
13.
14.
15.
16.
Disable interrupts.
Write 55h to EECON2.
Write AAh to EECON2.
Set the WR bit. This will begin the write cycle.
The CPU will stall for duration of the write (about
2 ms using internal timer).
Execute a NOP.
Re-enable interrupts.
Repeat steps 6-14 seven times, to write 64
bytes.
Verify the memory (Table Read).
Advance Information
DS39564A-page 61
PIC18FXX2
EXAMPLE 5-3:
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
D64
COUNTER
BUFFER_ADDR_HIGH
FSR0H
BUFFER_ADDR_LOW
FSR0L
CODE_ADDR_UPPER
TBLPTRU
CODE_ADDR_HIGH
TBLPTRH
CODE_ADDR_LOW
TBLPTRL
TBLRD*+
MOVFW
MOVWF
DECFSZ
GOTO
TABLAT
POSTINC0
COUNTER
READ_BLOCK
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
DATA_ADDR_HIGH
FSR0H
DATA_ADDR_LOW
FSR0L
NEW_DATA_LOW
POSTINC0
NEW_DATA_HIGH
INDF0
READ_BLOCK
;
;
;
;
;
MODIFY_WORD
; point to buffer
ERASE_BLOCK
MOVLW
CODE_ADDR_UPPER
MOVWF
TBLPTRU
MOVLW
CODE_ADDR_HIGH
MOVWF
TBLPTRH
MOVLW
CODE_ADDR_LOW
MOVWF
TBLPTRL
BSF
EECON1,EEPGD
BSF
EECON1,WREN
BSF
EECON1,FREE
BCF
INTCON,GIE
MOVLW
55h
MOVWF
EECON2
MOVLW
AAh
MOVWF
EECON2
BSF
EECON1,WR
NOP
BSF
INTCON,GIE
TBLRD*WRITE_BUFFER_BACK
MOVLW
8
MOVWF
COUNTER_HI
MOVLW
BUFFER_ADDR_HIGH
MOVWF
FSR0H
MOVLW
BUFFER_ADDR_LOW
MOVWF
FSR0L
PROGRAM_LOOP
MOVLW
8
MOVWF
COUNTER
WRITE_WORD_TO_HREGS
MOVFW
POSTINC0
MOVWF
TABLAT
TBLWT+*
DECFSZ COUNTER
GOTO
WRITE_WORD_TO_HREGS
DS39564A-page 62
;
;
;
;
; write 55H
; write AAH
; start erase (CPU stall)
; re-enable interrupts
; dummy read decrement
; number of write buffer groups of 8 bytes
; point to buffer
;
;
;
;
;
Advance Information
PIC18FXX2
EXAMPLE 5-3:
PROGRAM_MEMORY
BSF
EECON1,EEPGD
BSF
EECON1,WREN
BCF
INTCON,GIE
MOVLW
55h
MOVWF
EECON2
MOVLW
AAh
MOVWF
EECON2
BSF
EECON1,WR
NOP
BSF
INTCON,GIE
DECFSZ COUNTER_HI
GOTO PROGRAM_LOOP
BCF
EECON1,WREN
5.5.2
WRITE VERIFY
5.5.3
5.5.5
MAXIMIZING ENDURANCE
5.5.4
5.6
UNEXPECTED TERMINATION OF
WRITE OPERATION
TABLE 5-2:
Address
Bit 5
FF8h
TBLPTRU
bit21
FF7h
FF6h
FF5h
TABLAT
INTCON
FA7h
EECON2
FA6h
EECON1
FA2h
FA1h
Bit 3
Bit 2
Bit 1
Bit 0
Value on
all other
RESETS
Bit 7
FF2h
Bit 4
Value on:
POR,
BOR
Name
PEIE/
GIEL
TMR0IE
INTE
RBIE
TMR0IF
INTF
RBIF
EEPGD
CFGS
FREE
WRERR
WREN
WR
RD
IPR2
EEIP
BCLIP
LVDIP
TMR3IP
CCP2IP
PIR2
EEIF
BCLIF
LVDIF
TMR3IF
CCP2IF
FA0h
PIE2
EEIE
BCLIE
LVDIE
TMR3IE
CCP2IE
Legend:
Advance Information
DS39564A-page 63
PIC18FXX2
NOTES:
DS39564A-page 64
Advance Information
PIC18FXX2
6.0
EECON1
EECON2
EEDATA
EEADR
6.1
EEADR
6.2
Note:
Advance Information
DS39564A-page 65
PIC18FXX2
REGISTER 6-1:
R/W-x
U-0
R/W-0
R/W-x
R/W-0
R/S-0
R/S-0
EEPGD
EEFS
FREE
WRERR
WREN
WR
RD
bit 7
bit 0
bit 7
bit 6
bit 5
bit 4
bit 3
When a WRERR occurs, the EEPGD or FREE bits are not cleared. This allows tracing
of the error condition.
bit 2
bit 1
bit 0
DS39564A-page 66
W = Writable bit
- n = Value at POR
1 = Bit is set
0 = Bit is cleared
Advance Information
x = Bit is unknown
PIC18FXX2
6.3
EXAMPLE 6-1:
MOVLW
MOVWF
BCF
BSF
MOVF
6.4
;
;
;
;
;
EXAMPLE 6-2:
DATA_EE_ADDR
MOVWF
EEADR
MOVLW
DATA_EE_DATA
MOVWF
EEDATA
BCF
BSF
EECON1, WREN
; Enable writes
BCF
INTCON, GIE
; Disable Interrupts
MOVLW
55h
Required
MOVWF
EECON2
; Write 55h
Sequence
MOVLW
AAh
MOVWF
EECON2
; Write AAh
BSF
EECON1, WR
BSF
INTCON, GIE
; Enable Interrupts
SLEEP
BCF
; Disable writes
Advance Information
DS39564A-page 67
PIC18FXX2
6.5
Write Verify
6.5.1
6.7
MAXIMIZING ENDURANCE
6.6
TABLE 6-1:
Address
FF2h
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR,
BOR
Value on
all other
RESETS
INTCON
GIE/
GIEH
PEIE/
GIEL
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x
0000 000u
FA9h
EEADR
0000 0000
0000 0000
FA8h
EEDATA
0000 0000
0000 0000
FA7h
FA6h
EECON1
FA2h
FA1h
FA0h
Legend:
xx-0 x000
uu-0 u000
EEPGD
CFGS
FREE
WRERR
WREN
WR
RD
IPR2
EEIP
BCLIP
LVDIP
TMR3IP
CCP2IP
---1 1111
---1 1111
PIR2
EEIF
BCLIF
LVDIF
TMR3IF
CCP2IF
---0 0000
---0 0000
PIE2
EEIE
BCLIE
LVDIE
TMR3IE
CCP2IE
---0 0000
---0 0000
DS39564A-page 68
Advance Information
PIC18FXX2
7.0
8 X 8 HARDWARE MULTIPLIER
7.1
Introduction
TABLE 7-1:
8 x 8 unsigned
8 x 8 signed
16 x 16 unsigned
16 x 16 signed
Program
Memory
(Words)
13
Hardware multiply
33
Hardware multiply
@ 40 MHz
@ 10 MHz
@ 4 MHz
69
6.9 s
27.6 s
69 s
100 ns
400 ns
1 s
91
9.1 s
36.4 s
91 s
600 ns
2.4 s
6 s
21
242
24.2 s
96.8 s
242 s
24
24
2.4 s
9.6 s
24 s
52
254
25.4 s
102.6 s
254 s
Hardware multiply
36
36
3.6 s
14.4 s
36 s
Operation
EXAMPLE 7-2:
EXAMPLE 7-1:
ARG1, W
ARG2
Time
Cycles
(Max)
Multiply Method
MOVF
MULWF
PERFORMANCE COMPARISON
Routine
7.2
8 x 8 UNSIGNED
MULTIPLY ROUTINE
;
; ARG1 * ARG2 ->
;
PRODH:PRODL
8 x 8 SIGNED MULTIPLY
ROUTINE
MOVF
MULWF
ARG1,
ARG2
BTFSC
SUBWF
ARG2, SB
PRODH, F
MOVF
BTFSC
SUBWF
ARG2, W
ARG1, SB
PRODH, F
;
;
;
;
;
EQUATION 7-1:
RES3:RES0
Advance Information
=
=
16 x 16 UNSIGNED
MULTIPLICATION
ALGORITHM
ARG1H:ARG1L ARG2H:ARG2L
(ARG1H ARG2H 216)+
(ARG1H ARG2L 28)+
(ARG1L ARG2H 28)+
(ARG1L ARG2L)
DS39564A-page 69
PIC18FXX2
EXAMPLE 7-3:
MOVF
MULWF
16 x 16 UNSIGNED
MULTIPLY ROUTINE
EXAMPLE 7-4:
ARG1L, W
ARG2L
MOVFF
MOVFF
MOVF
MULWF
MOVF
MULWF
PRODH, RES1
PRODL, RES0
MOVF
MULWF
ARG1H, W
ARG2H
MOVFF
MOVFF
PRODH, RES3
PRODL, RES2
MOVF
MULWF
ARG1L, W
ARG2H
MOVF
ADDWF
MOVF
ADDWFC
CLRF
ADDWFC
PRODL,
RES1,
PRODH,
RES2,
WREG
RES3,
MOVF
MULWF
ARG1H, W
ARG2L
MOVF
ADDWF
MOVF
ADDWFC
CLRF
ADDWFC
PRODL,
RES1,
PRODH,
RES2,
WREG
RES3,
BTFSS
BRA
MOVF
SUBWF
MOVF
SUBWFB
ARG1H, W
ARG2H
ARG1L, W
ARG2L
MOVFF
MOVFF
16 x 16 SIGNED
MULTIPLY ROUTINE
ARG2H, 7
SIGN_ARG1
ARG1L, W
RES2
ARG1H, W
RES3
; ARG2H:ARG2L neg?
; no, check ARG1
;
;
;
ARG1H, 7
CONT_CODE
ARG2L, W
RES2
ARG2H, W
RES3
; ARG1H:ARG1L neg?
; no, done
;
;
;
MOVFF
MOVFF
MOVF
MULWF
ARG1L, W
ARG2H
MOVF
ADDWF
MOVF
ADDWFC
CLRF
ADDWFC
PRODL,
RES1,
PRODH,
RES2,
WREG
RES3,
W
F
W
F
F
;
;
;
;
;
;
;
;
W
F
W
F
F
;
;
;
;
;
;
;
;
;
MOVF
MULWF
ARG1H, W
ARG2L
MOVF
ADDWF
MOVF
ADDWFC
CLRF
ADDWFC
PRODL,
RES1,
PRODH,
RES2,
WREG
RES3,
W
F
W
F
F
;
;
;
;
;
;
;
;
;
W
F
W
F
F
;
;
;
;
;
;
;
;
;
EQUATION 7-2:
16 x 16 SIGNED
MULTIPLICATION
ALGORITHM
RES3:RES0
=
ARG1H:ARG1L ARG2H:ARG2L
=
(ARG1H ARG2H 216)+
(ARG1H ARG2L 28)+
(ARG1L ARG2H 28)+
(ARG1L ARG2L)+
(-1 ARG2H<7> ARG1H:ARG1L 216)+
(-1 ARG1H<7> ARG2H:ARG2L 216)
DS39564A-page 70
;
SIGN_ARG1
BTFSS
BRA
MOVF
SUBWF
MOVF
SUBWFB
;
CONT_CODE
:
Advance Information
PIC18FXX2
8.0
INTERRUPTS
RCON
INTCON
INTCON2
INTCON3
PIR1, PIR2
PIE1, PIE2
IPR1, IPR2
It is recommended that the Microchip header files supplied with MPLAB IDE be used for the symbolic bit
names in these registers. This allows the assembler/
compiler to automatically take care of the placement of
these bits within the specified register.
Each interrupt source has three bits to control its operation. The functions of these bits are:
Flag bit to indicate that an interrupt event
occurred
Enable bit that allows program execution to
branch to the interrupt vector address when the
flag bit is set
Priority bit to select high priority or low priority
When the IPEN bit is cleared (default state), the interrupt priority feature is disabled and interrupts are compatible with PICmicro mid-range devices. In
Compatibility mode, the interrupt priority bits for each
source have no effect. INTCON<6> is the PEIE bit,
which enables/disables all peripheral interrupt sources.
INTCON<7> is the GIE bit, which enables/disables all
interrupt sources. All interrupts branch to address
000008h in Compatibility mode.
When an interrupt is responded to, the Global Interrupt
Enable bit is cleared to disable further interrupts. If the
IPEN bit is cleared, this is the GIE bit. If interrupt priority
levels are used, this will be either the GIEH or GIEL bit.
High priority interrupt sources can interrupt a low
priority interrupt.
The return address is pushed onto the stack and the
PC is loaded with the interrupt vector address
(000008h or 000018h). Once in the Interrupt Service
Routine, the source(s) of the interrupt can be determined by polling the interrupt flag bits. The interrupt
flag bits must be cleared in software before re-enabling
interrupts to avoid recursive interrupts.
The return from interrupt instruction, RETFIE, exits
the interrupt routine and sets the GIE bit (GIEH or GIEL
if priority levels are used), which re-enables interrupts.
For external interrupt events, such as the INT pins or
the PORTB input change interrupt, the interrupt latency
will be three to four instruction cycles. The exact
latency is the same for one or two-cycle instructions.
Individual interrupt flag bits are set, regardless of the
status of their corresponding enable bit or the GIE bit.
Advance Information
DS39564A-page 71
PIC18FXX2
FIGURE 8-1:
INTERRUPT LOGIC
TMR0IF
TMR0IE
TMR0IP
RBIF
RBIE
RBIP
INT0IF
INT0IE
INT1IF
INT1IE
INT1IP
INT2IF
INT2IE
INT2IP
Interrupt to CPU
Vector to location
0008h
GIEH/GIE
TMR1IF
TMR1IE
TMR1IP
IPE
IPEN
XXXXIF
XXXXIE
XXXXIP
GIEL/PEIE
IPEN
Additional Peripheral Interrupts
TMR1IF
TMR1IE
TMR1IP
RBIF
RBIE
RBIP
XXXXIF
XXXXIE
XXXXIP
GIEL\PEIE
INT0IF
INT0IE
Additional Peripheral Interrupts
DS39564A-page 72
Interrupt to CPU
Vector to Location
0018h
TMR0IF
TMR0IE
TMR0IP
INT1IF
INT1IE
INT1IP
INT2IF
INT2IE
INT2IP
Advance Information
PIC18FXX2
8.1
INTCON Registers
Note:
The INTCON Registers are readable and writable registers, which contain various enable, priority and flag
bits.
REGISTER 8-1:
INTCON REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-x
GIE/GIEH
PEIE/GIEL
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
bit 7
bit 0
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
A mismatch condition will continue to set this bit. Reading PORTB will end the
mismatch condition and allow the bit to be cleared.
Legend:
R = Readable bit
W = Writable bit
1 = Bit is set
0 = Bit is cleared
Advance Information
x = Bit is unknown
DS39564A-page 73
PIC18FXX2
REGISTER 8-2:
INTCON2 REGISTER
R/W-1
R/W-1
R/W-1
R/W-1
U-0
R/W-1
U-0
R/W-1
RBPU
INTEDG0
INTEDG1
INTEDG2
TMR0IP
RBIP
bit 7
bit 0
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
W = Writable bit
1 = Bit is set
0 = Bit is cleared
Note:
DS39564A-page 74
x = Bit is unknown
Interrupt flag bits are set when an interrupt condition occurs, regardless of the state
of its corresponding enable bit or the global enable bit. User software should ensure
the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature
allows for software polling.
Advance Information
PIC18FXX2
REGISTER 8-3:
INTCON3 REGISTER
R/W-1
R/W-1
U-0
R/W-0
R/W-0
U-0
R/W-0
R/W-0
INT2IP
INT1IP
INT2IE
INT1IE
INT2IF
INT1IF
bit 7
bit 0
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
W = Writable bit
1 = Bit is set
0 = Bit is cleared
Note:
x = Bit is unknown
Interrupt flag bits are set when an interrupt condition occurs, regardless of the state
of its corresponding enable bit or the global enable bit. User software should ensure
the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature
allows for software polling.
Advance Information
DS39564A-page 75
PIC18FXX2
8.2
PIR Registers
The PIR registers contain the individual flag bits for the
peripheral interrupts. Due to the number of peripheral
interrupt sources, there are two Peripheral Interrupt
Flag Registers (PIR1, PIR2).
REGISTER 8-4:
PSPIF
R/W-0
R-0
R-0
R/W-0
R/W-0
R/W-0
R/W-0
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
bit 7
bit 0
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
DS39564A-page 76
W = Writable bit
1 = Bit is set
0 = Bit is cleared
Advance Information
x = Bit is unknown
PIC18FXX2
REGISTER 8-5:
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
EEIF
BCLIF
LVDIF
TMR3IF
CCP2IF
bit 7
bit 0
bit 7-5
bit 4
bit 3
bit 2
bit 1
bit 0
W = Writable bit
1 = Bit is set
0 = Bit is cleared
Advance Information
x = Bit is unknown
DS39564A-page 77
PIC18FXX2
8.3
PIE Registers
REGISTER 8-6:
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PSPIE(1)
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
bit 7
bit 0
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
DS39564A-page 78
W = Writable bit
- n = Value at POR
1 = Bit is set
0 = Bit is cleared
Advance Information
x = Bit is unknown
PIC18FXX2
REGISTER 8-7:
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
EEIE
BCLIE
LVDIE
TMR3IE
CCP2IE
bit 7
bit 0
bit 7-5
bit 4
bit 3
bit 2
bit 1
bit 0
W = Writable bit
- n = Value at POR
1 = Bit is set
0 = Bit is cleared
Advance Information
x = Bit is unknown
DS39564A-page 79
PIC18FXX2
8.4
IPR Registers
REGISTER 8-8:
PSPIP
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
ADIP
RCIP
TXIP
SSPIP
CCP1IP
TMR2IP
TMR1IP
bit 7
bit 0
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
- n = Value at POR
DS39564A-page 80
W = Writable bit
1 = Bit is set
0 = Bit is cleared
Advance Information
x = Bit is unknown
PIC18FXX2
REGISTER 8-9:
U-0
U-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
EEIP
BCLIP
LVDIP
TMR3IP
CCP2IP
bit 7
bit 0
bit 7-5
bit 4
bit 3
bit 2
bit 1
bit 0
W = Writable bit
- n = Value at POR
1 = Bit is set
0 = Bit is cleared
Advance Information
x = Bit is unknown
DS39564A-page 81
PIC18FXX2
8.5
RCON Register
REGISTER 8-10:
RCON REGISTER
R/W-0
U-0
U-0
R/W-1
R-1
R-1
R/W-0
R/W-0
IPEN
RI
TO
PD
POR
BOR
bit 7
bit 0
bit 7
bit 6-5
bit 4
bit 3
bit 2
bit 1
bit 0
DS39564A-page 82
W = Writable bit
1 = Bit is set
0 = Bit is cleared
Advance Information
x = Bit is unknown
PIC18FXX2
8.6
INT0 Interrupt
8.7
TMR0 Interrupt
8.8
PORTB Interrupt-on-Change
8.9
EXAMPLE 8-1:
MOVWF
MOVFF
MOVFF
;
; USER
;
MOVFF
MOVF
MOVFF
W_TEMP
STATUS, STATUS_TEMP
BSR,
BSR_TEMP
ISR CODE
BSR_TEMP, BSR
W_TEMP,
W
STATUS_TEMP,STATUS
; Restore BSR
; Restore WREG
; Restore STATUS
Advance Information
DS39564A-page 83
PIC18FXX2
NOTES:
DS39564A-page 84
Advance Information
PIC18FXX2
9.0
I/O PORTS
EXAMPLE 9-1:
9.1
INITIALIZING PORTA
CLRF PORTA
;
;
;
;
;
;
;
;
;
;
;
;
;
CLRF LATA
MOVLW 0x07
MOVWF ADCON1
MOVLW 0xCF
MOVWF TRISA
Initialize PORTA by
clearing output
data latches
Alternate method
to clear output
data latches
Configure A/D
for digital inputs
Value used to
initialize data
direction
Set RA<3:0> as inputs
RA<5:4> as outputs
FIGURE 9-1:
BLOCK DIAGRAM OF
RA3:RA0 AND RA5 PINS
PORTA is a 7-bit wide, bi-directional port. The corresponding Data Direction register is TRISA. Setting a
TRISA bit (= 1) will make the corresponding PORTA pin
an input (i.e., put the corresponding output driver in a
Hi-Impedance mode). Clearing a TRISA bit (= 0) will
make the corresponding PORTA pin an output (i.e., put
the contents of the output latch on the selected pin).
Reading the PORTA register reads the status of the
pins, whereas writing to it will write to the port latch.
RD LATA
Data
Bus
Q
VDD
WR LATA
or
PORTA
CK
CK
I/O pin(1)
VSS
Analog
Input
Mode
TRIS Latch
TTL
Input
Buffer
RD TRISA
Note:
WR TRISA
Data Latch
EN
RD PORTA
SS Input (RA5 only)
To A/D Converter and LVD Modules
Note 1:
Advance Information
DS39564A-page 85
PIC18FXX2
FIGURE 9-2:
BLOCK DIAGRAM OF
RA4/T0CKI PIN
FIGURE 9-3:
ECRA6 or
RCRA6 Enable
Data
Bus
RD LATA
Data
Bus
CK
RD LATA
Q
Q
WR LATA
or
PORTA
Data Latch
D
CK
WR TRISA
Q
Q
CK
WR LATA
or
PORTA
VSS
VDD
P
Data Latch
D
Schmitt
Trigger
Input
Buffer
TRIS Latch
I/O pin(1)
CK
WR
TRISA
I/O pin(1)
VSS
TRIS Latch
RD TRISA
Q
TTL
Input
Buffer
D
RD TRISA
EN
EN
ECRA6 or
RCRA6
Enable
RD PORTA
D
EN
Note 1:
DS39564A-page 86
Advance Information
PIC18FXX2
TABLE 9-1:
PORTA FUNCTIONS
Name
Bit#
Buffer
Function
RA0/AN0
bit0
TTL
RA1/AN1
bit1
TTL
RA2/AN2/VREF-
bit2
TTL
RA3/AN3/VREF+
bit3
TTL
RA4/T0CKI
bit4
ST
RA5/SS/AN4/LVDIN
bit5
TTL
OSC2/CLKO/RA6
bit6
TTL
TABLE 9-2:
Name
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR,
BOR
Value on all
other
RESETS
RA6
RA5
RA4
RA3
RA2
RA1
RA0
-x0x 0000
-u0u 0000
-xxx xxxx
-uuu uuuu
-111 1111
-111 1111
00-- 0000
00-- 0000
PORTA
LATA
TRISA
ADCON1
ADFM
ADCS2
PCFG3
PCFG2
PCFG1
PCFG0
Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by PORTA.
Advance Information
DS39564A-page 87
PIC18FXX2
9.2
PORTB is an 8-bit wide, bi-directional port. The corresponding Data Direction register is TRISB. Setting a
TRISB bit (= 1) will make the corresponding PORTB pin
an input (i.e., put the corresponding output driver in a
Hi-Impedance mode). Clearing a TRISB bit (= 0) will
make the corresponding PORTB pin an output (i.e., put
the contents of the output latch on the selected pin).
The Data Latch register (LATB) is also memory
mapped. Read-modify-write operations on the LATB
register reads and writes the latched output value for
PORTB.
EXAMPLE 9-2:
CLRF
PORTB
CLRF
LATB
MOVLW 0xCF
MOVWF TRISB
INITIALIZING PORTB
;
;
;
;
;
;
;
;
;
;
;
;
Initialize PORTB by
clearing output
data latches
Alternate method
to clear output
data latches
Value used to
initialize data
direction
Set RB<3:0> as inputs
RB<5:4> as outputs
RB<7:6> as inputs
Four of the PORTB pins, RB7:RB4, have an interrupton-change feature. Only pins configured as inputs can
cause this interrupt to occur (i.e., any RB7:RB4 pin
configured as an output is excluded from the interrupton-change comparison). The input pins (of RB7:RB4)
are compared with the old value latched on the last
read of PORTB. The mismatch outputs of RB7:RB4
are ORed together to generate the RB Port Change
Interrupt with flag bit, RBIF (INTCON<0>).
FIGURE 9-4:
BLOCK DIAGRAM OF
RB7:RB4 PINS
VDD
RBPU(2)
Weak
P Pull-up
Data Latch
Data Bus
Q
I/O pin(1)
WR LATB
or
PORTB
CK
TRIS Latch
D
Q
WR TRISB
TTL
Input
Buffer
CK
ST
Buffer
RD TRISB
RD LATB
Q
Latch
D
EN
RD PORTB
Q1
Set RBIF
D
RD PORTB
From other
RB7:RB4 pins
EN
Q3
b)
DS39564A-page 88
Advance Information
PIC18FXX2
FIGURE 9-5:
Weak
P Pull-up
Data Latch
D
Q
Data Bus
I/O pin(1)
WR Port
CK
TRIS Latch
D
Q
WR TRIS
TTL
Input
Buffer
CK
RD TRIS
Q
D
EN
RD Port
RB0/INT
Schmitt Trigger
Buffer
Note 1:
2:
RD Port
FIGURE 9-6:
Weak
P Pull-up
(2)
CCP2MX
CCP Output(3)
VDD
P
Enable(3)
CCP Output
Data Bus
WR LATB or
WR PORTB
0
Data Latch
D
I/O pin(1)
Q
N
CK
VSS
TRIS Latch
D
WR TRISB
CK
TTL
Input
Buffer
RD TRISB
RD LATB
Q
RD PORTB
D
EN
RD PORTB
CCP2 Input(3)
Schmitt Trigger
Buffer
Note 1:
2:
3:
CCP2MX = 0
Advance Information
DS39564A-page 89
PIC18FXX2
TABLE 9-3:
PORTB FUNCTIONS
Name
Bit#
Buffer
RB0/INT0
bit0
TTL/ST(1)
RB1/INT1
bit1
TTL/ST(1)
RB2/INT2
bit2
TTL/ST(1)
RB3/CCP2/INT3(3)
bit3
TTL/ST(4)
RB4
bit4
TTL
RB5/PGM
bit5
TTL/ST(2)
RB6/PGC
bit6
TTL/ST(2)
RB7/PGD
bit7
TTL/ST(2)
Legend:
Note 1:
2:
3:
4:
TABLE 9-4:
Name
PORTB
Function
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR,
BOR
Value on all
other
RESETS
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0
xxxx xxxx
uuuu uuuu
1111 1111
1111 1111
RBIE
TMR0IF
INT0IF
RBIF
0000 000x
0000 000u
LATB
TRISB
INTCON
GIE/
GIEH
PEIE/
GIEL
TMR0IE
INT0IE
INTCON2
RBPU
INTEDG0
INTEDG1
INTEDG2
TMR0IP
RBIP
1111 -1-1
1111 -1-1
INTCON3
INT2IP
INT1IP
INT2IE
INT1IE
INT2IF
INT1IF
11-0 0-00
11-0 0-00
DS39564A-page 90
Advance Information
PIC18FXX2
9.3
The pin override value is not loaded into the TRIS register. This allows read-modify-write of the TRIS register,
without concern due to peripheral overrides.
PORTC is an 8-bit wide, bi-directional port. The corresponding Data Direction register is TRISC. Setting a
TRISC bit (= 1) will make the corresponding PORTC
pin an input (i.e., put the corresponding output driver in
a Hi-Impedance mode). Clearing a TRISC bit (= 0) will
make the corresponding PORTC pin an output (i.e., put
the contents of the output latch on the selected pin).
The Data Latch register (LATC) is also memory
mapped. Read-modify-write operations on the LATC
register reads and writes the latched output value for
PORTC.
PORTC is multiplexed with several peripheral functions
(Table 9-5). PORTC pins have Schmitt Trigger input
buffers.
EXAMPLE 9-3:
CLRF
CLRF
INITIALIZING PORTC
PORTC
;
;
;
;
;
;
;
;
;
;
;
;
LATC
MOVLW 0xCF
MOVWF TRISC
Initialize PORTC by
clearing output
data latches
Alternate method
to clear output
data latches
Value used to
initialize data
direction
Set RC<3:0> as inputs
RC<5:4> as outputs
RC<7:6> as inputs
FIGURE 9-7:
RD LATC
Data Bus
WR LATC or
WR PORTC
Data Latch
D
CK
Q
Q
P
1
I/O pin(1)
TRIS Latch
D
Q
WR TRISC
CK
RD TRISC
VSS
Schmitt
Trigger
Peripheral Output
Enable(3)
Q
D
EN
RD PORTC
Peripheral Data In
Note 1:
2:
Port/Peripheral Select signal selects between port data (input) and peripheral output.
3:
Advance Information
DS39564A-page 91
PIC18FXX2
TABLE 9-5:
PORTC FUNCTIONS
Name
Bit#
Buffer Type
Function
RC0/T1OSO/T1CKI
bit0
ST
RC1/T1OSI/CCP2
bit1
ST
RC2/CCP1
bit2
ST
RC3/SCK/SCL
bit3
ST
RC3 can also be the synchronous serial clock for both SPI and I2C
modes.
RC4/SDI/SDA
bit4
ST
RC4 can also be the SPI Data In (SPI mode) or Data I/O (I2C mode).
RC5/SDO
bit5
ST
RC6/TX/CK
bit6
ST
RC7/RX/DT
bit7
ST
TABLE 9-6:
Name
PORTC
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR,
BOR
Value on all
other
RESETS
RC7
RC6
RC5
RC4
RC3
RC2
RC1
RC0
xxxx xxxx
uuuu uuuu
LATC
xxxx xxxx
uuuu uuuu
TRISC
1111 1111
1111 1111
DS39564A-page 92
Advance Information
PIC18FXX2
9.4
FIGURE 9-8:
RD LATD
Data
Bus
I/O pin(1)
WR LATD
or
PORTD
CK
Data Latch
D
WR TRISD
EXAMPLE 9-4:
CLRF
PORTD
CLRF
LATD
MOVLW 0xCF
MOVWF TRISD
Schmitt
Trigger
Input
Buffer
CK
RD TRISD
Q
PORTD can be configured as an 8-bit wide microprocessor port (parallel slave port) by setting control bit
PSPMODE (TRISE<4>). In this mode, the input buffers
are TTL. See Section 9.6 for additional information on
the Parallel Slave Port (PSP).
TRIS Latch
PORTD is an 8-bit port with Schmitt Trigger input buffers. Each pin is individually configurable as an input or
output.
Note:
D
EN
EN
RD PORTD
Note 1:
INITIALIZING PORTD
;
;
;
;
;
;
;
;
;
;
;
;
Initialize PORTD by
clearing output
data latches
Alternate method
to clear output
data latches
Value used to
initialize data
direction
Set RD<3:0> as inputs
RD<5:4> as outputs
RD<7:6> as inputs
Advance Information
DS39564A-page 93
PIC18FXX2
TABLE 9-7:
PORTD FUNCTIONS
Name
Bit#
Buffer Type
Function
RD0/PSP0
bit0
ST/TTL(1)
RD1/PSP1
bit1
ST/TTL(1)
RD2/PSP2
bit2
ST/TTL
(1)
RD3/PSP3
bit3
ST/TTL(1)
RD4/PSP4
bit4
ST/TTL(1)
RD5/PSP5
bit5
ST/TTL(1)
RD6/PSP6
bit6
ST/TTL
(1)
RD7/PSP7
bit7
ST/TTL(1)
TABLE 9-8:
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR,
BOR
Value on all
other RESETS
PORTD
RD7
RD6
RD5
RD4
RD3
RD2
RD1
RD0
xxxx xxxx
uuuu uuuu
LATD
xxxx xxxx
uuuu uuuu
TRISD
1111 1111
1111 1111
0000 -111
0000 -111
TRISE
IBF
OBF
IBOV
PSPMODE
Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by PORTD.
DS39564A-page 94
Advance Information
PIC18FXX2
9.5
FIGURE 9-9:
RD LATE
Data
Bus
Q
I/O pin(1)
WR LATE
or
PORTE
CK
Data Latch
D
WR TRISE
TRIS Latch
RD TRISE
Q
Register 9-1 shows the TRISE register, which also controls the parallel slave port operation.
PORTE pins are multiplexed with analog inputs. When
selected as an analog input, these pins will read as 0s.
TRISE controls the direction of the RE pins, even when
they are being used as analog inputs. The user must
make sure to keep the pins configured as inputs when
using them as analog inputs.
Note:
Schmitt
Trigger
Input
Buffer
CK
D
EN
EN
RD PORTE
To Analog Converter
Note 1:
EXAMPLE 9-5:
CLRF
PORTE
CLRF
LATE
MOVLW
MOVWF
MOVLW
0x07
ADCON1
0x03
MOVWF
TRISC
INITIALIZING PORTE
;
;
;
;
;
;
;
;
;
;
;
;
;
;
Initialize PORTE by
clearing output
data latches
Alternate method
to clear output
data latches
Configure A/D
for digital inputs
Value used to
initialize data
direction
Set RE<0> as inputs
RE<1> as outputs
RE<2> as inputs
Advance Information
DS39564A-page 95
PIC18FXX2
REGISTER 9-1:
TRISE REGISTER
R-0
R-0
R/W-0
R/W-0
U-0
R/W-1
R/W-1
R/W-1
IBF
OBF
IBOV
PSPMODE
TRISE2
TRISE1
TRISE0
bit 7
bit 0
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
DS39564A-page 96
W = Writable bit
- n = Value at POR
1 = Bit is set
0 = Bit is cleared
Advance Information
x = Bit is unknown
PIC18FXX2
TABLE 9-9:
PORTE FUNCTIONS
Name
Bit#
RE0/RD/AN5
RE1/WR/AN6
RE2/CS/AN7
Buffer Type
ST/TTL(1)
bit2
Input/output port pin or write control input in Parallel Slave Port mode
or analog input:
WR
1 = Not a write operation
0 = Write operation. Writes PORTD register (if chip selected).
ST/TTL(1)
bit1
Input/output port pin or read control input in Parallel Slave Port mode
or analog input:
RD
1 = Not a read operation
0 = Read operation. Reads PORTD register (if chip selected).
ST/TTL(1)
bit0
Function
Input/output port pin or chip select control input in Parallel Slave Port
mode or analog input:
CS
1 = Device is not selected
0 = Device is selected
TABLE 9-10:
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR,
BOR
Value on all
other
RESETS
RE2
RE1
RE0
PORTE
---- -000
---- -000
LATE
---- -xxx
---- -uuu
TRISE
IBF
OBF
IBOV
PSPMODE
0000 -111
0000 -111
ADFM
ADCS2
PCFG3
00-- 0000
00-- 0000
ADCON1
PCFG2
PCFG1
PCFG0
Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by PORTE.
Advance Information
DS39564A-page 97
PIC18FXX2
9.6
FIGURE 9-10:
Data Bus
D
WR LATD
or
PORTD
RDx
Pin
CK
TTL
Data Latch
Q
RD PORTD
D
EN
EN
TRIS Latch
RD LATD
PSPIF (PIR1<7>)
Read
TTL
RD
Chip Select
TTL
CS
Write
WR
TTL
FIGURE 9-11:
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
CS
WR
RD
PORTD<7:0>
IBF
OBF
PSPIF
DS39564A-page 98
Advance Information
PIC18FXX2
FIGURE 9-12:
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
CS
WR
RD
PORTD<7:0>
IBF
OBF
PSPIF
TABLE 9-11:
Value on all
other
RESETS
xxxx xxxx
uuuu uuuu
LATD
xxxx xxxx
uuuu uuuu
TRISD
1111 1111
1111 1111
---- -000
---- -000
Name
PORTD
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
LATE
---- -xxx
---- -uuu
IBF
OBF
IBOV
PSPMODE
0000 -111
0000 -111
GIE/
GIEH
PEIE/
GIEL
0000 000x
0000 000u
INTCON
TMR0IF
INT0IE
RBIE
TMR0IF
RE1
Bit 0
PORTE
TRISE
RE2
Bit 1
INT0IF
RE0
RBIF
PIR1
PSPIF
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
0000 0000
0000 0000
PIE1
PSPIE
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
0000 0000
0000 0000
IPR1
PSPIP
ADIP
RCIP
TXIP
SSPIP
CCP1IP
TMR2IP
TMR1IP
0000 0000
0000 0000
ADCON1
ADFM
ADCS2
PCFG3
PCFG2
PCFG1
PCFG0
00-- 0000
00-- 0000
Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by the Parallel Slave Port.
Advance Information
DS39564A-page 99
PIC18FXX2
NOTES:
DS39564A-page 100
Advance Information
PIC18FXX2
10.0
TIMER0 MODULE
REGISTER 10-1:
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
TMR0ON
T08BIT
T0CS
T0SE
PSA
T0PS2
T0PS1
T0PS0
bit 7
bit 0
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2-0
W = Writable bit
1 = Bit is set
0 = Bit is cleared
Advance Information
x = Bit is unknown
DS39564A-page 101
PIC18FXX2
FIGURE 10-1:
0
8
0
1
RA4/T0CKI pin
Programmable
Prescaler
Sync with
Internal
Clocks
TMR0
(2 TCY delay)
T0SE
PSA
Set Interrupt
Flag bit TMR0IF
on Overflow
Note:
Upon RESET, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale.
FIGURE 10-2:
FOSC/4
0
0
1
Programmable
Prescaler
T0CKI pin
T0SE
Sync with
Internal
Clocks
TMR0L
TMR0
High Byte
8
(2 TCY delay)
Set Interrupt
Flag bit TMR0IF
on Overflow
Read TMR0L
Write TMR0L
8
8
TMR0H
8
Data Bus<7:0>
Note:
Upon RESET, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale.
DS39564A-page 102
Advance Information
PIC18FXX2
10.1
Timer0 Operation
10.2.1
The prescaler assignment is fully under software control, (i.e., it can be changed on-the-fly during program
execution).
10.3
10.4
Prescaler
The PSA and T0PS2:T0PS0 bits determine the prescaler assignment and prescale ratio.
Clearing bit PSA will assign the prescaler to the Timer0
module. When the prescaler is assigned to the Timer0
module, prescale values of 1:2, 1:4,..., 1:256 are
selectable.
TABLE 10-1:
Name
Note:
Timer0 Interrupt
The TMR0 interrupt is generated when the TMR0 register overflows from FFh to 00h in 8-bit mode, or FFFFh
to 0000h in 16-bit mode. This overflow sets the TMR0IF
bit. The interrupt can be masked by clearing the
TMR0IE bit. The TMR0IE bit must be cleared in software by the Timer0 module Interrupt Service Routine
before re-enabling this interrupt. The TMR0 interrupt
cannot awaken the processor from SLEEP, since the
timer is shut-off during SLEEP.
10.2
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on all
other
RESETS
TMR0L
xxxx xxxx
uuuu uuuu
TMR0H
0000 0000
0000 0000
INTCON
GIE/GIEH
PEIE/GIEL
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
0000 000x
0000 000u
T0CON
TMR0ON
T08BIT
T0CS
T0SE
PSA
T0PS2
T0PS1
T0PS0
1111 1111
1111 1111
TRISA
-111 1111
-111 1111
Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by Timer0.
Advance Information
DS39564A-page 103
PIC18FXX2
NOTES:
DS39564A-page 104
Advance Information
PIC18FXX2
11.0
TIMER1 MODULE
REGISTER 11-1:
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RD16
T1CKPS1
T1CKPS0
T1OSCEN
T1SYNC
TMR1CS
TMR1ON
bit 7
bit 0
bit 7
bit 6
bit 5-4
bit 3
bit 2
bit 1
bit 0
W = Writable bit
1 = Bit is set
0 = Bit is cleared
Advance Information
x = Bit is unknown
DS39564A-page 105
PIC18FXX2
11.1
Timer1 Operation
When TMR1CS = 0, Timer1 increments every instruction cycle. When TMR1CS = 1, Timer1 increments on
every rising edge of the external clock input or the
Timer1 oscillator, if enabled.
FIGURE 11-1:
TMR1IF
Overflow
Interrupt
Flag Bit
TMR1
CLR
TMR1L
TMR1H
1
TMR1ON
On/Off
T1OSC
T1CKI/T1OSO
T1OSCEN
Enable
Oscillator(1)
T1OSI
Synchronized
Clock Input
T1SYNC
Synchronize
Prescaler
1, 2, 4, 8
FOSC/4
Internal
Clock
det
0
2
T1CKPS1:T1CKPS0
SLEEP Input
TMR1CS
Note 1: When enable bit T1OSCEN is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.
FIGURE 11-2:
Data Bus<7:0>
8
TMR1H
8
Write TMR1L
Read TMR1L
TMR1IF
Overflow
Interrupt
Flag bit
TMR1
8
Timer 1
High Byte
TMR1L
1
TMR1ON
on/off
T1OSC
T13CKI/T1OSO
T1OSI
Synchronized
Clock Input
0
CLR
T1SYNC
1
T1OSCEN
Enable
Oscillator(1)
FOSC/4
Internal
Clock
Synchronize
Prescaler
1, 2, 4, 8
det
0
2
SLEEP Input
TMR1CS
T1CKPS1:T1CKPS0
Note 1: When enable bit T1OSCEN is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.
DS39564A-page 106
Advance Information
PIC18FXX2
11.2
Timer1 Oscillator
11.4
TABLE 11-1:
Timer1 must be configured for either Timer or Synchronized Counter mode to take advantage of this feature.
If Timer1 is running in Asynchronous Counter mode,
this RESET operation may not work.
Osc Type
Freq
C1
C2
LP
32 kHz
TBD(1)
TBD(1)
20 PPM
In this mode of operation, the CCPR1H:CCPR1L registers pair effectively becomes the period register for
Timer1.
Crystal to be Tested:
32.768 kHz
Epson C-001R32.768K-A
11.3
Timer1 Interrupt
11.5
Advance Information
DS39564A-page 107
PIC18FXX2
TABLE 11-2:
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
all other
RESETS
INTCON
GIE/GIEH PEIE/GIEL
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
PIR1
PSPIF(1)
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
PIE1
PSPIE(1)
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
IPR1
PSPIP(1)
ADIP
RCIP
TXIP
SSPIP
CCP1IP
TMR2IP
RBIF
TMR1L
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
TMR1H
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
T1CON
RD16
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0-00 0000 u-uu uuuu
Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by the Timer1 module.
Note 1: The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18F2X2 devices; always maintain these bits clear.
DS39564A-page 108
Advance Information
PIC18FXX2
12.0
TIMER2 MODULE
12.1
REGISTER 12-1:
Timer2 Operation
R/W-0
R/W-0
R/W-0
R/W-0
TOUTPS3
TOUTPS2
TOUTPS1
TOUTPS0
R/W-0
R/W-0
TMR2ON T2CKPS1
R/W-0
T2CKPS0
bit 7
bit 0
bit 7
bit 6-3
bit 2
bit 1-0
W = Writable bit
1 = Bit is set
0 = Bit is cleared
Advance Information
x = Bit is unknown
DS39564A-page 109
PIC18FXX2
12.2
Timer2 Interrupt
12.3
FIGURE 12-1:
Output of TMR2
TMR2
Output(1)
Prescaler
1:1, 1:4, 1:16
FOSC/4
TMR2
RESET
Comparator
EQ
Postscaler
1:1 to 1:16
T2CKPS1:T2CKPS0
4
PR2
TOUTPS3:TOUTPS0
Note 1: TMR2 register output can be software selected by the SSP Module as a baud clock.
TABLE 12-1:
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
all other
RESETS
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
PIR1
PSPIF(1)
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
PIE1
PSPIE(1)
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
IPR1
PSPIP(1)
ADIP
RCIP
TXIP
SSPIP
CCP1IP
TMR2IP
TMR1IP
TMR2
T2CON
PR2
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by the Timer2 module.
Note 1: The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18F2X2 devices; always maintain these bits clear.
DS39564A-page 110
Advance Information
PIC18FXX2
13.0
TIMER3 MODULE
REGISTER 13-1:
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RD16
T3CCP2
T3CKPS1
T3CKPS0
T3CCP1
T3SYNC
TMR3CS
TMR3ON
bit 7
bit 0
bit 7
bit 6-3
bit 5-4
bit 2
bit 1
bit 0
W = Writable bit
1 = Bit is set
0 = Bit is cleared
Advance Information
x = Bit is unknown
DS39564A-page 111
PIC18FXX2
13.1
Timer3 Operation
When TMR3CS = 0, Timer3 increments every instruction cycle. When TMR3CS = 1, Timer3 increments on
every rising edge of the Timer1 external clock input or
the Timer1 oscillator, if enabled.
FIGURE 13-1:
TMR3IF
Overflow
Interrupt
Flag bit
TMR3H
Synchronized
Clock Input
CLR
TMR3L
1
TMR3ON
On/Off
T1OSC
T1OSO/
T13CKI
T3SYNC
(3)
T1OSI
Synchronize
Prescaler
1, 2, 4, 8
T1OSCEN FOSC/4
Enable
Internal
Oscillator(1) Clock
det
0
2
SLEEP Input
TMR3CS
T3CKPS1:T3CKPS0
Note 1: When enable bit T1OSCEN is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.
FIGURE 13-2:
Data Bus<7:0>
8
TMR3H
8
8
Write TMR3L
Read TMR3L
Set TMR3IF Flag bit
on Overflow
TMR3
Timer3
High Byte
TMR3L
CLR
Synchronized
Clock Input
1
To Timer1 Clock Input
T1OSO/
T13CKI
T1OSI
TMR3ON
On/Off
T1OSC
T3SYNC
1
T1OSCEN
Enable
Oscillator(1)
FOSC/4
Internal
Clock
Synchronize
Prescaler
1, 2, 4, 8
det
0
2
T3CKPS1:T3CKPS0
TMR3CS
SLEEP Input
Note 1: When the T1OSCEN bit is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.
DS39564A-page 112
Advance Information
PIC18FXX2
13.2
Timer1 Oscillator
13.4
13.3
Timer3 Interrupt
TABLE 13-1:
Timer3 must be configured for either Timer or Synchronized Counter mode to take advantage of this feature.
If Timer3 is running in Asynchronous Counter mode,
this RESET operation may not work. In the event that a
write to Timer3 coincides with a special event trigger
from CCP1, the write will take precedence. In this mode
of operation, the CCPR1H:CCPR1L registers pair
effectively becomes the period register for Timer3.
Value on
all other
RESETS
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
GIE/
GIEH
PEIE/
GIEL
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
PIR2
EEIF
BCLIF
LVDIF
TMR3IF
CCP2IF
PIE2
EEIE
BCLIE
LVDIE
TMR3IE
CCP2IE
EEIP
BCLIP
LVDIP
TMR3IP
CCP2IP
IPR2
TMR3L
Holding Register for the Least Significant Byte of the 16-bit TMR3 Register
TMR3H
Holding Register for the Most Significant Byte of the 16-bit TMR3 Register
T1CON
T3CON
Legend:
RD16
RD16
T3CCP2
T1SYNC
T3CKPS1 T3CKPS0
T3SYNC
T3CCP1
x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by the Timer1 module.
Advance Information
DS39564A-page 113
PIC18FXX2
NOTES:
DS39564A-page 114
Advance Information
PIC18FXX2
14.0
CAPTURE/COMPARE/PWM
(CCP) MODULES
REGISTER 14-1:
U-0
R/W-0
R/W-0
R/W-0
R/W-0
DCxB1
DCxB0
CCPxM3
CCPxM2
R/W-0
R/W-0
CCPxM1 CCPxM0
bit 7
bit 0
bit 7-6
bit 5-4
bit 3-0
W = Writable bit
1 = Bit is set
0 = Bit is cleared
Advance Information
x = Bit is unknown
DS39564A-page 115
PIC18FXX2
14.1
CCP1 Module
14.2
Capture/Compare/PWM Register 1 (CCPR1) is comprised of two 8-bit registers: CCPR1L (low byte) and
CCPR1H (high byte). The CCP1CON register controls
the operation of CCP1. All are readable and writable.
TABLE 14-1:
CCP2 Module
Capture/Compare/PWM Register2 (CCPR2) is comprised of two 8-bit registers: CCPR2L (low byte) and
CCPR2H (high byte). The CCP2CON register controls
the operation of CCP2. All are readable and writable.
CCP Mode
Timer Resource
Capture
Compare
PWM
Timer1 or Timer3
Timer1 or Timer3
Timer2
TABLE 14-2:
Interaction
Capture
Capture
Capture
Compare
Compare
Compare
PWM
PWM
PWM
Capture
None
PWM
Compare
None
DS39564A-page 116
The PWMs will have the same frequency and update rate
(TMR2 interrupt).
Advance Information
PIC18FXX2
14.3
14.3.3
Capture Mode
In Capture mode, the RC2/CCP1 pin should be configured as an input by setting the TRISC<2> bit.
Note:
14.3.2
If the RC2/CCP1 is configured as an output, a write to the port can cause a capture
condition.
FIGURE 14-1:
14.3.4
14.3.1
SOFTWARE INTERRUPT
CCP PRESCALER
EXAMPLE 14-1:
CLRF
MOVLW
MOVWF
CHANGING BETWEEN
CAPTURE PRESCALERS
TMR3L
Prescaler
1, 4, 16
CCP1 pin
TMR3
Enable
CCPR1H
and
Edge Detect
T3CCP2
CCPR1L
TMR1
Enable
TMR1H
TMR1L
TMR3H
TMR3L
CCP1CON<3:0>
Qs
Set Flag bit CCP2IF
T3CCP1
T3CCP2
TMR3
Enable
Prescaler
1, 4, 16
CCP2 pin
CCPR2H
and
Edge Detect
CCPR2L
TMR1
Enable
T3CCP2
T3CCP1
TMR1H
TMR1L
CCP2CON<3:0>
Qs
Advance Information
DS39564A-page 117
PIC18FXX2
14.4
14.4.2
Compare Mode
14.4.3
driven High
driven Low
toggle output (High to Low or Low to High)
remains unchanged
14.4.4
14.4.1
FIGURE 14-2:
S
R
TRISC<2>
Output Enable
Output
Logic
Comparator
Match
CCP1CON<3:0>
Mode Select
T3CCP2
TMR1H
TMR1L
TMR3H
TMR3L
Q
RC1/CCP2 pin
TRISC<1>
Output Enable
DS39564A-page 118
S
R
Output
Logic
T3CCP1
T3CCP2
Comparator
Match
CCPR2H CCPR2L
CCP2CON<3:0>
Mode Select
Advance Information
PIC18FXX2
TABLE 14-3:
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR,
BOR
Value on
all other
RESETS
INTCON
GIE/GIEH PEIE/GIEL
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
PIR1
PSPIF(1)
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
PIE1
PSPIE
(1)
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
IPR1
PSPIP(1)
ADIP
RCIP
TXIP
SSPIP
CCP1IP
TMR2IP
TMR1IP
TRISC
TMR1L
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
TMR1H
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
T1CON
RD16
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0-00 0000 u-uu uuuu
CCPR1L
CCPR1H
CCP1CON
DC1B1
DC1B0
CCPR2L
CCPR2H
CCP1M3
CCP2CON
DC2B1
DC2B0
CCP2M3
PIR2
EEIE
BCLIF
LVDIF
TMR3IF
CCP2IF
PIE2
EEIF
BCLIE
LVDIE
TMR3IE
CCP2IE
IPR2
EEIP
BCLIP
LVDIP
TMR3IP
CCP2IP
TMR3L
Holding Register for the Least Significant Byte of the 16-bit TMR3 Register
TMR3H
Holding Register for the Most Significant Byte of the 16-bit TMR3 Register
T3CON
RD16
T3CCP2
T3CKPS1 T3CKPS0
T3CCP1
Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by Capture and Timer1.
Note 1: The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18F2x2 devices; always maintain these bits clear.
Advance Information
DS39564A-page 119
PIC18FXX2
14.5
14.5.1
PWM Mode
FIGURE 14-3:
The PWM period is specified by writing to the PR2 register. The PWM period can be calculated using the following formula:
PWM period = (PR2) + 1] 4 TOSC
(TMR2 prescale value)
PWM frequency is defined as 1 / [PWM period].
When TMR2 is equal to PR2, the following three events
occur on the next increment cycle:
TMR2 is cleared
The CCP1 pin is set (exception: if PWM duty
cycle = 0%, the CCP1 pin will not be set)
The PWM duty cycle is latched from CCPR1L into
CCPR1H
Note:
CCP1CON<5:4>
PWM PERIOD
CCPR1L
14.5.2
CCPR1H (Slave)
Comparator
Q
RC2/CCP1
TMR2
(Note 1)
S
TRISC<2>
Comparator
Clear Timer,
CCP1 pin and
latch D.C.
PR2
FIGURE 14-4:
PWM OUTPUT
Period
Duty Cycle
TMR2 = PR2
TMR2 = Duty Cycle
Note:
TMR2 = PR2
DS39564A-page 120
Advance Information
PIC18FXX2
14.5.3
3.
4.
1.
2.
5.
TABLE 14-4:
PWM Frequency
2.44 kHz
9.77 kHz
39.06 kHz
156.25 kHz
312.50 kHz
416.67 kHz
TABLE 14-5:
16
0xFF
PR2 Value
Name
0xFF
0xFF
0x3F
0x1F
0x17
14
12
10
6.58
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR,
BOR
Value on
all other
RESETS
INTCON
GIE/GIEH PEIE/GIEL
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
PIR1
PSPIF(1)
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
PIE1
PSPIE(1)
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
IPR1
PSPIP(1)
ADIP
RCIP
TXIP
SSPIP
CCP1IP
TMR2IP
TMR1IP
TRISC
TMR2
PR2
T2CON
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
CCPR1L
CCPR1H
CCP1CON
DC1B1
DC1B0
CCPR2L
CCP1M3
CCP1M2
CCP1M1
CCPR2H
CCP2CON
DC2B1
DC2B0
CCP2M3
CCP2M2
CCP2M1
Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by PWM and Timer2.
Note 1: The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18F2X2 devices; always maintain these bits clear.
Advance Information
DS39564A-page 121
PIC18FXX2
NOTES:
DS39564A-page 122
Advance Information
PIC18FXX2
15.0
15.1
MASTER SYNCHRONOUS
SERIAL PORT (MSSP)
MODULE
Master SSP (MSSP) Module
Overview
15.3
SPI Mode
FIGURE 15-1:
Internal
Data Bus
Master mode
Multi-Master mode
Slave mode
15.2
Read
Write
SSPBUF reg
Control Registers
RC4/SDI/SDA
SSPSR reg
shift
clock
RC5/SDO
bit0
RA5/SS/AN4
SS Control
Enable
Edge
Select
2
Clock Select
RC3/SCK/
SCL/LVDIN
SSPM3:SSPM0
SMP:CKE 4
TMR2 output
2
2
Edge
Select
Prescaler TOSC
4, 16, 64
Advance Information
DS39564A-page 123
PIC18FXX2
15.3.1
REGISTERS
REGISTER 15-1:
R/W-0
R-0
R-0
R-0
R-0
R-0
R-0
SMP
CKE
D/A
R/W
UA
BF
bit 7
bit 0
bit 7
bit 6
bit 5
bit 4
P: STOP bit
Used in I2C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is
cleared.
bit 3
S: START bit
Used in I2C mode only
bit 2
bit 1
bit 0
- n = Value at POR
DS39564A-page 124
W = Writable bit
1 = Bit is set
0 = Bit is cleared
Advance Information
x = Bit is unknown
PIC18FXX2
REGISTER 15-2:
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
WCOL
SSPOV
SSPEN
CKP
SSPM3
SSPM2
SSPM1
SSPM0
bit 7
bit 0
bit 7
bit 6
bit 5
In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the SSPBUF register.
bit 4
bit 3-0
Bit combinations not specifically listed here are either reserved, or implemented in
I2C mode only.
Legend:
R = Readable bit
W = Writable bit
- n = Value at POR
1 = Bit is set
0 = Bit is cleared
Advance Information
x = Bit is unknown
DS39564A-page 125
PIC18FXX2
15.3.2
OPERATION
EXAMPLE 15-1:
MOVWF RXDATA
MOVF TXDATA, W
MOVWF SSPBUF
DS39564A-page 126
Advance Information
PIC18FXX2
15.3.3
15.3.4
TYPICAL CONNECTION
Any serial port function that is not desired may be overridden by programming the corresponding data direction (TRIS) register to the opposite value.
FIGURE 15-2:
SDI
SDI
Shift Register
(SSPSR)
MSb
SDO
LSb
MSb
SCK
Serial Clock
LSb
SCK
PROCESSOR 1
Shift Register
(SSPSR)
PROCESSOR 2
Advance Information
DS39564A-page 127
PIC18FXX2
15.3.5
MASTER MODE
The clock polarity is selected by appropriately programming the CKP bit (SSPCON1<4>). This then, would
give waveforms for SPI communication as shown in
FIGURE 15-3:
Write to
SSPBUF
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
4 Clock
Modes
SCK
(CKP = 0
CKE = 1)
SCK
(CKP = 1
CKE = 1)
SDO
(CKE = 0)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
SDO
(CKE = 1)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
SDI
(SMP = 0)
bit0
bit7
Input
Sample
(SMP = 0)
SDI
(SMP = 1)
bit0
bit7
Input
Sample
(SMP = 1)
SSPIF
Next Q4 cycle
after Q2
SSPSR to
SSPBUF
DS39564A-page 128
Advance Information
PIC18FXX2
15.3.6
SLAVE MODE
the SDO pin is no longer driven, even if in the middle of a transmitted byte, and becomes a floating
output. External pull-up/ pull-down resistors may be
desirable, depending on the application.
Note 1: When the SPI is in Slave mode with SS
pin control enabled (SSPCON<3:0> =
0100), the SPI module will reset if the SS
pin is set to VDD.
2: If the SPI is used in Slave mode with CKE
set, then the SS pin control must be
enabled.
15.3.7
SLAVE SELECT
SYNCHRONIZATION
FIGURE 15-4:
SS
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
Write to
SSPBUF
SDO
SDI
(SMP = 0)
bit7
bit6
bit7
bit0
bit0
bit7
bit7
Input
Sample
(SMP = 0)
SSPIF
Interrupt
Flag
Next Q4 cycle
after Q2
SSPSR to
SSPBUF
Advance Information
DS39564A-page 129
PIC18FXX2
FIGURE 15-5:
SS
Optional
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
Write to
SSPBUF
SDO
SDI
(SMP = 0)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
bit0
bit7
Input
Sample
(SMP = 0)
SSPIF
Interrupt
Flag
Next Q4 cycle
after Q2
SSPSR to
SSPBUF
FIGURE 15-6:
SS
Not Optional
SCK
(CKP = 0
CKE = 1)
SCK
(CKP = 1
CKE = 1)
Write to
SSPBUF
SDO
SDI
(SMP = 0)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
bit0
bit7
Input
Sample
(SMP = 0)
SSPIF
Interrupt
Flag
Next Q4 cycle
after Q2
SSPSR to
SSPBUF
DS39564A-page 130
Advance Information
PIC18FXX2
15.3.8
SLEEP OPERATION
15.3.10
TABLE 15-1:
15.3.9
0,
0,
1,
1,
CKE
0
0
1
1
0
1
0
1
1
0
1
0
Name
EFFECTS OF A RESET
TABLE 15-2:
Value on
all other
RESETS
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
GIE/GIEH
PEIE/
GIEL
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
PIR1
PSPIF(1)
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
PIE1
PSPIE(1)
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
IPR1
PSPIP(1)
ADIP
RCIP
TXIP
SSPIP
CCP1IP
TMR2IP
TMR1IP
TRISC
SSPBUF
SSPCON
TRISA
SSPSTAT
WCOL
SMP
SSPOV
SSPEN
CKP
SSPM3
SSPM2
SSPM1
SSPM0
D/A
R/W
UA
BF
Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by the MSSP in SPI mode.
Note 1: The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18C2X2 devices; always maintain these bits clear.
Advance Information
DS39564A-page 131
PIC18FXX2
15.4
I2C Mode
15.4.1
FIGURE 15-7:
Write
Shift
Clock
LSb
MSb
Match Detect
Addr Match
During transmission, the SSPBUF is not double buffered. A write to SSPBUF will write to both SSPBUF and
SSPSR.
SSPADD reg
START and
STOP bit Detect
DS39564A-page 132
SSPSR reg
RC4/
SDI/
SDA
SSPBUF reg
RC3/SCK/SCL
REGISTERS
Set, Reset
S, P bits
(SSPSTAT reg)
Advance Information
PIC18FXX2
REGISTER 15-3:
R/W-0
R-0
R-0
R-0
R-0
R-0
R-0
SMP
CKE
D/A
R/W
UA
BF
bit 7
bit 0
bit 7
bit 6
bit 5
bit 4
P: STOP bit
1 = Indicates that a STOP bit has been detected last
0 = STOP bit was not detected last
Note:
This bit is cleared on RESET and when SSPEN is cleared.
bit 3
S: START bit
1 = Indicates that a start bit has been detected last
0 = START bit was not detected last
Note:
This bit is cleared on RESET and when SSPEN is cleared.
bit 2
bit 1
bit 0
W = Writable bit
- n = Value at POR
1 = Bit is set
0 = Bit is cleared
Advance Information
x = Bit is unknown
DS39564A-page 133
PIC18FXX2
REGISTER 15-4:
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
WCOL
SSPOV
SSPEN
CKP
SSPM3
SSPM2
SSPM1
SSPM0
bit 7
bit 0
bit 7
bit 6
bit 5
When enabled, the SDA and SCL pins must be properly configured as input or output.
bit 4
bit 3-0
Bit combinations not specifically listed here are either reserved, or implemented in
SPI mode only.
Legend:
R = Readable bit
- n = Value at POR
DS39564A-page 134
W = Writable bit
1 = Bit is set
0 = Bit is cleared
Advance Information
x = Bit is unknown
PIC18FXX2
REGISTER 15-5:
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
GCEN
ACKSTAT
ACKDT
ACKEN
RCEN
PEN
RSEN
SEN
bit 7
bit 0
bit 7
bit 6
bit 5
Value that will be transmitted when the user initiates an Acknowledge sequence at
the end of a receive.
bit 4
bit 3
bit 2
bit 1
bit 0
For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I2C module is not in the IDLE
mode, this bit may not be set (no spooling) and the SSPBUF may not be written (or
writes to the SSPBUF are disabled).
Legend:
R = Readable bit
W = Writable bit
1 = Bit is set
0 = Bit is cleared
Advance Information
x = Bit is unknown
DS39564A-page 135
PIC18FXX2
15.4.2
OPERATION
15.4.3.1
15.4.3
SLAVE MODE
In Slave mode, the SCL and SDA pins must be configured as inputs (TRISC<4:3> set). The MSSP module
will override the input state with the output data when
required (slave-transmitter).
1.
2.
3.
4.
5.
2C
Addressing
6.
7.
8.
9.
DS39564A-page 136
Advance Information
PIC18FXX2
15.4.3.2
Reception
15.4.3.3
Transmission
Advance Information
DS39564A-page 137
DS39564A-page 138
Advance Information
CKP
A6
A4
A3
Receiving Address
A5
A2
SSPOV (SSPCON<6>)
BF (SSPSTAT<0>)
(PIR1<3>)
SSPIF
A7
A1
ACK
R/W = 0
D7
D4
D3
Receiving Data
D5
Cleared in software
SSPBUF is read
D6
D2
D1
D0
ACK
D7
D6
D4
D3
Receiving Data
D5
D2
D1
D0
Bus Master
terminates
transfer
SSPOV is set
because SSPBUF is
still full. ACK is not sent.
ACK
FIGURE 15-8:
SCL
SDA
PIC18FXX2
I2C SLAVE MODE TIMING WITH SEN = 0 (RECEPTION 7-BIT ADDRESS)
Advance Information
CKP
A6
Data in
sampled
BF (SSPSTAT<0>)
SSPIF (PIR1<3>)
A7
A5
A4
A3
A2
Receiving Address
A1
R/W = 1
ACK
D7
D5
D4
D3
D2
Cleared in software
D6
Transmitting Data
D0
ACK
D1
D7
D4
D3
D2
D0
ACK
D1
Transmitting Data
Cleared in software
D5
D6
FIGURE 15-9:
SCL
SDA
PIC18FXX2
DS39564A-page 139
DS39564A-page 140
Advance Information
A9 A8
UA (SSPSTAT<1>)
SSPOV (SSPCON<6>)
CKP
Cleared in software
BF (SSPSTAT<0>)
(PIR1<3>)
SSPIF
SCL
ACK
R/W = 0
A7
A4
A3
A0 ACK
Cleared by hardware
when SSPADD is updated
with low byte of address
A2 A1
Cleared in software
A5
A6
D7
Cleared in software
9
1
Cleared in software
D3 D2
D3 D2
D1 D0
P
Bus Master
terminates
transfer
SSPOV is set
because SSPBUF is
still full. ACK is not sent.
ACK
FIGURE 15-10:
SDA
PIC18FXX2
I2C SLAVE MODE TIMING WITH SEN = 0 (RECEPTION 10-BIT ADDRESS)
Advance Information
CKP (SSPCON<4>)
UA (SSPSTAT<1>)
BF (SSPSTAT<0>)
(PIR1<3>)
SSPIF
A9 A8
ACK
Cleared in software
A6 A5 A4 A3 A2 A1
A0
A7
ACK
Cleared in software
ACK
R/W=1
Completion of
data transmission
clears BF flag
ACK
Bus Master
terminates
transfer
D4 D3 D2 D1 D0
Cleared in software
D7 D6 D5
Write of SSPBUF
BF flag is clear
initiates transmit
at the end of the
third address sequence
A9 A8
Sr
FIGURE 15-11:
SCL
SDA
R/W = 0
PIC18FXX2
DS39564A-page 141
PIC18FXX2
15.4.4
CLOCK STRETCHING
15.4.4.3
15.4.4.1
15.4.4.2
15.4.4.4
In 10-bit Slave Transmit mode, clock stretching is controlled during the first two address sequences by the
state of the UA bit, just as it is in 10-bit Slave Receive
mode. The first two addresses are followed by a third
address sequence, which contains the high order bits
of the 10-bit address and the R/W bit set to 1. After
the third address sequence is performed, the UA bit is
not set, the module is now configured in transmit
mode, and clock stretching is controlled by the BF flag,
as in 7-bit Slave Transmit mode (see Figure 15-11).
DS39564A-page 142
Advance Information
PIC18FXX2
15.4.4.5
FIGURE 15-12:
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
SDA
DX
DX-1
SCL
CKP
Master device
asserts clock
Master device
de-asserts clock
WR
SSPCON
Advance Information
DS39564A-page 143
DS39564A-page 144
Advance Information
CKP
SSPOV (SSPCON<6>)
BF (SSPSTAT<0>)
(PIR1<3>)
SSPIF
A7
A6
A4
A3
Receiving Address
A5
A2
A1
ACK
R/W = 0
D4
D3
Receiving Data
D5
Cleared in software
D6
If BF is cleared
prior to the falling
edge of the 9th clock,
CKP will not be reset
to 0 and no clock
stretching will occur
SSPBUF is read
D7
D2
D1
ACK
D7
D0
CKP
written
to 1 in
software
D6
D4
D3
Receiving Data
D5
D2
D1
D0
Bus Master
terminates
transfer
SSPOV is set
because SSPBUF is
still full. ACK is not sent.
ACK
FIGURE 15-13:
SCL
SDA
PIC18FXX2
I2C SLAVE MODE TIMING WITH SEN = 1 (RECEPTION 7-BIT ADDRESS)
Advance Information
UA (SSPSTAT<1>)
SSPOV (SSPCON<6>)
CKP
A9 A8
Cleared in software
BF (SSPSTAT<0>)
(PIR1<3>)
SSPIF
ACK
R/W = 0
A7
A4
A3
A0
Note:
A2 A1
Cleared in software
A5
A6
ACK
Cleared in software
D3 D2
Note:
ACK
D2
Cleared in software
CKP written to 1
in software
D3
D1 D0
D7 D6 D5 D4
Bus Master
terminates
transfer
SSPOV is set
because SSPBUF is
still full. ACK is not sent.
D1 D0
ACK
FIGURE 15-14:
SCL
SDA
PIC18FXX2
DS39564A-page 145
PIC18FXX2
15.4.5
When the interrupt is serviced, the source for the interrupt can be checked by reading the contents of the
SSPBUF. The value can be used to determine if the
address was device specific or a general call address.
In 10-bit mode, the SSPADD is required to be updated
for the second half of the address to match, and the UA
bit is set (SSPSTAT<1>). If the general call address is
sampled when the GCEN bit is set, while the slave is
configured in 10-bit Address mode, then the second
half of the address is not necessary, the UA bit will not
be set, and the slave will begin receiving data after the
Acknowledge (Figure 15-15).
FIGURE 15-15:
SDA
Receiving data
ACK
D6
D5
D4
D3
D2
D1
D0
SCL
S
SSPIF
BF (SSPSTAT<0>)
Cleared in software
SSPBUF is read
SSPOV (SSPCON1<6>)
GCEN (SSPCON2<7>)
DS39564A-page 146
Advance Information
PIC18FXX2
15.4.6
MASTER MODE
Note:
In Firmware Controlled Master mode, user code conducts all I 2C bus operations based on START and
STOP bit conditions.
Once Master mode is enabled, the user has six
options.
3.
4.
5.
6.
START condition
STOP condition
Data transfer byte transmitted/received
Acknowledge Transmit
Repeated START
FIGURE 15-16:
Internal
Data Bus
Read
Write
SSPBUF
Baud
Rate
Generator
Shift
Clock
SDA
SDA in
SCL in
Bus Collision
LSb
Clock Cntl
SCL
Receive Enable
SSPSR
MSb
1.
2.
Advance Information
DS39564A-page 147
PIC18FXX2
15.4.6.1
DS39564A-page 148
Advance Information
PIC18FXX2
15.4.7
FIGURE 15-17:
SSPM3:SSPM0
Reload
SCL
Control
CLKOUT
TABLE 15-3:
SSPADD<6:0>
Reload
Fosc/4
FCY
FCY*2
BRG VALUE
FSCL
(2 rollovers of BRG)
10 MHz
20 MHz
19h
400 kHz(1)
10 MHz
20 MHz
20h
312.5 kHz
10 MHz
20 MHz
3Fh
100 kHz
4 MHz
8 MHz
0Ah
400 kHz(1)
4 MHz
8 MHz
0Dh
308 kHz
4 MHz
8 MHz
28h
100 kHz
1 MHz
2 MHz
03h
333 kHz(1)
1 MHz
2 MHz
0Ah
100kHz
1 MHz
2 MHz
00h
1 MHz(1)
Note 1: The I2C interface does not conform to the 400 kHz I2C specification (which applies to rates greater than
100 kHz) in all details, but may be used with care where higher rates are required by the application.
Advance Information
DS39564A-page 149
PIC18FXX2
15.4.7.1
Clock Arbitration
FIGURE 15-18:
SDA
DX
DX-1
SCL
BRG decrements on
Q2 and Q4 cycles
BRG
Value
03h
02h
01h
03h
02h
DS39564A-page 150
Advance Information
PIC18FXX2
15.4.8
15.4.8.1
Note:
FIGURE 15-19:
TBRG
SDA
2nd bit
TBRG
SCL
TBRG
S
Advance Information
DS39564A-page 151
PIC18FXX2
15.4.9
15.4.9.1
FIGURE 15-20:
Set S (SSPSTAT<3>)
Write to SSPCON2
occurs here.
SDA = 1,
SCL (no change)
SDA = 1,
SCL = 1
TBRG
TBRG
SDA
Write to SSPBUF occurs here
TBRG
SCL
TBRG
Sr = Repeated START
DS39564A-page 152
Advance Information
PIC18FXX2
15.4.10
15.4.10.3
15.4.10.1
BF Status Flag
15.4.11
15.4.11.1
BF Status Flag
15.4.11.2
15.4.11.3
15.4.10.2
Advance Information
DS39564A-page 153
DS39564A-page 154
S
Advance Information
R/W
PEN
SEN
BF (SSPSTAT<0>)
SSPIF
SCL
SDA
A6
A5
A4
A3
A2
A1
Cleared in software
D7
1
SCL held low
while CPU
responds to SSPIF
SSPBUF written
ACK = 0
R/W = 0
A7
D5
D4
D3
D2
D1
D0
D6
Cleared in software
ACK
ACKSTAT in
SSPCON2 = 1
FIGURE 15-21:
SEN = 0
PIC18FXX2
I 2C MASTER MODE WAVEFORM (TRANSMISSION, 7 OR 10-BIT ADDRESS)
Advance Information
ACKEN
SSPOV
BF
(SSPSTAT<0>)
SDA = 0, SCL = 1
while CPU
responds to SSPIF
SSPIF
SCL
SDA
A7
4
5
Cleared in software
A6 A5 A4 A3 A2
A1
R/W = 1
ACK
D0
ACK
Cleared in software
D7 D6 D5 D4 D3 D2 D1
Cleared in
software
ACK
P
Set SSPIF interrupt
at end of Acknowledge sequence
Bus Master
terminates
transfer
Set P bit
(SSPSTAT<4>)
and SSPIF
PEN bit = 1
written here
D0
RCEN cleared
automatically
RCEN = 1 start
next receive
Cleared in software
Cleared in software
D7 D6 D5 D4 D3 D2 D1
RCEN cleared
automatically
FIGURE 15-22:
SEN = 0
Write to SSPBUF occurs here
Start XMIT
Write to SSPCON2<4>
to start Acknowledge sequence
SDA = ACKDT (SSPCON2<5>) = 0
PIC18FXX2
DS39564A-page 155
PIC18FXX2
15.4.12
ACKNOWLEDGE SEQUENCE
TIMING
15.4.13
15.4.12.1
15.4.13.1
FIGURE 15-23:
TBRG
TBRG
SDA
D0
SCL
ACK
SSPIF
Cleared in
software
Cleared in
software
Set SSPIF at the end
of Acknowledge sequence
FIGURE 15-24:
Write to SSPCON2
Set PEN
Falling edge of
9th clock
TBRG
SCL
SDA
ACK
P
TBRG
TBRG
TBRG
DS39564A-page 156
Advance Information
PIC18FXX2
15.4.14
SLEEP OPERATION
15.4.17
15.4.15
EFFECT OF A RESET
15.4.16
MULTI-MASTER MODE
Address Transfer
Data Transfer
A START Condition
A Repeated START Condition
An Acknowledge Condition
Multi-Master mode support is achieved by bus arbitration. When the master outputs address/data bits onto
the SDA pin, arbitration takes place when the master
outputs a '1' on SDA, by letting SDA float high and
another master asserts a '0'. When the SCL pin floats
high, data should be stable. If the expected data on
SDA is a '1' and the data sampled on the SDA pin = '0',
then a bus collision has taken place. The master will set
the Bus Collision Interrupt Flag BCLIF and reset the I2C
port to its IDLE state (Figure 15-25).
If a transmit was in progress when the bus collision
occurred, the transmission is halted, the BF flag is
cleared, the SDA and SCL lines are de-asserted, and
the SSPBUF can be written to. When the user services
the bus collision Interrupt Service Routine, and if the
I2C bus is free, the user can resume communication by
asserting a START condition.
If a START, Repeated START, STOP, or Acknowledge
condition was in progress when the bus collision
occurred, the condition is aborted, the SDA and SCL
lines are de-asserted, and the respective control bits in
the SSPCON2 register are cleared. When the user services the bus collision Interrupt Service Routine, and if
the I2C bus is free, the user can resume communication
by asserting a START condition.
The master will continue to monitor the SDA and SCL
pins. If a STOP condition occurs, the SSPIF bit will be set.
A write to the SSPBUF will start the transmission of
data at the first data bit, regardless of where the transmitter left off when the bus collision occurred.
In Multi-Master mode, the interrupt generation on the
detection of START and STOP conditions allows the
determination of when the bus is free. Control of the I2C
bus can be taken when the P bit is set in the SSPSTAT register, or the bus is IDLE and the S and P bits are cleared.
FIGURE 15-25:
SDA
SCL
BCLIF
Advance Information
DS39564A-page 157
PIC18FXX2
15.4.17.1
b)
FIGURE 15-26:
SDA
SCL
Set SEN, enable START
condition if SDA = 1, SCL=1
SEN
BCLIF
SSPIF
DS39564A-page 158
Advance Information
PIC18FXX2
FIGURE 15-27:
TBRG
SDA
SCL
SEN
SCL = 0 before BRG time-out,
bus collision occurs. Set BCLIF.
BCLIF
Interrupt cleared
in software
S
SSPIF
FIGURE 15-28:
SDA
Set SSPIF
TBRG
SCL
S
SCL pulled low after BRG
Time-out
SEN
BCLIF
SSPIF
SDA = 0, SCL = 1
Set SSPIF
Advance Information
Interrupts cleared
in software
DS39564A-page 159
PIC18FXX2
15.4.17.2
If SCL goes from high to low before the BRG times out
and SDA has not already been asserted, a bus collision
occurs. In this case, another master is attempting to
transmit a data 1 during the Repeated START condition, Figure 15-30.
If, at the end of the BRG time-out both SCL and SDA
are still high, the SDA pin is driven low and the BRG is
reloaded and begins counting. At the end of the count,
regardless of the status of the SCL pin, the SCL pin is
driven low and the Repeated START condition is
complete.
FIGURE 15-29:
SDA
SCL
Sample SDA when SCL goes high.
If SDA = 0, set BCLIF and release SDA and SCL.
RSEN
BCLIF
Cleared in software
'0'
'0'
SSPIF
FIGURE 15-30:
TBRG
SDA
SCL
BCLIF
RSEN
0
S
SSPIF
DS39564A-page 160
Advance Information
PIC18FXX2
15.4.17.3
b)
FIGURE 15-31:
TBRG
SDA sampled
low after TBRG,
Set BCLIF
TBRG
SDA
SDA asserted low
SCL
PEN
BCLIF
P
SSPIF
FIGURE 15-32:
TBRG
TBRG
SDA
Assert SDA
SCL
PEN
BCLIF
P
SSPIF
Advance Information
DS39564A-page 161
PIC18FXX2
NOTES:
DS39564A-page 162
Advance Information
PIC18FXX2
16.0
ADDRESSABLE UNIVERSAL
SYNCHRONOUS
ASYNCHRONOUS RECEIVER
TRANSMITTER (USART)
Advance Information
DS39564A-page 163
PIC18FXX2
REGISTER 16-1:
R/W-0
TX9
R/W-0
TXEN
R/W-0
SYNC
U-0
bit 7
R/W-0
TX9D
bit 0
bit 5
R-1
TRMT
bit 6
R/W-0
BRGH
bit 4
bit 3
bit 2
bit 1
bit 0
DS39564A-page 164
W = Writable bit
1 = Bit is set
0 = Bit is cleared
Advance Information
x = Bit is unknown
PIC18FXX2
REGISTER 16-2:
R/W-0
RX9
R/W-0
SREN
R/W-0
CREN
R/W-0
ADDEN
R-0
FERR
R-0
OERR
R-x
RX9D
bit 0
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
W = Writable bit
1 = Bit is set
0 = Bit is cleared
Advance Information
x = Bit is unknown
DS39564A-page 165
PIC18FXX2
16.1
The BRG supports both the Asynchronous and Synchronous modes of the USART. It is a dedicated 8-bit
baud rate generator. The SPBRG register controls the
period of a free running 8-bit timer. In Asynchronous
mode, bit BRGH (TXSTA<2>) also controls the baud
rate. In Synchronous mode, bit BRGH is ignored.
Table 16-1 shows the formula for computation of the
baud rate for different USART modes, which only apply
in Master mode (internal clock).
Given the desired baud rate and Fosc, the nearest integer value for the SPBRG register can be calculated
using the formula in Table 16-1. From this, the error in
baud rate can be determined.
FOSC = 16 MHz
Desired Baud Rate = 9600
BRGH = 0
SYNC = 0
16.1.1
SAMPLING
EXAMPLE 16-1:
Desired Baud Rate
Solving for X:
= ( (FOSC / Desired Baud Rate) / 64 ) - 1
= ((16000000 / 9600) / 64) - 1
= [25.042] = 25
X
X
X
Calculated Baud Rate
=
=
Error
=
=
TABLE 16-1:
SYNC
0
(Asynchronous) Baud Rate = FOSC/(64(X+1))
(Synchronous) Baud Rate = FOSC/(4(X+1))
1
Legend: X = value in SPBRG (0 to 255)
TABLE 16-2:
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR,
BOR
Value on all
other
RESETS
TXSTA
CSRC
TX9
TXEN
SYNC
BRGH
TRMT
TX9D
0000 -010
0000 -010
RCSTA
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
0000 -00x
0000 -00x
0000 0000
0000 0000
SPBRG
Legend: x = unknown, - = unimplemented, read as '0'. Shaded cells are not used by the BRG.
DS39564A-page 166
Advance Information
PIC18FXX2
TABLE 16-3:
BAUD
RATE
(K)
FOSC = 20 MHz
FOSC = 16 MHz
FOSC = 10 MHz
Actual
Rate
(K)
%
Error
0.3
NA
NA
NA
NA
1.2
NA
1.221
+1.73
255
1.202
+0.16
207
1.202
+0.16
129
2.4
2.441
-1.70
255
2.404
+0.16
129
2.404
+0.16
103
2.404
+0.16
64
SPBRG Actual
value
Rate
(decimal)
(K)
%
Error
SPBRG Actual
value
Rate
(decimal)
(K)
%
Error
SPBRG Actual
value
Rate
(decimal)
(K)
%
Error
SPBRG
value
(decimal)
9.6
9.615
-0.16
64
9.469
-1.36
32
9.615
+0.16
25
9.766
+1.73
15
19.2
18.94
+1.38
32
19.53
+1.73
15
19.23
+0.16
12
19.53
+1.73
76.8
78.13
-1.70
78.13
+1.73
83.33
+8.51
78.13
+1.73
96
89.29
+7.52
104.2
+8.51
NA
NA
300
312.5
-4.00
312.5
+4.17
NA
NA
500
625.0
-20.0
NA
NA
NA
HIGH
2.441
255
312.5
250
156.3
LOW
625.0
1.221
255
0.977
255
0.6104
255
Actual
Rate
(K)
%
Error
SPBRG Actual
value
Rate
(decimal)
(K)
%
Error
FOSC = 4 MHz
SPBRG Actual
value
Rate
(decimal)
(K)
%
Error
SPBRG Actual
value
Rate
(decimal)
(K)
%
Error
SPBRG
value
(decimal)
0.3
NA
0.31
+3.13
255
0.3005
-0.17
207
0.301
+0.23
185
1.2
1.203
+0.23
92
1.2
65
1.202
+1.67
51
1.190
-0.83
46
2.4
2.380
-0.83
46
2.4
32
2.404
+1.67
25
2.432
+1.32
22
5
9.6
9.322
-2.90
11
9.9
+3.13
NA
9.322
-2.90
19.2
18.64
-2.90
19.8
+3.13
NA
18.64
-2.90
76.8
NA
79.2
+3.13
NA
NA
96
NA
NA
NA
NA
300
NA
NA
NA
NA
500
NA
NA
NA
NA
HIGH
111.9
79.2
62.500
55.93
LOW
0.437
255
0.3094
255
3.906
255
0.2185
255
FOSC = 1 MHz
BAUD
RATE
(K)
Actual
Rate
(K)
%
Error
0.3
0.300
+0.16
51
0.256
-14.67
1.2
1.202
+0.16
12
NA
2.4
2.232
-6.99
NA
9.6
NA
NA
SPBRG Actual
value
Rate
(decimal)
(K)
%
Error
SPBRG
value
(decimal)
19.2
NA
NA
76.8
NA
NA
96
NA
NA
300
NA
NA
500
NA
NA
HIGH
15.63
0.512
LOW
0.0610
255
0.0020
255
Advance Information
DS39564A-page 167
PIC18FXX2
TABLE 16-4:
BAUD
RATE
(K)
Actual
Rate
(K)
%
Error
FOSC = 20 MHz
SPBRG Actual
value
Rate
(decimal)
(K)
%
Error
FOSC = 16 MHz
SPBRG Actual
value
Rate
(decimal)
(K)
%
Error
FOSC = 10 MHz
SPBRG Actual
value
Rate
(decimal)
(K)
%
Error
SPBRG
value
(decimal)
64
9.6
9.766
-1.70
255
9.615
+0.16
129
9.615
+0.16
103
9.615
+0.16
19.2
19.231
-0.16
129
19.230
+0.16
64
19.230
+0.16
51
18.939
-1.36
32
38.4
38.461
-0.16
64
37.878
-1.36
32
38.461
+0.16
25
39.062
+1.7
15
57.6
58.139
-0.93
42
56.818
-1.36
21
58.823
+2.12
16
56.818
-1.36
10
115.2
113.64
1.38
21
113.63
-1.36
10
111.11
-3.55
125
+8.51
250
250
250
250
NA
625
625
625
NA
625
1250
1250
1250
NA
NA
FOSC = 7.16MHz
BAUD
RATE
(K)
Actual
Rate
(K)
%
Error
SPBRG Actual
value
Rate
(decimal)
(K)
%
Error
FOSC = 4 MHz
SPBRG Actual
value
Rate
(decimal)
(K)
%
Error
SPBRG Actual
value
Rate
(decimal)
(K)
%
Error
SPBRG
value
(decimal)
9.6
9.520
-0.83
46
9.6
32
NA
9.727
+1.32
22
19.2
19.454
+1.32
22
18.645
-2.94
16
1.202
+0.17
207
18.643
-2.90
11
38.4
37.286
-2.90
11
39.6
+3.12
2.403
+0.13
103
37.286
-2.90
57.6
55.930
-2.90
52.8
-8.33
9.615
+0.16
25
55.930
-2.90
115.2
111.860
-2.90
105.6
-8.33
19.231
+0.16
12
111.86
-2.90
250
NA
NA
NA
223.72
-10.51
625
NA
NA
NA
NA
1250
NA
NA
NA
NA
FOSC = 1 MHz
BAUD
RATE
(K)
Actual
Rate
(K)
%
Error
SPBRG Actual
value
Rate
(decimal)
(K)
%
Error
SPBRG
value
(decimal)
9.6
8.928
-6.99
NA
19.2
20.833
+8.51
NA
38.4
31.25
-18.61
NA
57.6
62.5
+8.51
NA
115.2
NA
NA
250
NA
NA
625
NA
NA
1250
NA
NA
DS39564A-page 168
Advance Information
PIC18FXX2
16.2
In this mode, the USART uses standard non-return-tozero (NRZ) format (one START bit, eight or nine data
bits and one STOP bit). The most common data format
is 8-bits. An on-chip dedicated 8-bit baud rate generator can be used to derive standard baud rate frequencies from the oscillator. The USART transmits and
receives the LSb first. The USARTs transmitter and
receiver are functionally independent, but use the
same data format and baud rate. The baud rate generator produces a clock, either x16 or x64 of the bit shift
rate, depending on bit BRGH (TXSTA<2>). Parity is not
supported by the hardware, but can be implemented in
software (and stored as the ninth data bit). Asynchronous mode is stopped during SLEEP.
1.
16.2.1
2.
3.
4.
USART ASYNCHRONOUS
TRANSMITTER
5.
FIGURE 16-1:
6.
7.
8.
TXREG Register
TXIE
8
MSb
LSb
(8)
Pin Buffer
and Control
TSR Register
RC6/TX/CK pin
Interrupt
TXEN
SPEN
SPBRG
Baud Rate Generator
TX9
TX9D
Advance Information
DS39564A-page 169
PIC18FXX2
FIGURE 16-2:
ASYNCHRONOUS TRANSMISSION
Write to TXREG
BRG Output
(Shift Clock)
Word 1
RC6/TX/CK (pin)
START bit
bit 0
bit 1
TXIF bit
(Transmit Buffer
Reg. Empty Flag)
TRMT bit
(Transmit Shift
Reg. Empty Flag)
FIGURE 16-3:
bit 7/8
STOP bit
Word 1
Word 1
Transmit Shift Reg
Write to TXREG
Word 1
BRG Output
(Shift Clock)
RC6/TX/CK (pin)
TXIF bit
(Interrupt Reg. Flag)
START bit
TRMT bit
(Transmit Shift
Reg. Empty Flag)
Note:
bit 0
bit 1
Word 1
bit 7/8
STOP bit
START bit
bit 0
Word 2
Word 1
Transmit Shift Reg.
Word 2
Transmit Shift Reg.
TABLE 16-5:
Name
Word 2
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR,
BOR
Value on
all other
RESETS
RBIF
0000 000x 0000 000u
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF
PIR1
PSPIF(1)
ADIF
RCIF
TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
PIE1
PSPIE(1)
ADIE
RCIE
TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
IPR1
PSPIP(1)
ADIP
RCIP
TXIP SSPIP CCP1IP TMR2IP TMR1IP 0000 0000 0000 0000
RCSTA
SPEN
RX9
SREN CREN ADDEN FERR
OERR
RX9D 0000 -00x 0000 -00x
TXREG USART Transmit Register
0000 0000 0000 0000
TXSTA
CSRC
TX9
TXEN SYNC
BRGH TRMT
TX9D 0000 -010 0000 -010
SPBRG Baud Rate Generator Register
0000 0000 0000 0000
Legend: x = unknown, - = unimplemented locations read as '0'.
Shaded cells are not used for Asynchronous Transmission.
Note 1: The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18F2X2 devices; always maintain these bits
clear.
DS39564A-page 170
Advance Information
PIC18FXX2
16.2.2
USART ASYNCHRONOUS
RECEIVER
16.2.3
FIGURE 16-4:
FERR
OERR
SPBRG
64
or
16
RSR Register
MSb
STOP (8)
LSb
0 START
Data
Recovery
RX9D
RCREG Register
FIFO
SPEN
8
Interrupt
RCIF
Data Bus
RCIE
Advance Information
DS39564A-page 171
PIC18FXX2
FIGURE 16-5:
ASYNCHRONOUS RECEPTION
START
bit
bit0
RX (pin)
bit1
bit7/8 STOP
bit
Rcv Shift
Reg
Rcv Buffer Reg
START
bit0
bit
bit7/8 STOP
bit
bit7/8
STOP
bit
Word 2
RCREG
Word 1
RCREG
Read Rcv
Buffer Reg
RCREG
START
bit
RCIF
(Interrupt Flag)
OERR bit
CREN
Note:
This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word, causing the OERR (overrun) bit to be set.
TABLE 16-6:
Name
Bit 6
INTCON
GIE/GIEH
PIR1
PIE1
IPR1
RCSTA
PSPIF(1)
PSPIE(1)
PSPIP(1)
SPEN
PEIE/
GIEL
ADIF
ADIE
ADIP
RX9
RCREG
TXSTA
SPBRG
Bit 5
RCIF
RCIE
RCIP
SREN
RBIE
TXIF
SSPIF
TXIE SSPIE
TXIP SSPIP
CREN ADDEN
Bit 2
Value on
POR,
BOR
Value on
all other
RESETS
RBIF
0000 000x
0000 000u
0000 0000
0000 0000
0000 0000
0000 0000
0000 -010
0000 -010
0000 0000
TMR0IE INT0IE
Bit 3
Bit 0
0000 0000
Bit 4
0000 0000
Bit 1
TMR0IF INT0IF
CCP1IF
CCP1IE
CCP1IP
FERR
TX9
TXEN
SYNC
BRGH
TRMT
TX9D
0000 -00x
DS39564A-page 172
Advance Information
PIC18FXX2
16.3
16.3.1
TABLE 16-7:
Name
INTCON
PIR1
PIE1
IPR1
RCSTA
TXREG
TXSTA
SPBRG
Legend:
Note 1:
Bit 7
2.
3.
4.
5.
6.
7.
8.
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR,
BOR
Value on all
other
RESETS
GIE/
PEIE/
TMR0IE INT0IE RBIE TMR0IF INT0IF
RBIF
0000 000x 0000 000u
GIEH
GIEL
PSPIF(1) ADIF
RCIF
TXIF
SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
PSPIE(1) ADIE
RCIE
TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
PSPIP(1) ADIP
RCIP
TXIP SSPIP CCP1IP TMR2IP TMR1IP 0000 0000 0000 0000
SPEN
RX9
SREN CREN ADDEN FERR
OERR
RX9D
0000 -00x 0000 -00x
USART Transmit Register
0000 0000 0000 0000
CSRC
TX9
TXEN SYNC
BRGH
TRMT
TX9D
0000 -010 0000 -010
Baud Rate Generator Register
0000 0000 0000 0000
x = unknown, - = unimplemented, read as '0'.
Shaded cells are not used for Synchronous Master Transmission.
The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18F2X2 devices; always maintain these bits
clear.
Advance Information
DS39564A-page 173
PIC18FXX2
FIGURE 16-6:
SYNCHRONOUS TRANSMISSION
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
RC7/RX/DT
pin
bit 0
bit 1
Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
bit 2
bit 7
Word 1
bit 0
bit 1
Word 2
bit 7
RC6/TX/CK
pin
Write to
TXREG Reg
Write Word1
Write Word2
TXIF bit
(Interrupt Flag)
TRMT bit TRMT
TXEN bit
Note:
FIGURE 16-7:
RC7/RX/DT pin
bit0
bit1
bit2
bit6
bit7
RC6/TX/CK pin
Write to
TXREG reg
TXIF bit
TRMT bit
TXEN bit
DS39564A-page 174
Advance Information
PIC18FXX2
16.3.2
TABLE 16-8:
Name
PIR1
PIE1
IPR1
RCSTA
RCREG
TXSTA
SPBRG
Legend:
Note 1:
Bit 7
INTCON
4.
5.
6.
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Value on
POR,
BOR
Bit 0
Value on all
other
RESETS
GIE/
PEIE/
TMR0IE INT0IE RBIE TMR0IF INT0IF
RBIF
0000 000x 0000 000u
GIEH
GIEL
PSPIF(1) ADIF
RCIF
TXIF
SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
PSPIE(1) ADIE
RCIE
TXIE
SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
PSPIP(1) ADIP
RCIP
TXIP
SSPIP CCP1IP TMR2IP TMR1IP 0000 0000 0000 0000
SPEN
RX9
SREN CREN ADDEN FERR
OERR
RX9D 0000 -00x 0000 -00x
USART Receive Register
0000 0000 0000 0000
CSRC
TX9
TXEN SYNC
BRGH
TRMT
TX9D 0000 -010 0000 -010
Baud Rate Generator Register
0000 0000 0000 0000
x = unknown, - = unimplemented, read as '0'. Shaded cells are not used for Synchronous Master Reception.
The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18F2X2 devices; always maintain these bits
clear.
FIGURE 16-8:
RC7/RX/DT pin
bit0
bit1
bit2
bit3
bit4
bit5
bit6
bit7
RC6/TX/CK pin
Write to
bit SREN
SREN bit
CREN bit
RCIF bit
(Interrupt)
Read
RXREG
Note:
Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0.
Advance Information
DS39564A-page 175
PIC18FXX2
16.4
16.4.1
b)
c)
d)
e)
1.
2.
3.
4.
5.
6.
a)
7.
8.
TABLE 16-9:
Name
INTCON
PIR1
PIE1
IPR1
RCSTA
TXREG
TXSTA
SPBRG
Legend:
Note 1:
Enable the synchronous slave serial port by setting bits SYNC and SPEN and clearing bit
CSRC.
Clear bits CREN and SREN.
If interrupts are desired, set enable bit TXIE.
If 9-bit transmission is desired, set bit TX9.
Enable the transmission by setting enable bit
TXEN.
If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
Start transmission by loading data to the TXREG
register.
If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR,
BOR
Value on all
other
RESETS
BRGH
TRMT
TX9D 0000 -010 0000 -010
Baud Rate Generator Register
0000 0000 0000 0000
x = unknown, - = unimplemented, read as '0'.
Shaded cells are not used for Synchronous Slave Transmission.
The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18F2X2 devices; always maintain these bits
clear.
DS39564A-page 176
Advance Information
PIC18FXX2
16.4.2
2.
3.
4.
5.
6.
7.
8.
9.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR,
BOR
Value on
all other
RESETS
BRGH TRMT
TX9D 0000 -010 0000 -010
Baud Rate Generator Register
0000 0000 0000 0000
x = unknown, - = unimplemented, read as '0'.
Shaded cells are not used for Synchronous Slave Reception.
The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18F2X2 devices; always maintain these bits
clear.
Advance Information
DS39564A-page 177
PIC18FXX2
NOTES:
DS39564A-page 178
Advance Information
PIC18FXX2
17.0
COMPATIBLE 10-BIT
ANALOG-TO-DIGITAL
CONVERTER (A/D) MODULE
The ADCON0 register, shown in Register 17-1, controls the operation of the A/D module. The ADCON1
register, shown in Register 17-2, configures the functions of the port pins.
REGISTER 17-1:
ADCON0 REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
R/W-0
ADCS1
ADCS0
CHS2
CHS1
CHS0
GO/DONE
ADON
bit 7
bit 7-6
bit 0
bit 5-3
ADCON0
<ADCS1:ADCS0>
00
01
10
11
00
01
10
11
Clock Conversion
FOSC/2
FOSC/8
FOSC/32
FRC (clock derived from the internal A/D RC oscillator)
FOSC/4
FOSC/16
FOSC/64
FRC (clock derived from the internal A/D RC oscillator)
bit 2
bit 1
bit 0
W = Writable bit
1 = Bit is set
0 = Bit is cleared
Advance Information
x = Bit is unknown
DS39564A-page 179
PIC18FXX2
REGISTER 17-2:
ADCON1 REGISTER
R/W-0
R/W-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
ADFM
ADCS2
PCFG3
PCFG2
PCFG1
PCFG0
bit 7
bit 0
bit 7
bit 6
FOSC/2
FOSC/8
FOSC/32
FRC (clock derived from the internal A/D RC oscillator)
FOSC/4
FOSC/16
FOSC/64
FRC (clock derived from the internal A/D RC oscillator)
00
01
10
11
00
01
10
11
0
0
0
0
1
1
1
1
Clock Conversion
bit 5-4
bit 3-0
AN7
AN6
AN5
AN4
0000
0001
VREF+
0010
0011
VREF+
0100
0101
VREF+
011x
AN3
AN2
AN1
AN0
VREF+
VREF-
C/R
VDD
VSS
8/0
AN3
VSS
7/1
VDD
VSS
5/0
AN3
VSS
4/1
VDD
VSS
3/0
AN3
VSS
2/1
0/0
1000
VREF+
VREF-
AN3
AN2
6/2
1001
VDD
VSS
6/0
1010
VREF+
AN3
VSS
5/1
1011
VREF+
VREF-
AN3
AN2
4/2
1100
VREF+
VREF-
AN3
AN2
3/2
1101
VREF+
VREF-
AN3
AN2
2/2
1110
VDD
VSS
1/0
1111
VREF+
VREF-
AN3
AN2
1/2
W = Writable bit
1 = Bit is set
0 = Bit is cleared
Note:
DS39564A-page 180
x = Bit is unknown
On any device RESET, the port pins that are multiplexed with analog functions (ANx) are
forced to be an analog input.
Advance Information
PIC18FXX2
The analog reference voltage is software selectable to
either the devices positive and negative supply voltage
(VDD and VSS), or the voltage level on the RA3/AN3/
VREF+ pin and RA2/AN2/VREF- pin.
FIGURE 17-1:
111
110
101
100
VAIN
011
(Input Voltage)
010
10-bit
Converter
A/D
001
PCFG0
000
VDD
AN7*
AN6*
AN5*
AN4
AN3
AN2
AN1
AN0
VREF+
Reference
Voltage
VREFVSS
* These channels are implemented only on the PIC18F4X2 devices.
Advance Information
DS39564A-page 181
PIC18FXX2
5.
OR
2.
3.
4.
6.
7.
17.1
FIGURE 17-2:
When the conversion is started, the holding capacitor is disconnected from the
input pin.
VT = 0.6V
Rs
RIC 1k
ANx
CPIN
VAIN
5 pF
VT = 0.6V
SS
RSS
I LEAKAGE
500 nA
CHOLD = 120 pF
VSS
Legend: CPIN
= input capacitance
VT
= threshold voltage
I LEAKAGE = leakage current at the pin due to
various junctions
RIC
SS
CHOLD
= interconnect resistance
= sampling switch
= sample/hold capacitance (from DAC)
VDD
6V
5V
4V
3V
2V
5 6 7 8 9 10 11
Sampling Switch (k)
DS39564A-page 182
Advance Information
PIC18FXX2
To calculate the minimum acquisition time,
Equation 17-1 may be used. This equation assumes
that 1/2 LSb error is used (1024 steps for the A/D). The
1/2 LSb error is the maximum error allowed for the A/D
to meet its specified resolution.
EQUATION 17-1:
TACQ
ACQUISITION TIME
TAMP + TC + TCOFF
EQUATION 17-2:
VHOLD =
or
=
TC
CHOLD
Rs
Conversion Error
VDD
Temperature
VHOLD
EXAMPLE 17-1:
TACQ =
=
=
=
=
=
120 pF
2.5 k
1/2 LSb
5V Rss = 7 k
50C (system max.)
0V @ time = 0
TAMP + TC + TCOFF
TACQ =
Advance Information
DS39564A-page 183
PIC18FXX2
17.2
2TOSC
4TOSC
8TOSC
16TOSC
32TOSC
64TOSC
Internal A/D module RC oscillator (2-6 s)
17.3
TABLE 17-1:
Operation
PIC18FXX2
PIC18LFXX2
2TOSC
000
1.25 MHz
666 kHz
4TOSC
100
2.50 MHz
1.33 MHz
8TOSC
001
5.00 MHz
2.67 MHz
16TOSC
101
10.00 MHz
5.33 MHz
32TOSC
010
20.00 MHz
10.67 MHz
64TOSC
110
40.00 MHz
21.33 MHz
RC
Note 1:
2:
3:
4:
ADCS2:ADCS0
011
The RC source has a typical TAD time of 4 s for F devices and 6 s for LF devices.
These values violate the minimum required TAD time.
For faster conversion times, the selection of another clock source is recommended.
For device frequencies above 1 MHz, the device must be in SLEEP for the entire conversion or the A/D
accuracy may be out of specification.
DS39564A-page 184
Advance Information
PIC18FXX2
17.4
A/D Conversions
(or the last value written to the ADRESH:ADRESL registers). After the A/D conversion is aborted, a 2TAD wait
is required before the next acquisition is started. After
this 2TAD wait, acquisition on the selected channel is
automatically started. The GO/DONE bit can then be
set to start the conversion.
FIGURE 17-3:
Note:
TCY - TAD TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9 TAD10 TAD11
b8
b9
b7
b5
b6
b4
b3
b1
b2
b0
b0
Conversion Starts
Holding capacitor is disconnected from analog input (typically 100 ns)
Set GO bit
Next Q4: ADRESH/ADRESL is loaded, GO bit is cleared,
ADIF bit is set, holding capacitor is connected to analog input.
17.4.1
FIGURE 17-4:
ADFM = 1
2107
0765
0000 00
0000 00
ADRESH
ADRESL
ADRESH
10-bit Result
ADRESL
10-bit Result
Left Justified
Right Justified
Advance Information
DS39564A-page 185
PIC18FXX2
17.5
TABLE 17-2:
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
all other
RESETS
INTCON
GIE/
GIEH
PEIE/
GIEL
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
0000 000x
0000 000u
PIR1
PSPIF(1)
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
0000 0000
0000 0000
PIE1
(1)
PSPIE
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
0000 0000
0000 0000
IPR1
PSPIP(1)
ADIP
RCIP
TXIP
SSPIP
CCP1IP
TMR2IP
TMR1IP
0000 0000
0000 0000
PIR2
EEIF
BCLIF
LVDIF
TMR3IF
CCP2IF
---0 0000
---0 0000
PIE2
EEIE
BCLIE
LVDIE
TMR3IE
CCP2IE
---0 0000
---0 0000
EEIP
BCLIP
LVDIP
TMR3IP
CCP2IP
IPR2
---1 1111
---1 0000
ADRESH
xxxx xxxx
uuuu uuuu
ADRESL
xxxx xxxx
uuuu uuuu
ADCON0
ADCS1
ADCS0
ADCON1
CHS2
CHS1
CHS0
GO/
DONE
ADON
0000 00-0
0000 00-0
ADFM
ADCS2
PCFG3
PCFG2
PCFG1
PCFG0
---- -000
---- -000
PORTA
RA6
RA5
RA4
RA3
RA2
RA1
RA0
--0x 0000
--0u 0000
TRISA
--11 1111
--11 1111
PORTE
RE2
RE1
RE0
---- -000
---- -000
LATE
LATE2
LATE1
LATE0
---- -xxx
---- -uuu
TRISE
IBF
OBF
IBOV
PSPMODE
0000 -111
0000 -111
Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used for A/D conversion.
Note 1: The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18F2X2 devices; always maintain these bits clear.
DS39564A-page 186
Advance Information
PIC18FXX2
18.0
Voltage
FIGURE 18-1:
VA
VB
Legend:
VA = LVD trip point
VB = Minimum valid device
operating voltage
Time
TA
TB
Advance Information
DS39564A-page 187
PIC18FXX2
FIGURE 18-2:
LVD Control
Register
16 to 1 MUX
VDD
Internally Generated
Reference Voltage
1.2V
LVDEN
FIGURE 18-3:
LVDIF
16 to 1 MUX
LVD Control
Register
LVDIN
Externally Generated
Trip Point
LVDEN
LVD
VxEN
BODEN
EN
BGAP
DS39564A-page 188
Advance Information
PIC18FXX2
18.1
Control Register
REGISTER 18-1:
LVDCON REGISTER
U-0
U-0
R-0
R/W-0
R/W-0
R/W-1
R/W-0
R/W-1
IRVST
LVDEN
LVDL3
LVDL2
LVDL1
LVDL0
bit 7
bit 0
bit 7-6
bit 5
bit 4
bit 3-0
LVDL3:LVDL0 modes which result in a trip point below the valid operating voltage
of the device are not tested.
Legend:
R = Readable bit
W = Writable bit
- n = Value at POR
1 = Bit is set
0 = Bit is cleared
Advance Information
x = Bit is unknown
DS39564A-page 189
PIC18FXX2
18.2
Operation
2.
3.
4.
5.
6.
Write the value to the LVDL3:LVDL0 bits (LVDCON register), which selects the desired LVD
Trip Point.
Ensure that LVD interrupts are disabled (the
LVDIE bit is cleared or the GIE bit is cleared).
Enable the LVD module (set the LVDEN bit in
the LVDCON register).
Wait for the LVD module to stabilize (the IRVST
bit to become set).
Clear the LVD interrupt flag, which may have
falsely become set until the LVD module has
stabilized (clear the LVDIF bit).
Enable the LVD interrupt (set the LVDIE and the
GIE bits).
FIGURE 18-4:
CASE 1:
.
VLVD
LVDIF
Enable LVD
Internally Generated
Reference Stable
TIVRST
LVDIF cleared in software
CASE 2:
VDD
VLVD
LVDIF
Enable LVD
Internally Generated
Reference Stable
TIVRST
DS39564A-page 190
Advance Information
PIC18FXX2
18.2.1
18.2.2
18.3
18.4
Effects of a RESET
CURRENT CONSUMPTION
Advance Information
DS39564A-page 191
PIC18FXX2
NOTES:
DS39564A-page 192
Advance Information
PIC18FXX2
19.0
There are several features intended to maximize system reliability, minimize cost through elimination of
external components, provide power saving operating
modes and offer code protection. These are:
OSC Selection
RESET
- Power-on Reset (POR)
- Power-up Timer (PWRT)
- Oscillator Start-up Timer (OST)
- Brown-out Reset (BOR)
Interrupts
Watchdog Timer (WDT)
SLEEP
Code Protection
ID Locations
In-Circuit Serial Programming
19.1
TABLE 19-1:
Configuration Bits
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Default/
Unprogrammed
Value
300001h
CONFIG1H
OSCSEN
FOSC2
FOSC1
FOSC0
--1- -111
300002h
CONFIG2L
BORV1
BORV0
BODEN
PWRTEN
---- 1111
300003h
CONFIG2H
WDTPS2
WDTPS1
WDTPS0
WDTEN
---- 1111
300005h
CONFIG3H
CCP2MX
---- ---1
300006h
CONFIG4L
DEBUG
LVP
STVREN
1--- -1-1
300008h
CONFIG5L
CP3
CP2
CP1
CP0
---- 1111
300009h
CONFIG5H
CPD
CPB
11-- ----
30000Ah
CONFIG6L
WRT3
WRT2
WRT1
WRT0
---- 1111
30000Bh
CONFIG6H
WRTD
WRTB
WRTC
111- ----
30000Ch
CONFIG7L
EBTR3
EBTR2
EBTR1
EBTR0
---- 1111
30000Dh
CONFIG7H
EBTRB
-1-- ----
3FFFFEh
DEVID1
DEV2
DEV1
DEV0
REV4
REV3
REV2
REV1
REV0
(1)
3FFFFFh
DEVID2
DEV10
DEV9
DEV8
DEV7
DEV6
DEV5
DEV4
DEV3
0000 0100
Advance Information
DS39564A-page 193
PIC18FXX2
REGISTER 19-1:
U-0
R/P-1
U-0
U-0
R/P-1
R/P-1
R/P-1
OSCSEN
FOSC2
FOSC1
FOSC0
bit 7
bit 0
bit 7-6
Unimplemented: Read as 0
bit 5
bit 4-3
Unimplemented: Read as 0
bit 2-0
P = Programmable bit
DS39564A-page 194
Advance Information
PIC18FXX2
REGISTER 19-2:
U-0
U-0
U-0
R/P-1
R/P-1
R/P-1
R/P-1
BORV1
BORV0
BOREN
PWRTEN
bit 7
bit 0
bit 7-4
Unimplemented: Read as 0
bit 3-2
bit 1
bit 0
Legend:
R = Readable bit
P = Programmable bit
Advance Information
DS39564A-page 195
PIC18FXX2
REGISTER 19-3:
U-0
U-0
U-0
R/P-1
R/P-1
R/P-1
R/P-1
WDTPS2
WDTPS1
WDTPS0
WDTEN
bit 7
bit 0
bit 7-4
Unimplemented: Read as 0
bit 3-1
bit 0
P = Programmable bit
REGISTER 19-4:
U-0
U-0
U-0
U-0
U-0
U-0
R/P-1
CCP2MX
bit 7
bit 0
bit 7-1
Unimplemented: Read as 0
bit 0
P = Programmable bit
DS39564A-page 196
Advance Information
PIC18FXX2
REGISTER 19-5:
U-0
U-0
U-0
U-0
R/P-1
U-0
R/P-1
BKBUG
LVP
STVREN
bit 7
bit 0
bit 7
bit 6-3
Unimplemented: Read as 0
bit 2
bit 1
Unimplemented: Read as 0
bit 0
C = Clearable bit
REGISTER 19-6:
U-0
U-0
U-0
R/C-1
R/C-1
R/C-1
R/C-1
CP3(1)
CP2(1)
CP1
CP0
bit 7
bit 0
bit 7-4
Unimplemented: Read as 0
bit 3
bit 2
bit 1
bit 0
C = Clearable bit
Advance Information
DS39564A-page 197
PIC18FXX2
REGISTER 19-7:
R/C-1
U-0
U-0
U-0
U-0
U-0
U-0
CPD
CPB
bit 7
bit 0
bit 7
bit 6
bit 5-0
Unimplemented: Read as 0
Legend:
R = Readable bit
C = Clearable bit
REGISTER 19-8:
U-0
U-0
U-0
R/P-1
R/P-1
R/P-1
R/P-1
WRT3(1)
WRT2(1)
WRT1
WRT0
bit 7
bit 0
bit 7-4
Unimplemented: Read as 0
bit 3
bit 2
bit 1
bit 0
P = Programmable bit
DS39564A-page 198
Advance Information
PIC18FXX2
REGISTER 19-9:
R/P-1
R-1
U-0
U-0
U-0
U-0
U-0
WRTD
WRTB
WRTC
bit 7
bit 0
bit 7
bit 6
bit 5
bit 4-0
Unimplemented: Read as 0
Note:
Legend:
R = Readable bit
P =Programmable bit
U-0
U-0
U-0
R/P-1
R/P-1
R/P-1
R/P-1
EBTR3(1)
EBTR2(1)
EBTR1
EBTR0
bit 7
bit 0
bit 7-4
Unimplemented: Read as 0
bit 3
bit 2
bit 1
bit 0
P = Programmable bit
Advance Information
DS39564A-page 199
PIC18FXX2
REGISTER 19-11: CONFIGURATION REGISTER 7 HIGH (CONFIG7H: BYTE ADDRESS 30000Dh)
U-0
R/P-1
U-0
U-0
U-0
U-0
U-0
U-0
EBTRB
bit 7
bit 0
bit 7
Unimplemented: Read as 0
bit 6
bit 5-0
Unimplemented: Read as 0
Legend:
R = Readable bit
P =Programmable bit
DEV2
DEV1
DEV0
REV4
REV3
REV2
REV1
REV0
bit 7
bit 0
bit 7-5
bit 4-0
P =Programmable bit
DEV10
DEV9
DEV8
DEV7
DEV6
DEV5
DEV4
DEV3
bit 7
bit 7-0
bit 0
P =Programmable bit
DS39564A-page 200
Advance Information
PIC18FXX2
19.2
The Watchdog Timer is a free running on-chip RC oscillator, which does not require any external components.
This RC oscillator is separate from the RC oscillator of
the OSC1/CLKI pin. That means that the WDT will run,
even if the clock on the OSC1/CLKI and OSC2/CLKO/
RA6 pins of the device has been stopped, for example,
by execution of a SLEEP instruction.
Note:
19.2.1
CONTROL REGISTER
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0
SWDTEN
bit 7
bit 0
bit 7-1
Unimplemented: Read as 0
bit 0
W = Writable bit
Advance Information
DS39564A-page 201
PIC18FXX2
19.2.2
WDT POSTSCALER
FIGURE 19-1:
WDT Timer
Postscaler
8
8 - to - 1 MUX
WDTEN
Configuration bit
WDTPS2:WDTPS0
SWDTEN bit
WDT
Time-out
Note:
TABLE 19-2:
Name
CONFIG2H
RCON
WDTCON
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
WDTPS2
WDTPS2
WDTPS0
WDTEN
IPEN
RI
TO
PD
POR
BOR
SWDTEN
DS39564A-page 202
Advance Information
PIC18FXX2
19.3
19.3.1
3.
19.3.2
Advance Information
DS39564A-page 203
PIC18FXX2
WAKE-UP FROM SLEEP THROUGH INTERRUPT(1,2)
FIGURE 19-2:
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
TOST(2)
CLKOUT(4)
INT pin
INTF flag
(INTCON<1>)
Interrupt Latency(3)
GIEH bit
(INTCON<7>)
Processor in
SLEEP
INSTRUCTION FLOW
PC
Instruction
Fetched
Instruction
Executed
Note
1:
2:
3:
4:
PC
PC+2
Inst(PC) = SLEEP
Inst(PC + 2)
PC+4
PC+4
Inst(PC - 1)
SLEEP
Inst(PC + 2)
PC + 4
Dummy Cycle
0008h
000Ah
Inst(0008h)
Inst(PC + 4)
Inst(000Ah)
Dummy Cycle
Inst(0008h)
DS39564A-page 204
Advance Information
PIC18FXX2
19.4
FIGURE 19-3:
16 Kbytes
(PIC18FX42)
32 Kbytes
(PIC18FX52)
Boot Block
Boot Block
000000h
0001FFh
Block 0
Address
Range
Block 0
000200h
CP0, WRT0, EBTR0
001FFFh
002000h
Block 1
Block 1
Unimplemented
Read 0s
Block 2
Unimplemented
Read 0s
Block 3
Unimplemented
Read 0s
Unimplemented
Read 0s
1FFFFFh
TABLE 19-3:
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CP3
CP2
CP1
CP0
300008h
CONFIG5L
300009h
CONFIG5H
CPD
CPB
30000Ah
CONFIG6L
WRT3
WRT2
WRT1
WRT0
30000Bh
CONFIG6H
WRTD
WRTB
WRTC
30000Ch
CONFIG7L
EBTR3
EBTR2
EBTR1
EBTR0
30000Dh
CONFIG7H
EBTRB
Advance Information
DS39564A-page 205
PIC18FXX2
19.4.1
PROGRAM MEMORY
CODE PROTECTION
Note:
FIGURE 19-4:
Register Values
Program Memory
WRTB,EBTRB = 11
TBLPTR = 000FFF
WRT0,EBTR0 = 01
PC = 001FFE
TBLWT *
001FFFh
002000h
WRT1,EBTR1 = 11
003FFFh
004000h
PC = 004FFE
WRT2,EBTR2 = 11
TBLWT *
005FFFh
006000h
WRT3,EBTR3 = 11
007FFFh
Results: All Table Writes disabled to Blockn whenever WRTn = 0.
DS39564A-page 206
Advance Information
PIC18FXX2
FIGURE 19-5:
Register Values
Program Memory
TBLPTR = 000FFF
WRT0,EBTR0 = 10
001FFFh
002000h
PC = 002FFE
TBLRD *
WRT1,EBTR1 = 11
003FFFh
004000h
WRT2,EBTR2 = 11
005FFFh
006000h
WRT3,EBTR3 = 11
007FFFh
Results: All Table Reads from external blocks to Blockn are disabled whenever EBTRn = 0.
TABLAT register returns a value of 0.
FIGURE 19-6:
Register Values
Program Memory
TBLPTR = 000FFF
PC = 001FFE
WRT0,EBTR0 = 10
TBLRD *
001FFFh
002000h
WRT1,EBTR1 = 11
003FFFh
004000h
WRT2,EBTR2 = 11
005FFFh
006000h
WRT3,EBTR3 = 11
007FFFh
Advance Information
DS39564A-page 207
PIC18FXX2
19.4.2
DATA EEPROM
CODE PROTECTION
19.4.3
CONFIGURATION REGISTER
PROTECTION
19.5
ID Locations
Eight memory locations (200000h - 200007h) are designated as ID locations, where the user can store
checksum or other code identification numbers. These
locations are accessible during normal execution
through the TBLRD and TBLWT instructions, or during
program/verify. The ID locations can be read when the
device is code protected.
19.6
PIC18FXXX microcontrollers can be serially programmed while in the end application circuit. This is
simply done with two lines for clock and data, and three
other lines for power, ground and the programming
voltage. This allows customers to manufacture boards
with unprogrammed devices, and then program the
microcontroller just before shipping the product. This
also allows the most recent firmware or a custom firmware to be programmed.
19.7
In-Circuit Debugger
TABLE 19-4:
DEBUGGER RESOURCES
I/O pins
Stack
RB6, RB7
2 levels
Program Memory
19.8
512 bytes
Data Memory
To use the In-Circuit Debugger function of the microcontroller, the design must implement In-Circuit Serial
Programming connections to MCLR/VPP, VDD, GND,
RB7 and RB6. This will interface to the In-Circuit
Debugger module available from Microchip or one of
the third party development tool companies.
10 bytes
DS39564A-page 208
Advance Information
PIC18FXX2
20.0
The PIC18FXXX instruction set adds many enhancements to the previous PICmicro instruction sets, while
maintaining an easy migration from these PICmicro
instruction sets.
Most instructions are a single program memory word
(16-bits), but there are three instructions that require
two program memory locations.
Each single word instruction is a 16-bit word divided
into an OPCODE, which specifies the instruction type
and one or more operands, which further specify the
operation of the instruction.
The instruction set is highly orthogonal and is grouped
into four basic categories:
Byte-oriented operations
Bit-oriented operations
Literal operations
Control operations
The file register designator 'f' specifies which file register is to be used by the instruction.
The destination designator d specifies where the
result of the operation is to be placed. If 'd' is zero, the
result is placed in the WREG register. If 'd' is one, the
result is placed in the file register specified in the
instruction.
1.
2.
Figure 20-1 shows the general formats that the instructions can have.
3.
The bit field designator 'b' selects the number of the bit
affected by the operation, while the file register designator 'f' represents the number of the file in which the
bit is located.
Advance Information
DS39564A-page 209
PIC18FXX2
TABLE 20-1:
Field
Description
bbb
BSR
dest
Destination either the WREG register or the specified register file location
fs
12-bit Register file address (0x000 to 0xFFF). This is the source address.
fd
12-bit Register file address (0x000 to 0xFFF). This is the destination address.
Literal field, constant data or label (may be either an 8-bit, 12-bit or a 20-bit value)
label
Label name
mm
The mode of the TBLPTR register for the Table Read and Table Write instructions
Only used with Table Read and Table Write instructions:
*+
*-
+*
n
The relative address (2s complement number) for relative branch instructions, or the direct address for Call/
Branch and Return instructions
PRODH
PRODL
Unused or Unchanged
WREG
Don't care (0 or 1)
The assembler will generate code with x = 0. It is the recommended form of use for compatibility with all
Microchip software tools.
TBLPTR
TABLAT
TOS
Top-of-Stack
PC
Program Counter
PCL
PCH
PCLATH
PCLATU
GIE
WDT
Watchdog Timer
TO
Time-out bit
PD
Power-down bit
C, DC, Z, OV, N
Optional
Contents
Assigned to
< >
In the set of
italics
DS39564A-page 210
Advance Information
PIC18FXX2
FIGURE 20-1:
10
9 8 7
OPCODE d
a
Example Instruction
0
ADDWF MYREG, W, B
f (FILE #)
0
f (Source FILE #)
12 11
f (Destination FILE #)
1111
12 11
9 8 7
OPCODE b (BIT #) a
0
BSF MYREG, bit, B
f (FILE #)
OPCODE
0
MOVLW 0x7F
k (literal)
8 7
OPCODE
15
0
GOTO Label
n<7:0> (literal)
12 11
0
n<19:8> (literal)
1111
8 7
OPCODE
15
0
CALL MYFUNC
n<7:0> (literal)
12 11
0
n<19:8> (literal)
S = Fast bit
15
OPCODE
15
OPCODE
11 10
0
BRA MYFUNC
n<10:0> (literal)
8 7
n<7:0> (literal)
Advance Information
BC MYFUNC
DS39564A-page 211
PIC18FXX2
TABLE 20-2:
Mnemonic,
Operands
Cycles
MSb
LSb
Status
Affected
Notes
DS39564A-page 212
Advance Information
PIC18FXX2
TABLE 20-2:
Mnemonic,
Operands
Cycles
MSb
CONTROL OPERATIONS
BC
n
Branch if Carry
BN
n
Branch if Negative
BNC
n
Branch if Not Carry
BNN
n
Branch if Not Negative
BNOV
n
Branch if Not Overflow
BNZ
n
Branch if Not Zero
BOV
n
Branch if Overflow
BRA
n
Branch Unconditionally
BZ
n
Branch if Zero
CALL
n, s
Call subroutine1st word
2nd word
CLRWDT
Clear Watchdog Timer
DAW
No Operation
NOP
No Operation (Note 4)
POP
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
2
1 (2)
1 (2)
1 (2)
2
1
1
2
1110
1110
1110
1110
1110
1110
1110
1101
1110
1110
1111
0000
0000
1110
1111
0000
1111
0000
0000
1101
0000
0000
LSb
0010
0110
0011
0111
0101
0001
0100
0nnn
0000
110s
kkkk
0000
0000
1111
kkkk
0000
xxxx
0000
0000
1nnn
0000
0000
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
kkkk
kkkk
0000
0000
kkkk
kkkk
0000
xxxx
0000
0000
nnnn
1111
0001
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
kkkk
kkkk
0100
0111
kkkk
kkkk
0000
xxxx
0110
0101
nnnn
1111
000s
Status
Affected
Notes
None
None
None
None
None
None
None
None
None
None
TO, PD
C
None
None
None
None
None
None
All
GIE/GIEH,
PEIE/GIEL
RETLW
k
Return with literal in WREG
2
0000 1100 kkkk kkkk None
RETURN
s
Return from Subroutine
2
0000 0000 0001 001s None
SLEEP
1
1
1
1
2
1
2
Advance Information
DS39564A-page 213
PIC18FXX2
TABLE 20-2:
Mnemonic,
Operands
Cycles
MSb
LSb
Status
Affected
Notes
LITERAL OPERATIONS
ADDLW
k
Add literal and WREG
1
0000 1111 kkkk
kkkk C, DC, Z, OV, N
ANDLW
k
AND literal with WREG
1
0000 1011 kkkk
kkkk Z, N
IORLW
k
Inclusive OR literal with WREG 1
0000 1001 kkkk
kkkk Z, N
LFSR
f, k
Move literal (12-bit) 2nd word
2
1110 1110 00ff
kkkk None
to FSRx 1st word
1111 0000 kkkk
kkkk
MOVLB
k
Move literal to BSR<3:0>
1
0000 0001 0000
kkkk None
MOVLW
k
Move literal to WREG
1
0000 1110 kkkk
kkkk None
MULLW
k
Multiply literal with WREG
1
0000 1101 kkkk
kkkk None
RETLW
k
Return with literal in WREG
2
0000 1100 kkkk
kkkk None
SUBLW
k
Subtract WREG from literal
1
0000 1000 kkkk
kkkk C, DC, Z, OV, N
XORLW
k
Exclusive OR literal with WREG 1
0000 1010 kkkk
kkkk Z, N
DATA MEMORY PROGRAM MEMORY OPERATIONS
TBLRD*
Table Read
2
0000 0000 0000
1000 None
TBLRD*+
Table Read with post-increment
0000 0000 0000
1001 None
TBLRD*Table Read with post-decre0000 0000 0000
1010 None
TBLRD+*
ment
0000 0000 0000
1011 None
TBLWT*
Table Read with pre-increment 2 (5)
0000 0000 0000
1100 None
TBLWT*+
Table Write
0000 0000 0000
1101 None
TBLWT*Table Write with post-increment
0000 0000 0000
1110 None
TBLWT+*
Table Write with post-decre0000 0000 0000
1111 None
ment
Table Write with pre-increment
Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that
value present on the pins themselves. For example, if the data latch is 1 for a pin configured as input and is
driven low by an external device, the data will be written back with a 0.
2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if
assigned.
3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second
cycle is executed as a NOP.
4: Some instructions are 2-word instructions. The second word of these instructions will be executed as a NOP,
unless the first word of the instruction retrieves the information embedded in these 16-bits. This ensures that all
program memory locations have a valid instruction.
5: If the Table Write starts the write cycle to internal memory, the write will continue until terminated.
DS39564A-page 214
Advance Information
PIC18FXX2
20.1
Instruction Set
ADDLW
ADD literal to W
Syntax:
[ label ] ADDLW
Operands:
0 k 255
Operation:
(W) + k W
Status Affected:
N, OV, C, DC, Z
Encoding:
0000
Description:
Syntax:
kkkk
kkkk
Words:
[ label ] ADDWF
0 f 255
d [0,1]
a [0,1]
Operation:
Status Affected:
N, OV, C, DC, Z
Encoding:
0010
Example:
Q3
Words:
1
1
Q4
Process
Data
Write to W
ADDLW
0x15
Before Instruction
W
0x10
ffff
Cycles:
Q2
Read
literal k
Decode
ffff
Q Cycle Activity:
Q1
01da
Description:
Cycles:
ADD W to f
Operands:
1111
ADDWF
Q Cycle Activity:
Q1
Decode
Q2
Q3
Q4
Read
register f
Process
Data
Write to
destination
After Instruction
W
0x25
Example:
ADDWF
REG, 0, 0
Before Instruction
W
REG
=
=
0x17
0xC2
After Instruction
W
REG
Advance Information
=
=
0xD9
0xC2
DS39564A-page 215
PIC18FXX2
ADDWFC
ANDLW
Syntax:
[ label ] ADDWFC
Syntax:
[ label ] ANDLW
Operands:
0 f 255
d [0,1]
a [0,1]
f [,d [,a]
Operands:
Operation:
Status Affected:
N,OV, C, DC, Z
Encoding:
0010
Description:
00da
ffff
ffff
0000
1011
kkkk
kkkk
Description:
Words:
Cycles:
Q Cycle Activity:
Q1
Decode
Cycles:
N,Z
Encoding:
Words:
(W) .AND. k W
Status Affected:
0 k 255
Operation:
Q2
Q3
Q4
Read literal
k
Process
Data
Write to W
1
Example:
Q Cycle Activity:
Q1
Decode
Q2
Q3
Q4
Read
register f
Process
Data
Write to
destination
ADDWFC
0x5F
Before Instruction
W
0xA3
After Instruction
W
Example:
ANDLW
0x03
REG, 0, 1
Before Instruction
Carry bit =
REG
=
W
=
1
0x02
0x4D
After Instruction
Carry bit =
REG
=
W
=
DS39564A-page 216
0
0x02
0x50
Advance Information
PIC18FXX2
ANDWF
AND W with f
BC
Syntax:
[ label ] ANDWF
Operands:
Syntax:
0 f 255
d [0,1]
a [0,1]
Status Affected:
N,Z
Encoding:
0001
if carry bit is 1
(PC) + 2 + 2n PC
Status Affected:
-128 n 127
Operation:
Operation:
[ label ] BC
Operands:
f [,d [,a]
Branch if Carry
None
Encoding:
01da
ffff
ffff
1110
0010
nnnn
nnnn
Description:
Words:
Cycles:
1(2)
Description:
Words:
Cycles:
Q Cycle Activity:
Q1
Decode
Q2
Q3
Q4
Read
register f
Process
Data
Write to
destination
Example:
ANDWF
REG, 0, 0
Before Instruction
W
REG
=
=
0x17
0xC2
=
=
Q2
Q3
Q4
Decode
Read literal
n
Process
Data
Write to PC
No
operation
No
operation
No
operation
No
operation
If No Jump:
Q1
Decode
After Instruction
W
REG
Q Cycle Activity:
If Jump:
Q1
Q2
Q3
Q4
Read literal
n
Process
Data
No
operation
0x02
0xC2
Example:
HERE
BC
Before Instruction
PC
address (HERE)
=
=
=
=
1;
address (HERE+12)
0;
address (HERE+2)
After Instruction
If Carry
PC
If Carry
PC
Advance Information
DS39564A-page 217
PIC18FXX2
BCF
Bit Clear f
Syntax:
[ label ] BCF
Operands:
0 f 255
0b7
a [0,1]
Operation:
Encoding:
1001
[ label ] BN
Operands:
-128 n 127
Operation:
if negative bit is 1
(PC) + 2 + 2n PC
Status Affected:
None
Branch if Negative
Syntax:
f,b[,a]
0 f<b>
Status Affected:
BN
None
Encoding:
bbba
ffff
ffff
1110
0110
nnnn
nnnn
Description:
Words:
Cycles:
Description:
1(2)
Words:
Cycles:
Q Cycle Activity:
Q1
Decode
Q2
Q3
Q4
Read
register f
Process
Data
Write
register f
Q Cycle Activity:
If Jump:
Q1
Example:
BCF
Before Instruction
FLAG_REG = 0xC7
After Instruction
FLAG_REG = 0x47
FLAG_REG,
Q2
Q3
Q4
Decode
Read literal
n
Process
Data
Write to PC
No
operation
No
operation
No
operation
No
operation
7, 0
If No Jump:
Q1
Decode
Q2
Q3
Q4
Read literal
n
Process
Data
No
operation
Example:
HERE
BN
Jump
Before Instruction
PC
address (HERE)
=
=
=
=
1;
address (Jump)
0;
address (HERE+2)
After Instruction
If Negative
PC
If Negative
PC
DS39564A-page 218
Advance Information
PIC18FXX2
BNC
BNN
Syntax:
[ label ] BNC
Syntax:
[ label ] BNN
Operands:
-128 n 127
Operands:
-128 n 127
Operation:
if carry bit is 0
(PC) + 2 + 2n PC
Operation:
if negative bit is 0
(PC) + 2 + 2n PC
Status Affected:
None
Status Affected:
None
Encoding:
1110
0011
nnnn
nnnn
Encoding:
1110
0111
nnnn
nnnn
Description:
Description:
Words:
Words:
Cycles:
1(2)
Cycles:
1(2)
Q Cycle Activity:
If Jump:
Q1
Q Cycle Activity:
If Jump:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
Decode
Read literal
n
Process
Data
Write to PC
Decode
Read literal
n
Process
Data
Write to PC
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
Q2
Q3
Q4
Read literal
n
Process
Data
No
operation
If No Jump:
Q1
Decode
Example:
HERE
BNC
Q2
Q3
Q4
Read literal
n
Process
Data
No
operation
HERE
BNN
Jump
Before Instruction
=
address (HERE)
PC
After Instruction
If Carry
PC
If Carry
PC
Decode
Example:
Jump
Before Instruction
PC
If No Jump:
Q1
address (HERE)
=
=
=
=
0;
address (Jump)
1;
address (HERE+2)
After Instruction
=
=
=
=
0;
address (Jump)
1;
address (HERE+2)
If Negative
PC
If Negative
PC
Advance Information
DS39564A-page 219
PIC18FXX2
BNOV
BNZ
Syntax:
[ label ] BNOV
Syntax:
[ label ] BNZ
Operands:
-128 n 127
Operands:
-128 n 127
Operation:
if overflow bit is 0
(PC) + 2 + 2n PC
Operation:
if zero bit is 0
(PC) + 2 + 2n PC
Status Affected:
None
Status Affected:
None
Encoding:
1110
0101
nnnn
nnnn
Encoding:
1110
0001
nnnn
nnnn
Description:
Description:
Words:
Words:
Cycles:
1(2)
Cycles:
1(2)
Q Cycle Activity:
If Jump:
Q1
Q Cycle Activity:
If Jump:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
Decode
Read literal
n
Process
Data
Write to PC
Decode
Read literal
n
Process
Data
Write to PC
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
Q2
Q3
Q4
Read literal
n
Process
Data
No
operation
If No Jump:
Q1
Decode
Example:
HERE
DS39564A-page 220
Q2
Q3
Q4
Read literal
n
Process
Data
No
operation
HERE
BNZ
Jump
Before Instruction
=
address (HERE)
PC
After Instruction
If Overflow
PC
If Overflow
PC
Decode
Example:
BNOV Jump
Before Instruction
PC
If No Jump:
Q1
address (HERE)
=
=
=
=
0;
address (Jump)
1;
address (HERE+2)
After Instruction
=
=
=
=
0;
address (Jump)
1;
address (HERE+2)
If Zero
PC
If Zero
PC
Advance Information
PIC18FXX2
BRA
Unconditional Branch
BSF
Bit Set f
Syntax:
[ label ] BRA
Syntax:
[ label ] BSF
Operands:
-1024 n 1023
Operands:
Operation:
(PC) + 2 + 2n PC
Status Affected:
None
0 f 255
0b7
a [0,1]
Operation:
1 f<b>
Status Affected:
None
Encoding:
Description:
1101
0nnn
nnnn
nnnn
Encoding:
Cycles:
Q Cycle Activity:
Q1
Q2
Q3
Q4
Read literal
n
Process
Data
Write to PC
No
operation
No
operation
Q Cycle Activity:
Q1
No
operation
Decode
Example:
HERE
BRA
Jump
PC
Q2
Q3
Q4
Read
register f
Process
Data
Write
register f
BSF
address (HERE)
FLAG_REG, 7, 1
Before Instruction
FLAG_REG
Before Instruction
0x0A
0x8A
After Instruction
address (Jump)
After Instruction
PC
ffff
Words:
Example:
ffff
Description:
No
operation
bbba
Cycles:
Words:
Decode
1000
f,b[,a]
FLAG_REG
Advance Information
DS39564A-page 221
PIC18FXX2
BTFSC
BTFSS
Syntax:
Syntax:
Operands:
0 f 255
0b7
a [0,1]
Operands:
0 f 255
0b<7
a [0,1]
Operation:
skip if (f<b>) = 0
Operation:
skip if (f<b>) = 1
Status Affected:
None
Status Affected:
None
Encoding:
1011
bbba
ffff
ffff
Encoding:
1010
bbba
ffff
ffff
Description:
Description:
Words:
Words:
Cycles:
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Cycles:
1(2)
Note:
Q Cycle Activity:
Q1
Q2
Q3
Q4
Read
register f
Decode
Process Data
Q Cycle Activity:
Q1
No
operation
If skip:
Q2
Q3
Q4
Read
register f
Decode
Process Data
No
operation
If skip:
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
Q4
Q4
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
Example:
HERE
FALSE
TRUE
BTFSC
:
:
FLAG, 1, 0
Before Instruction
PC
DS39564A-page 222
HERE
FALSE
TRUE
BTFSS
:
:
FLAG, 1, 0
Before Instruction
=
address (HERE)
PC
After Instruction
If FLAG<1>
PC
If FLAG<1>
PC
Example:
address (HERE)
=
=
=
=
0;
address (FALSE)
1;
address (TRUE)
After Instruction
=
=
=
=
0;
address (TRUE)
1;
address (FALSE)
If FLAG<1>
PC
If FLAG<1>
PC
Advance Information
PIC18FXX2
BTG
Bit Toggle f
BOV
Branch if Overflow
Syntax:
Syntax:
[ label ] BOV
Operands:
0 f 255
0b<7
a [0,1]
Operands:
-128 n 127
Operation:
if overflow bit is 1
(PC) + 2 + 2n PC
Status Affected:
None
Operation:
(f<b>) f<b>
Status Affected:
None
Encoding:
Encoding:
0111
bbba
ffff
ffff
1110
0100
nnnn
nnnn
Description:
Words:
Cycles:
Description:
1(2)
Words:
Cycles:
Q Cycle Activity:
Q1
Decode
Q2
Q3
Q4
Read
register f
Process
Data
Write
register f
Q Cycle Activity:
If Jump:
Q1
Example:
BTG
PORTC,
After Instruction:
PORTC
Q3
Q4
Read literal
n
Process
Data
Write to PC
No
operation
No
operation
No
operation
No
operation
4, 0
Before Instruction:
PORTC
Q2
Decode
If No Jump:
Q1
Decode
Q2
Q3
Q4
Read literal
n
Process
Data
No
operation
Example:
HERE
BOV
Jump
Before Instruction
PC
address (HERE)
=
=
=
=
1;
address (Jump)
0;
address (HERE+2)
After Instruction
If Overflow
PC
If Overflow
PC
Advance Information
DS39564A-page 223
PIC18FXX2
BZ
Branch if Zero
CALL
Subroutine Call
Syntax:
[ label ] BZ
Syntax:
Operands:
-128 n 127
Operands:
Operation:
if Zero bit is 1
(PC) + 2 + 2n PC
0 k 1048575
s [0,1]
Operation:
(PC) + 4 TOS,
k PC<20:1>,
if s = 1
(W) WS,
(STATUS) STATUSS,
(BSR) BSRS
Status Affected:
None
Status Affected:
None
Encoding:
1110
Description:
0000
nnnn
nnnn
Encoding:
1st word (k<7:0>)
2nd word(k<19:8>)
110s
k19kkk
k7kkk
kkkk
kkkk0
kkkk8
Cycles:
Cycles:
Description:
Words:
Words:
1(2)
Q Cycle Activity:
If Jump:
Q1
Q2
Q3
Q4
Decode
Read literal
n
Process
Data
Write to PC
No
operation
No
operation
No
operation
No
operation
Q2
Q3
Q4
Read literal
n
Process
Data
No
operation
If No Jump:
Q1
Decode
1110
1111
Example:
HERE
BZ
Q Cycle Activity:
Q1
Q3
Q4
Read literal
k<7:0>,
Push PC to
stack
Read literal
k<19:8>,
Write to PC
No
operation
Jump
Q2
Decode
No
operation
No
operation
No
operation
Before Instruction
PC
address (HERE)
=
=
=
=
1;
address (Jump)
0;
address (HERE+2)
After Instruction
If Zero
PC
If Zero
PC
Example:
HERE
CALL
THERE,1
Before Instruction
PC
address (HERE)
After Instruction
PC
=
TOS
=
WS
=
BSRS
=
STATUSS=
DS39564A-page 224
Advance Information
address (THERE)
address (HERE + 4)
W
BSR
STATUS
PIC18FXX2
CLRF
Clear f
CLRWDT
Syntax:
[label] CLRF
Operands:
0 f 255
a [0,1]
Operation:
[ label ] CLRWDT
Operands:
None
Operation:
000h WDT,
000h WDT postscaler,
1 TO,
1 PD
Status Affected:
TO, PD
000h f
1Z
Status Affected:
Syntax:
f [,a]
Encoding:
Description:
0110
101a
ffff
ffff
Encoding:
0000
0000
0000
0100
Description:
Words:
Words:
Cycles:
Cycles:
Q Cycle Activity:
Q1
Decode
Q Cycle Activity:
Q1
Q2
Q3
Q4
Read
register f
Process
Data
Write
register f
Decode
Example:
Example:
CLRF
FLAG_REG,1
Before Instruction
FLAG_REG
Q3
Q4
Process
Data
No
operation
CLRWDT
Before Instruction
WDT Counter
0x5A
0x00
After Instruction
FLAG_REG
Q2
No
operation
=
=
=
=
0x00
0
1
1
After Instruction
WDT Counter
WDT Postscaler
TO
PD
Advance Information
DS39564A-page 225
PIC18FXX2
COMF
Complement f
Syntax:
[ label ] COMF
Operands:
0 f 255
d [0,1]
a [0,1]
Operation:
( f ) dest
Status Affected:
N, Z
Encoding:
0001
Description:
Syntax:
ffff
ffff
Words:
0 f 255
a [0,1]
(f) (W),
skip if (f) = (W)
(unsigned comparison)
Status Affected:
None
Encoding:
Decode
ffff
Q2
Q3
Q4
Words:
Process
Data
Write to
destination
Cycles:
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
COMF
Before Instruction
=
0x13
After Instruction
REG
W
ffff
Read
register f
Example:
REG
001a
Q Cycle Activity:
Q1
0110
f [,a]
Description:
Cycles:
[ label ] CPFSEQ
Operation:
f [,d [,a]
Operands:
11da
CPFSEQ
=
=
0x13
0xEC
REG, 0, 0
Q Cycle Activity:
Q1
Decode
Q2
Q3
Q4
Read
register f
Process
Data
No
operation
If skip:
Q1
Q2
Q3
Q4
No
operation
No
operation
No
operation
No
operation
Q4
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
Example:
HERE
NEQUAL
EQUAL
CPFSEQ REG, 0
:
:
Before Instruction
PC Address
W
REG
=
=
=
HERE
?
?
=
=
W;
Address (EQUAL)
W;
Address (NEQUAL)
After Instruction
If REG
PC
If REG
PC
DS39564A-page 226
Advance Information
PIC18FXX2
CPFSGT
CPFSLT
Syntax:
[ label ] CPFSGT
Syntax:
[ label ] CPFSLT
Operands:
0 f 255
a [0,1]
Operands:
0 f 255
a [0,1]
Operation:
(f) (W),
skip if (f) > (W)
(unsigned comparison)
Operation:
(f) (W),
skip if (f) < (W)
(unsigned comparison)
Status Affected:
None
Status Affected:
None
Encoding:
Description:
0110
010a
f [,a]
ffff
ffff
Words:
Cycles:
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1
Decode
Encoding:
Q2
Q3
No
operation
If skip:
Q1
Q2
Q3
Q4
No
operation
No
operation
No
operation
No
operation
Cycles:
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1
Q2
Q3
Q4
No
operation
No
operation
No
operation
Q4
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
HERE
NGREATER
GREATER
CPFSGT REG, 0
:
:
Example:
Q4
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
HERE
NLESS
LESS
CPFSLT REG, 1
:
:
Before Instruction
PC
W
=
=
Address (HERE)
?
<
=
W;
Address (LESS)
W;
Address (NLESS)
After Instruction
=
=
Address (HERE)
?
>
=
W;
Address (GREATER)
W;
Address (NGREATER)
After Instruction
Q4
No
operation
Q1
No
operation
If REG
PC
If REG
PC
Q3
Process
Data
No
operation
No
operation
PC
W
Q2
Read
register f
If skip:
No
operation
Before Instruction
ffff
Words:
No
operation
Example:
ffff
Q4
Process
Data
000a
Description:
Decode
Read
register f
0110
f [,a]
If REG
PC
If REG
PC
Advance Information
DS39564A-page 227
PIC18FXX2
DAW
DECF
Decrement f
Syntax:
[label] DAW
Syntax:
Operands:
None
Operands:
Operation:
0 f 255
d [0,1]
a [0,1]
Operation:
(f) 1 dest
Status Affected:
C, DC, N, OV, Z
0000
Description:
0000
0000
Cycles:
Q Cycle Activity:
Q1
Q2
Q3
Cycles:
Write
W
Q2
Q3
Q4
Read
register f
Process
Data
Write to
destination
Q4
Process
Data
ffff
Words:
Decode
Read
register W
ffff
Q Cycle Activity:
Q1
01da
Description:
0111
Words:
Example1:
DAW
Before Instruction
W
C
DC
0000
Encoding:
Decode
Encoding:
=
=
=
0xA5
0
0
Example:
DECF
CNT,
1, 0
Before Instruction
CNT
Z
=
=
0x01
0
After Instruction
CNT
Z
=
=
0x00
1
After Instruction
W
C
DC
=
=
=
0x05
1
0
Example 2:
Before Instruction
W
C
DC
=
=
=
0xCE
0
0
After Instruction
W
C
DC
=
=
=
DS39564A-page 228
0x34
1
0
Advance Information
PIC18FXX2
DECFSZ
Decrement f, skip if 0
DCFSNZ
Syntax:
Syntax:
[label] DCFSNZ
Operands:
0 f 255
d [0,1]
a [0,1]
Operands:
0 f 255
d [0,1]
a [0,1]
Operation:
(f) 1 dest,
skip if result = 0
Operation:
(f) 1 dest,
skip if result 0
Status Affected:
None
Status Affected:
None
Encoding:
0010
11da
ffff
ffff
Encoding:
0100
11da
f [,d [,a]
ffff
ffff
Description:
Description:
Words:
Words:
Cycles:
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Cycles:
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Read
register f
Process
Data
Write to
destination
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
Decode
If skip:
Decode
Q2
Q3
Q4
Read
register f
Process
Data
Write to
destination
If skip:
Q4
Q4
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
DECFSZ
GOTO
CNT, 1, 1
LOOP
Example:
HERE
Example:
CONTINUE
Before Instruction
PC
=
=
=
=
DCFSNZ
:
:
TEMP, 1, 0
Before Instruction
Address (HERE)
After Instruction
CNT
If CNT
PC
If CNT
PC
HERE
ZERO
NZERO
TEMP
=
=
=
TEMP - 1,
0;
Address (ZERO)
0;
Address (NZERO)
After Instruction
CNT - 1
0;
Address (CONTINUE)
0;
Address (HERE+2)
TEMP
If TEMP
PC
If TEMP
PC
Advance Information
DS39564A-page 229
PIC18FXX2
GOTO
Unconditional Branch
INCF
Increment f
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
0 k 1048575
Operands:
Operation:
k PC<20:1>
Status Affected:
None
0 f 255
d [0,1]
a [0,1]
Operation:
(f) + 1 dest
Status Affected:
C, DC, N, OV, Z
Encoding:
1st word (k<7:0>)
2nd word(k<19:8>)
Description:
1110
1111
GOTO k
1111
k19kkk
k7kkk
kkkk
kkkk0
kkkk8
Encoding:
0010
f [,d [,a]
10da
ffff
ffff
Cycles:
Cycles:
Description:
Words:
Words:
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read literal
k<7:0>,
No
operation
Read literal
k<19:8>,
Write to PC
No
operation
No
operation
No
operation
No
operation
Example:
GOTO THERE
After Instruction
PC =
INCF
Address (THERE)
Q Cycle Activity:
Q1
Decode
Q2
Q3
Q4
Read
register f
Process
Data
Write to
destination
Example:
INCF
CNT, 1, 0
Before Instruction
CNT
Z
C
DC
=
=
=
=
0xFF
0
?
?
After Instruction
CNT
Z
C
DC
DS39564A-page 230
Advance Information
=
=
=
=
0x00
1
1
1
PIC18FXX2
INCFSZ
Increment f, skip if 0
INFSNZ
Syntax:
[ label ]
Syntax:
[label]
Operands:
0 f 255
d [0,1]
a [0,1]
Operands:
0 f 255
d [0,1]
a [0,1]
Operation:
(f) + 1 dest,
skip if result = 0
Operation:
(f) + 1 dest,
skip if result 0
Status Affected:
None
Status Affected:
None
Encoding:
0011
INCFSZ
11da
f [,d [,a]
ffff
ffff
Encoding:
0100
INFSNZ
10da
f [,d [,a]
ffff
ffff
Description:
Description:
Words:
Words:
Cycles:
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Cycles:
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Read
register f
Process
Data
Write to
destination
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
Decode
If skip:
Decode
Q2
Q3
Q4
Read
register f
Process
Data
Write to
destination
If skip:
Q4
Q4
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
Example:
HERE
NZERO
ZERO
INCFSZ
:
:
Before Instruction
PC
=
=
=
=
Example:
HERE
ZERO
NZERO
INFSNZ
REG, 1, 0
Before Instruction
Address (HERE)
After Instruction
CNT
If CNT
PC
If CNT
PC
CNT, 1, 0
PC
Address (HERE)
After Instruction
CNT + 1
0;
Address (ZERO)
0;
Address (NZERO)
REG
If REG
PC
If REG
PC
Advance Information
=
=
=
REG + 1
0;
Address (NZERO)
0;
Address (ZERO)
DS39564A-page 231
PIC18FXX2
IORLW
IORWF
Inclusive OR W with f
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
0 f 255
d [0,1]
a [0,1]
Operation:
Status Affected:
N, Z
IORLW k
Operands:
0 k 255
Operation:
(W) .OR. k W
Status Affected:
N, Z
Encoding:
0000
Description:
1001
kkkk
kkkk
Encoding:
0001
IORWF
00da
f [,d [,a]
ffff
ffff
Cycles:
Cycles:
Words:
Words:
Description:
Q Cycle Activity:
Q1
Q2
Example:
Q3
Q4
Read
literal k
Decode
Process
Data
Write to W
IORLW
Before Instruction
W
0x9A
After Instruction
W
0x35
Q Cycle Activity:
Q1
Decode
0xBF
Q2
Q3
Q4
Read
register f
Process
Data
Write to
destination
Example:
IORWF
RESULT, 0, 1
Before Instruction
RESULT =
W
=
0x13
0x91
After Instruction
RESULT =
W
=
DS39564A-page 232
Advance Information
0x13
0x93
PIC18FXX2
LFSR
Load FSR
MOVF
Move f
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
0f2
0 k 4095
Operands:
Operation:
k FSRf
0 f 255
d [0,1]
a [0,1]
Status Affected:
None
Operation:
f dest
Status Affected:
N, Z
Encoding:
LFSR f,k
1110
1111
1110
0000
00ff
k7kkk
k11kkk
kkkk
Description:
Words:
Cycles:
Encoding:
MOVF
0101
f [,d [,a]
00da
ffff
ffff
Q2
Q3
Read literal
k MSB
Process
Data
Read literal
k LSB
Process
Data
Write literal
k to FSRfL
1
1
Write
literal k
MSB to
FSRfH
Decode
Words:
Q4
Decode
Cycles:
Q Cycle Activity:
Q1
Description:
Example:
LFSR 2, 0x3AB
After Instruction
FSR2H
FSR2L
=
=
0x03
0xAB
Q Cycle Activity:
Q1
Decode
Example:
Q2
Q3
Q4
Read
register f
Process
Data
Write W
MOVF
REG, 0, 0
Before Instruction
REG
W
=
=
0x22
0xFF
=
=
0x22
0x22
After Instruction
REG
W
Advance Information
DS39564A-page 233
PIC18FXX2
MOVFF
Move f to f
MOVLB
Syntax:
[label]
Syntax:
[ label ]
Operands:
0 fs 4095
0 fd 4095
Operands:
0 k 255
Operation:
k BSR
None
MOVFF fs,fd
Operation:
(fs) fd
Status Affected:
Status Affected:
None
Encoding:
Encoding:
1st word (source)
2nd word (destin.)
1100
1111
Description:
ffff
ffff
ffff
ffff
ffffs
ffffd
MOVLB k
0000
0001
kkkk
kkkk
Description:
Words:
Cycles:
Q Cycle Activity:
Q1
Decode
Example:
Q2
Q3
Q4
Read literal
k
Process
Data
Write
literal k to
BSR
MOVLB
Before Instruction
BSR register
0x02
0x05
After Instruction
BSR register
Cycles:
2 (3)
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register f
(src)
Process
Data
No
operation
Decode
No
operation
No
operation
Write
register f
(dest)
No dummy
read
Example:
MOVFF
REG1, REG2
Before Instruction
REG1
REG2
=
=
0x33
0x11
=
=
0x33,
0x33
After Instruction
REG1
REG2
DS39564A-page 234
Advance Information
PIC18FXX2
MOVLW
Move literal to W
MOVWF
Move W to f
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
0 k 255
Operands:
Operation:
kW
0 f 255
a [0,1]
Status Affected:
None
Operation:
(W) f
Status Affected:
None
Encoding:
0000
Description:
MOVLW k
1110
kkkk
kkkk
Words:
0110
Description:
Q Cycle Activity:
Q1
Q2
Q3
Q4
Read
literal k
Decode
Process
Data
Write to W
MOVLW
0x5A
After Instruction
W
0x5A
Words:
ffff
ffff
Cycles:
Example:
111a
f [,a]
Cycles:
Encoding:
MOVWF
Q Cycle Activity:
Q1
Decode
Q2
Q3
Q4
Read
register f
Process
Data
Write
register f
Example:
MOVWF
REG, 0
Before Instruction
W
REG
=
=
0x4F
0xFF
After Instruction
W
REG
Advance Information
=
=
0x4F
0x4F
DS39564A-page 235
PIC18FXX2
MULLW
MULWF
Multiply W with f
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
0 f 255
a [0,1]
Operation:
Status Affected:
None
MULLW
Operands:
0 k 255
Operation:
(W) x k PRODH:PRODL
Status Affected:
None
Encoding:
Description:
0000
1101
kkkk
kkkk
Words:
Decode
Example:
Q2
Q3
Process
Data
Write
registers
PRODH:
PRODL
MULLW
0xC4
=
=
=
Cycles:
Q Cycle Activity:
Q1
Decode
W
PRODH
PRODL
Example:
=
=
=
Q2
Q3
Q4
Read
register f
Process
Data
Write
registers
PRODH:
PRODL
0xE2
?
?
After Instruction
0xE2
0xAD
0x08
ffff
Before Instruction
W
PRODH
PRODL
ffff
Words:
Q4
Read
literal k
001a
Q Cycle Activity:
Q1
0000
f [,a]
Description:
Cycles:
Encoding:
MULWF
MULWF
REG, 1
Before Instruction
W
REG
PRODH
PRODL
=
=
=
=
0xC4
0xB5
?
?
=
=
=
=
0xC4
0xB5
0x8A
0x94
After Instruction
W
REG
PRODH
PRODL
DS39564A-page 236
Advance Information
PIC18FXX2
NEGF
Negate f
NOP
Syntax:
[label]
Operands:
0 f 255
a [0,1]
NEGF
Syntax:
f [,a]
N, OV, C, DC, Z
110a
Q Cycle Activity:
Q1
Decode
Description:
0000
xxxx
0000
xxxx
0000
xxxx
No operation.
Words:
Cycles:
Q Cycle Activity:
Q1
Decode
Q2
Q3
Q4
No
operation
No
operation
No
operation
Example:
Q2
Q3
Q4
Read
register f
Process
Data
Write
register f
Example:
0000
1111
ffff
Cycles:
None
Encoding:
ffff
Words:
None
No operation
Status Affected:
Status Affected:
Description:
NOP
Operation:
(f)+1f
0110
[ label ]
Operands:
Operation:
Encoding:
No Operation
NEGF
None.
REG, 1
Before Instruction
REG
After Instruction
REG
Advance Information
DS39564A-page 237
PIC18FXX2
POP
PUSH
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
None
Operands:
None
Operation:
Operation:
(PC+2) TOS
Status Affected:
None
Status Affected:
None
Encoding:
0000
Description:
POP
0000
0000
0110
Words:
Cycles:
Q Cycle Activity:
Q1
Decode
Encoding:
Q2
Q3
Cycles:
No
operation
Example:
POP
GOTO
=
=
DS39564A-page 238
=
=
Q3
Q4
No
operation
No
operation
PUSH
TOS
PC
0031A2h
014332h
After Instruction
TOS
PC
Q2
PUSH PC+2
onto return
stack
Before Instruction
NEW
Before Instruction
TOS
Stack (1 level down)
0101
Words:
Q4
POP TOS
value
0000
Q Cycle Activity:
Q1
No
operation
0000
Description:
Decode
Example:
0000
PUSH
014332h
NEW
=
=
00345Ah
000124h
=
=
=
000126h
000126h
00345Ah
After Instruction
PC
TOS
Stack (1 level down)
Advance Information
PIC18FXX2
RCALL
Relative Call
RESET
Reset
Syntax:
[ label ] RCALL
Syntax:
[ label ]
Operands:
Operation:
-1024 n 1023
Operands:
None
(PC) + 2 TOS,
(PC) + 2 + 2n PC
Operation:
Status Affected:
None
Status Affected:
All
Encoding:
Description:
1101
1nnn
nnnn
nnnn
Words:
Cycles:
Q Cycle Activity:
Q1
Decode
Encoding:
0000
RESET
0000
1111
1111
Description:
Words:
Cycles:
Q Cycle Activity:
Q1
Q2
Example:
Q3
Q4
Start
reset
Decode
No
operation
No
operation
RESET
After Instruction
Q2
Q3
Q4
Read literal
n
Process
Data
Reset Value
Reset Value
Write to PC
No
operation
Registers =
Flags*
=
No
operation
Push PC to
stack
No
operation
Example:
No
operation
HERE
RCALL Jump
Before Instruction
PC =
Address (HERE)
After Instruction
PC =
TOS =
Address (Jump)
Address (HERE+2)
Advance Information
DS39564A-page 239
PIC18FXX2
RETFIE
RETLW
Return Literal to W
Syntax:
[ label ]
Syntax:
[ label ]
RETFIE [s]
RETLW k
Operands:
s [0,1]
Operands:
0 k 255
Operation:
(TOS) PC,
1 GIE/GIEH or PEIE/GIEL,
if s = 1
(WS) W,
(STATUSS) STATUS,
(BSRS) BSR,
PCLATU, PCLATH are unchanged.
Operation:
k W,
(TOS) PC,
PCLATU, PCLATH are unchanged
Status Affected:
None
Status Affected:
Encoding:
0000
0000
Description:
0000
0001
Words:
Cycles:
kkkk
Words:
Cycles:
000s
kkkk
Description:
GIE/GIEH, PEIE/GIEL.
Encoding:
1100
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
literal k
Process
Data
pop PC from
stack, Write
to W
No
operation
No
operation
No
operation
No
operation
Q Cycle Activity:
Q1
Decode
Example:
Q2
Q3
Q4
No
operation
No
operation
pop PC from
stack
Set GIEH or
GIEL
No
operation
No
operation
Example:
RETFIE
No
operation
No
operation
CALL TABLE ;
;
;
;
:
TABLE
ADDWF PCL ;
RETLW k0
;
RETLW k1
;
:
:
RETLW kn
;
W contains table
offset value
W now has
table value
W = offset
Begin table
End of table
After Interrupt
PC
W
BSR
STATUS
GIE/GIEH, PEIE/GIEL
DS39564A-page 240
=
=
=
=
=
TOS
WS
BSRS
STATUSS
1
Before Instruction
W
0x07
After Instruction
W
Advance Information
value of kn
PIC18FXX2
RETURN
RLCF
Syntax:
[ label ]
Syntax:
[ label ]
RETURN [s]
RLCF
f [,d [,a]
Operands:
s [0,1]
Operands:
Operation:
(TOS) PC,
if s = 1
(WS) W,
(STATUSS) STATUS,
(BSRS) BSR,
PCLATU, PCLATH are unchanged
0 f 255
d [0,1]
a [0,1]
Operation:
(f<n>) dest<n+1>,
(f<7>) C,
(C) dest<0>
Status Affected:
C, N, Z
None
Encoding:
Status Affected:
Encoding:
0000
0000
0001
001s
Description:
Q Cycle Activity:
Q1
Words:
Q2
Q3
Q4
No
operation
Process
Data
pop PC from
stack
No
operation
No
operation
No
operation
No
operation
After Interrupt
PC = TOS
ffff
Cycles:
Q Cycle Activity:
Q1
Decode
Q2
Q3
Q4
Read
register f
Process
Data
Write to
destination
Example:
RETURN
ffff
register f
Decode
Example:
01da
Cycles:
Description:
Words:
0011
RLCF
REG, 0, 0
Before Instruction
REG
C
=
=
1110 0110
0
After Instruction
REG
W
C
Advance Information
=
=
=
1110 0110
1100 1100
1
DS39564A-page 241
PIC18FXX2
RLNCF
RRCF
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
0 f 255
d [0,1]
a [0,1]
Operands:
0 f 255
d [0,1]
a [0,1]
Operation:
(f<n>) dest<n+1>,
(f<7>) dest<0>
Operation:
Status Affected:
N, Z
(f<n>) dest<n-1>,
(f<0>) C,
(C) dest<7>
Status Affected:
C, N, Z
Encoding:
0100
Description:
RLNCF
01da
f [,d [,a]
ffff
ffff
Encoding:
0011
Description:
Cycles:
00da
f [,d [,a]
ffff
ffff
register f
Words:
RRCF
1
Words:
Q Cycle Activity:
Q1
Decode
Q2
Q3
Q4
Read
register f
Process
Data
Write to
destination
Cycles:
Q Cycle Activity:
Q1
Decode
Example:
register f
RLNCF
REG, 1, 0
Q2
Q3
Q4
Read
register f
Process
Data
Write to
destination
Before Instruction
REG
1010 1011
After Instruction
REG
Example:
RRCF
REG, 0, 0
Before Instruction
0101 0111
REG
C
=
=
1110 0110
0
After Instruction
REG
W
C
DS39564A-page 242
Advance Information
=
=
=
1110 0110
0111 0011
0
PIC18FXX2
RRNCF
SETF
Set f
Syntax:
[ label ]
Syntax:
[label] SETF
Operands:
0 f 255
d [0,1]
a [0,1]
Operands:
0 f 255
a [0,1]
Operation:
(f<n>) dest<n-1>,
(f<0>) dest<7>
FFh f
Operation:
Status Affected:
None
Status Affected:
N, Z
Encoding:
0100
Description:
RRNCF
00da
f [,d [,a]
Encoding:
ffff
ffff
Words:
ffff
ffff
Description:
Words:
Cycles:
Q Cycle Activity:
Q1
Decode
100a
Q2
Q3
Q4
Read
register f
Process
Data
Write
register f
Cycles:
0110
f [,a]
SETF
REG,1
Before Instruction
Q Cycle Activity:
Q1
Decode
Example:
Q2
Q3
Q4
Read
register f
Process
Data
Write to
destination
Example 1:
RRNCF
REG
0x5A
0xFF
After Instruction
REG
REG, 1, 0
Before Instruction
REG
1101 0111
After Instruction
REG
Example 2:
1110 1011
RRNCF
REG, 0, 0
Before Instruction
W
REG
=
=
?
1101 0111
After Instruction
W
REG
=
=
1110 1011
1101 0111
Advance Information
DS39564A-page 243
PIC18FXX2
SLEEP
SUBFWB
Syntax:
[ label ] SLEEP
Syntax:
[ label ] SUBFWB
Operands:
None
Operands:
Operation:
00h WDT,
0 WDT postscaler,
1 TO,
0 PD
0 f 255
d [0,1]
a [0,1]
Operation:
Status Affected:
N, OV, C, DC, Z
TO, PD
Encoding:
Status Affected:
Encoding:
0000
0000
0000
0011
0101
Words:
Cycles:
Cycles:
Q2
No
operation
Q3
Process
Data
Q4
Go to
sleep
Q Cycle Activity:
Q1
Decode
Example:
SLEEP
?
?
Q3
Q4
Process
Data
Write to
destination
SUBFWB
REG, 1, 0
Before Instruction
REG
W
C
After Instruction
TO =
PD =
Q2
Read
register f
Example 1:
Before Instruction
TO =
PD =
ffff
Description:
Decode
ffff
Words:
Description:
Q Cycle Activity:
Q1
01da
f [,d [,a]
1
0
=
=
=
3
2
1
After Instruction
REG
W
C
Z
N
=
=
=
=
=
Example 2:
FF
2
0
0
1 ; result is negative
SUBFWB
REG, 0, 0
Before Instruction
REG
W
C
=
=
=
2
5
1
After Instruction
REG
W
C
Z
N
=
=
=
=
=
Example 3:
2
3
1
0
0
; result is positive
SUBFWB
REG, 1, 0
Before Instruction
REG
W
C
=
=
=
1
2
0
After Instruction
REG
W
C
Z
N
DS39564A-page 244
Advance Information
=
=
=
=
=
0
2
1
1
0
; result is zero
PIC18FXX2
SUBLW
SUBWF
Subtract W from f
Syntax:
[ label ] SUBLW k
Syntax:
[ label ] SUBWF
Operands:
0 k 255
Operands:
Operation:
k (W) W
Status Affected:
N, OV, C, DC, Z
0 f 255
d [0,1]
a [0,1]
Operation:
Status Affected:
N, OV, C, DC, Z
Encoding:
0000
1000
kkkk
kkkk
Description:
Words:
Cycles:
Q Cycle Activity:
Q1
SUBLW
0x02
1
?
Example 2:
1
1
0
0
SUBLW
; result is positive
=
=
0x02
Example 3:
0
1
1
0
SUBLW
=
=
; result is zero
0x02
=
=
=
=
SUBWF
REG, 1, 0
=
=
=
3
2
?
REG
W
C
Z
N
=
=
=
=
=
Example 2:
1
2
1
0
0
SUBWF
; result is positive
REG, 0, 0
Before Instruction
3
?
After Instruction
W
C
Z
N
Q4
Write to
destination
After Instruction
Before Instruction
W
C
Q3
Process
Data
Before Instruction
REG
W
C
2
?
=
=
=
=
Q2
Read
register f
Example 1:
After Instruction
W
C
Z
N
Decode
Before Instruction
W
C
Q Cycle Activity:
Q1
After Instruction
=
=
=
=
ffff
Q4
Before Instruction
W
C
Z
N
ffff
Description:
Write to W
=
=
11da
Cycles:
Q3
Process
Data
Example 1:
W
C
0101
Words:
Q2
Read
literal k
Decode
Encoding:
f [,d [,a]
REG
W
C
=
=
=
2
2
?
After Instruction
FF ; (2s complement)
0 ; result is negative
0
1
REG
W
C
Z
N
=
=
=
=
=
Example 3:
2
0
1
1
0
SUBWF
; result is zero
REG, 1, 0
Before Instruction
REG
W
C
=
=
=
1
2
?
After Instruction
REG
W
C
Z
N
Advance Information
=
=
=
=
=
DS39564A-page 245
PIC18FXX2
SUBWFB
SWAPF
Swap f
Syntax:
[ label ] SUBWFB
Syntax:
Operands:
0 f 255
d [0,1]
a [0,1]
Operands:
0 f 255
d [0,1]
a [0,1]
Operation:
Operation:
Status Affected:
N, OV, C, DC, Z
(f<3:0>) dest<7:4>,
(f<7:4>) dest<3:0>
Status Affected:
None
Encoding:
Description:
0101
10da
f [,d [,a]
ffff
ffff
Subtract W and the carry flag (borrow) from register 'f' (2s complement
method). If 'd' is 0, the result is stored
in W. If 'd' is 1, the result is stored
back in register 'f' (default). If a is 0,
the Access Bank will be selected,
overriding the BSR value. If a is 1,
then the bank will be selected as per
the BSR value (default).
Words:
0011
Description:
Decode
Words:
Q2
Q3
Q4
Read
register f
Process
Data
Write to
destination
Example 1:
SUBWFB
=
=
=
(0001 1001)
(0000 1101)
=
=
=
=
=
Example 2:
Q Cycle Activity:
Q1
Decode
Q2
Q3
Q4
Read
register f
Process
Data
Write to
destination
SWAPF
REG, 1, 0
Before Instruction
REG
0x53
After Instruction
After Instruction
REG
W
C
Z
N
Example:
0x19
0x0D
1
ffff
REG, 1, 0
Before Instruction
REG
W
C
ffff
Cycles:
Q Cycle Activity:
Q1
10da
Cycles:
Encoding:
0x0C
0x0D
1
0
0
(0000 1011)
(0000 1101)
REG
0x35
; result is positive
SUBWFB REG, 0, 0
Before Instruction
REG
W
C
=
=
=
0x1B
0x1A
0
(0001 1011)
(0001 1010)
0x1B
0x00
1
1
0
(0001 1011)
After Instruction
REG
W
C
Z
N
=
=
=
=
=
Example 3:
SUBWFB
; result is zero
REG, 1, 0
Before Instruction
REG
W
C
=
=
=
0x03
0x0E
1
(0000 0011)
(0000 1101)
(1111 0100)
; [2s comp]
(0000 1101)
After Instruction
REG
0xF5
W
C
Z
N
=
=
=
=
0x0E
0
0
1
DS39564A-page 246
; result is negative
Advance Information
PIC18FXX2
TBLRD
Table Read
TBLRD
Syntax:
[ label ]
Example1:
TBLRD
Operands:
None
Operation:
if TBLRD *,
(Prog Mem (TBLPTR)) TABLAT;
TBLPTR - No Change;
if TBLRD *+,
(Prog Mem (TBLPTR)) TABLAT;
(TBLPTR) +1 TBLPTR;
if TBLRD *-,
(Prog Mem (TBLPTR)) TABLAT;
(TBLPTR) -1 TBLPTR;
if TBLRD +*,
(TBLPTR) +1 TBLPTR;
(Prog Mem (TBLPTR)) TABLAT;
Before Instruction
Status Affected:None
Encoding:
0000
*+ ;
0000
0000
10nn
nn=0 *
=1 *+
=2 *=3 +*
Description:
0x55
0x00A356
0x34
=
=
0x34
0x00A357
After Instruction
TABLAT
TBLPTR
Example2:
TBLRD
+* ;
Before Instruction
TABLAT
TBLPTR
MEMORY(0x01A357)
MEMORY(0x01A358)
=
=
=
=
0xAA
0x01A357
0x12
0x34
=
=
0x34
0x01A358
After Instruction
TABLAT
TBLPTR
Cycles:
=
=
=
Words:
TABLAT
TBLPTR
MEMORY(0x00A356)
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
No
operation
No
operation
No
operation
No
operation
No operation
(Read Program
Memory)
No
No operation
operation (Write TABLAT)
Advance Information
DS39564A-page 247
PIC18FXX2
TBLWT
Table Write
TBLWT
Syntax:
[ label ]
Example1:
TBLWT
Before Instruction
Operands:
None
Operation:
if TBLWT*,
(TABLAT) Prog Mem (TBLPTR) or
Holding Register;
TBLPTR - No Change;
if TBLWT*+,
(TABLAT) Prog Mem (TBLPTR) or
Holding Register;
(TBLPTR) +1 TBLPTR;
if TBLWT*-,
(TABLAT) Prog Mem (TBLPTR) or
Holding Register;
(TBLPTR) -1 TBLPTR;
if TBLWT+*,
(TBLPTR) +1 TBLPTR;
(TABLAT) Prog Mem (TBLPTR) or
Holding Register;
0000
TABLAT
=
TBLPTR
=
MEMORY or HOLDING
REGISTER (0x00A356) =
0x55
0x00A356
0xFF
Example 2:
TBLWT
0x55
0x00A357
0x55
+*;
Before Instruction
TABLAT
TBLPTR
MEMORY or HOLDING
REGISTER (0x01389A)
MEMORY or HOLDING
REGISTER (0x01389B)
=
=
0x34
0x01389A
0xFF
0xFF
*+;
0000
0000
11nn
nn=0 *
=1 *+
=2 *=3 +*
Description:
0x34
0x01389B
0xFF
0x34
Cycles:
=
=
Words:
TABLAT
TBLPTR
MEMORY or HOLDING
REGISTER (0x01389A)
MEMORY or HOLDING
REGISTER (0x01389B)
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
No
operation
No
operation
No
operation
No
operation
No
operation
(Read
TABLAT)
No
operation
No
operation
(Write to Holding
Register or Memory)
DS39564A-page 248
Advance Information
PIC18FXX2
TSTFSZ
Test f, skip if 0
XORLW
Syntax:
Syntax:
[ label ] XORLW k
Operands:
0 f 255
a [0,1]
Operands:
0 k 255
Operation:
Operation:
skip if f = 0
(W) .XOR. k W
Status Affected:
N, Z
Status Affected:
None
Encoding:
Description:
Encoding:
0110
011a
ffff
ffff
Words:
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
1010
kkkk
kkkk
Description:
Words:
Cycles:
Q Cycle Activity:
Q1
Q2
Q3
Q4
Read
literal k
Decode
Process
Data
Write to W
Cycles:
0000
Q Cycle Activity:
Q1
Decode
Q2
Q3
Q4
Read
register f
Process
Data
No
operation
Example:
XORLW 0xAF
Before Instruction
W
0xB5
After Instruction
W
0x1A
If skip:
Q1
Q2
Q3
Q4
No
operation
No
operation
No
operation
No
operation
Q4
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
Example:
HERE
NZERO
ZERO
TSTFSZ
:
CNT, 1
Before Instruction
PC = Address (HERE)
After Instruction
If CNT
PC
If CNT
PC
=
=
0x00,
Address (ZERO)
0x00,
Address (NZERO)
Advance Information
DS39564A-page 249
PIC18FXX2
XORWF
Exclusive OR W with f
Syntax:
[ label ] XORWF
Operands:
0 f 255
d [0,1]
a [0,1]
Operation:
Status Affected:
N, Z
Encoding:
0001
10da
f [,d [,a]
ffff
ffff
Description:
Words:
Cycles:
Q Cycle Activity:
Q1
Decode
Q2
Q3
Q4
Read
register f
Process
Data
Write to
destination
Example:
XORWF
REG, 1, 0
Before Instruction
REG
W
=
=
0xAF
0xB5
After Instruction
REG
W
=
=
DS39564A-page 250
0x1A
0xB5
Advance Information
PIC18FXX2
21.0
DEVELOPMENT SUPPORT
21.1
21.2
MPASM Assembler
21.3
Advance Information
DS39564A-page 251
PIC18FXX2
21.4
21.6
21.5
The MPLAB SIM software simulator allows code development in a PC-hosted environment by simulating the
PICmicro series microcontrollers on an instruction
level. On any given instruction, the data areas can be
examined or modified and stimuli can be applied from
a file, or user-defined key press, to any of the pins. The
execution can be performed in single step, execute
until break, or trace mode.
21.7
The MPLAB SIM simulator fully supports symbolic debugging using the MPLAB C17 and the MPLAB C18 C compilers and the MPASM assembler. The software simulator
offers the flexibility to develop and debug code outside of
the laboratory environment, making it an excellent multiproject software development tool.
DS39564A-page 252
Advance Information
PIC18FXX2
21.8
Microchips In-Circuit Debugger, MPLAB ICD, is a powerful, low cost, run-time development tool. This tool is
based on the FLASH PICmicro MCUs and can be used
to develop for this and other PICmicro microcontrollers.
The MPLAB ICD utilizes the in-circuit debugging capability built into the FLASH devices. This feature, along
with Microchips In-Circuit Serial ProgrammingTM protocol, offers cost-effective in-circuit FLASH debugging
from the graphical user interface of the MPLAB
Integrated Development Environment. This enables a
designer to develop and debug source code by watching variables, single-stepping and setting break points.
Running at full speed enables testing hardware in realtime.
21.9
Advance Information
DS39564A-page 253
PIC18FXX2
21.13 PICDEM 3 Low Cost PIC16CXXX
Demonstration Board
The PICDEM 3 demonstration board is a simple demonstration board that supports the PIC16C923 and
PIC16C924 in the PLCC package. It will also support
future 44-pin PLCC microcontrollers with an LCD Module. All the necessary hardware and software is
included to run the basic demonstration programs. The
user can program the sample microcontrollers provided with the PICDEM 3 demonstration board on a
PRO MATE II device programmer, or a PICSTART Plus
development programmer with an adapter socket, and
easily test firmware. The MPLAB ICE in-circuit emulator may also be used with the PICDEM 3 demonstration
board to test firmware. A prototype area has been provided to the user for adding hardware and connecting it
to the microcontroller socket(s). Some of the features
include a RS-232 interface, push button switches, a
potentiometer for simulated analog input, a thermistor
and separate headers for connection to an external
LCD module and a keypad. Also provided on the
PICDEM 3 demonstration board is a LCD panel, with 4
commons and 12 segments, that is capable of displaying time, temperature and day of the week. The
PICDEM 3 demonstration board provides an additional
RS-232 interface and Windows software for showing
the demultiplexed LCD signals on a PC. A simple serial
interface allows the user to construct a hardware
demultiplexer for the LCD signals.
DS39564A-page 254
Advance Information
Software Tools
PIC18CXX2
PIC17C7XX
PIC17C4X
PIC16C9XX
PIC16F8XX
PIC16C8X
PIC16C7XX
PIC16C7X
PIC16F62X
PIC16CXXX
PIC16C6X
PIC16C5X
PIC14000
PIC12CXXX
Advance Information
MCRFXXX
24CXX/
25CXX/
93CXX
MCP2510
* Contact the Microchip Technology Inc. web site at www.microchip.com for information on how to use the MPLAB ICD In-Circuit Debugger (DV164001) with PIC16C62, 63, 64, 65, 72, 73, 74, 76, 77.
** Contact Microchip Technology Inc. for availability date.
Development tool is available on select devices.
PICDEMTM 17 Demonstration
Board
PICDEMTM 3 Demonstration
Board
PICDEMTM 2 Demonstration
Board
HCSXXX
PICDEMTM 1 Demonstration
Board
**
PRO MATE II
Universal Device Programmer
**
**
PIC18FXXX
MPASMTM Assembler/
MPLINKTM Object Linker
TABLE 21-1:
MPLAB Integrated
Development Environment
PIC18FXX2
DS39564A-page 255
PIC18FXX2
NOTES:
DS39564A-page 256
Advance Information
PIC18FXX2
22.0
ELECTRICAL CHARACTERISTICS
NOTICE: Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
Advance Information
DS39564A-page 257
PIC18FXX2
FIGURE 22-1:
6.0V
5.5V
5.0V
PIC18FXXX
Voltage
4.5V
4.2V
4.0V
3.5V
3.0V
2.5V
2.0V
40 MHz
Frequency
FIGURE 22-2:
6.0V
5.5V
Voltage
5.0V
PIC18LFXXX
4.5V
4.2V
4.0V
3.5V
3.0V
2.5V
2.0V
40 MHz
4 MHz
Frequency
FMAX = (20.0 MHz/V) (VDDAPPMIN - 2.0 V) + 4 MHz
Note: VDDAPPMIN is the minimum voltage of the PICmicro device in the application.
DS39564A-page 258
Advance Information
PIC18FXX2
22.1
PIC18LFXX2
(Industrial)
PIC18FXX2
(Industrial, Extended)
Param
No.
Symbol
Characteristic
Min
Typ
Max Units
Conditions
Supply Voltage
PIC18LFXX2 2.0
5.5
V
HS, XT, RC and LP osc mode
PIC18FXX2 4.2
5.5
V
VDR
RAM Data Retention
1.5
V
Voltage(1)
VDD Start Voltage
0.7
V
See section on Power-on Reset for details
VPOR
to ensure internal
Power-on Reset signal
SVDD
VDD Rise Rate
0.05
2.16
V
BORV1:BORV0 = 10 2.7
2.86
V
BORV1:BORV0 = 01 4.2
4.46
V
BORV1:BORV0 = 00 4.5
4.78
V
PIC18FXX2
BORV1:BORV0 = 1x N.A.
N.A.
V
Not in operating voltage range of device
BORV1:BORV0 = 01 4.2
4.46
V
BORV1:BORV0 = 00 4.5
4.78
V
Shading of rows is to assist in readability of the table.
This is the limit to which VDD can be lowered in SLEEP mode, or during a device RESET, without losing RAM
data.
The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin
loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an
impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD
MCLR = VDD; WDT enabled/disabled as specified.
The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is
measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD or VSS, and all
features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR,...).
For RC osc configuration, current through REXT is not included. The current through the resistor can be
estimated by the formula Ir = VDD/2REXT (mA) with REXT in kOhm.
VDD
D001
D001
D002
D003
D004
D005
D005
Legend:
Note 1:
2:
3:
4:
Advance Information
DS39564A-page 259
PIC18FXX2
22.1
PIC18LFXX2
(Industrial)
PIC18FXX2
(Industrial, Extended)
Param
No.
Symbol
IDD
Characteristic
Min
Typ
Max Units
Conditions
Supply Current(2,4)
D010
PIC18LFXX2
.068
mA
D010
PIC18FXX2
.4
mA
D010A
PIC18LFXX2
28
55
LP osc configuration
FOSC = 32 kHz, VDD = 2.0V
D010A
PIC18FXX2
88
250
LP osc configuration
FOSC = 32 kHz, VDD = 4.2V
D010C
PIC18LFXX2
38
mA
D010C
PIC18FXX2
38
mA
1.32
13.46
3.5
25
mA
mA
19.1
38
mA
13.46
25
mA
19.1
38
mA
HS osc configuration
FOSC = 25 MHz, VDD = 5.5V
HS + PLL osc configurations
FOSC = 10 MHz, VDD = 5.5V
29.6
55
D013
PIC18LFXX2
D013
PIC18FXX2
D014
PIC18LFXX2
D014
HS osc configuration
FOSC = 6 MHz, VDD = 2.0V
FOSC = 25 MHz, VDD = 5.5V
HS + PLL osc configurations
FOSC = 10 MHz, VDD = 5.5V
PIC18FXX2
Legend:
Note 1:
2:
3:
4:
DS39564A-page 260
Advance Information
PIC18FXX2
22.1
PIC18LFXX2
(Industrial)
PIC18FXX2
(Industrial, Extended)
Param
No.
Symbol
IPD
D020
Characteristic
Min
Typ
Max Units
Conditions
Power-down Current(3)
.09
2
A VDD = 2.0V, -40C to +85C
.11
4
A VDD = 5.5V, -40C to +85C
PIC18FXX2
.1
3
A VDD = 4.2V, -40C to +85C
.11
4
A VDD = 5.5V, -40C to +85C
.1
15
A VDD = 4.2V, -40C to +125C
.11
20
A VDD = 5.5V, -40C to +125C
Module Differential Current
IWDT
Watchdog Timer
1
A VDD = 2.0V
PIC18LFXX2
15
A VDD = 5.5V
Watchdog Timer
15
A VDD = 5.5V, -40C to +85C
PIC18FXX2
20
A VDD = 5.5V, -40C to +125C
IBOR
Brown-out Reset
45
A VDD = 5.5V
PIC18LFXX2
Brown-out Reset
50
A VDD = 5.5V, -40C to +85C
PIC18FXX2
50
A VDD = 5.5V, -40C to +125
ILVD
Low Voltage Detect
45
A VDD = 2.0V
PIC18LFXX2
Low Voltage Detect
40
A VDD = 4.2V, -40C to +85C
PIC18FXX2
50
A VDD = 4.2V, -40C to +125C
IOSCB
Timer1 Oscillator
15
A VDD = 2.0V
PIC18LFXX2
Timer1 Oscillator
D020
D021B
D022
D022
D022A
D022A
D022B
D022B
D025
D025
D026
Legend:
Note 1:
2:
3:
4:
Advance Information
DS39564A-page 261
PIC18FXX2
22.2
DC CHARACTERISTICS
Param
Symbol
No.
VIL
D030
D030A
D031
D032
D032A
D033
VIH
D040
Characteristic
Input Low Voltage
I/O ports:
with TTL buffer
with Schmitt Trigger buffer
RC3 and RC4
MCLR
OSC1 (in XT, HS and LP modes)
and T1OSI
OSC1 (in RC and EC mode)(1)
Input High Voltage
I/O ports:
with TTL buffer
D040A
D041
D042
D042A
D043
IIL
D060
Min
Max
Units
Conditions
Vss
Vss
Vss
VSS
VSS
0.15VDD
0.8
0.2VDD
0.3VDD
0.2VDD
0.3VDD
V
V
V
V
V
V
VSS
0.2VDD
0.25VDD +
0.8V
2.0
VDD
VDD
0.8VDD
0.7VDD
0.8VDD
0.7VDD
VDD
VDD
VDD
VDD
V
V
V
V
0.9VDD
VDD
5
A
MCLR
OSC1
5
A
IPU
Weak Pull-up Current
D070
IPURB
PORTB weak pull-up current
50
400
A VDD = 5V, VPIN = VSS
Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that
the PICmicro device be driven with an external clock while in RC mode.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current may be measured at different input
voltages.
3: Negative current is defined as current sourced by the pin.
4: Parameter is characterized but not tested.
D061
D063
DS39564A-page 262
Advance Information
PIC18FXX2
22.2
DC CHARACTERISTICS
Param
Symbol
No.
D090
D090A
D092
OSC2/CLKOUT
(RC mode)
D092A
D150
VOD
D100(4) COSC2
D101
D102
Note 1:
2:
3:
4:
0.6
0.6
VDD - 0.7
VDD - 0.7
VOH
0.6
VDD - 0.7
D083A
VDD - 0.7
OSC2/CLKOUT
(RC mode)
0.6
D083
Units
D080A
Max
Min
VOL
D080
Characteristic
8.5
15
Conditions
pF
50
pF To meet the AC Timing
(in RC mode)
Specifications
SCL, SDA
400
pF In I2C mode
CB
In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that
the PICmicro device be driven with an external clock while in RC mode.
The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current may be measured at different input
voltages.
Negative current is defined as current sourced by the pin.
Parameter is characterized but not tested.
Advance Information
DS39564A-page 263
PIC18FXX2
FIGURE 22-3:
VLVD
(LVDIF set by hardware)
LVDIF
TABLE 22-1:
Param
Symbol
No.
D420
Characteristic
LVD Voltage on
VDD transition high LVV = 0000
to low
LVV = 0001
Min
Typ
Max
Units
1.8
1.86
1.91
2.06
2.12
2.2
2.27
2.34
LVV = 0011
2.4
2.47
2.55
2.5
2.0
LVV = 0010
2.58
Conditions
2.66
V
LVV = 0100
LVV = 0101
2.7
2.78
2.86
V
LVV = 0110
2.8
2.89
2.98
V
LVV = 0111
3.0
3.1
3.2
V
LVV = 1000
3.3
3.41
3.52
V
LVV = 1001
3.5
3.61
3.72
V
LVV = 1010
3.6
3.72
3.84
V
LVV = 1011
3.8
3.92
4.04
V
LVV = 1100
4.0
4.13
4.26
V
LVV = 1101
4.2
4.33
4.46
V
LVV = 1110
4.5
4.64
4.78
V
Production tested at TAMB = 25C. Specifications over temp. limits guaranteed by characterization.
DS39564A-page 264
Advance Information
PIC18FXX2
TABLE 22-2:
DC Characteristics
Param
No.
Sym
Characteristic
Min
Typ
Max
Units
Conditions
VPP
9.00
13.25
(Note 2)
D112
IPP
mA
D113
IDDP
10
mA
D120
ED
Cell Endurance(3)
100K
1M
D120A ED
Cell
Endurance(3)
10K
100K
D121
VDRW
VMIN
5.5
D122
TDEW
ms
D130
EP
Cell Endurance(4)
10K
100K
D130A EP
Cell
Endurance(4)
1000
10K
D131
VPR
VMIN
5.5
D132
VIE
4.5
5.5
D132A VIW
4.5
5.5
D132B VPEW
VMIN
5.5
D133
ms
D133A TIW
ms
D133A TIW
ms
TIE
Data in Typ column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: These specifications are for programming the on-chip program memory through the use of Table Write
instructions.
2: The pin may be kept in this range at times other than programming, but it is not recommended.
3: See Section 6.5.1 for additional information.
4: See Section 5.5.2 for additional information.
Advance Information
DS39564A-page 265
PIC18FXX2
22.3
22.3.1
AC (Timing) Characteristics
TIMING PARAMETER SYMBOLOGY
DS39564A-page 266
3. TCC:ST
4. Ts
Time
osc
rd
rw
sc
ss
t0
t1
wr
OSC1
RD
RD or WR
SCK
SS
T0CKI
T1CKI
WR
P
R
V
Z
Period
Rise
Valid
Hi-impedance
High
Low
High
Low
SU
Setup
STO
STOP condition
Advance Information
PIC18FXX2
22.3.2
TIMING CONDITIONS
TABLE 22-3:
AC CHARACTERISTICS
FIGURE 22-4:
Load condition 2
VDD/2
RL
CL
Pin
VSS
CL
Pin
RL = 464
VSS
CL = 50 pF
Advance Information
DS39564A-page 267
PIC18FXX2
22.3.3
FIGURE 22-5:
Q1
Q2
Q3
Q4
Q1
OSC1
1
CLKOUT
TABLE 22-4:
Param.
No.
1A
Symbol
FOSC
TOSC
Characteristic
Min
Max
Units
External CLKIN
Frequency(1)
Oscillator Frequency(1)
DC
40
MHz
EC, ECIO
DC
0.1
4
4
5
4
4
25
10
200
MHz
MHz
MHz
MHz
kHz
RC osc
XT osc
HS osc
HS + PLL osc
LP osc mode
25
ns
EC, ECIO
250
250
25
100
25
10,000
250
250
ns
ns
ns
ns
s
RC osc
XT osc
HS osc
HS + PLL osc
LP osc
(1)
Oscillator Period
Conditions
100
ns
TCY = 4/FOSC
30
ns
XT osc
2.5
s
LP osc
10
ns
HS osc
External Clock in (OSC1)
20
ns
XT osc
4
TosR,
TosF
Rise or Fall Time
50
ns
LP osc
7.5
ns
HS osc
Note 1: Instruction cycle period (TCY) equals four times the input oscillator time-base period for all configurations
except PLL. All specified values are based on characterization data for that particular oscillator type under
standard operating conditions with the device executing code. Exceeding these specified limits may result in
an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to
operate at min. values with an external clock applied to the OSC1/CLKIN pin. When an external clock
input is used, the max. cycle time limit is DC (no clock) for all devices.
2
3
TCY
TosL,
TosH
DS39564A-page 268
Advance Information
PIC18FXX2
TABLE 22-5:
Param
No.
Sym
Characteristic
Min
Typ
Max
Units
Conditions
10
FSYS
16
40
trc
ms
-2
+2
%
CLK CLKOUT Stability (Jitter)
Data in Typ column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only
and are not tested.
FIGURE 22-6:
Q4
Q2
Q3
OSC1
11
10
CLKOUT
13
14
19
12
18
16
I/O Pin
(input)
17
I/O Pin
(output)
Note:
15
New Value
Old Value
20, 21
Refer to Figure 22-4 for load conditions.
Advance Information
DS39564A-page 269
PIC18FXX2
TABLE 22-6:
Param.
No.
10
11
12
13
14
15
16
17
18
18A
Symbol
Characteristic
Min
Typ
Max
TosH2ckL
TosH2ckH
TckR
TckF
TckL2ioV
TioV2ckH
TckH2ioI
TosH2ioV
TosH2ioI
OSC1 to CLKOUT
75
200
OSC1 to CLKOUT
75
200
CLKOUT rise time
35
100
CLKOUT fall time
35
100
CLKOUT to Port out valid
0.5TCY + 20
50
150
OSC1 (Q2 cycle) to PIC18FXXX
100
10
25
20A
PIC18LFXXX
60
21
TioF
Port output fall time
PIC18FXXX
10
25
21A
PIC18LFXXX
60
INT pin high or low time
Tcy
22
TINP
23
TRBP
RB7:RB4 change INT high or low time
Tcy
24
TRCP
RC7:RC4 change INT high or low time
20
These parameters are asynchronous events not related to any internal clock edges.
Note 1: Measurements are taken in RC mode, where CLKOUT output is 4 x TOSC.
FIGURE 22-7:
Units Conditions
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
(1)
(1)
(1)
(1)
(1)
(1)
(1)
ns
ns
ns
ns
ns
ns
ns
ns
VDD
MCLR
30
Internal
POR
33
PWRT
Time-out
32
OSC
Time-out
Internal
Reset
Watchdog
Timer
Reset
34
31
34
I/O Pins
Note:
DS39564A-page 270
Advance Information
PIC18FXX2
FIGURE 22-8:
VDD
35
VBGAP = 1.2V
VIRVST
TABLE 22-7:
Param.
Symbol
No.
30
31
TmcL
TWDT
32
33
34
TOST
TPWRT
TIOZ
35
TBOR
36
TIVRST
36
Characteristic
Typ
Max
Units
2
MCLR Pulse Width (low)
Watchdog Timer Time-out Period
7
(No Postscaler)
Oscillation Start-up Timer Period
1024TOSC
Power up Timer Period
28
I/O Hi-impedance from MCLR Low
18
33
s
ms
72
2
1024TOSC
132
ms
s
20
50
Min
Advance Information
Conditions
DS39564A-page 271
PIC18FXX2
FIGURE 22-9:
T0CKI
41
40
42
T1OSO/T1CKI
46
45
47
48
TMR0 or
TMR1
Note:
TABLE 22-8:
Param
Symbol
No.
Characteristic
40
Tt0H
41
Tt0L
42
Tt0P
T0CKI Period
45
Tt1H
T1CKI
Synchronous, no prescaler
High Time Synchronous,
PIC18FXXX
with prescaler
PIC18LFXXX
Asynchronous
46
47
48
No Prescaler
With Prescaler
No Prescaler
With Prescaler
No Prescaler
With Prescaler
PIC18FXXX
PIC18LFXXX
Tt1L
T1CKI Low Synchronous, no prescaler
Time
Synchronous,
PIC18FXXX
with prescaler
PIC18LFXXX
Asynchronous PIC18FXXX
PIC18LFXXX
Tt1P
T1CKI
Synchronous
input
period
Asynchronous
Ft1
T1CKI oscillator input frequency range
Tcke2tmrI Delay from external T1CKI clock edge to
timer increment
DS39564A-page 272
Min
Max
Units
0.5TCY + 20
10
0.5TCY + 20
10
TCY + 10
Greater of:
20 nS or TCY + 40
N
0.5TCY + 20
10
25
30
50
0.5TCY + 5
10
25
30
TBD
Greater of:
20 nS or TCY + 40
N
60
DC
2TOSC
ns
ns
ns
ns
ns
ns
TBD
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
50
7TOSC
ns
kHz
Advance Information
Conditions
N = prescale
value
(1, 2, 4,..., 256)
N = prescale
value
(1, 2, 4, 8)
PIC18FXX2
FIGURE 22-10:
50
51
52
CCPx
(Compare or PWM Mode)
53
Note:
TABLE 22-9:
54
Param.
Symbol
No.
Characteristic
Min
Max
Units
0.5TCY + 20
10
20
0.5TCY + 20
10
20
3TCY + 40
N
ns
ns
ns
ns
ns
ns
ns
25
45
25
45
ns
ns
ns
ns
50
TccL
51
TccH
CCPx input
high time
52
TccP
No Prescaler
With
PIC18FXXX
Prescaler PIC18LFXXX
CCPx input period
53
TccR
54
TccF
PIC18FXXX
PIC18LFXXX
PIC18FXXX
PIC18LFXXX
Advance Information
Conditions
N = prescale
value (1,4 or 16)
DS39564A-page 273
PIC18FXX2
FIGURE 22-11:
RE2/CS
RE0/RD
RE1/WR
65
RD7:RD0
62
64
63
Note:
Symbol
Characteristic
Min
Max
Units
62
TdtV2wrH
63
TwrH2dtI
64
TrdL2dtV
65
66
TrdH2dtI
TibfINH
20
25
20
35
10
80
90
30
3TCY
ns
ns
ns
ns
ns
ns
ns
DS39564A-page 274
RD or CS to dataout invalid
Inhibit of the IBF flag bit being cleared from
WR or CS
Advance Information
Conditions
PIC18FXX2
FIGURE 22-12:
SS
70
SCK
(CKP = 0)
71
72
78
79
79
78
SCK
(CKP = 1)
80
bit6 - - - - - -1
MSb
SDO
LSb
75, 76
SDI
MSb IN
bit6 - - - -1
LSb IN
74
73
Note:
Symbol
TssL2scH,
TssL2scL
TscH
TscL
TdiV2scH,
TdiV2scL
TB2B
75
TscH2diL,
TscL2diL
TdoR
76
78
TdoF
TscR
Characteristic
Min
Tcy
Continuous
Single Byte
SCK input low time
Continuous
(Slave mode)
Single Byte
Setup time of SDI data input to SCK edge
Last clock edge of Byte1 to the 1st clock edge
of Byte2
Hold time of SDI data input to SCK edge
SDO data output rise time
1.25TCY + 30
40
1.25TCY + 30
40
ns
ns
ns
ns
100
ns
1.5TCY + 40
ns
100
ns
25
45
25
25
45
25
50
100
Conditions
ns
ns
ns
ns
ns
ns
ns
ns
ns
PIC18FXXX
PIC18LFXXX
PIC18FXXX
PIC18LFXXX
79
TscF
SCK output fall time (Master mode)
80
TscH2doV, SDO data output valid after
PIC18FXXX
TscL2doV SCK edge
PIC18LFXXX
Note 1: Requires the use of Parameter # 73A.
2: Only if Parameter # 71A and # 72A are used.
Max Units
Advance Information
(Note 1)
(Note 1)
(Note 2)
DS39564A-page 275
PIC18FXX2
FIGURE 22-13:
SS
81
SCK
(CKP = 0)
71
72
79
73
SCK
(CKP = 1)
80
78
MSb
SDO
bit6 - - - - - -1
LSb
75, 76
SDI
MSb IN
bit6 - - - -1
LSb IN
74
Note:
Symbol
TscH
TscL
TdiV2scH,
TdiV2scL
TB2B
75
TscH2diL,
TscL2diL
TdoR
76
78
TdoF
TscR
Characteristic
SCK input high time
(Slave mode)
Continuous
Single Byte
SCK input low time
Continuous
(Slave mode)
Single Byte
Setup time of SDI data input to SCK edge
Last clock edge of Byte1 to the 1st clock edge
of Byte2
Hold time of SDI data input to SCK edge
SDO data output rise time
PIC18FXXX
PIC18LFXXX
PIC18FXXX
PIC18LFXXX
79
TscF
SCK output fall time (Master mode)
80
TscH2doV, SDO data output valid after
PIC18FXXX
TscL2doV SCK edge
PIC18LFXXX
81
TdoV2scH, SDO data output setup to SCK edge
TdoV2scL
Note 1: Requires the use of Parameter # 73A.
2: Only if Parameter # 71A and # 72A are used.
DS39564A-page 276
Advance Information
Min
Max Units
1.25TCY + 30
40
1.25TCY + 30
40
ns
ns
ns
ns
100
ns
1.5TCY + 40
ns
100
ns
25
45
25
25
45
25
50
100
ns
ns
ns
ns
ns
ns
ns
ns
Conditions
ns
TCY
(Note 1)
(Note 1)
(Note 2)
PIC18FXX2
FIGURE 22-14:
SS
70
SCK
(CKP = 0)
83
71
72
78
79
79
78
SCK
(CKP = 1)
80
MSb
SDO
bit6 - - - - - -1
LSb
77
75, 76
SDI
MSb IN
bit6 - - - -1
LSb IN
74
73
Note:
TABLE 22-13: EXAMPLE SPI MODE REQUIREMENTS (SLAVE MODE TIMING (CKE = 0))
Param.
No.
70
Symbol
Characteristic
Min
TCY
Continuous
1.25TCY + 30
Single Byte
40
TscL
SCK input low time
Continuous
1.25TCY + 30
(Slave mode)
Single Byte
40
TdiV2scH, Setup time of SDI data input to SCK edge
100
TdiV2scL
Last clock edge of Byte1 to the first clock edge of Byte2 1.5TCY + 40
73A
TB2B
74
TscH2diL, Hold time of SDI data input to SCK edge
100
TscL2diL
75
TdoR
SDO data output rise time
PIC18FXXX
PIC18LFXXX
76
TdoF
SDO data output fall time
77
TssH2doZ SS to SDO output hi-impedance
10
78
TscR
SCK output rise time (Master mode)
PIC18FXXX
PIC18LFXXX
79
TscF
SCK output fall time (Master mode)
80
TscH2doV, SDO data output valid after SCK edge PIC18FXXX
TscL2doV
PIC18LFXXX
83
TscH2ssH, SS after SCK edge
1.5TCY + 40
TscL2ssH
Note 1: Requires the use of Parameter # 73A.
2: Only if Parameter # 71A and # 72A are used.
71
71A
72
72A
73
Advance Information
ns
ns
ns
ns
ns
ns
ns
ns
25
45
25
50
25
45
25
50
100
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
(Note 1)
(Note 1)
(Note 2)
DS39564A-page 277
PIC18FXX2
FIGURE 22-15:
SS
SCK
(CKP = 0)
70
83
71
72
SCK
(CKP = 1)
80
MSb
SDO
bit6 - - - - - -1
LSb
75, 76
SDI
Note:
MSb IN
77
bit6 - - - -1
LSb IN
74
Refer to Figure 22-4 for load conditions.
Symbol
TssL2scH,
TssL2scL
TscH
TscL
75
TB2B
TscH2diL,
TscL2diL
TdoR
76
77
78
Characteristic
Min
TCY
Continuous
1.25TCY + 30
Single Byte
40
SCK input low time
Continuous
1.25TCY + 30
(Slave mode)
Single Byte
40
Last clock edge of Byte1 to the first clock edge of Byte2 1.5TCY + 40
Hold time of SDI data input to SCK edge
100
TdoF
TssH2doZ
TscR
PIC18FXXX
PIC18LFXXX
10
DS39564A-page 278
Advance Information
1.5TCY + 40
ns
ns
ns
ns
ns
ns
ns
25
45
25
50
25
45
25
50
100
50
100
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
(Note 1)
(Note 1)
(Note 2)
PIC18FXX2
FIGURE 22-16:
SCL
91
93
90
92
SDA
STOP
Condition
START
Condition
Note:
Characteristic
TSU:STA
START condition
Setup time
THD:STA START condition
Hold time
TSU:STO STOP condition
Setup time
THD:STO STOP condition
Hold time
FIGURE 22-17:
Min
Units
Conditions
4700
600
4000
600
4700
600
4000
600
Max
ns
ns
ns
ns
102
100
101
SCL
90
106
107
91
92
SDA
In
110
109
109
SDA
Out
Note:
Advance Information
DS39564A-page 279
PIC18FXX2
TABLE 22-16: I2C BUS DATA REQUIREMENTS (SLAVE MODE)
Param.
No.
THIGH
Characteristic
Clock high time
Min
Max
Units
Conditions
4.0
100
Symbol
0.6
SSP Module
TLOW
1.5TCY
4.7
101
1.3
1.5TCY
1000
ns
20 + 0.1CB
300
ns
300
ns
20 + 0.1CB
300
ns
CB is specified to be from
10 to 400 pF
START condition
setup time
4.7
0.6
4.0
0.6
SSP Module
102
103
90
91
106
TR
TF
TSU:STA
THD:STA
THD:DAT
109
110
D102
TSU:STO
TAA
TBUF
CB
250
ns
100
ns
STOP condition
setup time
4.7
0.6
3500
ns
ns
4.7
1.3
400
ns
0.9
92
0
0
TSU:DAT
107
CB is specified to be from
10 to 400 pF
pF
(Note 2)
(Note 1)
Time the bus must be free
before a new transmission can
start
Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of
the falling edge of SCL to avoid unintended generation of START or STOP conditions.
2: A fast mode I2C bus device can be used in a standard mode I2C bus system, but the requirement TSU:DAT 250 ns must
then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a
device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line.
TR max. + TSU:DAT = 1000 + 250 = 1250 ns (according to the standard mode I2C bus specification) before the SCL line is
released.
DS39564A-page 280
Advance Information
PIC18FXX2
FIGURE 22-18:
SCL
93
91
90
92
SDA
STOP
Condition
START
Condition
Note:
TSU:STA
Characteristic
Min
Max
Units
ns
ns
START condition
2(TOSC)(BRG + 1)
Setup time
2(TOSC)(BRG + 1)
(1)
1 MHz mode
2(TOSC)(BRG + 1)
92
2(TOSC)(BRG + 1)
2(TOSC)(BRG + 1)
2(TOSC)(BRG + 1)
Hold time
91
2(TOSC)(BRG + 1)
93
Hold time
2(TOSC)(BRG + 1)
2(TOSC)(BRG + 1)
2(TOSC)(BRG + 1)
ns
2(TOSC)(BRG + 1)
2(TOSC)(BRG + 1)
1 MHz mode(1)
Setup time
Conditions
(1)
1 MHz mode
ns
FIGURE 22-19:
102
100
101
SCL
90
106
91
107
92
SDA
In
109
109
110
SDA
Out
Note:
Advance Information
DS39564A-page 281
PIC18FXX2
TABLE 22-18: MASTER SSP I2C BUS DATA REQUIREMENTS
Param.
Symbol
No.
Characteristic
Min
Max
Units
Conditions
ms
400 kHz mode
2(TOSC)(BRG + 1)
ms
ms
1 MHz mode(1) 2(TOSC)(BRG + 1)
101
TLOW
Clock low time
100 kHz mode
2(TOSC)(BRG + 1)
ms
400 kHz mode
2(TOSC)(BRG + 1)
ms
ms
1 MHz mode(1) 2(TOSC)(BRG + 1)
102
TR
SDA and SCL
100 kHz mode
1000
ns
CB is specified to be from
rise time
10 to 400 pF
400 kHz mode
20 + 0.1CB
300
ns
300
ns
1 MHz mode(1)
103
TF
SDA and SCL
100 kHz mode
300
ns
CB is specified to be from
fall time
10 to 400 pF
400 kHz mode
20 + 0.1CB
300
ns
100
ns
1 MHz mode(1)
90
TSU:STA START condition 100 kHz mode
2(TOSC)(BRG + 1)
ms Repeated START
(1)
1 MHz mode
2(TOSC)(BRG + 1)
ms condition
91
THD:STA START condition 100 kHz mode
2(TOSC)(BRG + 1)
ms
106
THD:DAT Data input
100 kHz mode
0
ns
hold time
400 kHz mode
0
0.9
ms
1 MHz mode(1)
TBD
ns
107
TSU:DAT Data input
100 kHz mode
250
ns
(Note 2)
setup time
400 kHz mode
100
ns
1 MHz mode(1)
TBD
ns
92
TSU:STO STOP condition 100 kHz mode
2(TOSC)(BRG + 1)
ms
setup time
400 kHz mode
2(TOSC)(BRG + 1)
ms
1 MHz mode(1) 2(TOSC)(BRG + 1)
ms
109
TAA
Output valid from 100 kHz mode
3500
ns
clock
400 kHz mode
1000
ns
1 MHz mode(1)
ns
110
TBUF
Bus free time
100 kHz mode
4.7
ms can start
D102
CB
Bus capacitive loading
400
pF
Note 1: Maximum pin capacitance = 10 pF for all I2C pins.
2: A fast mode I2C bus device can be used in a standard mode I2C bus system, but parameter #107 250 ns
must then be met. This will automatically be the case if the device does not stretch the LOW period of the
SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to
the SDA line, parameter #102.+ parameter #107 = 1000 + 250 = 1250 ns (for 100 kHz mode) before the SCL
line is released.
100
THIGH
DS39564A-page 282
Advance Information
PIC18FXX2
FIGURE 22-20:
RC6/TX/CK
pin
121
121
RC7/RX/DT
pin
120
Note:
122
Symbol
Characteristic
121
Tckrf
122
Tdtrf
FIGURE 22-21:
Min
PIC18FXXX
PIC18LFXXX
PIC18FXXX
PIC18LFXXX
PIC18FXXX
PIC18LFXXX
Max
Units
40
100
20
50
20
50
Conditions
ns
ns
ns
ns
ns
ns
RC6/TX/CK
pin
125
RC7/RX/DT
pin
126
Note:
Symbol
125
TdtV2ckl
126
TckL2dtl
Characteristic
SYNC RCV (MASTER & SLAVE)
Data hold before CK (DT hold time)
Data hold after CK (DT hold time)
Min
Max
Units
10
15
ns
ns
Advance Information
Conditions
DS39564A-page 283
PIC18FXX2
TABLE 22-21: A/D CONVERTER CHARACTERISTICS: PIC18FXX2 (INDUSTRIAL, EXTENDED)
PIC18LFXX2 (INDUSTRIAL)
Param
Symbol
No.
Characteristic
Min
Typ
Max
Units
bit
bit
Conditions
VREF = VDD 3.0V
VREF = VDD < 3.0V
A01
NR
Resolution
10
TBD
A03
EIL
<1
TBD
A04
EDL
<1
TBD
A05
EFS
<1
TBD
A06
EOFF
Offset error
<1
TBD
A10
Monotonicity
A20
VREF
Reference voltage
(VREFH - VREFL)
A20A
guaranteed(3)
0V
3V
A21
VREFH
AVss
AVDD + 0.3V
A22
VREFL
AVss - 0.3V
AVdd
A25
VAIN
AVSS - 0.3V
Vref + 0.3V
A30
ZAIN
Recommended impedance of
analog voltage source
10.0
A40
IAD
180
90
10
1000
10
A50
IREF
Average current
consumption when
A/D is on (Note 1)
During VAIN acquisition.
Based on differential of
VHOLD to VAIN. To charge
CHOLD see Section 17.0.
During A/D conversion cycle
Note 1: When A/D is off, it will not consume any current other than minor leakage current. The power-down current
spec includes any such leakage from the A/D module.
VREF current is from RA2/AN2/VREF- and RA3/AN3/VREF+ pins or AVDD and AVSS pins, whichever is
selected as reference input.
2: Vss VAIN VREF
3: The A/D conversion result never decreases with an increase in the Input Voltage, and has no missing codes.
DS39564A-page 284
Advance Information
PIC18FXX2
FIGURE 22-22:
BSF ADCON0, GO
(Note 2)
131
Q4
130
A/D CLK
132
A/D DATA
...
...
NEW_DATA
OLD_DATA
ADRES
TCY
ADIF
GO
DONE
SAMPLING STOPPED
SAMPLE
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts.
This allows the SLEEP instruction to be executed.
2: This is a minimal RC delay (typically 100 nS), which also disconnects the holding capacitor from the analog input.
TAD
Characteristic
A/D clock period
PIC18FXXX
Min
Max
Units
1.6
20(5)
(5)
PIC18LFXXX
3.0
PIC18FXXX
2.0
20
6.0
PIC18LFXXX
Conditions
TOSC based, VREF 3.0V
A/D RC mode
A/D RC mode
3.0
9.0
131
TCNV
Conversion time
(not including acquisition time) (Note 1)
11
12
TAD
132
TACQ
15
10
s
s
135
TSWC
(Note 4)
136
TAMP
Advance Information
DS39564A-page 285
PIC18FXX2
NOTES:
DS39564A-page 286
Advance Information
PIC18FXX2
23.0
DC AND AC
CHARACTERISTICS GRAPHS
AND TABLES
Advance Information
DS39564A-page 287
PIC18FXX2
NOTES:
DS39564A-page 288
Advance Information
PIC18FXX2
24.0
PACKAGING INFORMATION
24.1
Example
PIC18F242-I/SP
XXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXX
YYWWNNN
28-Lead SOIC
Example
XXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXX
YYWWNNN
Legend:
Note:
0117017
XX...X
Y
YY
WW
NNN
PIC18F242-E/SO
0110017
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line thus limiting the number of available characters
for customer specific information.
Standard PICmicro device marking consists of Microchip part number, year code, week code, and
traceability code. For PICmicro device marking beyond this, certain price adders apply. Please check
with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP
price.
Advance Information
DS39564A-page 289
PIC18FXX2
Package Marking Information (Contd)
40-Lead PDIP
Example
XXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXX
YYWWNNN
44-Lead TQFP
XXXXXXXXXX
XXXXXXXXXX
XXXXXXXXXX
YYWWNNN
44-Lead PLCC
XXXXXXXXXX
XXXXXXXXXX
XXXXXXXXXX
YYWWNNN
DS39564A-page 290
PIC18F442-I/P
0112017
Example
PIC18F452
-I/L
0120017
Example
PIC18F442
-E/PT
0120017
Advance Information
PIC18FXX2
24.2
Package Details
2
n
A2
A
L
B1
A1
eB
Units
Number of Pins
Pitch
Dimension Limits
n
p
INCHES*
MIN
NOM
MILLIMETERS
MAX
MIN
NOM
28
MAX
28
.100
2.54
.140
.150
.160
3.56
3.81
4.06
A2
.125
.130
.135
3.18
3.30
3.43
8.26
A1
.015
.300
.310
.325
7.62
7.87
E1
.275
.285
.295
6.99
7.24
7.49
Overall Length
1.345
1.365
1.385
34.16
34.67
35.18
L
c
.125
.130
.135
3.18
3.30
3.43
.008
.012
.015
0.20
0.29
0.38
B1
.040
.053
.065
1.02
1.33
1.65
Lead Thickness
Upper Lead Width
Lower Lead Width
Overall Row Spacing
Mold Draft Angle Top
Mold Draft Angle Bottom
0.38
.016
.019
.022
0.41
0.48
0.56
eB
.320
.350
.430
8.13
8.89
10.92
10
15
10
15
10
15
10
15
* Controlling Parameter
Significant Characteristic
Notes:
Dimension D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010 (0.254mm) per side.
JEDEC Equivalent: MO-095
Advance Information
DS39564A-page 291
PIC18FXX2
28-Lead Plastic Small Outline (SO) Wide, 300 mil (SOIC)
E
E1
p
B
2
1
n
h
45
c
A2
L
Units
Dimension Limits
n
p
Number of Pins
Pitch
Overall Height
Molded Package Thickness
Standoff
Overall Width
Molded Package Width
Overall Length
Chamfer Distance
Foot Length
Foot Angle Top
Lead Thickness
Lead Width
Mold Draft Angle Top
Mold Draft Angle Bottom
* Controlling Parameter
Significant Characteristic
A
A2
A1
E
E1
D
h
L
c
B
A1
MIN
.093
.088
.004
.394
.288
.695
.010
.016
0
.009
.014
0
0
INCHES*
NOM
28
.050
.099
.091
.008
.407
.295
.704
.020
.033
4
.011
.017
12
12
MAX
.104
.094
.012
.420
.299
.712
.029
.050
8
.013
.020
15
15
MILLIMETERS
NOM
28
1.27
2.36
2.50
2.24
2.31
0.10
0.20
10.01
10.34
7.32
7.49
17.65
17.87
0.25
0.50
0.41
0.84
0
4
0.23
0.28
0.36
0.42
0
12
0
12
MIN
MAX
2.64
2.39
0.30
10.67
7.59
18.08
0.74
1.27
8
0.33
0.51
15
15
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010 (0.254mm) per side.
JEDEC Equivalent: MS-013
Drawing No. C04-052
DS39564A-page 292
Advance Information
PIC18FXX2
40-Lead Plastic Dual In-line (P) 600 mil (PDIP)
E1
2
1
n
E
A2
B1
A1
eB
B
Units
Dimension Limits
n
p
MIN
INCHES*
NOM
40
.100
.175
.150
MAX
MILLIMETERS
NOM
40
2.54
4.06
4.45
3.56
3.81
0.38
15.11
15.24
13.46
13.84
51.94
52.26
3.05
3.30
0.20
0.29
0.76
1.27
0.36
0.46
15.75
16.51
5
10
5
10
MIN
Number of Pins
Pitch
Top to Seating Plane
A
.160
.190
Molded Package Thickness
A2
.140
.160
Base to Seating Plane
A1
.015
Shoulder to Shoulder Width
E
.595
.600
.625
Molded Package Width
E1
.530
.545
.560
Overall Length
D
2.045
2.058
2.065
Tip to Seating Plane
L
.120
.130
.135
c
Lead Thickness
.008
.012
.015
Upper Lead Width
B1
.030
.050
.070
Lower Lead Width
B
.014
.018
.022
Overall Row Spacing
eB
.620
.650
.680
Advance Information
MAX
4.83
4.06
15.88
14.22
52.45
3.43
0.38
1.78
0.56
17.27
15
15
DS39564A-page 293
PIC18FXX2
44-Lead Plastic Thin Quad Flatpack (PT) 10x10x1 mm Body, 1.0/0.10 mm Lead Form (TQFP)
E
E1
#leads=n1
p
D1
2
1
B
n
CH x 45
A
c
A1
A2
(F)
Units
Dimension Limits
n
p
Number of Pins
Pitch
Pins per Side
Overall Height
Molded Package Thickness
Standoff
Foot Length
Footprint (Reference)
Foot Angle
Overall Width
Overall Length
Molded Package Width
Molded Package Length
Lead Thickness
Lead Width
Pin 1 Corner Chamfer
Mold Draft Angle Top
Mold Draft Angle Bottom
* Controlling Parameter
Significant Characteristic
n1
A
A2
A1
L
(F)
E
D
E1
D1
c
B
CH
MIN
.039
.037
.002
.018
0
.463
.463
.390
.390
.004
.012
.025
5
5
INCHES
NOM
44
.031
11
.043
.039
.004
.024
.039
3.5
.472
.472
.394
.394
.006
.015
.035
10
10
MAX
.047
.041
.006
.030
7
.482
.482
.398
.398
.008
.017
.045
15
15
MILLIMETERS*
NOM
44
0.80
11
1.00
1.10
0.95
1.00
0.05
0.10
0.45
0.60
1.00
0
3.5
11.75
12.00
11.75
12.00
9.90
10.00
9.90
10.00
0.09
0.15
0.30
0.38
0.64
0.89
5
10
5
10
MIN
MAX
1.20
1.05
0.15
0.75
7
12.25
12.25
10.10
10.10
0.20
0.44
1.14
15
15
Notes:
Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010 (0.254mm) per side.
JEDEC Equivalent: MS-026
Drawing No. C04-076
DS39564A-page 294
Advance Information
PIC18FXX2
44-Lead Plastic Leaded Chip Carrier (L) Square (PLCC)
E
E1
#leads=n1
D1 D
n 1 2
CH2 x 45
CH1 x 45
A3
A2
35
A
B1
B
A1
p
E2
D2
Units
Dimension Limits
n
p
INCHES*
MIN
NOM
44
.050
11
.165
.173
.145
.153
.020
.028
.024
.029
.040
.045
.000
.005
.685
.690
.685
.690
.650
.653
.650
.653
.590
.620
.590
.620
.008
.011
.026
.029
.013
.020
0
5
0
5
MAX
MILLIMETERS
NOM
44
1.27
11
4.19
4.39
3.68
3.87
0.51
0.71
0.61
0.74
1.02
1.14
0.00
0.13
17.40
17.53
17.40
17.53
16.51
16.59
16.51
16.59
14.99
15.75
14.99
15.75
0.20
0.27
0.66
0.74
0.33
0.51
0
5
0
5
MIN
Number of Pins
Pitch
Pins per Side
n1
Overall Height
A
.180
Molded Package Thickness
A2
.160
Standoff
A1
.035
Side 1 Chamfer Height
A3
.034
Corner Chamfer 1
CH1
.050
Corner Chamfer (others)
CH2
.010
Overall Width
E
.695
Overall Length
D
.695
Molded Package Width
E1
.656
Molded Package Length
D1
.656
Footprint Width
E2
.630
Footprint Length
D2
.630
c
Lead Thickness
.013
Upper Lead Width
B1
.032
B
.021
Lower Lead Width
Advance Information
MAX
4.57
4.06
0.89
0.86
1.27
0.25
17.65
17.65
16.66
16.66
16.00
16.00
0.33
0.81
0.53
10
10
DS39564A-page 295
PIC18FXX2
NOTES:
DS39564A-page 296
Advance Information
PIC18FXX2
APPENDIX A:
REVISION HISTORY
APPENDIX B:
TABLE 1:
DEVICE
DIFFERENCES
DEVICE DIFFERENCES
Feature
PIC18F242
PIC18F252
PIC18F442
PIC18F452
16
32
16
32
768
1536
768
1536
A/D Channels
Parallel Slave Port (PSP)
Package Types
No
No
Yes
Yes
28-pin DIP
28-pin SOIC
28-pin DIP
28-pin SOIC
40-pin DIP
44-pin PLCC
44-pin TQFP
40-pin DIP
44-pin PLCC
44-pin TQFP
Advance Information
DS39564A-page 297
PIC18FXX2
APPENDIX C:
CONVERSION
CONSIDERATIONS
This appendix discusses the considerations for converting from previous versions of a device to the ones
listed in this data sheet. Typically, these changes are
due to the differences in the process technology used.
An example of this type of conversion is from a
PIC16C74A to a PIC16C74B.
Not Applicable
DS39564A-page 298
APPENDIX D:
MIGRATION FROM
BASELINE TO
ENHANCED DEVICES
Advance Information
PIC18FXX2
APPENDIX E:
MIGRATION FROM
MID-RANGE TO
ENHANCED DEVICES
APPENDIX F:
MIGRATION FROM
HIGH-END TO
ENHANCED DEVICES
A detailed discussion of the migration pathway and differences between the high-end MCU devices (i.e.,
PIC17CXXX) and the enhanced devices (i.e.,
PIC18FXXX) is provided in AN726, PIC17CXXX to
PIC18FXXX Migration. This Application Note is available as Literature Number DS00726.
Advance Information
DS39564A-page 299
PIC18FXX2
NOTES:
DS39564A-page 300
Advance Information
PIC18FXX2
INDEX
A
Advance Information
DS39564A-page 301
PIC18FXX2
C
DS39564A-page 302
E
Effect ................................................................................ 157
Electrical Characteristics .................................................. 257
Errata ................................................................................... 5
F
Firmware Instructions ....................................................... 209
FLASH Program Memory ................................................... 55
Associated Registers ................................................. 63
Block Diagrams
Table Writes to FLASH Program Memory ......... 61
Control Registers ....................................................... 56
EECON1 Register ...................................................... 57
Erase Sequence ........................................................ 60
Erasing ....................................................................... 60
Example ............................................................. 60
Operation During Code Protect ................................. 63
Reading ..................................................................... 59
Example ............................................................. 59
TABLAT Register ....................................................... 58
Table Pointer ............................................................. 58
Boundaries Based on Operation ........................ 58
Table Pointer Boundaries .......................................... 58
Table Reads and Table Writes .................................. 55
Block Diagrams
Reads from FLASH Program Memory ....... 59
Table Read Operation ............................... 55
Table Write Operation ............................... 56
Writing to .................................................................... 61
Protection Against Spurious Writes ................... 63
Unexpected Termination .................................... 63
Write Verify ........................................................ 63
G
General Call Address Sequence ...................................... 146
General Call Address Support ......................................... 146
GOTO .............................................................................. 230
Advance Information
PIC18FXX2
I
I/O Ports ............................................................................. 85
I2C (SSP Module)
ACK Pulse ........................................................ 136, 137
Read/Write Bit Information (R/W Bit) ....................... 137
I2C Master Mode Reception ............................................. 153
I2C Mode
Clock Stretching ....................................................... 142
I2C Mode (SSP Module) ................................................... 132
Registers .................................................................. 132
I2C Module
ACK Pulse ........................................................ 136, 137
Acknowledge Sequence Timing ............................... 156
Baud Rate Generator ............................................... 149
Block Diagram .......................................................... 132
Baud Rate Generator ....................................... 149
BRG Reset due to SDA Collision ............................. 159
BRG Timing ............................................................. 150
Bus Collision
Acknowledge .................................................... 157
Restart Condition ............................................. 160
Restart Condition Timing (Case1) .................... 160
Restart Condition Timing (Case2) .................... 160
START Condition ............................................. 158
START Condition Timing ......................... 158, 159
STOP Condition ............................................... 161
STOP Condition Timing (Case1) ..................... 161
STOP Condition Timing (Case2) ..................... 161
Transmit Timing ............................................... 157
Bus Collision and Arbitration .................................... 157
Bus Collision timing .................................................. 157
Clock Arbitration ....................................................... 150
Effects of a RESET .................................................. 157
General Call Address Support ................................. 146
Master Mode ............................................................ 147
Operation ......................................................... 148
Repeated START Timing ................................. 152
Master Mode 7-bit Reception Timing ....................... 155
Master Mode START Condition ............................... 151
Master Mode Timing (Transmission) ........................ 154
Master Mode Transmission ...................................... 153
Master Mode Transmit Sequence ............................ 148
Multi-Master Mode ................................................... 157
Operation ................................................................. 136
Read/Write Bit Information (R/W Bit) ............... 136, 137
Repeat START Condition Timing ............................. 152
Serial Clock (RC3/SCK/SCL) ................................... 137
Slave Mode .............................................................. 136
Addressing ....................................................... 136
Reception ......................................................... 137
Transmission .................................................... 137
Slave Mode Timing (10-bit Reception, SEN = 0) ..... 140
Slave Mode Timing (10-bit reception, SEN = 1) ....... 145
Slave Mode Timing (10-bit Transmission) ................ 141
Slave Mode Timing (7-bit Reception, SEN = 0) ....... 138
Slave Mode Timing (7-bit reception, SEN = 1) ......... 144
Slave Mode Timing (7-bit Transmission) .................. 139
SLEEP Operation ..................................................... 157
SSPCON1 Register ................................................. 134
SSPCON2 Register ................................................. 135
SSPSTAT Register .................................................. 133
STOP Condition Receive or Transmit Timing .......... 156
STOP Condition Timing ........................................... 156
Timing Diagram, Data .............................................. 279
Timing Diagram, START/STOP Bits ........................ 279
Advance Information
DS39564A-page 303
PIC18FXX2
RETLW ..................................................................... 240
RETURN .................................................................. 241
RLCF ........................................................................ 241
RLNCF ..................................................................... 242
RRCF ....................................................................... 242
RRNCF ..................................................................... 243
SETF ........................................................................ 243
SLEEP ...................................................................... 244
SUBFWB .................................................................. 244
SUBLW .................................................................... 245
SUBWF .................................................................... 245
SUBWFB .................................................................. 246
SWAPF .................................................................... 246
TBLRD ..................................................................... 247
TBLWT ..................................................................... 248
TSTFSZ .................................................................... 249
XORLW .................................................................... 249
XORWF .................................................................... 250
Summary Table ........................................................ 212
INT Interrupt (RB0/INT). See Interrupt Sources.
INTCON Register
RBIF Bit ...................................................................... 88
INTCON Registers ............................................................. 73
Inter-Integrated Circuit. See I2C.
Interrupt Sources .............................................................. 193
A/D Conversion Complete ........................................ 182
Capture Complete (CCP) ......................................... 117
Compare Complete (CCP) ....................................... 118
INT0 ........................................................................... 83
Interrupt-on-Change (RB7:RB4 ) ............................... 88
PORTB, Interrupt-on-Change .................................... 83
RB0/INT Pin, External ................................................ 83
TMR0 ......................................................................... 83
TMR0 Overflow ........................................................ 103
TMR1 Overflow ................................................ 105, 107
TMR2 to PR2 Match ................................................. 110
TMR2 to PR2 Match (PWM) ............................ 109, 120
TMR3 Overflow ................................................ 111, 113
USART Receive/Transmit Complete ........................ 163
Interrupts ............................................................................ 71
Logic ........................................................................... 72
Interrupts, Enable Bits
CCP1 Enable (CCP1IE Bit) ...................................... 117
Interrupts, Flag Bits
A/D Converter Flag (ADIF Bit) .................................. 181
CCP1 Flag (CCP1IF Bit) .......................................... 117
CCP1IF Flag (CCP1IF Bit) ....................................... 118
Interrupt-on-Change (RB7:RB4)
Flag (RBIF Bit) ................................................... 88
IORLW ............................................................................. 232
IORWF ............................................................................. 232
IPR Registers ..................................................................... 80
K
KEELOQ Evaluation and Programming Tools ................... 254
L
LATE Register .................................................................... 95
LFSR ................................................................................ 233
Low Voltage Detect .......................................................... 187
Block Diagrams
External Reference Source .............................. 188
Internal Reference Source ............................... 188
Converter Characteristics ......................................... 264
Effects of a RESET .................................................. 191
Operation ................................................................. 190
Current Consumption ....................................... 191
DS39564A-page 304
M
Master SSP (MSSP) Module Overview ........................... 123
Master Synchronous Serial Port (MSSP). See MSSP.
Master Synchronous Serial Port. See MSSP.
Memory Organization
Data Memory ............................................................. 42
Program Memory ....................................................... 35
Memory Programming Requirements .............................. 265
Migration from Baseline to Enhanced Devices ................ 298
Migration from High-End to Enhanced Devices ............... 299
Migration from Mid-Range to Enhanced Devices ............ 299
MOVF .............................................................................. 233
MOVFF ............................................................................ 234
MOVLB ............................................................................ 234
MOVLW ........................................................................... 235
MOVWF ........................................................................... 235
MPLAB C17 and MPLAB C18 C Compilers ..................... 251
MPLAB ICD In-Circuit Debugger ..................................... 253
MPLAB ICE High Performance Universal
In-Circuit Emulator with MPLAB IDE ....................... 252
MPLAB Integrated Development
Environment Software ............................................. 251
MPLINK Object Linker/MPLIB Object Librarian ............... 252
MSSP ............................................................................... 123
Block Diagram (SPI Mode) ...................................... 123
Control Registers (general) ...................................... 123
Enabling SPI I/O ...................................................... 127
Operation ................................................................. 126
Typical Connection .................................................. 127
MSSP Module
SPI Master Mode ..................................................... 128
SPI Master/Slave Connection .................................. 127
SPI Slave Mode ....................................................... 129
MULLW ............................................................................ 236
Multi-Master Mode ........................................................... 157
MULWF ............................................................................ 236
N
NEGF ............................................................................... 237
NOP ................................................................................. 237
O
OPCODE Field Descriptions ............................................ 210
OPTION_REG Register
PSA Bit .................................................................... 103
T0CS Bit .................................................................. 103
T0PS2:T0PS0 Bits ................................................... 103
T0SE Bit ................................................................... 103
Oscillator Configuration ...................................................... 17
EC .............................................................................. 17
ECIO .......................................................................... 17
HS .............................................................................. 17
HS + PLL ................................................................... 17
LP .............................................................................. 17
RC .............................................................................. 17
RCIO .......................................................................... 17
XT .............................................................................. 17
Oscillator Selection .......................................................... 193
Oscillator, Timer1 ..............................................105, 107, 113
Oscillator, Timer3 ............................................................. 111
Oscillator, WDT ................................................................ 201
Advance Information
PIC18FXX2
P
Packaging ........................................................................ 289
Parallel Slave Port (PSP) ............................................. 93, 98
Associated Registers ................................................. 99
Block Diagram ............................................................ 98
RE0/RD/AN5 Pin .................................................. 97, 98
RE1/WR/AN6 Pin ................................................. 97, 98
RE2/CS/AN7 Pin .................................................. 97, 98
Read Waveforms ....................................................... 99
Select (PSPMODE Bit) ........................................ 93, 98
Timing Diagram ........................................................ 274
Write Waveforms ....................................................... 98
PICDEM 1 Low Cost PICmicro
Demonstration Board ............................................... 253
PICDEM 17 Demonstration Board ................................... 254
PICDEM 2 Low Cost PIC16CXX
Demonstration Board ............................................... 253
PICDEM 3 Low Cost PIC16CXXX
Demonstration Board ............................................... 254
PICSTART Plus Entry Level
Development Programmer ....................................... 253
PIE Registers ..................................................................... 78
Pin Functions
MCLR/VPP ............................................................ 10, 13
OSC1/CLKI ................................................................ 10
OSC1/CLKIN .............................................................. 13
OSC2/CLKO/RA6 ...................................................... 10
OSC2/CLKOUT .......................................................... 13
RA0/AN0 .............................................................. 10, 13
RA1/AN1 .............................................................. 10, 13
RA2/AN2/VREF- .......................................................... 10
RA2/AN2/VREF- .......................................................... 13
RA3/AN3/VREF+ ................................................... 10, 13
RA4/T0CKI ........................................................... 10, 13
RA5/AN4/SS .............................................................. 13
RA5/AN4/SS/LVDIN ................................................... 10
RB0/INT ..................................................................... 14
RB0/INT0 ................................................................... 11
RB1 ............................................................................ 14
RB1/INT1 ................................................................... 11
RB2 ............................................................................ 14
RB2/INT2 ................................................................... 11
RB3 ............................................................................ 14
RB3/CCP2 ................................................................. 11
RB4 ...................................................................... 11, 14
RB5/PGM ............................................................. 11, 14
RB6/PGC ............................................................. 11, 14
RB7/PGD ............................................................. 11, 14
RC0/T1OSO/T1CKI ............................................. 12, 15
RC1/T1OSI/CCP2 ................................................ 12, 15
RC2/CCP1 ........................................................... 12, 15
RC3/SCK/SCL ..................................................... 12, 15
RC4/SDI/SDA ...................................................... 12, 15
RC5/SDO ............................................................. 12, 15
RC6/TX/CK .......................................................... 12, 15
RC7/RX/DT .......................................................... 12, 15
RD0/PSP0 .................................................................. 16
RD1/PSP1 .................................................................. 16
RD2/PSP2 .................................................................. 16
RD3/PSP3 .................................................................. 16
RD4/PSP4 .................................................................. 16
RD5/PSP5 .................................................................. 16
RD6/PSP6 .................................................................. 16
RD7/PSP7 .................................................................. 16
RE0/RD/AN5 .............................................................. 16
RE1/WR/AN6 ............................................................. 16
RE2/CS/AN7 .............................................................. 16
VDD .......................................................................12, 16
VSS .......................................................................12, 16
Pinout I/O Descriptions
PIC18F2X2 ................................................................ 10
PIR Registers ..................................................................... 76
PLL Lock Time-out ............................................................. 26
Pointer, FSR ...................................................................... 50
POP ................................................................................. 238
POR. See Power-on Reset.
PORTA
Associated Registers ................................................. 87
Initialization ................................................................ 85
LATA Register ........................................................... 85
PORTA Register ........................................................ 85
RA3:RA0 and RA5 Port Pins ..................................... 85
RA4/T0CKI Pin .......................................................... 86
RA6 Pin ..................................................................... 86
TRISA Register .......................................................... 85
PORTB
Associated Registers ................................................. 90
Initialization ................................................................ 88
LATB Register ........................................................... 88
PORTB Register ........................................................ 88
RB0/INT Pin, External ................................................ 83
RB2:RB0 Port Pins .................................................... 89
RB3 Pin ..................................................................... 89
RB7:RB4 Interrupt-on-Change Flag (RBIF Bit) .......... 88
RB7:RB4 Port Pins .................................................... 88
TRISB Register .......................................................... 88
PORTC
Associated Registers ................................................. 92
Block Diagram (Peripheral Output Override) ............. 91
Initialization ...........................................................91, 93
LATC Register ........................................................... 91
PORTC Register ........................................................ 91
RC3/SCK/SCL Pin ................................................... 137
RC7/RX/DT Pin ........................................................ 166
TRISC Register ...................................................91, 163
PORTD .............................................................................. 98
Associated Registers ................................................. 94
Block Diagram (I/O Mode) ......................................... 93
LATD Register ........................................................... 93
Parallel Slave Port (PSP) Function ............................ 93
PORTD Register ........................................................ 93
TRISD Register .......................................................... 93
PORTE
Analog Port Pins ...................................................97, 98
Associated Registers ................................................. 97
Block Diagram (I/O Mode) ......................................... 95
Initialization ................................................................ 95
LATE Register ........................................................... 95
PORTE Register ........................................................ 95
PSP Mode Select (PSPMODE Bit) .......................93, 98
RE0/RD/AN5 Pin ..................................................97, 98
RE1/WR/AN6 Pin ..................................................97, 98
RE2/CS/AN7 Pin ...................................................97, 98
TRISE Register .....................................................95, 96
Postscaler, WDT
Assignment (PSA Bit) .............................................. 103
Rate Select (T0PS2:T0PS0 Bits) ............................. 103
Switching Between Timer0 and WDT ...................... 103
Power-down Mode. See SLEEP.
Power-on Reset (POR) ...............................................26, 193
Advance Information
DS39564A-page 305
PIC18FXX2
Oscillator Start-up Timer (OST) ......................... 26, 193
Power-up Timer (PWRT) .................................... 26, 193
Time-out Sequence .................................................... 26
Time-out Sequence on Power-up ........................ 32, 33
Timing Diagram ........................................................ 270
Prescaler, Capture ........................................................... 117
Prescaler, Timer0 ............................................................. 103
Assignment (PSA Bit) ............................................... 103
Rate Select (T0PS2:T0PS0 Bits) ............................. 103
Switching Between Timer0 and WDT ...................... 103
Prescaler, Timer1 ............................................................. 106
Prescaler, Timer2 ............................................................. 120
PRO MATE II Universal Device Programmer ................... 253
Product Identification System ........................................... 311
Program Counter
PCl, PCLATH and PCLATU Register ......................... 39
PCLATH Register ....................................................... 39
Program Memory
Interrupt Vector .......................................................... 35
Map and Stack for PIC18F442/242 ............................ 36
Map and Stack for PIC18F452/252 ............................ 36
RESET Vector ............................................................ 35
Program Verification ......................................................... 205
Program Verification and Code Protection
Associated Registers ............................................... 205
Programming, Device Instructions ................................... 209
PSP.See Parallel Slave Port.
Pulse Width Modulation. See PWM (CCP Module).
PUSH ............................................................................... 238
PWM (CCP Module) ......................................................... 120
Associated Registers ............................................... 121
Block Diagram .......................................................... 120
CCPR1H:CCPR1L Registers ................................... 120
Duty Cycle ................................................................ 120
Example Frequencies/Resolutions ........................... 121
Output Diagram ........................................................ 120
Period ....................................................................... 120
Setup for PWM Operation ........................................ 121
TMR2 to PR2 Match ......................................... 109, 120
Q
Q Clock ............................................................................ 120
R
RAM. See Data Memory.
RC Oscillator ...................................................................... 18
RCALL .............................................................................. 239
RCON Register .................................................................. 53
RCSTA Register
SPEN Bit .................................................................. 163
Register File ....................................................................... 42
Registers
ADCON0 (A/D Control 0) ......................................... 179
ADCON1 (A/D Control 1) ......................................... 180
CCP1CON and CCP2CON
(Capture/Compare/PWM Control) .................... 115
CONFIG1H (Configuration 1 High) .......................... 194
CONFIG2H (Configuration 2 High) .......................... 196
CONFIG2L (Configuration 2 Low) ............................ 195
CONFIG3H (Configuration 3 High) .......................... 196
CONFIG4L (Configuration 4 Low) ............................ 197
CONFIG5H (Configuration 5 High) .......................... 198
CONFIG5L (Configuration 5 Low) ............................ 197
CONFIG6H (Configuration 6 High) .......................... 199
CONFIG6L (Configuration 6 Low) ............................ 198
CONFIG7H (Configuration 7 High) .......................... 200
DS39564A-page 306
S
SCI. See USART.
SCK ................................................................................. 123
SDI ................................................................................... 123
SDO ................................................................................. 123
Serial Clock, SCK ............................................................ 123
Serial Communication Interface. See USART.
Serial Data In, SDI ........................................................... 123
Serial Data Out, SDO ....................................................... 123
Serial Peripheral Interface. See SPI.
SETF ................................................................................ 243
Slave Select Synchronization .......................................... 129
Slave Select, SS .............................................................. 123
SLEEP ..............................................................193, 203, 244
Software Simulator (MPLAB SIM) .................................... 252
Special Event Trigger. See Compare.
Advance Information
PIC18FXX2
Special Features of the CPU ............................................ 193
Configuration Registers ................................... 194200
Special Function Registers ................................................ 42
Map ............................................................................ 45
SPI
Master Mode ............................................................ 128
Serial Clock .............................................................. 123
Serial Data In ........................................................... 123
Serial Data Out ........................................................ 123
Slave Select ............................................................. 123
SPI Clock ................................................................. 128
SPI Mode ................................................................. 123
SPI Master/Slave Connection .......................................... 127
SPI Module
Associated Registers ............................................... 131
Bus Mode Compatibility ........................................... 131
Effects of a RESET .................................................. 131
Master/Slave Connection ......................................... 127
Slave Mode .............................................................. 129
Slave Select Synchronization .................................. 129
Slave Synch Timing ................................................. 129
Slave Timing with CKE = 0 ...................................... 130
Slave Timing with CKE = 1 ...................................... 130
SLEEP Operation ..................................................... 131
SSPCON1 Register ................................................. 125
SSPSTAT Register .................................................. 124
SS .................................................................................... 123
SSP
I2C Mode. See I2C.
SPI Mode ................................................................. 123
SPI Mode. See SPI.
SSPBUF ................................................................... 128
SSPSR ..................................................................... 128
TMR2 Output for Clock Shift ............................ 109, 110
SSPOV ............................................................................. 153
SSPSTAT Register
R/W Bit ............................................................. 136, 137
STATUS Register ............................................................... 52
STKPTR Register ............................................................... 38
SUBFWB .......................................................................... 244
SUBLW ............................................................................ 245
SUBWF ............................................................................ 245
SUBWFB .......................................................................... 246
SWAPF ............................................................................ 246
T
TABLAT Register ............................................................... 58
Table Pointer Operations (table) ........................................ 58
TBLPTR Register ............................................................... 58
TBLRD ............................................................................. 247
TBLWT ............................................................................. 248
Timer0 .............................................................................. 101
16-bit Mode Timer Reads and Writes ...................... 103
Associated Registers ............................................... 103
Block Diagrams
16-bit Mode ...................................................... 102
8-bit Mode ........................................................ 102
Clock Source Edge Select (T0SE Bit) ...................... 103
Clock Source Select (T0CS Bit) ............................... 103
Operation ................................................................. 103
Overflow Interrupt .................................................... 103
Prescaler. See Prescaler, Timer0.
T0CON Register ...................................................... 101
Timing Diagram ........................................................ 272
Advance Information
DS39564A-page 307
PIC18FXX2
Repeat START Condition ......................................... 152
Slave Synchronization .............................................. 129
Slow Rise Time (MCLR Tied to VDD) ......................... 33
SPI Mode Timing (Master Mode) SPI Mode
Master Mode Timing Diagram .......................... 128
SPI Mode Timing (Slave Mode with CKE = 0) ......... 130
SPI Mode Timing (Slave Mode with CKE = 1) ......... 130
STOP Condition Receive or Transmit ...................... 156
Time-out Sequence on POR w/PLL Enabled
(MCLR Tied to VDD) ........................................... 33
Time-out Sequence on Power-up
(MCLR Not Tied to VDD)
Case 1 ................................................................ 32
Case 2 ................................................................ 32
Time-out Sequence on Power-up
(MCLR Tied to VDD) ........................................... 32
Timing for Transition Between Timer1 and
OSC1 (HS with PLL) .......................................... 23
Transition Between Timer1 and
OSC1 (HS, XT, LP) ............................................ 22
Transition Between Timer1 and
OSC1 (RC, EC) .................................................. 23
Transition from OSC1 to Timer1 Oscillator ................ 22
USART Asynchronous Master Transmission ........... 170
USART Asynchronous Reception ............................ 172
USART Synchronous Reception .............................. 175
USART Synchronous Transmission ......................... 174
Wake-up from SLEEP via Interrupt .......................... 204
Timing Diagrams and Specifications ................................ 268
A/D Conversion ........................................................ 285
A/D Conversion Requirements ................................. 285
Brown-out Reset (BOR) ........................................... 271
Capture/Compare/PWM (CCP) ................................ 273
Capture/Compare/PWM Requirements ................... 273
CLKOUT and I/O ...................................................... 269
CLKOUT and I/O Requirements .............................. 270
Example SPI Master Mode (CKE = 0) ..................... 275
Example SPI Master Mode (CKE = 1) ..................... 276
Example SPI Mode Requirements
(Master Mode, CKE = 0) .................................. 275
Example SPI Mode Requirements
(Master Mode, CKE = 1) .................................. 276
Example SPI Mode Requirements
(Slave Mode CKE = 0) ..................................... 277
Example SPI Slave Mode (CKE = 0) ....................... 277
Example SPI Slave Mode (CKE = 1) ....................... 278
Example SPI Slave Mode Requirements
(CKE = 1) ......................................................... 278
External Clock (All Modes except PLL) .................... 268
External Clock Requirements ................................... 268
I2C Bus Data ............................................................ 279
I2C Bus Data Requirements (Slave Mode) .............. 280
I2C Bus START/STOP Bits ...................................... 279
Master SSP I2C Bus Data Requirements ................. 282
Master SSP I2C Bus START/STOP
Bits Requirements ............................................ 281
Oscillator Start-up Timer (OST) ............................... 270
Parallel Slave Port (PSP) ......................................... 274
Parallel Slave Port Requirements ............................ 274
PLL Clock ................................................................. 269
Power-up Timer (PWRT) .......................................... 270
RESET ..................................................................... 270
RESET, Watchdog Timer, Oscillator Start-up
Timer, Power-up Timer and Brown-out
Reset Requirements ........................................ 271
DS39564A-page 308
U
Universal Synchronous Asynchronous Receiver
Transmitter. See USART.
USART ............................................................................. 163
Asynchronous Mode ................................................ 169
Associated Registers, Receive ........................ 172
Associated Registers, Transmit ....................... 170
Master Transmission ....................................... 170
Receive Block Diagram ................................... 171
Receiver .......................................................... 171
Reception ........................................................ 172
Transmit Block Diagram .................................. 169
Transmitter ....................................................... 169
Baud Rate Generator (BRG) ................................... 166
Associated Registers ....................................... 166
Baud Rate Error, Calculating ........................... 166
Baud Rate Formula .......................................... 166
Baud Rates, Asynchronous Mode
(BRGH=0) ................................................ 167
Baud Rates, Asynchronous Mode
(BRGH=1) ................................................ 168
High Baud Rate Select (BRGH Bit) ................. 166
Sampling .......................................................... 166
RCSTA Register ...................................................... 165
Serial Port Enable (SPEN Bit) ................................. 163
Synchronous Master Mode ...................................... 173
Associated Registers, Reception ..................... 175
Associated Registers, Transmit ....................... 173
Reception ........................................................ 175
Timing Diagram, Synchronous Receive .......... 283
Timing Diagram, Synchronous
Transmission ........................................... 283
Transmission ................................................... 174
Associated Registers ............................... 173
Synchronous Slave Mode ........................................ 176
Associated Registers, Receive ........................ 177
Associated Registers, Transmit ....................... 176
Reception ........................................................ 177
Transmission ................................................... 176
TXSTA Register ....................................................... 164
Advance Information
PIC18FXX2
W
Advance Information
DS39564A-page 309
PIC18FXX2
NOTES:
DS39564A-page 310
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PIC18FXX2
ON-LINE SUPPORT
013001
www.microchip.com
The file transfer site is available by using an FTP service to connect to:
ftp://ftp.microchip.com
The web site and file transfer site provide a variety of
services. Users may download files for the latest
Development Tools, Data Sheets, Application Notes,
Users Guides, Articles and Sample Programs. A variety of Microchip specific business information is also
available, including listings of Microchip sales offices,
distributors and factory representatives. Other data
available for consideration is:
Latest Microchip Press Releases
Technical Support Section with Frequently Asked
Questions
Design Tips
Device Errata
Job Postings
Microchip Consultant Program Member Listing
Links to other useful web sites related to
Microchip Products
Conferences for products, Development Systems,
technical information and more
Listing of seminars and events
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DS39564A-page 311
PIC18FXX2
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation
can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150.
Please list the following information, and use this outline to provide us with your comments about this Data Sheet.
To:
RE:
Reader Response
From: Name
Company
Address
City / State / ZIP / Country
Telephone: (_______) _________ - _________
Application (optional):
Would you like a reply?
Device: PIC18FXX2
N
Literature Number: DS39564A
Questions:
1. What are the best features of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this data sheet easy to follow? If not, why?
4. What additions to the data sheet do you think would enhance the structure and subject?
5. What deletions from the data sheet could be made without affecting the overall usefulness?
8. How would you improve our software, systems, and silicon products?
DS39564A-page 312
Advance Information
PIC18FXX2
PIC18FXX2 PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.
Device
Device
/XX
Temperature
Range
XXX
Package
Pattern
PIC18FXX2(1), PIC18FXX2T(2);
VDD range 4.2V to 5.5V
PIC18LFXX2(1), PIC18LFXX2T(2);
VDD range 2.5V to 5.5V
Temperature
Range
I
E
=
=
-40C to
-40C to
Package
PT
SO
SP
P
L
=
=
=
=
=
Pattern
+85C
+125C
Examples:
a)
b)
c)
(Industrial)
(Extended)
Note 1: F
LF
2: T
Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.
New Customer Notification System
Register on our web site (www.microchip.com/cn) to receive the most current information on our products.
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DS39564A-page 313
ASIA/PACIFIC
Japan
Corporate Office
Australia
Rocky Mountain
China - Beijing
Atlanta
500 Sugar Mill Road, Suite 200B
Atlanta, GA 30350
Tel: 770-640-0034 Fax: 770-640-0307
Austin - Analog
8303 MoPac Expressway North
Suite A-201
Austin, TX 78759
Tel: 512-345-2030 Fax: 512-345-6085
Boston
2 Lan Drive, Suite 120
Westford, MA 01886
Tel: 978-692-3848 Fax: 978-692-3821
Boston - Analog
Unit A-8-1 Millbrook Tarry Condominium
97 Lowell Road
Concord, MA 01742
Tel: 978-371-6400 Fax: 978-371-0050
Chicago
333 Pierce Road, Suite 180
Itasca, IL 60143
Tel: 630-285-0071 Fax: 630-285-0075
China - Chengdu
Microchip Technology Consulting (Shanghai)
Co., Ltd., Chengdu Liaison Office
Rm. 2401, Ming Xing Financial Tower
No. 88 TIDU Street
Chengdu 610016, China
Tel: 86-28-6766200 Fax: 86-28-6766599
China - Fuzhou
Microchip Technology Consulting (Shanghai)
Co., Ltd., Fuzhou Liaison Office
Rm. 531, North Building
Fujian Foreign Trade Center Hotel
73 Wusi Road
Fuzhou 350001, China
Tel: 86-591-7557563 Fax: 86-591-7557572
China - Shanghai
Dayton
China - Shenzhen
New York
India
Dallas
Detroit
Tri-Atria Office Building
32255 Northwestern Highway, Suite 190
Farmington Hills, MI 48334
Tel: 248-538-2250 Fax: 248-538-2260
Los Angeles
San Jose
Microchip Technology Inc.
2107 North First Street, Suite 590
San Jose, CA 95131
Tel: 408-436-7950 Fax: 408-436-7955
Toronto
6285 Northam Drive, Suite 108
Mississauga, Ontario L4V 1X5, Canada
Tel: 905-673-0699 Fax: 905-673-6509
Korea
Microchip Technology Korea
168-1, Youngbo Bldg. 3 Floor
Samsung-Dong, Kangnam-Ku
Seoul, Korea 135-882
Tel: 82-2-554-7200 Fax: 82-2-558-5934
Singapore
Microchip Technology Singapore Pte Ltd.
200 Middle Road
#07-02 Prime Centre
Singapore, 188980
Tel: 65-334-8870 Fax: 65-334-8850
Taiwan
Microchip Technology Taiwan
11F-3, No. 207
Tung Hua North Road
Taipei, 105, Taiwan
Tel: 886-2-2717-7175 Fax: 886-2-2545-0139
EUROPE
Denmark
Microchip Technology Denmark ApS
Regus Business Centre
Lautrup hoj 1-3
Ballerup DK-2750 Denmark
Tel: 45 4420 9895 Fax: 45 4420 9910
France
Arizona Microchip Technology SARL
Parc dActivite du Moulin de Massy
43 Rue du Saule Trapu
Batiment A - ler Etage
91300 Massy, France
Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79
Germany
Arizona Microchip Technology GmbH
Gustav-Heinemann Ring 125
D-81739 Munich, Germany
Tel: 49-89-627-144 0 Fax: 49-89-627-144-44
Germany - Analog
Lochhamer Strasse 13
D-82152 Martinsried, Germany
Tel: 49-89-895650-0 Fax: 49-89-895650-22
Italy
Arizona Microchip Technology SRL
Centro Direzionale Colleoni
Palazzo Taurus 1 V. Le Colleoni 1
20041 Agrate Brianza
Milan, Italy
Tel: 39-039-65791-1 Fax: 39-039-6899883
United Kingdom
Arizona Microchip Technology Ltd.
505 Eskdale Road
Winnersh Triangle
Wokingham
Berkshire, England RG41 5TU
Tel: 44 118 921 5869 Fax: 44-118 921-5820
06/01/01
DS39564A-page 314
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