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Solution to trapped charge in

FGMOS transistors
E. Rodriguez-Villegas and H. Barnes
A solution to the problem of charge being trapped on the gate of a
floating gate MOS transistor during fabrication is presented. The
solution does not alter the floating nature of the gate of the device
since it does not use any kind of active or passive device to get rid of
the accumulated charge. In addition, it does not require any post-
processing techniques such as exposure to UV light and does not
require any extra masks.
Introduction: Until recently, floating gate MOS (FGMOS) transistors
have been used only in digital electronics where they form the basis of
EEPROM devices [1]. However, as demand for low voltage, low
power portable systems grows, FGMOS transistors have the potential
to play an important role in analogue circuits. Many novel circuit
topologies have been developed, some of which offer impressive
reductions in supply voltage and power consumption [2, 3]. Despite
this, industry has been reluctant to make use of FGMOS devices. This
is because of the trapped charge problem, which occurs during
fabrication when an uncertain amount of charge is trapped on the
floating gate and gives rise to large variations in threshold voltage.
The implications of the trapped charge depends on the circuit in
question, but often the design will not work unless the charge is
removed. Reported solutions include UV cleaning [4]; the use of the
tunnelling effect and hot electron injection [5]; and forcing an initial
condition with a switch [6]. The first solution sometimes gives
acceptable results, but the passivation mask must be removed if it
reflects UV light. Unfortunately this is not compatible with present
industrial production and risks the longevity of the chip. The second
solution requires extra circuitry and high voltages which are not
compatiable with low voltage technologies. The third solution dele-
teriously influences the operation of the device. For example, if a
switch is introduced so that the floating gate can be discharged, then
subsequently, during normal FGMOS operation, the switch will
provide a large but finite resistance path from the floating gate to
the substrate of the switch. The gate is therefore no longer genuinely
floating and its DC voltage will drift towards the substrate voltage of
the switch. This technique has been successfully used for digital and
sampled-data applications, but it is not suitable for general purpose
continuous-time analogue circuits.
Fig. 1 Four-input n-type FGMOS transistor
a Equivalent circuit b Symbol
Discussion: In this Letter, a new technique to solve the trapped
charge problem is proposed. The solution is based on a novel
layout technique that takes advantage of the fabrication process
itself.
A floating gate MOS transistor is an MOS device with a gate which is
not resistively connected to anything else. Instead, the gate is subject to
capacitive couplings between itself and one or more input terminal.
The voltages at these terminals determine the current flow through the
channel. Fig. 1a shows the equivalent circuit of a four-input n-type
FGMOS transistor, whilst Fig. 1b shows its symbol. A possible layout
for this device is shown in Fig. 2. The poly1 layer, which forms the
floating gate of the device, continues beyond the active area and
together with a second conducting layer forms a number of capacitors.
While there are other possibilities, the most common choice for the
second conducting layer is poly2. This is because high quality capaci-
tors can be made by overlapping poly2 and poly1. The connections
made to the poly2 sides of the capacitors are the inputs to the transistor.
When the device is fabricated, charge accumulates on the floating gate
and it remains there because there are no resistive paths from the poly1
layer to other parts of the chip.
poly1/metal1
poly1/metal1
metal1/metal2
Fig. 2 Four-input FGMOS transistor layout with gate to metal contacts to
get rid of charge
The voltage at the gate of an N-input FGMOS transistor can be
determined by applying the charge conservation law to an N-input
capacitive network, which is an extension of the four-input network
shown in Fig. 1a. The gate voltage is given by
V
FG
¼
P
N
i¼1
C
i
C
T
V
i
þ
C
GD
C
T
V
D
þ
C
GS
C
T
V
S
þ
Q
FG
C
T
ð1Þ
where C
T
is the sum of all the capacitances connected to the gate and
includes parasitic couplings to the bulk (C
GB
), source (C
GS
) and drain
(C
GD
). Therefore
C
T
¼
P
N
i¼1
C
i
þ C
GB
þ C
GS
þ C
GB
ð2Þ
The voltages V
FG
, V
D
and V
S
are the floating gate, drain and source
voltages referred to bulk, respectively. Q
FG
is the aforementioned
residual charge trapped in the oxide–silicon interface during the
fabrication process. The solution to the trapped charge problem
proposed in this Letter is to add a poly1 to metalk contact, where k
represents the number of metals available in the technology. So, if the
technology has more than one metal, metalk is the one which is
deposited and etched last. The contact does not connect the floating
gate to any other part of the circuit, so functionally it does not alter the
device. However, the added contact resolves the trapped charge problem
as is now explained.
ELECTRONICS LETTERS 18th September 2003 Vol. 39 No. 19
Fig. 3 Cascade of two equally sized inverters, and experimental char-
acterisation
a Cascade of two equally sized inverters, first one FGMOS with two equal inputs,
second one CMOS
b Experimental characterisation of inverters
The stages of fabrication prior to the deposition of metalk lead to an
accumulation of trapped charge on the floating gates. Because metalk is the
top layer of metal, it is the last to be deposited and etched. Before
etching takes place all the parts of the chip in contact with metalk are
connected together. Since all the floating gates are connected to metalk via
a poly1 to metalk contact, the charge trapped on each gate flows to other
parts of the chip. For example, if there are substrate to metalk contacts then
the floating gates might discharge to the substrate via these contacts. The
fabrication process we used included substrate to metalk contacts. The key
is that during one of the final stages of fabrication the floating gates are not
floating. Then, when metalk is etched away, their floating nature is
restored. The layout in Fig. 2 shows how this can be done. The poly1
gate of the FGMOS transistor is connected to the extra region of poly1 via
a metal1 bridge, which is only required here because the two poly1 regions
are disconnected. The poly1 to metal1 contact in conjunction with the
metal1 to metal2 contact provides the connection from the floating gate to
the top layer of metal in this technology, i.e. metal2.
Results: Different circuits, which have been fabricated in several
technologies over a number of runs, have been tested [3]. In all
cases the experimental results were in agreement with the expected
performance. No charge accumulation was detected, whereas circuits
fabricated without using the technique did not work at all. As an
example of the technique, Fig. 3 shows the performance of a simple
two-input FGMOS inverter followed by an identical inverter using
conventional MOS transistors. Ignoring the effects of conventional
transistor mismatch, the switching threshold of both inverters will be
the same in the absence of trapped charge [3]. Fig. 3b shows experi-
mentally the results of sweeping one of the inputs between 0 and
5 V and varying the other input in steps of 1 V. The thresholds were
found to be the same to within a few millivolts. These small differ-
ences can be attributed to conventional transistor mismatching and
in any case do not change the performance. The transfer function of
the same inverter fabricated without the metalk contact would have
been saturated for the whole input range.
Acknowledgments: The authors wish to thank R. Gonzalez Carvajal
and K. Fobelets for time spent discussing technological issues.
# IEE 2003 18 July 2003
Electronics Letters Online No: 20030900
DOI: 10.1049/el:20030900
E. Rodriguez-Villegas and H. Barnes (Department of Electrical and
Electronic Engineering, Imperial College of Science, Technology and
Medicine, Exhibition Road, London SW7 2AZ, United Kingdom)
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ELECTRONICS LETTERS 18th September 2003 Vol. 39 No. 19