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11, NOVEMBER 1995 97 1
conductance. In addition, the process constants IO and K are assumed
to be the same for both NMOS and PMOS devices. In this way,
we are dealing with ideal devices and hence our results represent an
upper bound on the achievable dynamic range.
The noise in a subthreshold MOS transistor can be reasonably-
well modeled as a bias-dependent shot noise with a one-sided power
spectrum s,,,(w) =2q1DS. According to [20], the power spectrum
of flicker noise is proportional to I& and inversely proportional to
the gate-capacitance. Thus, by operating at low current levels with
large transistor dimensions, the flicker noise corner frequency can be
made to fall below the audio frequency range.
The substantial contributions of W. Liu who is coauthor of several
original papers are gratefully acknowledged. The authors thank the
anonymous reviewers for their carefully constructed criticisms of an
earlier document.
C. E. Shannon, “A mathematical theory of communication,” Bell Syst.
Tech. J. , vol. 27, pp. 379-423, July 1948 and vol. 27, pp. 623-656, Oct.
P. M. Furth, “On the design of optimal continuous-timefilter banks
in subthreshold CMOS,” Ph.D. dissertation, Johns Hopkins Univ.,
Baltimore, MD, 1995.
C. A. Mead, Analog VLSI and Neural Systems. Reading, MA: Addison-
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A. G. Andreou and K. A. Boahen, “Neural information processing II,”
in Analog VLSI Signal and Information Processing, M. Ismail and T.
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D. B. Roe and J. G. Wilpon, Eds. Voice Communication Between
Humans and Machines. Wash., DC: National Academy, 1994
W. Liu, “An analog cochlear model: Signal representation and VLSI
realization,” Ph.D. dissertation, Johns Hopkins Univ., Baltimore, MD,
W. Liu, A. G. Andreou, and M. H. Goldstein, Jr. “Analog cochlear
model for multiresolution speech analysis,” in Advances in Neural
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L. Giles, Eds. San Mateo, CA Morgan Kaufmann, 1993, pp. 666-673.
J . B. Allen, “Cochlear modeling,” IEEE ASSP Magazine, vol. 2, pp.
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T. Kamm, A. G. Andreou, and J. Cohen, “Vocal tract normalization
in speech recognition: Compensating for speaker variability,” in 15th
Speech Res. Symp., BaltimoreMD, June 1995, pp. 175-178.
G. Groenewold, “Optimal dynamic range integrators,” IEEE Trans.
Circuits Syst. I , vol. 39, pp. 614-627, Aug. 1991.
E. A. Vittoz, “Micropower techniques,” in Design of MOS VLSI Circuits
for Telecommunications and Signal Processing, J. Franca and Y. P.
Tsividis, Eds. Englewood Cliffs, NJ: Prentice-Hall, 1994.
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New York McGraw-Hill, 1994.
[17] P. M. Furth and A. G. Andreou, “Linearised differential transconductors
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[18] J. Max, “Quantizing for minimumdistortion,” IRE Trans. Inform.
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[19] H. Nevarez-Lozano and E. Sanchez-Sinencio, “Minimumparasitic ef-
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[20] Y. P. Tsividis, Oj7eration and Modeling of the MOS Transistor. New
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Low-Voltage Circuits Building Blocks Using
Multiple-Input Floating-Gate Transistors
J . Ram’rez-Angulo, S.C. Choi, and G. Gonzhlez-Altamirano
Abstract- A systeniatic approach for designing analog circuits with
low supply voltage requirements is discussed. This approach is based on
the utilization of multiiple-input floating-gate transistors. Current mirrors
and differential pair building blocks are discussed as well as a low voltage
BiCMOS operational amplifer based on these building blocks.
Recently, a host of applications using Multiple-Input Floating-
Gate (MIFG) transistors in analog circuit design has been reported
111-181. Most of these applications refer to analog memories and
analog computation. These applications are based, on one hand, on
the the long term retention characteristics of the charge injected into
the floating-gate of an MOS transistor; and, on the other hand, on
the addition of the voltage signals applied at the input terminals
of an MIFG transistor. Voltage addition takes place due to the
fact that each of the input terminals can induce charge on the
common floating-gate. In this brief, the utilization of MIFG MOS
transistors for the implementation of circuits with low-voltage supply
requirements is discussed. Fig. l(a) shows the layout of a two-
input floating-gate transistor. Fig. l(b) shows the symbol for this
device and Fig. l(c) shows an equivalent circuit model where CI
and C, are the capacitances formed between the input gates (usually
the poly 11layer) and the floating-gate (usually the poly I layer).
CO is the capacitance between the floating gate and the substrate
(channel). Following the analysis presented in [ 11, the threshold
voltage of the MOS transistor, VTN~, with respect to input terminal
“1,” depends on the threshold voltage of the floating gate, VTH,
which is the conventional threshold voltage of the MOS transistor
(e.g. VTH PZ 0.85 V for 2 pm CMOS technology); and on the
voltage applied to the second input, V2, according to
c1+(72 +
VTH - -v2* c2
c1 Cl
If the condition (70 <<Cz is satisfied, then (1) reduces to:
%PHI =VTH +-(VTH c1 - Vz).
Manuscript received April 9, 1995; revised J une 15, 1995. This paper
was recommended by Guest Editors A. Rodriguez-Vgzquez and E. Sbchez-
The authors are with The Klipsch School of Electrical and Computer
Engineering, New Mexico State University, Las Cruces, NM 88003 USA.
IEEE Log Number 9415354.
1057-7122/95$04.00 0 1995 IEEE
0 0
@ @
mms (POLY rr)
(a) (3) (C)
Fig. 1. (a) Layout of multiple-input floating-gatetransistor. (b) Symbol. (c) Equivalent circuit model.
Typically, the capacitance per unit area between the input gates
and the floating-gate is of similar value. In order for the condition
CO <<Cz to be satisfied. The geometry for CZ should beat least an
order of magnitude larger than that of the area of the MOS transistor’s
channel (W . L) . For values of CZ at least a factor two larger than
C1and for VZ >VTW, essential reduction of VTHI can beachieved.
For example, assuming a MOS transistor with VTH =0.85 V, of
dimensions WI L =512 (in pm),Cz =2.25c1, and VZ =1.2 V,
then a value VTH~ close to zero results. This is achieved by using
dimensions for the input gates of W1 x Ll =10 x 10 pmz and of
W2 x L2 =15 x 15 pm2, respectively. As a matter of fact, and as
reported in [ 11, the MOS transistor can perform as a depletion device
( VTHI <0 ) by the proper selection of the ratio Cz/CI and/or VZ. I n
the remaining text, VZ - VTH is denoted as the “overdrive voltage.”
The possibility for decreasing the threshold voltage relative to one
of the input terrmnals can be used, with advantage, for the design of
low-voltage circuits. The idea is to use one of the input terminals of an
MIFG transistor for biasing purposes; and to use the other terrninal(s)
for signal processing purposes. This allows to reduce and even to
practically cancel the threshold voltage for the signal processing input
terminal(s), in such a manner that these terminals arenot required to
include a biasing voltage component. Fig. 2(a) shows a low-voltage
current mrror using two-input floating-gate transistors. Fig. 2@)
shows two different ways to build this mirror. In Fig. 2(c), the input
terminals, as well as Cl and CZ, are shared by both transistors. In
the circuit of Fig. 2(a), one of the input terminals of each transistor
is connected to a dc bias voltage, Vblas; while the other terminals
are used as conventional input and output mirror terminals. Supply
requirements on both input and output (signal) sides can be reduced
to only those required by signal variations. Notice that the overall
supply voltage range (VDD - VSS) is available to bias the current
mirror. Fig. 2(c) shows a low-voltage differential pair with two-
input floating-gate transistors biased using a floating voltage source,
Vblas, which is connected between one of the transistor’s floating
inputs and the common-source node of the differential pair. A diode
connected MQS transistor, biased with a current source, can be used
to implement the floating voltage source. In this circuit, the supply
voltage range (VDD - VSS) , reduced by the biasing requirements
of two dc current sources (2VFi) is available as biasing voltage.
It can operate with low voltage; but, it is not appropriate for wide
common-mode input signal variations. Fig. 2(d) shows a different
(and simpler) approach for biasing the MIFG differential pair. In this
circuit, a constant-voltage source is applied to the biasing terminals
of theMIFG transistors. The common-source node voltage, VS, is
dependent on the common-mode input signal V,, =(E++E- ) / 2.
It can beshown from(1) and (2) that V . is given by:
where VDS,,t =JIB/(pC,,W/L), and p, Cox and W/ L have
the usual meaning of mobility, oxide capacitance per unit area, and
width over lenght ratio, respectively. The sensitivity of VS with
respect to variations in Vcm is given by
These characteristics make this circuit specially suitable for low
supply-voltage operation and wide common-mode input range vari-
ations. For illustration, consider the availability of a single 1.5 V
supply (VDD =0.75 V, Vss =-0.75 V ) , Vgt =0.2 V , Klas
VDD =0.75 V, VTH =0.8 V , and Cz/C, =2.5. It can be shown
that VCM variations in from -0.5 to +0.5 V lead approximately to
variations in VS from-0.6 to -0.3 V leaving over most of this range
enough voltage for the current source I B to operate maintaining the
differential pair functional. All the circuits of Fig. 2 can function from
a single 1.5 V supply and with with relatively large signal swings (1
V) on the signal terminals. As indicated in Section I, the overdrive
voltage requirements, - VTH, can be reduced if large values for
the ratio Cz/Ci areused. In practice, a compromise has to be made
between reducing the voltage supply requirements and increasing the
circuit’s area.
Fig. 3 shows a BiCMOS low-voltage operational amplifier based
on a conventional one-stage architecture. It uses a differential input
stage and a three current m o r differencing network. The differential
pair and thetwo P-channel current mirrors use two-input floating-gate
transistors similar to those of Fig. 2. A bipolar mirror implemented
with NPN transistors also helps to minimize the supply requirements
of the circuit. This circuit, as well as the building blocks of Fig. 2,
were fabricated in a 2 pm N-well BiCMOS process through MOSIS
[8]. The dimensions of the N- and P-channel floating-gate MOS
transistors were W/ L =2513 and W/ L =5013, respectively.
Poly-I Poly-11 capacitors with dimensions 10 x 30 pm2 and 20 x
30 pmz corresponding to nominal capacitances C1 =144 fF and
CZ =288 fF were used for the floating-gate transistors. Minimum
size NPN vertical bipolar transistors (01 and Q z ) and cascode
transistors (M7 and Ma) with dimensions W/ L =9013 were used.
buT vBK3
Q b,”T Va,,i,s
l e
I . ?
& &
Fig. 2. Low-voltage building blocks using MIFG transistors: (a) Current-mirror. (b) Implementations. (c) Differential pair I. (d) Differential pair 11.
Fig. 3. One-stage BiCMOS operational transconductance amplifer using multiple-input floating-gatetransistors.
Fig. 4(a) shows the experimental results obtained using f0.75 supply
voltages and with bias voltages V,,, =-0.2 V, Vfsn =VDD =
VBd, =0.75 V,V,, =0.5 V,V& =-0.6 V. Fig. 4(a) shows
the input and output voltage waveforms obtained by connecting the
circuit as a voltage follower (no load, output terminal connected
were introduced and a BiCMOS operational amplifier based on
these building blocks was presented. The principles for low-voitage
operation using MIFG transistors presented and discussed here can
be extended to develop a family of low-voltage linear and nonlinear
signal processing circuits.
to negative input terminal). Fig. 4(b) shows the transconductance
transfer characteristic (Iout versus vu) obtained by applying a single-
ended input signal and connecting a load resistor RL =100 kR
between the output terminal and ground. It can be seen that the
circuit is functional with f0.75 V supplies and with input-output
signal swings of approximately 1 V. The output waveform in Fig. 4(a)
shows slew-rate distortion caused by the lack of a high-frequency
buffer on chip (a high-frequency buffer that operates with +0.75 V
was not available at the time).
The conditions required to operate MIFGT circuits with low
supply voltages were discussed. Low-voltage circuit building blocks
T. Shibata and T. Ohmi, “A functional MOS transistor featuring gate-
level weighted sumand threshold operations,” ZEEE Trans. Electron
Devices, vol. 39, pp. 1444-1455, June 1992.
K Yang and A G Andreou, “Multiple input floating gate MOS
differenhal amplifiers and applications of analog computation,” in Proc.
ISCAS 1992, San Diego, CA, May 10-13, 1992, pp. 1212-1216.
B. W. Lee, B. J. Sheu, and H. Yang, “Analog floating gate-synapses for
general purpose VLSI neural computation,” IEEE Trans. Circuits Syst.,
vol. 38, pp. 654-657, June 1991.
A. Thomsen and M. Brooke, “A floating gateMOSFET with tunneling
injector fabricated using astandard double polysilicon CMOS process,”
IEEE Electron Device Lett., vol. 12, pp. 111-113, Mar. 1991.
Fig. 4. Experimental results of BiCMOS operational transconductance am-
plifer of Fig. 3: (a) Input and output waveforms in voltage follower config-
uration (vertical scale0.2 V/div, horizontal scale0.2 ms/div). (b) Transcon-
ductance characteristic I,,t versus V,, for RL =200 kR, vertical and
horizontal scales 0.2 V/div.
[5] W. Gao and M. Snelgrove, “Floating gate charge sharing: A novel circuit
for analog trimming,” in Proc. ISCAS 1994, London, UK, May 30/June
2, 1994, pp. 315-318.
[6] M. Lanzoni, L. Briozzo, and B. Ricco, “ A novel aproach to controlled
programming of tunnel-based floating gate MOSFETs,” IEEE J. Solid
State Circuits, vol. 29, pp. 147-150, Feb. 1994.
[7] E. Sackinger and W. Guggenbuhl, “ An analog trimming circuit based on
a floating gate,” IEEE J Solid State Circuits, vol. 23, pp. 1437-1440,
Dec. 1988.
[XI J . Ram’rez-Angulo, S. C. Choi, and G. Gonzalez-Altamirano, “Low
supply voltageOTA architectures using floating gate transistors,” in 38th
Mzdwest Symp. Circts. and Syst., Rio deJaneiro, Brazil, Aug. 13-16,
Charge Sharing Problems in the Dynamic Logic Circuits:
BiCMOS versus CMOS and a 1.5 V BiCMOS Dynamic
Logic Circuit Free from Charge Sharing Problems
J. B. Kuo and C. S. Chiang
Absh.act--This brief reports comparison of the charge sharing problems
between the BiCMOS and the CMOS dynamic logic circuits for both 5 V
and 1.5 V operations. In addition, a 1.5 V BiCMOS dynamic logic circuit
free from charge sharing problems is reported. Based on the analysis,
the 1.5 V futl-swing BiCMOS dynamic logic gate circuit without charge
sharing problem shows amore than 1.5 times improvement in speed as
compared to the CMOS one.
CMOS dynamic logic circuits, which have advantages in speed
performance, may have race problems [l ] and charge sharing prob-
lems [2]. By proper arrangement, race problems can be avoided in
the CMOS dynamic logic circuits [l ]. On the other hand, charge
sharing problems may degrade the noise margin performance. For
1.5 V operation, charge sharing problems are particularly important
for CMOS dynamic circuits using deep submicron CMOS technology.
For BiCMOS dynamic logic circuits [3]-[7], charge sharing problems
can beeven worse as a result of the bipolar device involved. In fact,
the charge sharing problem in the BiCMOS dynamic logic circuit
is quite from that in the CMOS one. Until now, no paper reported
the charge sharing problems in the BiCMOS dynamic circuits. In
this brief, comparison of the charge sharing problems between the
BiCMOS and the CMOS dynamic logic circuits for both 5 V and 1.5
V operations is described. A 1.5 V BiCMOS dynamic logic circuit
free from charge sharing problems is introduced. It will be shown
that the 1.5V ful-swing BiCMOS dynamic logic gate circuit without
charge sharing problems shows a greater than 1.5 times improvement
in speed as compared to the CMOS one. In the following sections,
charge sharing problems of the CMOS and BiCMOS dynamic logic
circuits using 5 V and 1.5 V supply voltages are analyzed first,
followed by the new 1.5 V BiCMOS dynamic logic circuit without
the charge sharing problems.
In the CMOS dynamic logic circuit, as shown in Fig. l(a) [l ],
during the precharge period, the wout node is precharged to 5 V
by Mpc. During the logic evaluation period, if the input i~ is hgh
(MN2 is on) and the input il is low (MN1 is off), the l i p node is
predischarged to 0 V. During the next logic evaluation period, if the
input i 2 switches to low (MN2 turns off) and the input 21 switches to
high (MN2 turns on), the vOUt node is supposed to stay high but it may
be pulled low since the charge at the wont node will redistribute with
the parasitic capacitance at the up node. If the parasitic capacitance at
the wp node is comparable to that at the uout node, the noise margin
Manuscript received June 4, 1995. This work was supported by the
R.O.C. Nahonal Science Council under Contracts 83-0404-E002-013, 029
and 83-0618-EOO2-007. Th~s paper was recommended by Guest Editors A.
Rodriguez-Vhquez and E. Sinchez-Sinencio.
Theauthors are with the Department of Electrical Engineering, National
Taiwan University, Trupei, Taiwan 106-17.
IEEE Log Number 9415062.
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