You are on page 1of 3

add $3, $4, $6

sub $5, $3, $2


lw $7, 100($5)
add $8, $7, $2


The first instruction add $3, $4, $2 does not contain any dependency as it is the first fragment to be
executed. The second instruction sub $5, $3, $1 depends upon the first instruction, however this
dependency can be solved simply using forwarding (the value of $3 will be taken from the EX stage of
first instruction). The third instruction lw $6, 200($3) does depend upon the first instruction and can be
solved by forwarding as well. The last instruction add $7, $3, $6 depends upon the first as well as the
last instruction. In this case the first instruction will not cause any problem however the Load instruction
will cause 2 stalls. These 2 stalls can be limited to a single stall using forwarding but 1 stall will occur.

add $2, $3, $1
sub $4, $3, $5
add $5, $3, $7
add $7, $6, $1
add $8, $2, $6
As we can see that at the end of the fifth cycle of execution, the first add instruction is writing back the
result into $2 whereas the fourth instruction is reading data from $6 and $ 1.
IF ID EX MEM WB
IF ID EX MEM WB
IF ID EX MEM WB
IF bubble ID EX MEM WB
IF ID EX MEM WB
IF ID EX MEM WB
IF ID EX MEM WB
IF ID EX MEM WB
IF ID EX MEM WB
Q 6.3
Q 6.4
Q 6.17
Branch 1: T-T-T
a) Always taken:
b) Always not taken:
c) 1-bit predictor, initialized to predict taken:
d) 2-bit predictor, initialized to weakly predict taken:

Branch 2: N-N-N
a) Always taken:
b) Always not taken:
c) 1-bit predictor, initialized to predict taken:
d) 2-bit predictor, initialized to weakly predict taken:

Branch 3: T-N-T-N-T-N
a) Always taken:
b) Always not taken:
c) 1-bit predictor, initialized to predict taken:
d) 2-bit predictor, initialized to weakly predict taken:

Branch 4: T-T-T-N-T
a) Always taken:
b) Always not taken:
c) 1-bit predictor, initialized to predict taken:
d) 2-bit predictor, initialized to weakly predict taken:


Q 6.17
Branch 5: T-T-N-T-T-N-T
a) Always taken:
b) Always not taken:
c) 1-bit predictor, initialized to predict taken:
d) 2-bit predictor, initialized to weakly predict taken:

Rearrange the instruction sequence such that the instruction reading a value produced by a load
instruction is right after the load. In this way, there will be a stall after the load since the load value is
not available till after its MEM stage.
lw $2, 100($6)
lw $3, 200($7)
add $4, $2, $3
add $6, $3, $5
sub $8, $4, $6
lw $7, 300($8)
beq $7, $8, Loop
Q 6.17