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Tanner Tutorial – CMOS NAND2
Bryan Ackland
January 2014

The purpose of this document is to give the first time user of the Tanner tools an introduction to CMOS
layout by constructing a simple four transistor, two-input CMOS NAND gate. The NMOS and PMOS
devices are first constructed as leaf cells. The NAND gate is then drawn as a higher level cell, instancing
the NMOS and PMOS cells. The layout is created in L-Edit using the simplified lambda (λ) based design
rules in which circuits are laid-out in a standard cell type topology on an 8-λ wiring grid. These rules are
also known as the Alternative MOSIS scaled CMOS (SCMOS) rules. In addition to building a full custom
layout, this tutorial shows how to perform design rule check (DRC), extract a SPICE description of a
layout and simulate the extracted circuit using Tanner T-Spice. We will be assuming that our lambda
based design will ultimately be targeted at a 180nm CMOS process. When simulating, therefore, we will
be using 180nm CMOS SPICE device models.
It is assumed that the user has already downloaded and installed the Tanner tools, has set up a design
folder (directory) and is familiar with the basic drawing operations of L-Edit.
Creating a new Design File
1. Start L-Edit. From the pull-down menus, select File > New > Design. In the pop-up window, select
TDB (single-user, single file). In the pathname field type C:\690_Designs\CMOS_Tutorial
(assuming you have already set up C:\690_Designs as a design folder).
2. Under Technology Reference, select TDB. A TDB reference file pathname field will now appear. In
this pathname field type (or browse to) C:\690_Designs\example.tdb. This file contains the
technology information we will be using (layers, design rules etc. for our lambda based CMOS
process).
3. Check the One-time import box and click OK. This will create a new design file
CMOS_Tutorial.tdb and import all the relevant technology information from the file example.tdb. If
you select the Layer Palette, you should now be able to see the design layers correctly set up.
Creating an NMOS Transistor
1. We will be creating the layout of an NMOS device whose gate width is 4λ and whose gate length is
2λ. From the pull-down menus, select Cell > New. In the pop-up window, name the cell NMOS_4x2.
Enter your author information and click OK. You should now see an empty grid in the drawing area.
Pan the layout so that the origin mark is approximately in the middle of the screen. If you select the
Libraries sub-window, you should see the name of your new cell listed.
2. We will start by defining the source/drain regions. Using the left mouse button, draw an Active layer
box from (-2, -2) to (10, 2). The Active layer box should be shown as a filled green rectangle.
3. The next step is to make the active region N+(rather than P+). This is done with the layer
N_Implant. In SCMOS design rules, the N_Implant box must completely enclose the Active box by
at least 2λ. Draw a box in layer N_Implant from (-4, -4) to (12, 4). The N_Implant box appears as a
lightly shaded blue rectangle around the active region.
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4. We now draw the Poly (polysilicon) gate. SCMOS rules require that the minimum width of a Poly
region is 2λ. Also, the poly gate must overlap the active region by at least 2λ and be at least 3λ from
the end of the active region. Draw a rectangle in layer Poly from (3, -4) to (5, 4). The Poly Layer is
red in color.
5. This completes the physical (mask) layers required to define our NMOS transistor. Save your cell by
selecting File > Save All. The layout should appear as in Figure 1.

Figure 1

Performing a Design Rule Check (DRC)
1. It is now time to check that we have not violated any design rules by running a design rule check.
Click the Setup DRC button on the Verification toolbar. In the Setup DRC pop-up, make sure
that the box next to DRC Standard Rule Set is checked. This pop-up can be used to set up and modify
the DRC rule set. If you want to see how the rules are constructed, you can click the Edit button at
the top of the pop-up. This will give you a second pop-up which lists the various rules and their
specification. Click OK (twice if you went to the edit window).
2. Start the Design Rule Check by clicking the DRC button on the Verification toolbar. A DRC
pop-up appears showing progress of the DRC checks (these happen pretty quickly with a simple cell
like this). Once all the checks have been performed, a Verification Navigator sub-window appears at
the bottom of the screen. This will list any DRC errors that were found. Hopefully, there are none.
3. To see what happens when there are errors, move the right hand edge of the poly gate to the left by
1λ. The gate is now only 1λ wide. Re-run the DRC. The Verification Navigator should now tell you
that there is a violation of the Poly minimum width rule. If you expand the symbols (as shown in
Figure 2(a)) it tells you that there is one error is cell NMOS_4x2. If you click on this error, it will
highlight the error as shown in Figure 2(b).
4. Restore the poly gate to its correct width. Re-run the DRC to verify that the cell is error free and then
close the Verification Navigator sub-window.

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Figure 2(a)

Creating a PMOS Transistor
1. In like fashion, create a new PMOS transistor leaf cell named PMOS_8x2 with the following physical
mask objects:
a) An Active box from (-2, -4) to (10, 4)
b) A P_Implant box from (-4, -6) to (12, 6)
c) A Poly box from (3, -6) to (5,6)
2. Save the cell and run a DRC to check your layout for design rule violations.
3. The cell should appear as in Figure 3

Figure 3

Creating Contact & Via Cells
We will now make five contact cells that will be useful when constructing more complex layouts.
1. Make a new cell called MACON. This cell will be used to make connection from Metal1 to the
Active device regions.
a. Draw an Active box from (-2, -2) to (2, 2)
b. Draw a Contact box from (-1, -1) to (1, 1).

Figure 2(b)
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c. Draw a Metal1 box from (-2, -2) to (2, 2). ). Metal1 and Active must overlap a contact
window by 1λ.
2. Make a new cell called MPCON. This cell will be used to make connection from Metal1 to Poly.
a. Draw a Contact box from (-1, -1) to (1, 1).
b. Draw a Metal1 box from (-2, -2) to (2, 2).
c. Draw a Poly box from (-2,-2) to (2, 2). Poly must also overlap a contact window by at least 1λ.
3. Make a new cell called NWTIE. This cell will be used to make connection from Metal1 to the
N_Well layer.
a. Draw a Metal1 box from (-2, -2) to (2, 2)
b. Draw an Active box from (-2, -2) to (2, 2) and an N_Implant box from (-4, -4) to (4, 4). (The
Active layer and the N_Implant layer together define an N+ active region which will make an
ohmic contact to the underlying N_Well).
c. Draw a Contact box from (-1, -1) to (1, 1) (The Contact layer connects the Metal1 layer to the
N+active region)
4. Make a new cell called SBTIE. This cell will be used to make connection from Metal1 to the p-type
substrate.
a. Draw a Metal1 box from (-2, -2) to (2, 2)
b. Draw an Active box from (-2, -2) to (2, 2) and a P_Implant box from (-4, -4) to (4, 4). (The
Active layer and the P_Implant layer together define a P+active region which makes ohmic
contact to the underlying p-type substrate).
c. Draw a Contact box from (-1, -1) to (1, 1) (The Contact layer connects the Metal1 layer to the
P+active region)
5. Make a new cell called M12VIA. This cell will be used to make connection from Metal1 to Metal2.
a. Draw a Metal1 box from (-2, -2) to (2, 2)
b. Draw an Metal2 box from (-2, -2) to (2, 2).
c. Draw a Via1 box from (-1, -1) to (1, 1) (The Via1 layer connects the Metal1 layer to the
Metal2 layer)
6. The five contact/via cells should look similar to those shown in Figure 4.

Figure 4

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Building a CMOS 2-input NAND gate
We now have all the components we need to assemble a simple CMOS NAND gate:
1. Create a new cell called NAND2.
2. Add an instance of cell NMOS_4x2. Move the instanced cell so that it is center is at (4, 8).
3. Now add a second instance of cell NMOS_4x2. Move this instance so that it is centered at (12, 8).
The two NMOS transistors should appear as in Figure 5. Note that the right-hand source/drain region
of the transistor on the left completely overlaps the left-hand source/drain region of the transistor on
the right. These two transistors are therefore connected through the Active layer – the source of one
connects to the drain of the other.









4. Add a first instance of cell PMOS_8x2 centered at (4, 34) and a second instance of PMOS_8x2 at (12,
34). The two PMOS transistors also share a common source/drain.
5. Add a VSS rail by drawing a Metal1 path from (-8, 0) to (24, 0).
6. Add a VDD rail by adding a Metal1 path from (-8, 44) to (24, 44).
7. The layout should now look like Figure 6.
8. Place source/drain contacts on the NMOS devices by adding two instances of MACON centered at
(0, 8) and (16, 8)
9. Place source drain contacts on the PMOS devices by adding six instances of MACON centered at (0,
32), (0, 36), (8, 32), (8, 36), (16, 32) and (16, 36).
10. The layout should now look like Figure 7.
11. Connect the source of the left-most NMOS device to VSS by drawing a Metal1 path from (0,0) to
(0,8).
12. Connect the source of both PMOS devices to VDD by drawing Metal1 paths from (0, 32) to (0, 44)
and from (16, 32) to (16, 44).
13. Draw a Metal1 path from (8,36) to (8,24) to (24, 24). This will be the NAND gate output.
14. Draw a Metal2 path from (16, 8) to (16, 24).
15. Now place two M12VIA vias, centered at (16, 8) and (16, 24). These connect the Metal2 strap down
to the Metal1 layer and join the right-hand NMOS transistor drain to the output.

Figure 5
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Figure 6

Figure 7
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16. Connect the NMOS and PMOS gates together with a first Poly path from (4, 8) to (4, 34) and a
second Poly path from (12, 8) to (12, 34).
17. Add an input wire by adding a Metal1 path from (-8, 24) to (0, 24) and a Poly box from (-2, 22) to (5,
26). Add an MPCON at (0,24) to connect the Metal1 path to the Poly box.
18. Add a second input wire by adding a Metal1 path from (-8, 16) to (11, 16). Add an MPCON at (11,
16) to connect the Metal1 path to the Poly path.
19. Create an N_Well region around the PMOS devices by adding an N_Well box from (-8, 24) to (24,
50).
20. Add an nwell tie contact NWTIE centered at (0, 44). This will bias the N_Well by connecting it to
VDD.
21. Add a substrate tie contact SBTIE centered at (0, 0). This will bias the p-type substrate to VSS.
22. Final step is to name the circuit nodes. With the drawing layer set to Metal1, and the text size set to
3λ, draw a port named:
a. VSS at (23, -1) to (25, 1) with the text to the right of the port
b. VDD at (23, 43) to (25, 45) with the text to the right of the port
c. Z at (23, 23) to (25, 25) with the text to the right of the port
d. A at (-9, 23) to (-7, 25) with the text to the left of the port
e. B at (-9, 15) to (-7, 17) with the text to the left of the port
23. The layout is now complete! It should look like Figure 8. Save the file and run a DRC to make sure
there are no errors in the layout.

Figure 8
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Extracting a SPICE file from the layout
Now that the layout of our NAND2 gate is complete, we can use the L-Edit extraction utility to extract a
SPICE netlist from the layout we have created.
1. Click the Setup Extract button on the Verification toolbar to bring up the Setup Extract pop-up.
Select the General tab. Ensure sure the Generic_180nm.ext extraction command file is selected. Set
the SPICE extract output file name to be NAND2.sp. The General tab should appear as shown in
Figure 9.

Figure 9

2. Now select the Options tab. In the Statements to include before netlist window type:
. i ncl ude mosi s_t smc_180nm_18. model
. opt i ons gmi n=1E- 9
Vvdd vdd 0 dc 3
Vvss vss 0 dc 0

These statements will (i) tell the SPICE simulator where the find the transistor models, (ii) add a
small conductance to each circuit node to improve numerical stability and (iii) set up the VDD and
VSS voltage sources.
3. Click the boxes Write empty subcircuit definitions and Write hierarchical netlist. Leave the other
boxes unchecked. Click the radio button Extract as: Toplevel cell. The Options tab should now
appear as shown in Figure 10. Click OK.
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Figure 10

4. Initiate the extraction by clicking the HiPer Extract button on the Verification toolbar.
5. Once the extraction has completed it will generate two new windows. At the bottom of the screen you
will see the Verification Navigator sub-window which will list any errors that occurred during the
extraction (similar to what we obtained when running DRC). Above this window will be a new sub-
window which shows the extracted SPICE listing. Take a look at this listing. At the top you will see
the four statements we added when setting up the extraction. Then you will see a listing of all the
components in your circuit. There are two NMOS transistors and two PMOS transistors.
6. When you have finished examining the SPICE listing, close the SPICE listing sub-window and the
Verification Navigator sub-window to return to your layout.
Simulating the circuit with LTspice

We now invoke the Tanner SPICE simulator T-Spice to check out the behavior of our NAND gate..
1. Start T-Spice by finding it in the Windows Start menu or by double clicking the icon on the
desktop.
2. Select File > Open and browse to open C:\690_Designs\NAND2.sp. The SPICE file that we just
extracted will appear in a sub-window.
3. Immediately under the line that reads: Vvss vss 0 dc 0 , type the following:

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Vi nA A 0 dc 0 pul se 0 3 0ns 1ns 1ns 25ns 50ns
Vi nB B 0 dc 0 pul se 0 3 12ns 1ns 1ns 25ns 50ns
cout Z 0 50f F

. t r an . 1ns 100ns
. pr i nt v( A) v( B) v( Z)

The first two lines set up repetitive clock signals to drive the two inputs nodes A and B.
The third line adds a load capacitance of 50fF to the output node Z.
The fourth line sets the maximum time-step and duration of the transient simulation
The last line asks the simulator to plot the voltages on input nodes A and B and output node Z.
4. Save this file (NAND2.sp). That way you have the circuit description and the simulation control
commands saved in one file. Remember that if you subsequently re-extract the file NAND2, it will
overwrite this file and you will have to re-enter the simulation control commands.
5. Start the simulation by clicking the Run Simulation button on the T-Spice Simulation toolbar.
A pop-up window shows the status of the simulation and reports any simulation errors. Once the
simulation is complete, T-Spice automatically starts up the Tanner Waveform Editor W-Edit. This
utility will display your simulation waveforms as shown in Figure 11.


Figure 11

6. Remove the Waveform Calculator and Command sub-windows from the bottom of the W-Edit
window. This will give you more room to see your waveforms.
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7. If you right click in the waveform window and select Expand Traces, it will separate the waveforms
on to three separate axes which will make it much easier to read. You should now see waveforms as
shown in Figure 12.

Figure 12

8. Now, back in T-Spice, close the Simulation Status sub-window. Now try changing the load
capacitance in the SPICE file from 50fF to 500fF. Re-run the simulation and see how it changes the
output waveform.
9. Congratulations. You made it to the finish line.