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Dr. Ahmed H.

Madian-VLSI
Very Large Scale Integration
(VLSI)
Dr. Ahmed H. Madian
ah_madian@hotmail.com
Lecture 8
Dr. Ahmed H. Madian-VLSI
Content
Array Subsystems
Introduction
General memory array architecture
SRAM (6-T cell)
CAM
Read only memory
Dr. Ahmed H. Madian-VLSI
Introduction
Mask Rom
Progrmmable
ROM (PROM)
Erasable
Programmable
ROM
(EPROM)
Electrically
Erasable
Programmable
ROM
(EEPROM)
Flash Rom
Serial In
Parallel out
(SIPO)
Memory Arrays
Random Access memory
Content addressable
memory (CAM)
Read/write
memory
(RAM)
(volatile)
Read only
memory
(ROM)
(non- volatile)
Static
RAM
(SRAM)
Dynamic
RAM
(DRAM)
Shift registers Queues
Parallel In
Serial out
(PISO)
First In
First out
(FIFO)
Last In
First out
(LIFO)
Serial Access memory
Dr. Ahmed H. Madian-VLSI
Design Tradeoffs
Density: bits/unit area. Usually higher density also
means lower cost per bit. Improvements due to finer
lithography, better capacitor structures, new
materials with higher dielectric constants.
Speed: access time (latency) and bandwidth.
Improvements due to better sensing (smaller
voltage swing), increased parallelism
(overlapped accesses), faster I/O.
Power consumption: want
power to depend on access
pattern not quantity of bits
stored. Improvements due
to lower supply voltage.
I mprovements in one
dimension come at an
increased cost in the other
dimensions.
Dr. Ahmed H. Madian-VLSI
Memory Array architecture
Why we need a
column decoder?
Dr. Ahmed H. Madian-VLSI
Memory Array (cont.)
Typically want an aspect ratio that is not too far from
square
How to divide up the row, column address decoding?
Use an 8K x 32 SRAM = 256 Kb = 2
18
2
18
= 2
9
rows x 2
9
columns
Row decoder is 9 to 512 decoder
Every 32 (2
5
) columns is a ‘word’, and we only need to
decode words. So, column decoder needs to decode 2
4
words, so need a 4 to 16 column decoder.
Dr. Ahmed H. Madian-VLSI
6-transistor SRAM cell
6-T cell needs a careful and clever
layout to achieve good density
Dr. Ahmed H. Madian-VLSI
6-T SRAM cell (cont.)
Sense amplifier is
used to detect any
small changes
between the bit line
and its complement
Dr. Ahmed H. Madian-VLSI
6-T SRAM cell (cont.)
Only one control terminal for
access
Word-line
Read
Both bit lines start at V
DD
Cell pulls one down
Cell value remains unchanged
Write
One bit line is pulled low
Low bit line value over-powers cell
Cell changes state
Dr. Ahmed H. Madian-VLSI
Bit-line vs. word-line
Assertion of word-line accesses all cells in a row
Not all bits that are read from a row may be used.
Loading on word line is high
Bit lines connect all cells in a column, only one
cell in a column can ever be on at a time
Would like to keep bit-line swing low in order to
preserve power
Sense Amp function is to detect bit line change and
produce a full ‘0’ or ‘1’ for output latch
Dr. Ahmed H. Madian-VLSI
Write circuitry
Dr. Ahmed H. Madian-VLSI
Bit-line biasing (cont.)
Method I: Similar to pseudo
nMOS
Permanent pull-up
Still need to equalize!
Swing is now "clamped" to
∆V=I
drive
·R
pMOS
Sense amplifier must still
operate around V
DD
Dr. Ahmed H. Madian-VLSI
Bit-line biasing (cont.)
Method II: "nMOS"
Swing is clamped and
levels are shifted by V
THn
Dr. Ahmed H. Madian-VLSI
Bit-line biasing
Bit lines are typically biased somewhere
between 0 and V
dd
improve speed of cell for reading/writing
limit bit-line voltage swing for power savings
Bit line biasing circuit at top of each column
Bit line biasing circuit can either be static or
dynamic (dynamic operation controlled by
clock or pulse generated by address line
change).
Dr. Ahmed H. Madian-VLSI
Read Delay
How do we get high-speed operation?
Parasitic delay of this gate (cell driving bit-line) is
large
Changing the transistor sizes doesn’t help!
(much)
Parasitic delay changes only slowly with sizing
(wire cap)
Memory area will grow with larger transistor
Needs to be small to get good density
Dr. Ahmed H. Madian-VLSI
How to Speed up Read?
Use very short bit-lines
16 to 32 cells might be ok
Use small swings
Remember: ∆t = C·∆V/I
Why does that help?
C
load
· ∆V
load
is the charge we have to supply to
the load
Having smaller ∆V
load
is equivalent to having
smaller C
load
Dr. Ahmed H. Madian-VLSI
Small Swings
Cause two problems:
How to generate them?
How to sense them?
Creating small swings
Clamp the bit-line swings
Make the word-line a pulse
J ust sense the bit-lines early
Need to reset bit-lines to make sure both start high for read
Sensing small swings
Need low noise sensitivity
implies differential inputs
Need to build an amplifier.
Dr. Ahmed H. Madian-VLSI
Word selection
Column decoder is similar to word-line decoder
Need to select 1 out of 2
m
columns for read/write
Dr. Ahmed H. Madian-VLSI
Word selection (cont.)
Need transmission
gate for column select
nMOS good for pulling
Bit-line low (write)
pMOS good for
passing voltage near
V
DD
to sense amplifier
(read)
Dr. Ahmed H. Madian-VLSI
Word selection (cont.)
Possible to split signal path
and make column signals
unidirectional
– nMOS for pulling word-line
low (write)
– pMOS for passing voltage
near VDD to sense amplifier
(read)
More wires, but they are
shorter
Puts large write driver
parasitics on already loaded
bit-lines
Not at sense amp input
Dr. Ahmed H. Madian-VLSI
Sense amplifier
Only one bit line will swing.
Want Sense Amplifier turned on for short amount of
time in order to save power.
J ob of SA is to sense bit line swing, amplify to full
swing output.
Dr. Ahmed H. Madian-VLSI
Sense amplifier sharing
Dr. Ahmed H. Madian-VLSI
4 to 1 tree decoder
Are able to use nmos-
only pass transistors
because of limited
swing.
Number of pass
transistors in series is
a concern, but limited
swing helps speed.
Dr. Ahmed H. Madian-VLSI
Decoders
Dr. Ahmed H. Madian-VLSI
Decoders (cont.)
Increasing number
of input lines
increase the area of
the decoder
Dr. Ahmed H. Madian-VLSI
Pre-decoding
Decoders with
many inputs can
be formed from
cascade of smaller
gates. This
technique is called
“pre-decoding”
Dr. Ahmed H. Madian-VLSI
Bit line to bit line coupling
Dr. Ahmed H. Madian-VLSI
Transposed Bit lines
Does not reduce noise
coupling, but couples same
noise into both bitlines so
appears as common node
noise and is rejected.
Dr. Ahmed H. Madian-VLSI
Content
addressable
memory (CAM)
Dr. Ahmed H. Madian-VLSI
Dynamic Memory Cell
Dr. Ahmed H. Madian-VLSI
Dynamic Ram (cont.)
Voltage swing on Bitline is small
Want Bitline capacitance as small as possible, Bit
cell capacitance as large as possible to increase
charge transfer
Read is destructive – part of read cycle is
used to restore level inside of bit cell
capacitor
Capacitor leaks, must be refreshed
periodically
Noise sources in DRAM are word line to bit
line coupling, bit line to bit line coupling
Dr. Ahmed H. Madian-VLSI
Read Only Memory (ROM)
Dr. Ahmed H. Madian-VLSI
Mask-programmed ROMs
Y
0
Y
1
Y
2
Y
3
Y
4
=00101
Dr. Ahmed H. Madian-VLSI
Programmable ROMs
PROM can be fabricated as
ROM fully populated with
pull-down transistors in
every position.
Each transistor is placed in
series with a fuse made of
polysilicon, or any other
conductor that can be burnt
out by applying a high
current.
PROM is one time
programmed
Dr. Ahmed H. Madian-VLSI
EPROM, EEPROM and Flash
Reprogrammable nonvolatile memory.
These memories use a second layer of polysilicon to form a floating
gate between the primary gate and the channel
The floating gate is a good conductor, but it is not attached to
anything.
Applying a high voltage for the upper gate causes electrons to jump
through the thin oxide onto floating gate through the processes
called avalanche injection.
Injecting electrons includes a negative voltage on the floating gate,
which increasing threshold voltage of the transistor to the point that
it is always OFF.
n+ n+
source Drain
Gate
Polysilicon
Floating gate
Dr. Ahmed H. Madian-VLSI
Assignment 4
It would be available on web today the
due date Tuesday, 15/12/2009
Quiz 2 will be next week