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Feasibility study and on-chip antenna for fully integrated μRFID

tag at 60 GHz in 65 nm CMOS SOI

A. Fonte, S. Saponara, G. Pinto, B. Neri
Dipartimento di Ingegneria dell’Informazione, Università di Pisa, I-56122, Pisa, Italy

Abstract—This paper reports the feasibility study of a novel
passive tag for μRFID applications in the worldwide available
free 60-GHz band. The feasibility analysis indicates that a passive
fully-integrated μRFID tag, with on-chip antenna, can be realized
in 65-nm SOI CMOS technology at 60 GHz with an operating
range of about 20 cm. The 65-nm SOI CMOS technology
represents a good candidate due to its better performance in
terms of low-losses, low-power consumption and lower leakage
current if compared with standard bulk process. The proposed
circuit does not require complex package or bonding, thanks to
the on-chip antenna, and it does not need battery. The low-cost
technology and low-weight and low-area occupation are
important features of this μRFID, especially if produced in large
scale for the mass-market. Since the design of integrated
antennas in silicon technology is one of the main challenge,
especially for this proposal, two 60-GHz antennas have been
designed by means of 3D-EM simulator: a CPW double-slot
antenna and a CPS dipole one. The simulation results show a
gain of 4.44 dBi and 3.23 dBi for the proposed double slot and
dipole on-chip antennas, respectively.
Index Terms— 60-GHz, 65nm CMOS SOI (Silicon on Insula-
tor), CoPlanar Waveguide (CPW), CoPlanar Strip (CPS), On-
chip integrated antenna, Radio Frequency IDentification (RFID)
ADIO Frequency Identification (RFID) technology is
now extensively utilized in many commercial applications
such as access control, security and also in the modern supply
chain management in order to identify and track the goods. A
basic RFID system consists of at least two components, one or
more transponders (tags), which are located on the objects to
be identified and tracked, and the reader, which, depending on
the technology used and the application, can be a read or a
read/write device. The operating principle is very easy: the tag
receives a signal from the reader and then sends back a signal
including the unique serial number and some additional data.
There are generally three types of RFID tags: i) active tags,
which include a battery for their working and to transmit the
signal to the reader autonomously; ii) passive tags, which have
no battery and collect from the reader all the energy required
for their working and to transmit the signal back to the reader;
iii) semi-passive tags, which include a battery only for their
working but collect from the reader the energy to transmit the
signal. Though active RFID tags have better performance in
terms of maximum operating range and more embedded func-
tions, they are mainly used for high-price merchandise due to
their high-manufacturing cost. On the other hand, the passive
tags dominate the market due to a lower production cost, even
if the size of these devices is often limited to the external an-
tenna [1-3].
Indeed, passive μRFID tags can be efficiently adopted for a
series of new short-range applications (see Fig. 1) such as con-
tact-less cards (e.g. credit or debit card), secure keys (secure
automobile or door keys) and they can also be integrated into
banknotes in order to increase the security against falsifica-
tion. The key limitations of these tags are the power consump-
tion and the difficulty to design the system as small as possible
preserving a low manufacturing-cost.
The passive μRFID tag presented in this paper has been de-
signed to achieve these goals. In detail, in Section II, a feasi-
bility study of a 60-GHz fully integrated passive μRFID tag in
65-nm CMOS SOI technology is presented. In Section III the
3D-EM designs of different 60-GHz on-chip integrated anten-
nas are shown. Finally, in Section IV conclusions are drawn.
The proposed chip for the 60-GHz μRFID tag is made up of
an on-chip integrated single-ended antenna, the radio-
frequency front-end and the digital circuits. I/O pins and
battery are not required thus simplifying packaging and bond-
ing. The architecture of the passive tag is shown in Fig. 2. In
detail the chip consists of i) the integrated antenna which rece-
ives the reader signal and collects the energy for the tag opera-
tion, ii) the matching network in order to ensure the maximum
power transfer from the transponder’s antenna to the input of
the rectifier, iii) the rectifier which provides the power supply
to the analog blocks, iv) the voltage regulator to supply stable
output voltage, v) the ring oscillator for the clock generation,
vi) the backscatter modulator which modules the load of the
antenna in order to send the unique serial number and/or some
additional data to the reader and finally vii) the digital section
which typically is a very simple finite-state machine able to
manage the communication protocol.

Fig. 1. Some possible applications of the fully integrated 60-GHz passive
μRFID tag: a) contact-less smart card, b) secure banknote, c) secure car keys.

2011 IEEE International Conference on RFID-Technologies and Applications
978-1-4577-0027-9/11/$26.00 ©2011 IEEE 457

Since this tag is completely passive (no battery), the operat-
ing range is small (tens of centimeters): it has been estimated
by considering the restriction applied for devices operating in
the 60-GHz frequency range.
A. Operating Range
Around 60 GHz there are 7-GHz of unlicensed bandwidth
with few regulatory specifications. The allocated frequency
bandwidth varies from country to country. In detail, European
Telecommunications Standards Institute (ETSI) has recently
published a new version of a European standard which prom-
ises to significantly increase the broadband capacity to meet
the ever-growing demands foreseen for European communica-
tions [4]. The standard now covers microwave links that oper-
ate in the frequency bands between 57 and 66 GHz. Moreover,
the Federal Communications Commission (FCC) in the fre-
quency allocation table provides, for Canada and USA, fre-
quency bands between 57 and 64 GHz for unlicensed applica-
tions [5]. Different specifications are adopted in Australia
(59.4 – 62.9 GHz) and Japan (59 – 66 GHz), but in any case
there is an overlap of about 3 GHz around 60 GHz which is
worldwide available, as shown in Fig. 3.
In order to estimate the operating range, defined as the max-
imum distance between reader and tag at which the link radio
can be considered reliable, some considerations have been
made and the power limits required in the 60-GHz bandwidth
have been taken into account.
The ETSI and FCC specifications limit the average power
density of any emission in this band to 9 µW/cm
and the peak
power density to 18 µW/cm
, both measured at a distance of
3 meters from the radiating structure. These average and peak
power density limits are equivalent to average and peak of the
Effective Isotropic Radiated Power (EIRP) limits of 10 W
(40 dBm) and 20 W (43 dBm), respectively. The rules also
limit the peak transmitter output power to 500 mW (27 dBm)
with an emission bandwidth of at least 100 MHz. Anyhow, the
Wireless Communications Association International (WCAI)
requests that the EIRP emission limit for point-to-point sys-
tems, employing very high gain antennas, should be 82 dBm
less 2 dB for every dB that the systems’ antenna gain is below
51 dBi. In this way, the EIRP limits are those in Table I.
By taking into account the specifications in term of antenna
gain, EIRP limit and frequency bandwidth, the operating range
of the 60-GHz passive tag has been estimated. Plausible val-
ues of the reader antenna gain (G
) and EIRP for our applica-
tion can be 30 dBi and 40 dBm, respectively. Since the system
works correctly when the power collected by the tag (P
) is
higher than the minimum power consumption of the tag, then
the maximum distance between the reader and the tag (R
can be calculated as:

= ⋅
where G
is the antenna gain of the tag, and λ
is the wave-
However, the signal power received by the reader from the
tag has to be higher than the reader sensitivity (S
). Therefore,
taking into account this limit, the maximum distance between
the reader and the tag can be estimated by using the following
max 2
⋅ ⋅
= ⋅

Obviously the operating range is the smaller between r

and r
. Now, by considering a plausible value of the tag an-
tenna gain G
of at least 0 dBi (see results in Section III),
the minimum tag power consumption of about 5 μW as in [6],
and the efficiency of the rectifier at 60 GHz close to 5% as in
[7], then the P
has to be at least 100 μW, and then
= 12.6 cm. Moreover, S
depends on the bit error rate
(BER) of the system and the noise figure of the reader. A feas-
ible value of S
for 60 GHz designs can be close to -60 dBm
with a BER of 10
[8] and then r
= 70.76 cm. Therefore
the operating range for 60-GHz μRFID tags is due to r
The RFID tag architecture in Fig. 2 is similar to other state-
of-art designs apart the on-chip antenna, the new key element
of this design described in details in Section III. In order to
build the 60-GHz fully-integrated tag proposed in this paper,
an accurate design of the on-chip antenna is required for
transmission and reception. It is worth nothing that the inte-
gration of antennas on silicon substrates is a critical require-

Fig. 2. Block diagram of the fully integrated 60-GHz passive μRFID tag.

Fig. 3. Worldwide frequency allocation around 60 GHz.

Antenna Gain
EIRP limit Transmitter Power
30 dBi 40 dBm (10 W) 10 dBm
40 dBi 60 dBm (1 KW) 20 dBm
50 dBi 80 dBm (100 KW) 27 dBm


ment enabling the entire system to be realized as a monolithic
unit that does not require any external transmission line con-
nections or sophisticated packaging. As shown in the next sec-
tion the 65-nm SOI CMOS process is a good candidate to effi-
ciently implement integrated antennas in the 60 GHz band.
B. SOI CMOS: Technology description
The SOI CMOS technology shows very attractive perfor-
mance for the millimeter-wave system-on-chip design, since
the high active performance of MOS transistors, such those
available in standard CMOS technology used in digital de-
signs [16-24], are combined with the high-resistivity (HR) of
the SOI substrate. Indeed, the feature that the circuit elements
are isolated dielectrically allows the SOI technology to signif-
icantly reduce junction capacitances and allows the circuits to
operate at high speed or substantially with lower power at the
same speed. Moreover, the device structure also eliminates the
latch-up in bulk CMOS and improves the short channel effect
immunity. A comparison between SOI and bulk CMOS tech-
nologies is shown in Fig. 4, in which the buried oxide (BOX)
layer (ε
= 4) and the high resistive (HR) substrate (ε
= 11.7,
= 0.0001 S/m, and h
= 355 μm) can be noted in the SOI
process. Finally, the performance of the antennas designed in
SOI CMOS process are better than those designed on standard
CMOS process, as demonstrated in [9-13]. This improvement
is due to a reduced amount of energy stored in the supporting
In this section the designs and the simulation results of two
different antennas, integrated in 65-nm SOI CMOS technolo-
gy, will be described.
A. Cross-section of the SOI CMOS process
The cross-section of a standard industrial SOI CMOS back-
end is shown in Fig. 5a. In this technology the back-end con-
sists of a very complex multi-layer in which the dielectric
multi-layer is composed by an alternation of SiO
and Si
For computing time reasons, since the 3D-EM simulator used
is a volume field solver (i.e. Ansoft HFSS), the multi-layer
back-end has been simplified to an equivalent back-end with a
reduced number of equivalent ticker layers that results in a
more efficient solution. In detail, the parameters took into ac-
count in order to build the simplified cross-section of the SOI
CMOS process are the metallization thickness made of 6 thick
copper staked layers (M
), the aluminum capping layer
(AP) and the multi-layer dielectrics. The simplified cross-
section for the 3D-EM simulations are reported in Fig. 5b
where the multi-layer stack has been significantly compressed
without compromising the accuracy. For that purpose, a
weighted average of the dielectric material properties and
thickness calculated by means of the formula described in [14]
has been applied. The relative permittivity of each equivalent
layer (ε
) is calculated by:
( )
, 1
e eq n n n
n n
h h
ε ε ε ε

⎡ ⎤
= + −
⎢ ⎥
⎣ ⎦
where n is the layer index, ε
and h
are the relative permittivi-
ty and the thickness of the n
layer, respectively.
B. Antennas design
According to the above analysis, the CPW (Coplanar wave-
guide) topology is a good candidate to design the antenna for
the 60-GHz μRFID tag. The work in [15] has also demonstrat-
ed that in HR SOI substrates the losses are drastically reduced
if compared with the bulk silicon technology, in which the
CPW transmission lines are made only on top metal layer in
order to reduce substrate losses. The design presented herein
makes use of staked structure (M
-AP) for the ground paths
and AP and M
metal layers for the signal paths. It is worth
noting that the ground planes have to be large enough to intro-
duce negligible effects on the antenna property, and then a
compromise has been reached between infinite ground planes
and suitable dimensions for silicon applications. Fig. 6 shows
the simplified CPW architecture dedicated to SOI CMOS
process; in Fig 6 W is the width of the signal line and G is the
gap between the signal line and the ground plane.
To realize a balanced and simpler feeding line for the radia-

Fig. 4. a) Simplified cross section of SOI CMOS process and b) Simplified
cross-section of bulk CMOS process.

Fig. 5. a) Cross section of SOI CMOS back-end and b) Simplified cross-
section of SOI CMOS back-end for 3D-EM simulations.

Fig. 6. Simplified CPW architecture implemented for the SOI CMOS tech-
Fig. 5. a) Cross section of SOI CMOS back-end and b) Simplified cross-
section of SOI CMOS back-end for 3D-EM simulations.


tion structure, also the CPS (Coplanar strip) topology has been
looked at. In Fig 7, a CPS with a finite dielectric thickness
configuration is depicted, where S, W, H, and ε
represent the
slot width, strip width, substrate thickness, and relative dielec-
tric constant of the substrate material, respectively. The design
presented herein makes use of M
metal layers for the signal
The integrated antennas proposed hereafter in Sections III.C
and III.D are designed taking into account the following
guidelines: i) the 65-nm SOI CMOS process by ST-
Microelectronics has been used, ii) the 3D-EM designs did not
consider the pad effects since these parasitic effects will be
removed by de-embedding during the measurements, iii) the
knowledge of the effective dielectric constants are necessary
to determine the resonant frequency.
At the operating frequency the antenna reactance (Im{Z
must be null and the real part of intrinsic antenna impedance
}) must be matched to the communication circuit out-
put impedance. In the considered case of an on-chip integrated
antenna the impedance value can be taken as a parameter of
the design.
C. CPW Double slot antenna
The first proposed antenna is a CPW double slot (see geo-
metrical parameters and layout in Fig. 8). There are many
coupling matching networks that can be used to connect the
transmission line to the antenna element such as quarter-
wavelength transformer, stub, T-match and others. For exam-
ple, a λ/4 transformer can be used to match CPW double slot
antenna to the canonical 50 Ω impedance. In order to provide
the matching, the λ/4 transformer characteristic impedance Z

has been set equal to:
/ 4 0 IN
= ⋅
where Z
= 50 Ω represents the characteristic impedance of
the CPW transmission line and R
= Re{Z
} is the input im-
pedance of the antenna.
In this design, the gap between ground plane and antenna
and G
in Fig. 8) is carefully selected to obtain a good
radiation pattern and resonant behavioral at the operating fre-
quency. An unbalanced CPW feed line is choice as input of
the antenna.
The final 60 GHz fully integrated double-slot antenna is
realized with the following parameters: slot’s length = 910.22
μm (L
), width = 22.76 μm (W
) and 40 μm gap between
ground plane and antenna’s arm. The CPW parameters are W
= 12 μm and G = 12.2 μm. The feeding line’s length is of 560
μm (L
). Output impedance is about 14.3 Ω at work fre-
quency. The simulated radiation pattern of this antenna is
mainly directed toward the SOI substrate, therefore, with a
backside metallization the radiation pattern is directed outward
the substrate. The distance between radiating arms and the ref-
lector (355 μm ~ λ
/4) is close to the optimal distance to pre-
vent TM mode which reduces radiation efficiency.
The area needed for the antenna design is roughly 1 mm
compliant with on-chip realization. The 3D polar plot of the
antenna gain and the radiation pattern obtained by means of
3D-EM simulations are shown in Fig. 9. In detail, a maximum

Fig. 8. 60-GHz SOI CMOS CPW double slot antenna a) geometrical para-
meters and b) design on the 3D-EM simulator.

Fig. 9. 60-GHz SOI CMOS CPW double slot antenna. 3D polar plot of the
antenna gain and radiation pattern.

Fig. 7. Simplified CPS architecture implementation.


gain of 4.44 dBi, a return loss (S11) equal to - 21.82 dB and an
efficiency of 67% at 59.4 GHz have been obtained. Finally, a
directivity peak of about 4.15 is obtained. With a tag antenna
gain (G
) of 4.44 dBi the value of r
in equation (1),
which determines the operating range, is about 21 cm.
D. CPS dipole antenna
As alternative to the antenna in Section III.C we also de-
signed and characterized by 3D-EM simulations a CPS dipole
antenna. The antenna we designed (see Fig. 10) is directly fed
by a coplanar strip (CPS) input matching network. The area
occupied by the antenna is 0.244 mm
, which is suited for on
chip integration. The radiation pattern of the CPS dipole an-
tenna obtained by means of 3D-EM simulations is shown in
Fig. 11. In detail, a maximum gain of 3.23 dBi and a return
loss (S11) equal to -23.7 dB at 60 GHz, respectively, have
been obtained. With a tag antenna gain (G
) of 3.23 dBi the
value of r
in equation (1), which determines the operating
range, amounts to 18.25 cm.
In this design, the arm width is carefully selected to reduce
the quality factor of resonance and obtain a wider operating
bandwidth. A balanced CPS feed line is choice as input of the
dipole antenna, and its length is tuned in order to obtained the
wished input impedance (≈ 20 Ω at work frequency). The final
60 GHz fully integrated dipole antenna is realized with the fol-
lowing parameters: dipole's length = 760 μm (L
), width =
22.76 μm (W
) and 1.1 μm gap between the two dipole’s
arms. The feeding line’s length is of 300 μm (L
The radiation pattern of the integrated dipole shows that the
radiation is mainly directed toward the SOI substrate, where
losses occur. The backside metallization under the wafer can
be advantageously used to act as a reflector. The radiation pat-
tern is directed outward of the substrate when backside metal-
lization is added. The distance between radiating arms and the
reflector (355 μm ~ λ
/4) is close to the optimal distance. Fi-
nally, the dipole antenna has 68.8% of radiation efficiency,
with peak directivity of about 3.
Both designed antennas are suitable for on chip integration.
The first type of antenna is the most conventional, and takes
larger chip area, but it presents a higher gain and a particular
behavioral of imaginary part of impedance. As we can see in
Fig. 12, there are many resonant points, so the antenna can be
useful in different frequency ranges. The bandwidth of the
double-slot antenna is thin, only 900 MHz, however, it’s
enough for the RFID applications. The dipole antenna, instead,
presents a balanced feed line, useful in differential elaboration
of signals, and a very small chip area.
A fully integrated passive μRFID tag for applications in the
60-GHz license-free band has been presented and the advan-
tages of a fully integration have been described. The 60-GHz
tag does not require pads, bonding or package and does not
needs battery, therefore it represents an important innovation
to further extend the applications of RFIDs. The 65-nm SOI
CMOS process by ST-Microelectronics used in the design,
allowed us, to design a more efficient antenna thanks to its
higher isolation between the substrate and active region, if
compared with a traditional CMOS bulk process. Two inte-
grated 60-GHz antennas have been designed and simulated by
means of the 3D-EM simulator HFSS. The results have shown
a gain of 4.44 dBi and 3.23 dBi, respectively, for the double-
slot and dipole antennas.
Finally, the low-cost, the very low-weight, and the low-area
occupation due to the fact that there are no external elements,
makes the proposed μRFID tag very attractive for the mass-
market, especially in those sectors where traditional tags can-
not be used.

Fig. 10. 60-GHz SOI CMOS Dipole antenna: a) geometrical parameters
and b) design on the 3D-EM simulator.

Fig. 11. 60-GHz SOI CMOS CPS dipole antenna: radiation pattern.


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30 35 40 45 50 55 60 65 70 75 80 85 90
Freq [GHz]
Fig. 12. 60-GHz SOI CMOS CPW double slot antenna a) input resistance and b) input reactance.