H.

265 intra prediction

(d on trong nh)

DOAN VAN LOC_INTRA_PREDICTION.

DOAN VAN LOC_INTRA_PREDICTION.

Table of Contents
Figure 1: H.264 intra prediction block diagram 8................................................................... 6
Figure 2: Block diagram of controller 9................................................................................... 6
Figure 3: Block diagram of I4M_top 10...................................................................................

Figure 4: Intra4x4_controller block diagram 12...................................................................... 6

Figure 5: Prediction mode selection in I4M_controller 14...................................................... 6
Figure 6: I4M_PE 15.................................................................................................................... 6
Figure 7: I4M_PE architecture 16............................................................................................. 6
Figure 8: Block diagram of I4M_neigh_mem 17...................................................................... 6
Figure 9: Block diagram of I4M_pred_mem 18......................................................................

Figure 10: Block diagram of I4M_res_mem 19.......................................................................... 6

Figure 11: Block diagram of I4M_res_cal 20............................................................................. 6
Figure 12: Block diagram of I16M_top 21................................................................................ 6
Figure 13: I16M_controller 22.................................................................................................... 6
Figure 14: I16M_PE 24................................................................................................................ 6
Figure 15: Block diagram of I16M_neigh_mem 25................................................................... 6
Figure 16: Block diagram of I16M_pred_mem 26................................................................... 6
Figure 17: Block diagram of I16M_res_mem 27...................................................................... 6
Figure 18: Block diagram of I16M_res_cal 28.......................................................................... 6
Table 1: I/O description of the Intra Prediction 9...................................................................... 7
Table 2: I/O description of controller 10................................................................................... 7
Table 3: I/O description of I4M_top 11....................................................................................... 7
Table 4: I/O description of I4M_controller 13..........................................................................

Table 5: I/O description of I4M_PE 15....................................................................................... 7

Table 6: I/O description of I4M_neigh_mem 17......................................................................

Table 7: I/O description of I4M_pred_mem 18.......................................................................... 7

Table 8: I/O description of I4M_res_mem 19............................................................................. 7
Table 9: I/O description of I4M_res_cal 20................................................................................ 7
Table 10: I/O description of I16M_top 22................................................................................... 7
Table 11: I/O description of I16M_controller 23...................................................................... 7
Table 12: I/O description of I16M_PE 25................................................................................... 7
Table 13: I/O description of I16M_neigh_mem 26................................................................... 7
Table 14: I/O description of I16M_pred_mem 27...................................................................... 7
Table 15: I/O description of I16M_res_mem 27......................................................................

Table 16: I/O description of I16M_res_cal 29.......................................................................... 7

I. Introduction............................................................................................................................. 8
II. Intra prediction block............................................................................................................. 8
3

DOAN VAN LOC_INTRA_PREDICTION.

II.1. Abstract ........................................................................................................................................... 8

II.2. Top-block Diagram.........................................................................................................................

II.3. I/O Description................................................................................................................................ 9

II.4. Sub-block Specifications.............................................................................................................. 10
II.4.1. Controller................................................................................................................................

10

II.4.1.1) Abstract..............................................................................................................

10

II.4.1.2) Block Diagram....................................................................................................

10

II.4.1.3) I/O Description....................................................................................................

11

II.4.2. I4M_top.................................................................................................................................... 11
II.4.2.1) Abstract..............................................................................................................

11

II.4.2.2) Block Diagram....................................................................................................

11

II.4.2.3) I/O Description....................................................................................................

11

II.4.3. I4M_controller.........................................................................................................................

12

II.4.3.1) Abstract..............................................................................................................

12

II.4.3.2) Block Diagram....................................................................................................

13

II.4.3.3) I/O Description....................................................................................................

13

II.4.3.4) Algorithm description............................................................................................ 14

II.4.4. I4M_PE.................................................................................................................................... 15
II.4.4.1) Abstract..............................................................................................................

15

II.4.4.2) Block diagram....................................................................................................

16

II.4.4.3) I/O description....................................................................................................

16

II.4.4.4) Algorithm description............................................................................................ 17

II.4.5. I4M_neigh_mem.....................................................................................................................

17

II.4.5.1) Abstract..............................................................................................................

17

II.4.5.2) Block diagram....................................................................................................

18

II.4.5.3) I/O description....................................................................................................

18

II.4.6. I4M_pred_mem.....................................................................................................................

19

II.4.6.1) Abstract..............................................................................................................

19

II.4.6.2) Block diagram....................................................................................................

19

II.4.6.3) I/O description....................................................................................................

19

II.4.7. I4M_res_mem.........................................................................................................................

19

II.4.7.1) Abstract..............................................................................................................

19

II.4.7.2) Block diagram....................................................................................................

20

II.4.7.3) I/O description....................................................................................................

20

II.4.8. I4M_res_cal.............................................................................................................................

20

II.4.8.1) Abstract..............................................................................................................

20

II.4.8.2) Block diagram....................................................................................................

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DOAN VAN LOC_INTRA_PREDICTION.

II.4.8.3) I/O description....................................................................................................

21

II.4.9. I16M_top................................................................................................................................

22

II.4.9.1) Abstract..............................................................................................................

22

II.4.9.2) Block Diagram....................................................................................................

22

II.4.9.3) I/O Description....................................................................................................

22

II.4.10. I16M_controller.....................................................................................................................

23

II.4.10.1) Abstract.............................................................................................................. 23
II.4.10.2) Block diagram.................................................................................................... 23
II.4.10.3) I/O description.................................................................................................... 23
II.4.11. I16M_PE................................................................................................................................ 24
II.4.11.1) Abstract.............................................................................................................. 24
II.4.11.2) Block diagram....................................................................................................

25

II.4.11.3) I/O description.................................................................................................... 25

II.4.12. I16M_neigh_mem.................................................................................................................. 26
II.4.12.1) Abstract.............................................................................................................. 26
II.4.12.2) Block diagram.................................................................................................... 26
II.4.12.3) I/O description.................................................................................................... 26
II.4.13. I16M_pred_mem..................................................................................................................... 27
II.4.13.1) Abstract.............................................................................................................. 27
II.4.13.2) Block diagram.................................................................................................... 27
II.4.13.3) I/O description.................................................................................................... 27
II.4.14. I16M_res_mem.....................................................................................................................

28

II.4.14.1) Abstract.............................................................................................................. 28
II.4.14.2) Block diagram.................................................................................................... 28
II.4.14.3) I/O description.................................................................................................... 28
II.4.15. I16M_res_cal.........................................................................................................................

28

II.4.15.1) Abstract.............................................................................................................. 28
II.4.15.2) Block diagram.................................................................................................... 29
II.4.15.3) I/O description.................................................................................................... 29

DOAN VAN LOC_INTRA_PREDICTION.

List of Figures
Figure 1: H.264 intra prediction block diagram.......................................................................... 9
Figure 2: Block diagram of controller...................................................................................

10

Figure 3: Block diagram of I4M_top.......................................................................................

11

Figure 4: Intra4x4_controller block diagram.......................................................................... 13

Figure 5: Prediction mode selection in I4M_controller.......................................................... 15
Figure 6: I4M_PE....................................................................................................................... 16
Figure 7: I4M_PE architecture................................................................................................ 17
Figure 8: Block diagram of I4M_neigh_mem.......................................................................... 18
Figure 9: Block diagram of I4M_pred_mem..........................................................................

19

Figure 10: Block diagram of I4M_res_mem..........................................................................

20

Figure 11: Block diagram of I4M_res_cal................................................................................ 21

Figure 12: Block diagram of I16M_top................................................................................... 22
Figure 13: I16M_controller....................................................................................................... 23
Figure 14: I16M_PE................................................................................................................

25

Figure 15: Block diagram of I16M_neigh_mem...................................................................... 26

Figure 16: Block diagram of I16M_pred_mem...................................................................... 27
Figure 17: Block diagram of I16M_res_mem.......................................................................... 28
Figure 18: Block diagram of I16M_res_cal............................................................................. 29

DOAN VAN LOC_INTRA_PREDICTION.

List of Tables
Table 1: I/O description of the Intra Prediction...................................................................... 10
Table 2: I/O description of controller....................................................................................... 11
Table 3: I/O description of I4M_top.......................................................................................... 12
Table 4: I/O description of I4M_controller.............................................................................

14

Table 5: I/O description of I4M_PE.......................................................................................... 16

Table 6: I/O description of I4M_neigh_mem..........................................................................

18

Table 7: I/O description of I4M_pred_mem............................................................................. 19

Table 8: I/O description of I4M_res_mem.............................................................................

20

Table 9: I/O description of I4M_res_cal................................................................................... 21

Table 10: I/O description of I16M_top...................................................................................

23

Table 11: I/O description of I16M_controller.......................................................................... 24

Table 12: I/O description of I16M_PE....................................................................................... 26
Table 13: I/O description of I16M_neigh_mem...................................................................... 27
Table 14: I/O description of I16M_pred_mem.......................................................................... 28
Table 15: I/O description of I16M_res_mem..........................................................................

28

Table 16: I/O description of I16M_res_cal ............................................................................. 30

DOAN VAN LOC_INTRA_PREDICTION.

I. Introduction
Intra prediction l mt hm c chc nng to ra khi d on PU (Prediction Unit) da trn
kch thc v mu tn hiu ca cc khi bn cnh (neighboring spartially). Kch thc ca khi PU
c th thay i t 4x4 ti kch thc ti a c quy nh trong file .cfg (thng th tt c u m
phng vi kch thc u vo max l 64x64). Kch thc PU thay i ty thuc vo c im, tnh
cht ca nh. Khi mt khi PU c kch thc ln, nhng kt qu d on khng tt( SAD ln) th
n s c chia thnh 4 khi PU c kch thc nh hn. Qu trnh c in ra quy nh vy, cho
n khi khng th chia c na ( kch thc PU l 4x4) th dng li. Sau n s chn khi c
kch thc sao cho c SAD nh nht.Trong H264 c tng cng 9 mode tm kim khc nhau cho
mi PU c xy dng theo hnh vung (4x4 hoc 16x16).Cn H265 HEVC h tr 35 mode trong
gm DC,Planner v 33 mode khc.(tinh toan theo cong thuc cua nguoi viet ra)

II.
Intra prediction block
II.1.

Abstract

Intra prediction gm 3 khi chnh : controller,I4M_top v I16M_top.

Khi Controller iu khin tt c cc tn hiu tnh ton ca 2 khi cn li

II.2.

Top-block Diagram

DOAN VAN LOC_INTRA_PREDICTION.

Figure 1 : H.264 intra prediction block diagram

II.3.

I/O Description
Name

clk
rst
I_seq_start
next_frame
I4M_done
I4M_frame_done
I4M_ready

Dir
I
I
I
I
O
O
I

Description
Clock (sn ln)
Reset ( mc cao)
Bt u khung hnh
Bo chuyn tip khung hnh
Tm kim block 4x4 xong
D on khung hnh 4x4 xong
nh gc sn sng

I4M_rden

tn hiu cho php c ca Luma ti org_mem

I4M_addr

c a ch ca Luma ti org_mem

I4M_org_data

D liu luma t org_mem ra

I16M_rden

Tn hiu cho php c ca chrom ti org_mem

I16M_addr

c a ch ca chm ti org_mem

I16M_org_data

D liu Chroma ti org_mem

rem_intra4x4_predmode

gi tr gi ti b gii m nu mode d on khc nhau

prev_intra4x4_pred_flag

C bo s dng mode d on khc nhau

I4M_mode_vld

Gi tr ca mode d on cho luma

chroma_pred_mode

Gi tr ca mode d on cho luma

DOAN VAN LOC_INTRA_PREDICTION.

I4M_T_req

Yu cu tn hiu t TQ_if

I4M_res_rden

Tn hiu enable cho TQ_if

I4M_res_data

D liu d tha ti ca luma TQ (luma)

I16M_T_req

Yu cu tn hiu t TQ_if

I16M_res_rden

Tn hiu enable enable from TQ_if

I16M_res_data

D liu d tha ti TQ (chroma)

I4M_pred_rden

Tn hiu cho php c ca reconstruct (luma)

I16M_pred_rden

Tn hiu cho php c reconstruct (chroma)

reconY_in_vld

Gi tr Reconstruct Y

reconC_in_vld

Gi tr Reconstruct C

recon_data_in

D liu t reconstruct

I4M_pred_data

Gi tr d on ti reconstruct

I16M_pred_data

Gi tr d on ti reconstruct

Table 1

II.4.

: I/O description of the Intra Prediction

Sub-block Specifications
II.4.1.

Controller

II.4.1.1)

Abstract

Controller iu khin ton hang ca c khi m ha intra

II.4.1.2)

Block Diagram

Figure 2 : Block diagram of controller

10

DOAN VAN LOC_INTRA_PREDICTION.

II.4.1.3)

I/O Description

Name

Dir

Description

clk

Clock (sn ln)

rst

Reset input (mc cao)

I_seq_start

Bt u frame

Intra4x4_done

d on 4x4 xong

chroma_done

d on Chroma xong

mbAddr_x

Ta macroblock hin ti theo X

mbAddr_y

Ta macroblock hin ti theo X

mbA_avail

khi bn tri c th dng

mbB_avail

khi trn c th dng

mbC_avail

khi bn tri pha trn c th dng

frame_done

d on 1 frame xong

Intra4x4_enable

cho php intra 4x4 block

Chroma_enable

cho php choroma block

Table 2 : I/O description of controller

II.4.2.

I4M_top

II.4.2.1)

Abstract

D on cho block P c thc hin theo 5 cch khc nhau : horizontal, vertical, DC, diagonal down left,
diagonal down right .Mode no c SAD nh nht s c chn lm mode d on.

II.4.2.2)

Block Diagram

Figure 3 : Block diagram of I4M_top

II.4.2.3)

I/O Description

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DOAN VAN LOC_INTRA_PREDICTION.

Name

Dir

Description

clk

Clock (sn ln)

rst

Reset input (mc cao)

I4M_enable

Enable signal from controller //

mbA_avail

Left neighbor mb avaiability()

mbB_avail

Up neighbor mb availability

mbC_avail

Upper left neighbor mb availability

mbAddr_x

Current X mb

mbAddr_y

Current Y mb

orgY_ready

Ready signal from org_mem

orgY_rd_en

Read enable to org_mem

orgY_addr

Read address to org_mem

orgY_data_in

Data from org_mem

reconY_data_in

Data from reconstruct

reconY_in_vld

Data valid from reconstruct

Y_T_req

Request signal from TQ_if

I4M_pred_rden

Read enable from reconstruct

I4M_pred_data

Predict data to reconstruct

I4M_res_rden

Residual read enable from TQ

I4M_res_data

Residual read data to TQ

Additional value sent to decoder if predict mode is

rem_intra4x4_predmode

changed
prev_intra4x4_pred_flag

Flag indicates predict mode is changed

I4M_mode_vld

Predict mode valid

I4M_done

Predict completed

Table 3 : I/O description of I4M_top

II.4.3.

I4M_controller

II.4.3.1)

Abstract

This module controls operation of intra prediction for luma components. It gives control signals such as
enable, disable, mode selection,

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II.4.3.2)

Block Diagram

Figure 4 : Intra4x4_controller block diagram

II.4.3.3)
Name

I/O Description
Dir

Description

clk

Clock signal

rst

Reset signal (active high)

in_vld

mbA_avail

Left neigbour macroblock availability

mbB_avail

Up neighbour macroblock availability

mbC_avail

Upper left neighbor mb availability

mbAddr_x

Current mb X

mbAddr_y

Current mb Y

block_rst

reset predict 1 block 4x4

better_mode

Signal indicates that current mode is better than previous

Intra4x4 enable

mode
compare_vld

Signal enables compare between two modes

I4M_T_req

Request signal to TQ_if

13

DOAN VAN LOC_INTRA_PREDICTION.

I4M_T_done

Signal interacts with TQ_if

blkA_avail

Left neigbour block 4x4 availability

blkB_avail

Up neigbour block 4x4 availability

ver_mode

Predicting vertical mode

hor_mode

predicting horizontal mode

dc_mode

predicting DC mode

ddleft_mode

Predicting ddleft mode

ddright_mode

Predicting ddright mode

Start predicting

cnt4x4blk

Current 4x4 block

orgY_ready

Signal from org_mem

orgY_rden

Read enable org_mem

orgY_addr

Read address org_mem

neighY_rden

Read enable from reconstruction

neighY_addr

Read address from reconstruction

reconY_in_vld

rem_intra4x4_predmode

Value sent to decoder if prev_intra4x4_pred_flag = 0

prev_intra4x4_pred_flag

Signal indicates mode prediction is changed or not

I4M_done

Prediction completed

I4M_mode_vld

Mode prediction valid

run_pred

Neigbour availability

Table 4 : I/O description of I4M_controller

II.4.3.4)

Algorithm description

I4M_controller controls all operation of I4M_top. It sets prediction modes by a FSM described in figure 5

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DOAN VAN LOC_INTRA_PREDICTION.

Figure 5 : Prediction mode selection in I4M_controller

II.4.4.

I4M_PE

II.4.4.1)

Abstract

This module calculates prediction value of current 4x4 block.

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DOAN VAN LOC_INTRA_PREDICTION.

II.4.4.2)

Block diagram

Figure 6 : I4M_PE

II.4.4.3)
Name

I/O description
Dir

Description

clk

Clock signal

neigh_in_vld

Neigbour samples from reconstruction in valid

neigh

Data bus

d_reg

Upper left sample bus

mbA_avail

Left neigbour macroblock availability

mbB_avail

Up neighbour macroblock availability

ver_mode

Vertical mode selection

hor_mode

Horizontal mode selection

dc_mode

DC mode selection

ddleft_mode

Diagonal down left mode

ddright_mode

Diagonal down right mode

run_pred

Run prediction

I4M_pred0

Predict value

I4M_pred1

Predict value

I4M_pred2

Predict value

I4M_pred3

Predict value

out_vld

Output valid
Table 5 : I/O description of I4M_PE

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DOAN VAN LOC_INTRA_PREDICTION.

II.4.4.4)

Algorithm description

This mode calculates prediction value by using a shift register.

Figure 7 : I4M_PE architecture

II.4.5.

I4M_neigh_mem

II.4.5.1)

Abstract

This module is a buffer of neighbouring samples of current block 4x4. It contains 1 row of
sample above current macroblock and samples of a column of macroblock at left side of
current macroblock. The I4M_PE block reads samples from this module to calculate
prediction value of current block.

17

DOAN VAN LOC_INTRA_PREDICTION.

II.4.5.2)

Block diagram

Figure 8 : Block diagram of I4M_neigh_mem

II.4.5.3)
Name

I/O description
Dir

Description

clk

Clock signal

mbC_avail

Upper left neighbour macroblock availability

cnt4x4blk

Current block 4x4

ver_mode

Current mode is vertical

ddleft_mode

Current mode is diagonal down left

reconY_in_vld

Reconstruct samples in valid

neighY_rden

Read enable from I4M_controller

neighY_addr

Read address from I4M_controller

data_in

Data in from reconstruct

data_out

Data out to I4M_PE

neigh_out_vld

Data out valid

d_out

Sample [-1,-1]

Table 6 : I/O description of I4M_neigh_mem

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DOAN VAN LOC_INTRA_PREDICTION.

II.4.6.

I4M_pred_mem

II.4.6.1)

Abstract

This module contains predict values resulted from I4M_PE

II.4.6.2)

Block diagram

Figure 9 : Block diagram of I4M_pred_mem

II.4.6.3)
Name

I/O description
Dir

Description

clk

Clock signal

mb_rst

Macroblock reset

better_mode

Better mode signal from I4M_controller

rd_en

Read enable memory

wr_en

Write enable memory

data_in

Data in port

data_out

Data out port

Table 7 : I/O description of I4M_pred_mem

II.4.7.

I4M_res_mem

II.4.7.1)

Abstract

This block contains residual values which are calculated by I4M_res_cal.

19

DOAN VAN LOC_INTRA_PREDICTION.

II.4.7.2)

Block diagram

Figure 10 : Block diagram of I4M_res_mem

II.4.7.3)
Name

I/O description
Dir

Description

clk

Clock signal

mb_rst

Macroblock reset

better_mode

Better mode signal indicates current mode is better than

previous one

rd_en

Read enable memory

wr_en

Write enable memory

data_in

Data in port

data_out

Data out port

I4M_T_done

Read 1 mb done

Table 8 : I/O description of I4M_res_mem

II.4.8.

I4M_res_cal

II.4.8.1)

Abstract

This module calcutes the differences between the original block 4x4 and the predicted
bock. It also compare the SAD (sum of absolute differences) of all prediction modes. The
mode which has minimum SAD is chosen and sent to next block. Residual values are
temporarily stored at I4M_res_mem before sent to TQ block.

20

DOAN VAN LOC_INTRA_PREDICTION.

II.4.8.2)

Block diagram

Figure 11 : Block diagram of I4M_res_cal

II.4.8.3)
Name

I/O description
Dir

Description

clk

Clock signal

mb_rst

Macroblock reset

mp_mode_vld

Mode valid

org

Orginal samples

pred_vld

Prediction valid for read

pred0

Predicted value

pred1

Predicted value

pred2

Predicted value

pred3

Predicted value

res0

Residual value

res1

Residual value

res2

Residual value

res3

Residual value

res_out_vld

Residual valid

compare_vld

Compare valid enough data for compare 2 modes

better_mode

Signal indicates current mode is better than previous one

Table 9 : I/O description of I4M_res_cal

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DOAN VAN LOC_INTRA_PREDICTION.

II.4.9.

I16M_top

II.4.9.1)

Abstract

I16M_top is the top level of intra prediction for chroma component. There are 4 modes: DC, vertical,
horizontal and Plane for each 8x8 block Cb and Cr. The prediction mode of Cb component and Cr
component are always the same.

II.4.9.2)

Block Diagram

Figure 12 : Block diagram of I16M_top

II.4.9.3)
Name

I/O Description
Dir

Description

Clk

Clock (rising edge)

Rst

Reset input (Active high)

I16M_enable

Enable signal from controller

mbA_avail

Left neighbor macroblock availability

mbB_avail

Up neighbor macroblock availability

mbAddr_x

Current X coordinate macroblock

mbAddr_y

Current Y coordinate macroblock

orgC_rd_en

Read enable to org_mem

orgC_addr

Read address to org_mem

orgC_data_in

Read data from org_mem

reconC_data_in

Neighbor data from reconstruct

reconC_in_vld

Neighbor data in valid

Cbr_T_req

Request signal to TQ

I16M_pred_rden

Predict read enable from recontruct

I16M_pred_data

Predict data to reconstruct

22

DOAN VAN LOC_INTRA_PREDICTION.

I16M_res_rden

Residual read enable from TQ

I16M_res_data

Residual read data to TQ

Cbr_bestmode

Best mode selected

I16M_done

Chroma prediction done

Table 10 : I/O description of I16M_top

II.4.10.

I16M_controller

II.4.10.1)

Abstract

I16M_controller controls operation of intra prediction for chroma block. It gives set of
control signals such as enable, disable, valid signal, It also gives addresses and read
enable, write enable for reading/writing memory.

II.4.10.2)

Block diagram

Figure 13 : I16M_controller

II.4.10.3)
Name

I/O description
Dir

Description

clk

Clock signal

rst

Reset signal (active high)

in_vld

Enable signal
23

DOAN VAN LOC_INTRA_PREDICTION.

mbA_avail

Left neigbour mb availability

mbB_avail

Up neigbour mb availability

mbAddr_x

Current mb (X coordinate)

mbAddr_y

Current mb (Y coordinate)

Cb_vld

Cb component valid

Cr_vld

Cr component valid

sel_dc

Predicting DC mode

sel_ver

Predicting vertical mode

sel_hor

Predicting horizontal mode

sel_plane

Predicting plane mode

run_pred

Run predict

cnt4x4blk

Current 4x4 block

neighC_addr

Read neighbour address from reconstruction

neighC_rden

Read enable from reconstruction

reconC_in_vld

Reconstruction samples in valid

better_mode

Signal indicates current mode is better than previous mode

compare_vld

Signal indicates valid state for compare mode

cmp_rst

Compare reset start compare

Cbr_T_req

Signal interacts with TQ_if

Cbr_T_done

Signal interacts with TQ_if

orgC_rd_en

Read enable original memory

orgC_addr

Read address original memory

Cbr_bestmode

Best mode selected

I16M_done

Predict completed

Table 11 : I/O description of I16M_controller

II.4.11.

I16M_PE

II.4.11.1)

Abstract

This module performs calculating prediction value of a block 8x8 Cb and a block 8x8 Cr.
There are 4 modes: DC, vertical, horizontal and plane for each block 8x8 of chroma
component. The control signals is given from I16M_controller. The neigbour samples are
read from I16M_neigh_mem.

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DOAN VAN LOC_INTRA_PREDICTION.

II.4.11.2)

Block diagram

Figure 14 : I16M_PE

II.4.11.3)
Name

I/O description
Dir

Description

clk

Clock signal

rst

Reset signal (active high)

neigh_in_vld

Neighbour samples are valid for reading

neigh

Neigbour data

d_reg

Sample at [-1,-1] location

cnt4x4blk

Current 4x4 block

mbA_avail

Left neighbour mb is available for predicting

mbB_avail

Up neighbour mb is available for predicting

Cb_vld

Cb component in valid

Cr_vld

Cr component in valid

sel_chrom_ver

Current mode is vertical

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DOAN VAN LOC_INTRA_PREDICTION.

sel_chrom_hor

Current mode is horizontal

sel_chrom_dc

Current mode is DC

sel_chrom_plane

Current mode is plane

run_pred

Start predict

I16M_pred0

Predict result

I16M_pred1

Predict result

I16M_pred2

Predict result

I16M_pred3

Predict result

out_vld

Output valid

Table 12 : I/O description of I16M_PE

II.4.12.

I16M_neigh_mem

II.4.12.1)

Abstract

This module is a buffer of neighbour memory of chroma component.

II.4.12.2)

Block diagram

Figure 15 : Block diagram of I16M_neigh_mem

II.4.12.3)
Name

I/O description
Dir

Description

clk

Clock signal

wr_en

Write enable memory (reconstruct in valid)

rd_en

Read enable memory (from I16M_controller)

Cb_vld

Cb valid
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DOAN VAN LOC_INTRA_PREDICTION.

sel_plane

Plane mode

sel_dc

DC mode

mbA_avail

Left neigbour mb avail

mbB_avail

Up neighbour mb avail

addr

Read address

data_in

Data in from reconstruction

data_out

Data out to I16M_PE

neigh_out_vld

Data out valid

d_reg

Sample [-1,-1]

Table 13 : I/O description of I16M_neigh_mem

II.4.13.

I16M_pred_mem

II.4.13.1)

Abstract

This module is a buffer of predicted samples. Predicted samples are calculated by

I16M_PE and temporarily stored by this module.

II.4.13.2)

Block diagram

Figure 16 : Block diagram of I16M_pred_mem

II.4.13.3)
Name

I/O description
Dir

Description

clk

Clock signal

mb_rst

Macroblock reset

better_mode

Better mode signal from I4M_controller

rd_en

Read enable memory

wr_en

Write enable memory

data_in

Data in port
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DOAN VAN LOC_INTRA_PREDICTION.

data_out

Data out port

Table 14: I/O description of I16M_pred_mem

II.4.14.

I16M_res_mem

II.4.14.1)

Abstract

This module stores residual values (differences between original macroblock and
predicted macroblock). Residual values are calculated by I16M_res_mem.

II.4.14.2)

Block diagram

Figure 17 : Block diagram of I16M_res_mem

II.4.14.3)
Name

I/O description
Dir

Description

clk

Clock signal

mb_rst

Macroblock reset

better_mode

Better mode signal indicates current mode is better than

previous one

rd_en

Read enable memory

wr_en

Write enable memory

data_in

Data in port

data_out

Data out port

Cbr_T_done

Read 1 mb done

Table 15 : I/O description of I16M_res_mem

II.4.15.

I16M_res_cal

II.4.15.1)

Abstract

This module calcutes the differences between the original block 8x8 of chroma component
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DOAN VAN LOC_INTRA_PREDICTION.

Cb and Cr and the predicted bock. It also compare the SAD (sum of absolute differences)
of all prediction modes. The mode which has minimum SAD is chosen and sent to next
block. Residual values are temporarily stored at I4M_res_mem before sent to TQ block.

II.4.15.2)

Block diagram

Figure 18 : Block diagram of I16M_res_cal

II.4.15.3)
Name

I/O description
Dir

Description

clk

Clock signal

mb_rst

Reset macroblock

in_vld

Data in valid

sel_chrom_dc

DC mode

sel_chrom_hor

Horizontal mode

pred0

Predicted value

pred1

Predicted value

pred2

Predicted value

pred3

Predicted value

org0

Original value

org1

Original value

org2

Original value

org3

Original value

res

Residual value

cmp_vld

Compare valid-enough data for comparing 2 modes

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DOAN VAN LOC_INTRA_PREDICTION.

better_mode

Signal indicates current mode is better than previous one

Table 16: I/O description of I16M_res_cal

30