Strained Silicon Technology

:
Strained silicon is a layer of silicon in which the silicon atoms are stretched beyond their normal interatomic distance. This can be accomplished by putting the layer of silicon over a substrate of silicon germanium (SiGe). As the atoms in the silicon layer align with the atoms of the underlying silicon germanium layer (which are arranged a little farther apart, with respect to those of a bulk silicon crystal), the links between the silicon atoms become stretched - thereby leading to strained silicon. Moving these silicon atoms farther apart reduces the atomic forces that interfere with the movement of electrons through the transistors and thus better mobility, resulting in better chip performance and lower energy consumption. These electrons can move 70% faster allowing strained silicon transistors to switch 35% faster.

The image on the left shows electrons flowing through a current silicon chip. On the right is an image of electrons flowing through "strained silicon". The electrons flow up to 70 percent faster through strained silicon because there is less resistance, resulting in chip speed increases of up to 35 percent. IBM scientists are able to strain, or stretch the silicon by taking advantage of the natural tendency of atoms inside of different crystals to align with one another. When silicon is deposited on top of another material which has atoms spaced farther apart -- in this case, silicon germanium -- the atoms in silicon stretch to line up with the atoms beneath.

Orbital orientation The speed of current flow depends on the crystal structure of silicon. Inside the silicon lattice, the electrons around each atom form patterns of energy states called orbitals. These states merge to form a continuous band that allows electrons and positively charged "holes" to move through the lattice. The orientation of the orbitals is important. Each atom has six lobe-shaped orbitals: two in the direction of electron flow and four that are perpendicular to it (see graphic). In ordinary silicon, all six orbitals have the same energy so there is no preferred direction of flow. But stretching the lattice decreases the energy of the two orbitals in that direction, letting electrons flow more easily along the aligned orbitals. Similarly, squeezing the lattice lets positive charges to flow more easily. Turning this to practical advantage is difficult, though. Transistors contain regions of silicon that are doped with a material such as phosphorus to create an excess of electrons in the conduction band - "n-doped" silicon - and regions that are doped with boron, which adds positively-charged holes to form "p-doped" silicon. Intel's trick is to stretch the n-doped areas while compressing the p-doped ones. Carved trenches Bohr says the company compresses p-doped regions by carving trenches along their opposite ends and filling them with silicon germanium, which has a larger lattice size than silicon alone and so compresses the regions nearby. This improves hole conduction by 25 per cent. To stretch the silicon lattice, Intel deposits a film of silicon nitride over the whole transistor at high temperature. Because silicon nitride contracts less than silicon as it cools, it locks the silicon lattice beneath it in place with a wider spacing than it would normally adopt. This improves electron conduction by 10 per cent. Intel says the approach gives it a significant speed advantage over its competitors and is using the technique in its latest generation of chips, whose individual features are as small as 90 nanometres. Intel claims its technique boosts chip performance by up to 20 per cent compared with ordinary chips of the same size. "Intel's performance is pretty impressive," says Judy Hoyt, a physicist at the Massachusetts Institute of Technology, who pioneered the strained-silicon idea in 1992. She adds that other strained-silicon techniques are likely to emerge soon. IBM says it is now planning to introduce strained silicon in its 90-nanometre chips.