1

CHAPTER 1
COMPANY-PROFILE
Associated Electronics Research Foundation is governed by section 25 of The Companies
Act 1956, association not for profit. In consonance with the object of this memorandum, the
company is organized into “Key Functional Areas” in pursuit of extending the benefits of
scientific knowledge through development of projects, tools and services for the growth of
industry as well as to promote consumerism. AERF is having full fledged Research
laboratories in a built up area of around 4300sq.mt. on 16573sq.mt. of land. The principal
activities revolve around development of Projects which are undertaken on behalf of the
industry. It will not be out of place to mention that AERF has monopoly in development of
Jigs and Testers in around NCR. Some of these have been well acknowledged by DSIR and
Indian Army. For the development activities the Foundation is also closely associated with
Academia. AERF is recognized by DSIR Government of India, for its development activities
under SIRO Scheme.
Similarly the Testing and Calibration laboratories of AERF are recognized by the
Government of India through NABL, (National Accreditation Board for Testing and
Calibration Laboratories), Department of Science and Technology, for Testing and
Calibration of Electrical and Electronic items. These facilities are utilized by the industry and
also other development institutes, in and around NCR, for Type Approval, and Defect
Investigation.
Our activities also encompass training of undergraduate engineering students from rural areas
or small towns or colleges who do not have full fledged laboratories. The aim is to impart
practical knowledge beyond the realms of academic books and prepare students to be useful
for the industrial expectations after graduation. For this very nominal fee is charged just to
cover the cost of components.






2

CHAPTER 2
VLSI

2.1 Introduction
From a modest beginning in early 1984 at Gateway Design Automation, the Verilog
hardware description language has become an industry standard of extensive use in the
design of integrated circuit chips and digital systems. Verilog came into being as a
proprietary language supported by a simulation environment provided a powerful and
uniform method to express digital designs as well as tests that were meant to verify such
designs.
There were three key factors that drove the acceptance and dominance of Verilog in the
marketplace. First, the introduction of the programming language interface(PLI) permitted
users of Verilog to literally extend and customize the simulation environment. Since then,
users have exploited the PLI and their success at adapting Verilog to their environment has
been a real winner for Verilog. The second key factor which drove Verilog‟s dominance
came from Gateways paying close partnership with Motorola, National, and UTMC in the
1987-1989 time frame. The realization that the vast majority of logic simulation was being
done by designers of ASIC chips drove this effort. With ASIC foundries blessing the use of
Verilog and even adopting it as their internal sign off simulator, the industry acceptance of
Verilog was introduction of Verilog based synthesis technology by synopsis in 1987.
Gateway licensed its proprietary Verilog language to Synopsis for this purpose. The
combination of the simulation and synthesis technologies served to make Verilog the
language of choice for the hardware designers.
The arrival of the VHDL (VHSIC Hardware Description Language), along with the powerful
alignment of the remaining EDA vendors driving VHDL as an IEEE standard, led to the
placement of Verilog in the public domain. Verilog was inducted as the IEEE 1364 standard
in 1995. Since 1995, many enhancements were made to Verilog HDL based on requests from
Verilog users. These changes were incorporated into the latest IEEE 1364-2001 Verilog
standard. Today, Verilog has become the languages of choice for digital design and is the
basis for synthesis, verification, and route technologies.
VLSI: -Verilog HDL originated in 1983 at Gateway Design Automation.
Digital Circuits could be described at a Register Transfer Level by use of a HDL (Hardware
Descriptive Language).
3

VHDL: - VHSIC HDL (Very High Speed Integrated Circuit Hardware Descriptive
Language).
.
2.2 HDL: -HDL is also begin to be used all system level design. HDL where used for
simulation of system boards interconnected buses, FPGA (Field Programmable Gate Array)
& PAL (Programmable Array Logic). A common approach is to design each IC chip using
system functionality by a simulation.
Three main things which should be kept in mind for VLSI designs are:-
Timing
Area
Power
HDL has many advantages compare to traditional schematic best design:-
Designs can be described at a very abstract level by use of HDL.
Designer can write their RTL description without choosing a specific fabrication technology.
If a new technology emerges. Designers do not need to redesign there circuit. They simply
input the RTL description to the logic synthesis tool & create a new gate level net list using
the new fabrication technology.
By describing design in HDL‟s functional verification of the design can be done early in the
design cycle since designer work at the RTL level. They can optimise and modify the RTL
description until it meets the desired functionality.

2.3 System Specifications:-
It is a high level representation of the system.
Factors considered including performance, functionality & physical dimensions.
In results are specifications for the size, speed, power & functionality of VLSI system.
Architectural Design:-
Basic architecture of the system is designed in the step includes decision as RISC(Reduced
Instruction Set Computer) vs. CISC(Complex Instruction Set Computer) no of ALU, floating
point units, numbers & structures of pipelining & size of cache among others. For example
for mobile computing such as laptop, computer, low power consumption is a critical factor
early estimates based on architecture can be used to determine if the design is likely to meet
its power specification.


4

SYSTEM SPECIFICATION

ARCHITECTURAL DESIGN

FUNCTIONAL DESIGN

LOGIC DESIGN

CIRCUIT DESIGN

PHYSICAL DESIGN

FABRICATION

PACKAGING & TESTING

Fig. 2.1 VLSI design flowchart.


2.3.1 Functional Design:-
In this step main functional unit of the system are identified. It also identified the interconnect
requirements between the units. The area, power & other parameters of each units are
estimated. For example it may specify that a multiplication is required but exactly in which
mode such multiplication may be executed is not specified.
2.3.2 Logic Design:-
Control Flow
Word Width
Register Allocation
Arithmetic Operations &
Logic Operations
2.3.3 Circuit Design: -
Boolean expression is converted into circuit representation by taking into consideration the
speed, power requirements of the original design.
5

2.3.4 Physical Design:-
In this state the circuit representation or net list is converted into a geometric representation
of a circuit is called „lay out‟.
Layout is created by converting each logic components into a geometric representation. Most
of the layout of a high performance design such as microprocessor may be done using manual
design while many low to medium performance design which needs faster time to market
may be done automatically
2.3.5 Fabrication: -
After layout & verification the design is ready for fabrication since layout is typically sent to
fabrication on a tape the event of release of data is called tape out.
Layout data is converted to photolithographic mask one for each layer mask identify species
on the wafer certain material need to be deposited, diffused or even removed.
2.3.6 Packaging testing & debugging:-
Finally the wafer is fabricated & dice into the individual chip in a fabrication facility. Each
chip is then packaged & tested to ensure that it meets all the design specifications & that it
function properly.
Chips used in printed circuit board are packaged dual in line packaging , pin grid array(PGA),
ball grid array(BGA), quad flat package(QFP).
















6


CHAPTER 3
VERILOG HDL

3.1 Modelling Techniques:-
Module: - A module is a basic building block in a Verilog. A module provides the necessary
functionality to the higher level block through its port interface but hide internal
implementation.
3.1.1 Behavioural Modelling: -
This is the highest level of abstraction provided by Verilog HDL. A module can be
implemented in terms of the desired design algorithm without concerned of the hardware
implementation details. It does not have any need of hardware. Designing at this level is very
similar to C programming.
3.1.2 Data Flow Modelling: -
At this level the module is designed by specifying the data flow. The designer is aware of
how the data flow between hardware registers & how the data is processed in the design.
3.1.3 Gate Level Modelling: -
The module is implemented in terms of logic gates & interconnection between these gates
Three types of keywords for defining ports:-
Input
Output
In out
Data types are of two types:-
NET data type (keyword is wire) & (default value is Z(high impedance))
REG data type (keyword is reg) & (default value is X (0 or 1))

3.2 NET: -
NET represents connection between hardware & software elements. NET‟s are declared
primarily with the keyword wire. NET‟s are 1 bit value by default unless they are declared
explicitly as vector. The term wire & net are often used interchangeably. The default value of
NET is Z.



7

3.3 REG: -
The registers represent data storage elements. Registers retain value until another value is
placed onto them.
Do not confuse the term register in Verilog with hardware register built from edge triggered
flip flop in real circuits.
In Verilog the term register merely means a variable that can hold a value. Unlike *a NET
register does not need a driver.
Verilog REG do not need a clock as hardware register need.

3.4 AND Gate
3.4.1 AND Programming - Using Gate Level Modelling in Verilog
module and1(y,a,b);
output y;
input a,b;
and A1(y,a,b);
endmodule
3.4.2 AND test bench - Using Gate Level Modelling
module andtb(y,a,b);
wire y;
reg a,b;
and1 B1(y,a,b);
initial
begin
a=0 ; b=0;
#10
a=0 ; b=1;
#10
a=1 ; b=0;
#10
a=1 ; b=1;
end
endmodule


8















Fig. 3.1 AND Wave form Using Gate Level Modelling.



















9

CHAPTER 4
PCB DESIGNING

4.1 Introduction
Protel 99 SE
Protel 99 SE is designed as a "client - server” application, i.e. the main application program
of Protel 99 SE, called Client99.exe, provides the basic infrastructure and user interface for
Protel 99 SE, while specific services, such as editing a schematic or PCB are provided by a
series of plug-in "servers".
When you click on the Protel 99 SE icon in the Windows Start menu, Client99.exe is the
application that is started. You do not then need to launch a schematic editor, PCB editor, etc.
as separated programs - all your Protel EDA tools are available from within the Protel 99 SE
desktop.
The use of a "client – server" architecture for Protel 99 SE means that you can easily expand
the capabilities of the software. As well as the servers supplied with Protel 99 SE, various
add-on servers are available from both Protel and numerous third-party vendors. To use
Protel 99 SE it is not necessary to understand how the client – server architecture works,
however a basic knowledge of servers will help you get the most from Protel 99SE

4.2 Creating a new DDB Using the Design Explorer
To create a new Design Database select File» New Design from the menus. The New
Design Database dialog will pop up. Complete the following steps:
1. Select the Storage Type
2. Enter the Database name
3. Set the location as required
If you would like to password-protect the Design Database now, click on the Password tab
and enter the password. This password is assigned to the default user name Admin. You can
password-protect a Design Database at any time, by going to the Members folder and
entering a password for the Admin member. To unprotect a Database remove the password
from the Admin member. Note that you can only password-protect a design database whose
storage type is MS Access database.
Once the new design database is created an icon for it will appear in the navigation tree of the
Design Explorer, and its corresponding design window will open in the work area.

10

4.3 Working with SCH. Documents
A schematic is a diagrammatic representation of an electronic circuit, and schematic capture
is the process of capturing a design as a schematic in a computer-aided design environment.
A computer-based schematic is more than a simple drawing of the circuit. It also contains
information about the connectivity of the circuit and the parts that make up the circuit.
In Protel, the basic workspace for capturing a schematic is called a schematic sheet.
Electrical, drawing and directive objects are placed on a schematic sheet to design the circuit
and produce working schematic drawings. A complete circuit design can use just a single
sheet, or it can comprise a number of electrically linked sheets. Protel allows you to create
complex hierarchical and modular designs by linking any number of sheets to form a
complete project.

4.4 Open Printed Circuit Board File
To begin the PCB design phase of a project, create a new PCB document in your design
database (see the Adding a new document or folder to a design topic in the Links section
below).
Before bringing design information from the schematic, you should first create the
mechanical and electrical board outline for your board, and configure the layer stack. The
mechanical outline defines the physical shape and size of the board, and also includes items
such as dimension detail, photo tool targets and other company and fabrication specific
information. This information is usually placed on the four Mechanical layers.
Tile electrical board outline defines the routing and component placement limits of the board.
This is done by defining an outline of the board on the Keep Out layer. The Keep Out layer is
a special layer that allows you to define "legitimate" placement and routing areas in the PCB
workspace. Generally you would define an area which is the same as the physical board
outline. All signal-layer objects and routing would then be confined within this area. You
could also define areas on the Keep Out layer within the board outline to act as "no go" areas
for placement and routing.
The layer stack defines what signal and plane layers are available. Part of the layer stack
definition process is to define the drill-pairs.
Protel 99 SE includes a powerful Board Wizard that guides you through the complete process
of creating a new PCB document and board definition. The Wizard includes a number of
predefined board templates, and allows you to create your own templates.

11

4.5 PCB Definition Topics
4.5.1 Open Schematic File
A schematic is a diagrammatic representation of an electronic circuit, and schematic capture
is the process of capturing a design as a schematic in a computer-aided design environment.
A computer-based schematic is more than a simple drawing of the circuit. It also contains
information about the connectivity of the circuit and the parts that make up the circuit.
In Protel, the basic workspace for capturing a schematic is called a schematic sheet.
Electrical, drawing and directive objects are placed on a schematic sheet to design the circuit
and produce working schematic drawings. A complete circuit design can use just a single
sheet, or it can comprise an number of electrically linked sheets. Protel allows you to create
complex hierarchical and modular designs by linking any number of sheets to form a
complete project.
4.5.2 Creating a new schematic Symbols
To create a new schematic component; from a schematic library document select Tools» New
Component from the menus. A new component will be created in the library and you
will be presented with an empty component sheet. Rename the component by selecting Tools
» Rename Component from the menus.
Initially the schematic component sheet is shown fully zoomed out. The origin for the sheet is
marked by the intersection of the crossed guide lines. Before drawing your component, you
should zoom in [shortcut Page Up] until the grid becomes visible. You should also draw your
component based around the component sheet origin. Select Edit » Jump » Origin [shortcut
JO] to centre the origin in the workspace.
To define your new component, complete the following steps:
1. Define the component body using the various drawing objects available from the Place
menu, or from the SchLib Drawing Tools toolbar. These tools provide the same drawing
object available in schematic sheets.
2. Place the component pins by selecting Place» Pins from the menu [shortcut P P]. When
you enter Pin placement mode, the pin will appear floating on the cursor. Note that you
“hold" the pin by its non-electrical end, which goes against the component body. Press
SPACEBAR to rotate the pin while it is floating on the cursor. Press the TAB key during
placement to edit the pin's properties before placing it.
3. If you are creating a multipart component, select Tools» New Part to add another part to
the component and repeat the above steps to create the symbols for all parts in the
component.
12

4. Set the component's properties by selecting Tools» Description from the menus. This
opens the Component Text Fields dialog in which you set the component's default designator
and PCB footprint, a description of the component, and set up the various part
fields and library fields that are displayed when the component properties are edited from a
schematic sheet.
5. Save the component sheet to save the component in the library.
Note: The IEEE symbols can be resized during placement. Press the „+‟ and „-‟ keys to
enlarge and shrink the symbols as you place them.
4.5.3 Creating a new PCB component
To create a new component, you must first open the library that will hold the component (see
Opening a PCB library for editing in the Links section below)
Once the desired PCB library file is open and active, select the Tools» New Component menu
item. The Component Wizard will automatically start to guide you through the process of
building a new PCB component.
If you do not want to use the Component Wizard, press Cancel to manually create a
component. You will be presented with an empty component footprint workspace. Select
Tools » Rename Component to give your new component a name (255 characters maximum).
4.5.4 Placing design objects in documents
The method for placing objects is similar for both schematic and PCB documents. The basic
placement steps are outlined below. For help on placing specific objects, use the See also...
link at the bottom of the page
1. Select the object that you want to place - You can do this by selecting an object from the
Place menu or by clicking on one of buttons from the various placement toolbars. For
components and footprints, you can also click the Place button in the Panel when browsing
libraries.
2. When an object is selected for placement, the cursor will change to a crosshair, indicating
that you are in editing mode, and, if relevant, the object will appear "floating" on the cursor.
3. Press the TAB key to edit the properties of the object before placing it. This will open the
property dialog for the particular object, allowing you to change various options. Once you
have finished setting the properties, close the dialog to return to placement mode.
4. Position the cursor and left-click or press ENTER to place the object. For complex objects
such as wires, tracks, polygons, etc. you must continue the position and click procedure to
place all vertices of the object. Note: If auto panning is active, you can move around the
13

document by simply moving the cursor past the edge of the editing window in the direction
that you wish to go.
5. After placing an object you will remain in placement mode (indicated by the crosshair
cursor), allowing you to place another object of the same type immediately.
6. To end placement mode, right-click or press the ESC key (in some cases, such as placing a
polygon, you may need to do this twice; once to finish placing the object and once to exit
placement mode). When you exit placement mode, the cursor will return its default shape.
4.5.5 Preparing a schematic for making a PCB layout : -
In Protel 99 SE, creating a PCB layout from a schematic is a fully automated process handled
by Protel's design synchronizer. The synchronizer allows you to initially transfer the design
to a PCB, maintaining full connectivity, and subsequently update design changes from the
schematic to the PCB and vice versa.
Before you can use Protel's synchronization features, you must create a PCB document based
on your schematic design. To do this, create a new PCB document in the design database,
draw the board outline and then run the design synchronizer to transfer the schematic
information to the PCB. For information on creating a new PCB document, see the topic
Adding a new document or folder to a design in the Links section below. For information on
creating the board outline, see the topic creating a PCB outline in the Links section below.
For information on using the design synchronizer, see the topic Synchronizing schematic &
PCB documents in the Links section below.
Note: It is advisable to perform an ERC on your schematic and fix and errors before starting
the PCB layout process.
The following topics detail the steps necessary to prepare a schematic for transfer to a PCB
layout:
Reassigning part designators in a schematic design
Checking schematic parts for missing PCB footprints
Including PCB layout information in a schematic
4.5.6 Component Footprint (PCB design object) : -
Toolbar: Placement Tools-
Menu: Place» Component [P C]
Valid layers:- Top or Bottom signal layers Can be connected to a net?: No (Component pads,
however, can be assigned to net)
14

Description: A component footprint is the representation of a physical device on a PCB. A
footprint may contain pads for connecting to the pins of a device, a physical outline of the
package, device mounting features, etc.
To place: When you enter component placement mode the Place Component dialog will
open. In this dialog, type the name or browse for a component footprint from a loaded PCB
library. Set the appropriate designator and any comment text, then click OK to close the
dialog. You will return to the PCB document and an outline of the component will be
"floating" on the cursor. Position the component and left-click or press ENTER to place it.
The Place Component dialog will re-open, allowing you place another component. Press
Cancel to exit component placement mode.
Graphical editing:- A component footprint cannot be focused and graphically edited directly.
To edit the graphical attributes of a component you must open it the relevant PCB library.
Notes: Generally when you start a new PCB you will load information from a schematic. This
process is known as synchronization. When the PCB is synchronized with the schematic
project, the necessary PCB footprints are placed on the board ready for positioning, and the
connectivity of the schematic is preserved on the PCB. Component footprints can be
converted to a set of primitive objects by selecting Tools» Convert» Explode Component to
Free Primitives from the menus. Once a component is exploded it can no longer be
manipulated as a group object.

4.6 Using PCB design rules
You design your PCB by placing components, tracks, vias and other design objects. These
objects must be placed in the workspace with regard to each other. Components must not
overlap, nets must not short, power nets must be kept clear of signal nets, etc.
To allow you to remain focused on the task of designing the board, Protel 99 SE can monitor
these design requirements for you. You instruct the PCB editor of your requirements by
setting up a series of design rules. These design rules are monitored as you layout the PCB.
As soon as an object is placed in violation of a design rule it is highlighted. Also, during the
board verification process you can run the integrated Design Rule Checker, which will
generate a report of any design rule violations in you PCB.
Protel allows a wide range of design rules to be defined for a PCB. These include clearances,
object geometry, parallelism, impedance control, routing priority and topology, placement
rules, and signal integrity rules. Each rule has a Rule Scope that defines how it is applied. The
15

scope allows you to apply a rule to objects, nets, net classes, components, component classes,
layers, regions, through to the whole board.
Design rules are set up and configured in the Design Rules dialog box (from the PCB
document select Design » Rules).

Fig. 4.1 +5V Power Supply Circuit Diagram.



Fig. 4.2 +5V Power supply PCB design.
1 2 3 4
A
B
C
D
4 3 2 1
D
C
B
A
Ti t l e
Number Re vi si on Si ze
A4
Da t e: 9-Ma y-2014 She et of
Fi l e: D: \ YOGITA DITM. DDB Dra wn By:
T1
TRANSFORMER
1 2
D1
1N4G07
1 2
D2
1N4G07
1 2
D3
1N4G07
1 2
D4
1N4G07
C1
1
0
0
0
U
F
3
5
V
C2
104PF
IP
1
G
N
D
2
OP
3
U1
IC7805
C
3
2
2
0
U
F
1
6
V
C4
104PF
R1
1K
L1
LED
+5V
WIRE
1
W1
WIRE
WIRE
1
W2
WIRE
WIRE
1
W3
WIRE
WIRE
1
W4
WIRE
+5 V POWER SUPPLY
VIKRAM SINGH
16



Fig. 4.3 PCB Circuit Design using bus.




Fig. 4.4 Bus PCB Design.

1 2 3 4
A
B
C
D
4 3 2 1
D
C
B
A
Ti t l e
Number Re vi si on Si ze
A4
Da t e: 9-Ma y-2014 She et of
Fi l e: D: \ YOGITA DITM. DDB Dra wn By:
1
2
3
4 5
6
7
8
U1
NE555
1
2
3
4 5
6
7
8
U2
NE555
A1
A2
A3
A4 A1
A2
A3
A4 A1
A2
A3
A4
A1
A2
A3
A4
CIRCUIT USING BUS
VIKRAM SINGH
17



Fig. 4.5 Traffic light controller circuit.




Fig. 4.6 Traffic Light controller PCB.

1 2 3 4
A
B
C
D
4 3 2 1
D
C
B
A
Ti t l e
Number Re vi si on Si ze
A4
Da t e: 9-Ma y-2014 She et of
Fi l e: D: \ YOGITA DITM. DDB Dra wn By:
R1
22K
R2
22K
C2
CAP
R3
10K
D1
1N4148
D2
1N4148
D3
1N4148
D4
1N4148
D5
1N4148
D6
1N4148
R4
1K
1 5 6 9
1
1
1
0
12
8
1
3
1
5
1
6
14
U2
IC 4017
R5
1K
R6
1K
D7
DIODE
D8
DIODE
D9
DIODE
R7
RES
C3
CAP
W1
WIRE
1
2
3
4
5
6
7
8
U1
U1 555
W2
WIRE
W3
WIRE
W4
WIRE
W5
WIRE
WIRE
1
W6
WIRE
WIRE
1
W7
WIRE
9
-
1
2
V
C1
47uF
TRAFFIC LIGHT CONTROLLER CKT DIAGRAM
VIKRAM SINGH
18



Fig. 4.7 PCB Design using hierarchy circuit.



Fig. 4.8 PCB design Hierarchy circuit.

1 2 3 4 5 6
A
B
C
D
6 5 4 3 2 1
D
C
B
A
Ti t l e
Number Re vi si on Si ze
B
Da t e: 9-Ma y-2014 She et of
Fi l e: D: \ VIKRAMSHOBHIT. ddb Dra wn By:
Na me
SHEETV1
Na me
SHEETV2
Na me
SHEETV3
CIRCUIT DIAGR AM USING HIERARCHY
VIKRAM SINGH
19



Fig. 4.9 Sheet 1
st
+5V power supply.




Fig. 4.10 Sheet 2
nd
using bus.

1 2 3 4
A
B
C
D
4 3 2 1
D
C
B
A
Ti t l e
Number Re vi si on Si ze
A4
Da t e: 9-Ma y-2014 She et of
Fi l e: D: \ VIKRAMSHOB HIT. ddb Dra wn By:
T1
TRANSFORMER
1 2
D1
1N4G07
1 2
D2
1N4G07
1 2
D3
1N4G07
1 2
D4
1N4G07
C1
1
0
0
0
U
F
3
5
V
C2
104PF
IP
1
G
N
D
2
OP
3
U1
IC7805
C
3
2
2
0
U
F
1
6
V
C4
104PF
R1
1K
L1
LED
+5V
WIRE
1
W1
WIRE
WIRE
1
W2
WIRE
WIRE
1
W3
WIRE
WIRE
1
W4
WIRE
VIKRAM
+5V POWER SUPPLY
1 2 3 4
A
B
C
D
4 3 2 1
D
C
B
A
Ti t l e
Number Re vi si on Si ze
A4
Da t e: 9-Ma y-2014 She et of
Fi l e: D: \ VIKRAMSHOB HIT. ddb Dra wn By:
1
2
3
4 5
6
7
8
U2
NE555
1
2
3
4 5
6
7
8
U3
NE555
A1
A2
A3
A4 A1
A2
A3
A4 A1
A2
A3
A4
A1
A2
A3
A4
BUS CIRCUIT
VIKR AM SINGH
20



Fig. 4.11 Sheet 3
rd
Circuit Diagram.

















1 2 3 4
A
B
C
D
4 3 2 1
D
C
B
A
Ti t l e
Number Re vi si on Si ze
A4
Da t e: 9-Ma y-2014 She et of
Fi l e: D: \ VIKRAMSHOB HIT. ddb Dra wn By:
1
2
3
4 5
6
7
8
U4
NE555
R2
RES1
C5
CAP
D5
DIODE
B
2
C
3
E
1
Q1
NPN_1
R3
RES1
VIKR AM SINGH
21

CHAPTER 5
C LANGUAGE

5.1 Programming In “C” Language
The C programming language (often, just "C") is a general-purpose, procedural, imperative
computer programming language developed in the early 1970s by Dennis Ritchie for use on
the Unix operating system. It has since spread to many other operating systems, and is now
one of the most widely used programming languages. C has also had a great influence on
most other popular languages, especially C++ which was originally designed as an
enhancement to C. It is distinguished for the efficiency of the code it produces, and is the
most commonly used programming language for writing system software, though it is also
widely used for writing applications. Though not originally designed as a language for
teaching, and despite its somewhat unforgiving character, C is commonly used in computer
science education, in part because the language is so pervasive. Note that C# is a very
different programming language.
C also has the following specific properties:
Low-level access to computer memory via machine addresses and pointers
Function pointers allow for a rudimentary form of closures and runtime polymorphism
A standardized C pre-processor for macro definition, source code file inclusion, conditional
compilation, etc.
A simple, small core language, with functionality such as mathematical functions and file
handling provided by library routines
C (and partially B) was the language that originally discarded well established operators such
as and, or and = (for equality test).
As a systems implementation language, C lacks features found in other languages:
No non-scalar operations such as copying of arrays or strings (old versions of C did not even
copy struts automatically).
No automatic garbage collection
No bounds checking of arrays (expensive in languages with only scalar operations)
No semi-dynamic (i.e. stacked, runtime-sized) arrays until the C99 standard (despite not
requiring garbage collection).
No syntax for ranges, such as the A..B notation used in both newer and older languages (does
not fit scalar-only semantics well).
22

No nested functions, though the GCC compiler provides this feature as an extension
No closures or functions as parameters, only machine-level function pointers
No generators or co routines; intra-thread control flow consists of nested function calls,
barring the (somewhat arcane) use of the longjmp or set context library functions
No exception handling; standard library functions signify error conditions with the global
error variable
Very rudimentary support for modular programming; a cumbersome compilation model
dependent on operating system-specific tools.
No compile-time polymorphism in the form of function or operator overloading; only
rudimentary support for generic programming
No support for object-oriented programming, although C++ was originally implemented as a
pre-processor that translated C++ into C; there are libraries offering object systems for C, and
many object-oriented languages are themselves written in C
No native support for multithreading and networking, though these facilities are provided by
popular libraries
Although the list of built-in features C lacks is long, this has contributed significantly to its
acceptance, as new C compilers can be developed quickly for new platforms. The relatively
low-level nature of the language affords the programmer close control over what the program
is doing, while allowing solutions that can be specially tailored and aggressively optimized
for a particular platform. This allows the code to run efficiently on very limited hardware,
such as mass-produced consumer embedded systems, which today are as capable as the first
machines used to implement C. Often, only hand-tuned assembly language code runs faster,
although advances in compiler technology have narrowed this gap.

5.2 Variables
In C, a variable must be declared before it can be used. Variables can be declared at the start
of any block of code, but most are found at the start of each function. Most local variables are
created when the function is called, and are destroyed on return from that function
C provides a wide range of types. The most common are
int An integer
float A floating point (real) number
char A single byte of memory, enough to hold a character
short An integer, possibly of reduced range
long An integer, possibly of increased range
23

unsigned An integer with no negative range, the spare capacity being used to
increase the positive range
unsigned long Like unsigned possibly of increased range
double A double precision floating point number
All of the integer types plus the char are called the integral types. float and double are called
the real types.

5.3 Constants
A C constant is usually just the written version of a number. For example 1, 0, 5.73, 12.5e9.
We can specify our constants in octal or hexadecimal, or force them to be treated as long
integers.
Octal constants are written with a leading zero - 015.
Hexadecimal constants are written with a leading 0x - 0x1ae.
Long constants are written with a trailing L - 890L.
Character constants are usually just the character enclosed in single quotes; 'a', 'b', 'c'. Some
characters can't be represented in this way, so we use a 2 character sequence.
\n newline
\t tab
\\ backslash
\’ single quote
\0 null (used automatically to terminate character strings).

5.4 Arrays
An array is a collection of variables of the same type. Individual array elements are identified
by an integer index. In C the index begins at zero and is always written inside square
brackets.
We have already met single dimensioned arrays which are declared like this
int results[20];
Arrays can have more dimensions, in which case they might be declared as
int results_2d[20][5];
int results_3d[20][5][3];
Each index has its own set of square brackets.
Where an array is declared in the main function it will usually have details of dimensions
included. It is possible to use another type called a pointer in place of an array. This means
24

that dimensions are not fixed immediately, but space can be allocated as required. This is an
advanced technique which is only required in certain specialized programs.
When passed as an argument to a function, the receiving function need not know the size of
the array. So for example if we have a function which sorts a list (represented by an array)
then the function will be able to lists of different sizes.


























Fig. 5.1 To insert an element in an array.


START
INPUT
a [11],pos,value

Is
k >pos

k = 11
k = k-1
NO
a [k] = a[k-1]


PRINT a [j]
a [pos] =value
j = 0
j = j+1
Is
j <11
YES
NO
STOP
25




























Fig. 5.2 To delete an element from an array.

5.5 Program
5.5.1 Fibonacci Number : -
#include<stdio.h>
#include<conio.h>
void main()
START
INPUT
a [11], pos, value
k = pos


Is
k< 11

k = k+1
NO
a [k] = a[k+1]


PRINT a [j]
j = 0
j = j+1
Is
j <10
YES
NO
STOP





26

{
int f1=0;f2=1,f,I,n;
printf(“enter the total no u want to enter”);
scanf(“%d”,&n);
printf(“\nthefibonnaci no series is:%d\t%d”,f1,f2);
for(i=0;i<n-2;i++)
{
f1=f1+f2;
f1=f2;
f2=f;
printf(“\t%d”,f);
}
getch();
}

Output :
Enter the total no. you want to print : 12
The Fibonacci series is : 0 1 1 2 3 5 8 13 21
34 55 89

Enter the total no. you want to print : 15
The Fibonacci series is : 0 1 1 2 3 5 8 13 21
34 55 89 144 233 377

Enter the total no. you want to print : 10
The Fibonacci series is : 0 1 1 2 3 5 8 13 21
34
Enter the total no. you want to print : 5
The Fibonacci series is : 0 1 1 2 3

Enter the total no. you want to print : 7
The Fibonacci series is : 0 1 1 2 3 5 8


27

5.5.2 Largest Number among Five Number : -
#include<stdio.h>
#include<conio.h>
void main()
{
inta[5], I,l;
for(i=0;i<5;i++)
{
scanf(“%d”,&a[i]);
}
i=a[0];
for(i=0;i<5;i++)
{
if(a[i])>1)
{
l=a[i];
}
}
printf(“\nlargest no of the array is:%d”,l);
getch();
}
Output:
Enter the array of 5 no. :
-2
5
23
-76
0
The largest no. of the array : 23

Enter the array of 5 no. :
3
45
2
28

21
67
The largest no. of the array : 67

Enter the array of 5 no. :
-3
-5
-87
-9
-23
The largest no. of the array : -3

5.5.3 Table between two number : -
#include<stdio.h>
#include<conio.h>
void main()
{
clrscr();
inta,b,I,j,sum=0;
printf(“enter two numbers”);
scanf(“%d%d”,&a,&b);
for(j=0;i<10;j++)
{
for(i=a;i<=b;i++)
{
sum=i*j;
printf(“%*%d=%d”,I,j,sum);
printf(“\t”);
}
printf(“\n”);
}
getch();
}

29

Output of the Tables
Enter two numbers :
3
6
3*1=3 4*1=4 5*1=5 6*1=6
3*2=6 4*2=8 5*2=10 6*2=12
3*3=9 4*3=12 5*3=15 6*3=18
3*4=12 4*4=16 5*4=20 6*4=24
3*5=15 4*5=20 5*5=25 6*5=30
3*6=18 4*6=24 5*6=30 6*6=36
3*7=21 4*7=28 5*7=35 6*7=42
3*8=24 4*8=32 5*8=40 6*8=48
3*9=27 4*9=36 5*9=45 6*9=54
3*10=30 4*10=40 5*10=50 6*10=60




















30

CHAPTER 6
EMBEDDED SYSTEM

6.1 MIROCONTOLLER 89C2051
6.1.1 8-bit Microcontroller with 2K Bytes Flash
• Compatible with MCS-51™ Products
• 2K Bytes of Reprogrammable Flash Memory
– Endurance: 1,000 Write/Erase Cycles
• 2.7V to 6V Operating Range
• Fully Static Operation: 0 Hz to 24 MHz
• Two-level Program Memory Lock
• 128 x 8-bit Internal RAM
• 15 Programmable I/O Lines
• Two 16-bit Timer/Counters
• Six Interrupt Sources
• Programmable Serial UART Channel
• Direct LED Drive Outputs
• On-chip Analog Comparator
6.1.2 Pin Description
•VCC Supply voltage.
•GND Ground.
6.1.3 Port 1
Port 1 is an 8-bit bi-directional I/O port. Port pins P1.2 to P1.7 provide internal pull up. P1.0
and P1.1 require external pull-ups. P1.0 and P1.1 also serve as the positive input (AIN0) and
the negative input (AIN1), respectively, of the on-chip precision analog comparator. The Port
1 output buffers can sink 20mA and can drive LED displays directly. When 1s are written to
Port 1 pins, they can be used as inputs. When pins P1.2 to P1.7 are used as inputs and are
externally pulled low, they will source current (IIL) because of the internal pull-ups. Port 1
also receives code data during Flash programming and verification.
Port 3 pins P3.0 to P3.5, P3.7 are seven bi-directional I/O pins with internal pull-ups.
P3.6 is hard-wired as an input to the output of the on-chip comparator and is not accessible as
a general purpose I/O pin.


31

6.1.4 RST
Reset input. All I/O pins are reset to 1s as soon as RST goes high. Holding the RST pin high
for two machine cycles while the oscillator is running resets the device.
6.1.5 Idle
In idle mode, the CPU puts itself to sleep while all the on chip peripherals remain active. The
mode is invoked by software. The content of the on-chip RAM and all the special functions
registers remain unchanged during this mode. The idle mode can be terminated by any
enabled interrupt or by a hardware reset.
6.1.6 Power-down
In the power down mode the oscillator is stopped, and the instruction that invokes power
down is the last instruction executed. The on-chip RAM and Special Function Registers
retain their values until the power down mode is terminated. The only exit from power down
is a hardware reset. Reset redefines the SFRs but does not change the on-chip RAM. The
reset should not be activated before VCC is restored to its normal operating level and must be
held active long enough to allow the oscillator to restart and stabilize.

6.2 AT89S8252 Features
Compatible with MCS-51™ Products
8K Bytes of In-System Reprogrammable Downloadable Flash Memory
SPI Serial Interface for Program Downloading
Endurance: 1,000 Write/Erase Cycles
2K Bytes EEPROM
4V to 6V Operating Range
Fully Static Operation: 0 Hz to 24 MHz
Three-level Program Memory Lock
256 x 8-bit Internal RAM
32 Programmable I/O Lines
Three 16-bit Timer/Counters
Nine Interrupt Sources
Programmable UART Serial Channel
SPI Serial Interface
Low-power Idle and Power-down Modes
Interrupt Recovery From Power-down
Programmable Watchdog Timer
32

Dual Data Pointer
Power-off Flag

6.3 PIN DESCRIPTION OF AT89S8252
VCC Supply voltage.
GND Ground.
Port 0:- Port 0 is an 8-bit open drain bi-directional I/O port. As an output port, each pin can
sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as high
impedance inputs.
Port 1:- Port 1 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 1 output
buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins, they are pulled
high by the internal pull-ups and can be used as inputs. As inputs, Port 1 pins that are
externally being pulled low will source current (IIL) because of the internal pull ups.
Port 2:- Port 2 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 2 output
buffers can sink/source four TTL inputs.
When 1s are written to Port 2 pins, they are pulled high by the internal pull-ups and can be
used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current
(IIL) because of the internal pull-ups.
Port 3:- Port 3 is an 8 bit bi-directional I/O port with internal pull-ups. The Port 3 output
buffers can sink/source four TTL inputs. When 1s are written to Port 3 pins, they are pulled
high by the internal pull-ups and can be used as inputs.
RST:- Reset input. A high on this pin for two machine cycles while the oscillator is running
resets the device.
XTAL1:- Input to the inverting oscillator amplifier and input to the internal clock operating
circuit.
XTAL2:- Output from the inverting oscillator amplifier.
Timer 0 and 1:- Timer 0 and Timer 1 in the AT89S8252 operate the same way as Timer 0 and
Timer 1 in the AT89C51, AT89C52 and AT89C55. For further information, see the October
1995 Microcontroller Data Book, page 2-45, section titled, “Timer/Counters.”
Timer 2:- Timer 2 is a 16 bit Timer/Counter that can operate as either a timer or an event
counter. The type of operation is selected by bit C/T2 in the SFR T2CON (shown in Table 2).
Timer 2 has three operating modes: capture, auto-reload (up or down counting), and baud rate
generator. The modes are selected by bits in T2CON; Timer 2 consists of two 8-bit registers,
TH2 and TL2. In the Timer function, the TL2 register is incremented every machine cycle.
33

Since a machine cycle consists of 12 oscillator periods, the count rate is 1/12 of the oscillator
frequency.

Fig. 6.2 Pin Diagram of AT89C52.

6.4 7-SEGMENT DISPLAYS

The 7 segment display is used as a numerical indicator on many types of test equipment. It is
an assembly of light emitting diodes which can be powered individually. They most
commonly emit red light. They are arranged and labelled as shown in the diagram. Powering
all the segments will display the number 8.Powering a, b, c, d, and g will
display the number 3. Numbers 0
to 9 can be displayed. The d.p. represents a decimal point. The one shown is a common anode
display since all anodes are joined together and go to the positive supply. The cathodes are
connected individually to zero volts. Resistors must be placed in series with each diode to
limit the current through each diode to a safe value. Early wrist watches used this type of
display but they used so much current that the display was normally switched off. To see the
time you had to push a button. Common cathode displays where all the cathodes are joined
are also available. Liquid crystal displays do a similar job and consume much less power.
Alphanumeric displays are available which can show letters as well as numbers.
The seven-segment LED display has four individual digits, each with a decimal point. Each
of the seven segments (and the decimal point) in a given digit contains an individual LED.
When a suitable voltage is applied to a given segment LED, current flows through and
illuminates that segment LED. By choosing which segments to illuminate, any of the nine
34

digits can be shown. For example, as shown in the figure below, a 2 can be displayed by
illuminating segments a, b, d, e, and g.
Seven segment displays come in two varieties - common anode (CA) and common cathode
(CC). In a CA display, the anodes for the seven segments and the decimal point are joined
into a single circuit node. To illuminate a segment in a CA display, the voltage on a cathode
must be at a suitably lower voltage (about .7V) than the anode. In a CC display, the cathodes
are joined together, and the segments are illuminated by bringing the anode voltage higher
than the cathode node (again, by about .7V). The Dig lab board uses CA displays.
The seven LED‟s in each digit are labelled a-g. Since the Dig lab board uses CA displays, the
anodes for each of the four digits are connected in a common node, so that four separate
anode circuit nodes exist (one per digit). Similar cathode leads from each digit have also been
tied together to form seven common circuit nodes, so that one node exists for each segment
type. These four anode and seven cathode circuit nodes are available at the J2 connector pins
labelled A1-A4 and CA-CG. With this scheme, any segment of any digit can be driven
individually. For example, to illuminate segments b and c in the second digit, the b and c
cathode nodes would be brought to a suitable low voltage (by connecting the corresponding
circuit node available at the J2 connector to ground), and anode 2 would be brought to a
suitable high voltage (by connecting the corresponding circuit node available at the J2
connector to Vdd).


Fig. 6.3 Illuminated Segment to show digit.

35


Fig. 6.4 a) Common cathode display b) Common anode display c) In the Digilab 4-
digit display, the individual cathode from the 4-digits have been combined into
seven individual circuit nodes.


6.5 Liquid Crystal Display(LCD)
6.5.1 Introduction
The ORIOLE DISPLAY MODULE is a dot matrix liquid crystal display that displays
alphanumeric, kana (Japanese) characters and symbols. The built in controller & driver LSI‟s
provide convenient connectivity between a dot matrix LCD and most 4-8 bit micro‟s or
microc‟s. All the functions required for dot matrix crystal display drive are internally
provided .Internal refresh is provided by the ODM. The CMOS technology makes the device
ideal for application in hand held, portable and other battery powered instruments with low
consumption.
6.5.2 Features
Easy interface with a 4 bit or 8 bit MPU.
Built in dot matrix LCD controller with font 5*7 or 5*10dots.
Display data RAM for 80 characters (80*8bits)
Character generator ROM, which provides 160 characters with font 5*7 dots and 32
characters with font 5*10 dots.
Both display data and character generator RAM‟s can be read from the MPU.
Internal automatic reset circuit at power ON.
Build in oscillator circuit.(no external ckt is required)
Wide range of instruction functions, clear display, cursor home, display on/off, cursor on/off,
cursor shift, display shift

36

CHAPTER-7
PROJECT ACTIVITIES TAKEN

7.1 Full Adder Programming - Using Data Flow Modelling
module fulladder(s,c,a,b,c1);
output s,c;
input a,b,c1;
wire m,n,o;
assign s=a^b^c1;
assign c= (a&b)|(b&c1)|(c1&a);
endmodule

Full Adder Test Bench - Using Data Flow Modelling
module fulladdertb(s,c,a,b,c1);
wire s,c;
reg a,b,sc1;
fulladder F(s,c,a,b,c1);
initial
begin
a=0; b=0; c1=0;
#20
a=0; b=0; c1=1;
#20
a=0; b=1; c1=0;
#20
a=0; b=1; c1=1;
#20
a=1; b=0; c1=0;
#20
a=1; b=0; c1=1;
#20
a=1; b=1; c1=0;
#20
a=1; b=1; c1=1;
37

end
end module

Fig. 7.1 Full Adder Wave form Using Data Flow Modelling.

7.2 Half Subtracter Programming - using Gate Level Modelling
module halfsub(s,c,a,b);
output s,c;
input a,b;
and A1(c,a,b);
xor x1(s,a,b)
endmodule

Half Subtracter Test Bench - using Gate Level Modelling
module halfsubtb(s,c,a,b);
wire c,s;
reg a,b;
halfsub hs(s,c,a,b);
38

initial
begin

Fig. 7.2 Half Subtracter Wave form using Gate Level Modelling.

a=0 ; b=0;
#10
a=0 ; b=1;
#10
a=1 ; b=0;
#10
a=1 ; b=1;
end
endmodule

7.3 Traffic Light Controller :
Program:
#include <REG2051.H>
39

#include<stdio.h>
void delay1();
void delay2();
void main()
{
while(1)
{
P1=0x21;

Fig. 7.3 Traffic Light Controller Designed on Proteus.

P3=0x09;
delay1();
P1=0x14;
40

P3=0x09;
delay2();
P1=0x0c;
P3=0x09;
delay1();
P1=0xa4;
P3=0x08;
delay2();
P1=0x64;
P3=0x08;
delay1();
P1=0x24;
P3=0x05;
delay2();
P1=0x24;
P3=0x03;
delay1();
}
}
void delay1()
{
unsigned int i;
unsigned char j;
for(i=0;i<=10000;i++)
{
for(j=0;j<=100;j++);
}
}
void delay2()
{
unsigned int m;
unsigned char n;
for(m=0;m<=10000;m++)
{
41

for(n=0;n<=50;n++);
}
}


7.4 Seven Segment Display:
Program :
#include <REG2051.H>
#include<stdio.h>
void delay();
void main()
{
while(1)
{
char num[]={0x3f,0x06,0x9b,0x8f,0xa6,0xad,0xbd,0x07,0xbf,0xaf};
intc,d;
for(c=0;c<10;c++)
{
for(d=0;d<10;d++)
{
P1=num[d];
P3=num[c];
delay();
}
}
}
}
void delay()
{
unsigned int i;
unsigned int j;
for(i=0;i<1000;i++)
{
for(j=0;j<20;j++);
42

}
}



Fig. 7.4 Seven Segment Display on Designed On Proteus.











43

CONCLUSION

In this four months, training is a must for any engineering course, the practical training helps
the student to put into practice whatever he has studied in theory. The bookish knowledge the
student has in college is put into practical difficulties what so ever he come across, are solved
by the practical experience of the seniors in the organization establishment, where the student
is undergoing the practical training.
In my six months training schedule. I practically had a total overview of electronics field. I
came to know many different types of software‟s, tools, languages which is used in designing
and simulating any circuit in ECE.
I worked on following:-
1. Verilog (Model Sim Software)
2. Embedded System (Keil & Proteus Software‟s)
3. PSIM Software
4. PCB Designing (Protel 99 SE and CAM Castic Software)
5. C Language (Turbo C++ Software)


I have studied about all topics mentioned above and made projects also using these software.
For example:-
1. Traffic light Controller using protel.
2. Seven Segment Display using Embedded and proteus.
3. +5V power Supply











44

REFERENCES

1. Let us C by:- Yashwant Kanetkar
2. Electronics for you magazines
3. R S Components on CD April 2009
4. Second Edition VERILOG HDL (A guide to Digital Design and Synthesis) by Samir
Palnitkar
5. http://www.ipc.org/ContentPage.aspx?pageid=World-PCB-Market-Grew-in-2012 IPC
World PCB Production Report 2013
6. Jump up ^ http://www.cs.berkeley.edu/~prabal/teaching/cs194-05-s08/cs194-
designflow.ppt Printed Circuit Board Design Flow Methodology
7. http://www.sunburst-
design.com/papers/CummingsSNUG2003Boston_SystemVerilog_VHDL.pdf
8. Jump up ^ D. Michael Miller; Mitchell A. Thornton (2008). Multiple valued logic:
concepts and representations. Synthesis lectures on digital circuits and systems 12.
Morgan & Claypool Publishers. ISBN 978-1-59829-190-2
9. Dennis M. Ritchie. "The History of the C Programming Language". Retrieved
February 26, 2014. ^ "TIOBE Programming Community Index". 2009. Retrieved 6
May 2009.
10. http://www.engineersgarage.com/tutorials/emebedded-c-language
11. Jump up ^ http://www.engineersgarage.com/tutorials/emebedded-c-language
12. Jump up ^ http://www.engineersgarage.com/tutorials/emebedded-c-language


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