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Error correction codes (ECCs) are commonly used to
protect memories against errors. Among ECCs, orthogonal latin squares
(OLS) codes have gained renewed interest for memory protection due to
their modularity and the simplicity of the decoding algorithm that enables
low delay implementations. An important issue is that when ECCs are
used, the encoder and decoder circuits can also suffer errors. In this
brief, a concurrent error detection technique for OLS codes encoders
and syndrome computation is proposed and evaluated. The proposed
method uses the properties of OLS codes to efficiently implement a parity
prediction scheme that detects all errors that affect a single circuit node

Error correction codes (ECCs) are commonly used to
protect memories against errors. Among ECCs, orthogonal latin squares
(OLS) codes have gained renewed interest for memory protection due to
their modularity and the simplicity of the decoding algorithm that enables
low delay implementations. An important issue is that when ECCs are
used, the encoder and decoder circuits can also suffer errors. In this
brief, a concurrent error detection technique for OLS codes encoders
and syndrome computation is proposed and evaluated. The proposed
method uses the properties of OLS codes to efficiently implement a parity
prediction scheme that detects all errors that affect a single circuit node

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Concurrent Error Detection for Orthogonal Latin Squares

Encoders and Syndrome Computation

Pedro Reviriego, Salvatore Pontarelli, and Juan Antonio Maestro

AbstractError correction codes (ECCs) are commonly used to

protect memories against errors. Among ECCs, orthogonal latin squares

(OLS) codes have gained renewed interest for memory protection due to

their modularity and the simplicity of the decoding algorithm that enables

low delay implementations. An important issue is that when ECCs are

used, the encoder and decoder circuits can also suffer errors. In this

brief, a concurrent error detection technique for OLS codes encoders

and syndrome computation is proposed and evaluated. The proposed

method uses the properties of OLS codes to efciently implement a parity

prediction scheme that detects all errors that affect a single circuit node.

Index TermsConcurrent error detection, error correction codes

(ECC), Latin squares, majority logic decoding (MLD), memory.

I. INTRODUCTION

Error correction codes (ECCs) have been used to protect memories

for many years [1], [2]. There is a wide range of codes that are used or

have been proposed for memory applications. Single error correction

(SEC) codes that can correct one bit per word are commonly used.

More advanced codes that can also correct double adjacent errors [3]

or double errors in general have also been studied [4]. The use of

more complex codes that can correct more errors is limited by their

impact on delay and power, which can limit their applicability to

memory designs [5]. To overcome those issues, the use of codes that

are one step majority logic decodable (OS-MLD) has recently been

proposed. OS-MLD codes can be decoded with low latency and are,

therefore, used to protect memories [6]. Among the codes that are

OS-MLD, a type of euclidean geometry (EG) code has been proposed

to protect memories [7], [8]. The use of difference set code has also

been recently analyzed in [9]. Another type of code that is OS-MLD

is orthogonal latin squares (OLS) code [10].

The use of OLS codes has gained renewed interest for intercon-

nections [11], memories [12], and caches [13]. This is due to their

modularity such that the error correction capabilities can be easily

adapted to the error rate [11] or to the mode of operation [13].

OLS codes typically require more parity bits than other codes to

correct the same number of errors. However, their modularity and

the simple and low delay decoding implementation (as OLS codes

are OS-MLD), offset this disadvantage in many applications.

An important issue is that the encoder and decoder circuits needed

to use (ECCs) can also suffer errors. When an error affects the

encoder, an incorrect word may be written into the memory. An error

in the decoder can cause a correct word to be interpreted as erroneous

or the other way around, an incorrect word to be interpreted as a

correct word.

Manuscript received April 1, 2012; revised October 24, 2012; accepted

November 25, 2012. Date of publication December 28, 2012; date of current

version October 14, 2013. This work was supported by the Spanish Ministry of

Science and Education under Grant AYA2009-13300-C03. This brief is part of

a collaboration in the framework of COST ICT Action 1103 Manufacturable

and Dependable Multicore Architectures at Nanoscale.

P. Reviriego and J. A. Maestro are with Universidad Antonio de Nebrija,

Madrid 28040, Spain (e-mail: previrie@nebrija.es; jmaestro@nebrija.es).

S. Pontarelli is with the University of Rome Tor Vergata, Rome 00133, Italy

(e-mail: pontarelli@ing.uniroma2.it).

Color versions of one or more of the gures in this paper are available

online at http://ieeexplore.ieee.org.

Digital Object Identier 10.1109/TVLSI.2012.2230655

1063-8210 2012 IEEE

The protection of the encoders and decoders has been studied

for different ECCs. For example, in [8] EG codes were studied.

The protection of ReedSolomon, Hamming, and BCH encoders and

decoders has also been studied in [14] and [15], and more general

techniques for systematic and cyclic codes have been proposed in

[16] and [17]. Finally, the protection of encoders for SEC codes

against soft errors was discussed in [18].

The ECC encoder computes the parity bits, and in most cases the

decoder starts by checking the parity bits to detect errors. This is

commonly referred to as syndrome computation. For some codes, it

is possible to perform encoding and syndrome computation serially

based on the properties of the code. However, when delay has to

be low, parallel implementations are preferred. This is the case for

OLS codes that are commonly used in high-speed applications. The

reader is referred to [6] for a detailed discussion of ECC encoders

and decoders. After syndrome computation, when errors are detected,

the rest of the decoding is done to correct the errors. This means

that generating and checking the parity bits are important parts of

the encoder and decoder circuitry. Therefore, its protection is an

important issue.

In this brief, the protection of the encoders and syndrome compu-

tation for OLS codes when used in SRAM memories and caches

is considered. Based on the specic properties of these codes, it

is shown that parity prediction is an effective technique to detect

errors in the encoder and syndrome computation. This is not the

case for most other block codes for which parity prediction cannot

provide effective protection. Therefore, this is another advantage of

OLS codes in addition to their modularity and simple decoding.

The rest of this brief is organized as follows. Section II introduces

OLS codes and summarizes some of their properties that are used in

the rest of this brief. In Section III, the proposed parity prediction

scheme is described. Section IV evaluates its cost in terms of circuit

area and delay. Finally, the conclusion from this brief is presented in

Section V.

II. ORTHOGONAL LATIN SQUARES CODES

OLS codes are based on the concept of Latin squares. A Latin

square of size m is an m m matrix that has permutations of the

digits 0, 1,, m 1 in both its rows and columns [19]. Two Latin

squares are orthogonal if when they are superimposed every ordered

pair of elements appears only once. OLS codes are derived from

OLS [10]. These codes have k = m

2

data bits and 2tm check bits,

where t is the number of errors that the code can correct. For a double

error correction code t = 2, and, therefore, 4m check bits, are used.

As mentioned in the introduction, one advantage of OLS codes is that

their construction is modular. This means that to obtain a code that

can correct t +1 errors, simply 2m check bits are added to the code

that can correct t errors. This can be useful to implement adaptive

error correction schemes, as discussed in [11] and [13]. The modular

property also enables the selection of the error correction capability

for a given word size.

As mentioned before, OLS codes can be decoded using OS-MLD

as each data bit participates in exactly 2t check bits and each other bit

participates in at most one of those check bits. This enables a simple

correction when the number of bits in error is t or less. The 2t check

bits are recomputed and a majority vote is taken. If a value of one is

obtained, the bit is in error and must be corrected. Otherwise the bit

is correct. As long as the number of errors is t or less, the remaining

t 1 errors can, in the worst case, affect t 1 check bits. Therefore,

still a majority of t + 1 triggers the correction of an erroneous bit.

In any case, the decoding starts by recomputing the parity check bits

and checking against the stored parity check bits.

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 21, NO. 12, DECEMBER 2013 2335

Fig. 1. Parity check matrix for OLS code with k = 16 and t = 1.

The parity check matrix H for OLS codes is constructed from the

OLS. As an example, the matrix for a code with k = 16 and 8 check

bits that can correct single errors is shown in Fig. 1. As discussed

earlier, due to the modular construction of OLS codes this matrix

forms part of the H matrix for codes that can correct more errors.

For example, to obtain a code that can correct two errors, eight

additional rows are added to the H matrix.

For an arbitrary value of k = m

2

, the H matrix for a SEC OLS

code is constructed as follows:

H =

M

1

I

2m

M

2

(1)

where I

2m

is the identity matrix of size 2m and M

1

, M

2

are matrices

of size m m

2

. The matrix M

1

has m ones in each row. For

the rth row, the ones are at positions (r 1) m + 1,(r 1)

m + 2,(r 1) m + m 1, (r 1) m + m. The matrix

M

2

is constructed as follows:

M

2

= [I

m

I

m

. . . I

m

]. (2)

For m = 4, the matrices M

1

and M

2

can be clearly observed in

Fig. 1. The encoding matrix G is just the H matrix on which the

check bits are removed

G =

M

1

M

2

. (3)

In summary, the encoder takes k = m

2

data bits (d

i

) and computes

2tm parity check bits (c

i

) using a matrix G, which is derived from

Latin squares and has the following properties.

1) Each data bit participates exactly in 2t parity checks.

2) A pair of data bits participates (both bits) in at most one of the

parity checks.

These properties are used in the next section to discuss the

proposed technique.

III. PROPOSED CONCURRENT ERROR DETECTION TECHNIQUE

Before describing the proposed error detection techniques, the

standard denition of self-checking circuits that are used in this

section is presented. During normal, or fault-free, operation, a circuit

receives only a subset of the input space, called the input code space,

and produces a subset of the output space, called the output code

space. The outputs that are not members of the output code space

form the output error space. In general, a circuit may be designed

to be self-checking only for an assumed fault set. In this brief, we

consider the fault set F corresponding to the single stuck-at fault

model [20].

A circuit is self-checking [20] if and only if it satises the

following properties: 1) it is self-testing, and 2) fault-secure.

A circuit is self-testing if, for each fault f in the fault set F, there

is at least one input belonging to the input code space, for which the

circuit provides an output belonging to the output error space.

d

1

d

2

d

3

d

4

c1

d

5

d

6

d

7

d

8

c2

d

9

d

10

d

11

d

12

c3

d

13d

14

d

15d16

c4

d

1

d

5

d

9

d

13

c5

d

2

d

6

d

10d

14

c6

d

3

d

7

d

11

d

15

c7

d

4 d

8

d

12d16

c8

r

2

ENCODER

r1

Fig. 2. Proposed self-checking encoder for OLS code with k = 16 and t = 1.

A circuit is fault-secure if, for each fault f in the fault set F and

for each input belonging to the input code space, the circuit provides

the correct output, or an output belonging to the output error space.

The fault-secure property guarantees that the circuit gives the

correct response, or signals the presence of a fault that provides an

output in the error space. Faults are always detected, since there is an

input that produces an output that identies the presence of the fault.

This property is related to the assumption that the interval between

the occurrences of two faults is enough to permit to all the elements

belonging to the input code space to appear as circuit inputs before

the occurrence of the second fault. Thus, an output belonging to the

output error space appears at the circuit output before the occurrence

of the second fault.

The technique that we propose is based on the use of parity

prediction, which is one of the techniques commonly used to detect

error in general logic circuits [21], [22]. In our case, the problem

is substantially simpler, given the structure of the OLS codes. For

the encoder, it is proposed that the parity of the computed check

bits (c

i

) is compared against the parity of all the check equations.

The parity of all the check equations is simply the equation obtained

by computing the parity of the columns in G. For OLS codes, since

each column in G has exactly 2t ones, the null equation is obtained

(see, for example, Fig. 1). Therefore, the concurrent error detection

(CED) scheme is simply to check

c

1

c

2

c

3

c

2t m

= 0. (4)

This enables an efcient implementation that is not possible in

other codes. For example, in a Hamming code a signicant part of

the columns in G has an odd weight and for some codes the number

is even larger as they are designed to have odd weights [23].

The input code space of the OLS encoder corresponds to the

input space, since the encoder can receive all the possible 2

k

input congurations. The output code space of the OLS encoder is

composed by the outputs satisfying (4), while the output error space

is the complement of the output code space.

A fault that occurs in one of the gates composing the OLS encoder

can change at most one of the c

i

check bits. When this change occurs,

the OLS encoder provides an output that does not satisfy (4), i.e., an

output belonging to the output error space. Hence, this guarantees the

fault-secure property for this circuit. Additionally, since the encoder

is composed only by XOR gates, no logic masking is performed in the

circuit. Therefore, when a fault is activated the error is propagated

to the output. This ensures the self-testing property of the circuit.

In order to check if the output of the OLS encoder belongs to

the output code space or the output error space, a self-checking

implementation of a parity checker is used [20]. The checker controls

the parity of its inputs and is realized with a repetition code. The

two outputs (r

1

, r

2

) are each equal to the parity of one of two

disjoint subsets of the checker inputs (c

i

), as proposed in [24].

When a set of inputs with the correct parity is provided, the output

2336 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 21, NO. 12, DECEMBER 2013

code {r

1,

r

2

} takes the values 00 or 11. When the checker receives

an erroneous set of inputs, the checker provides the output codes

01 or 10. Also, if a fault occurs in the checker, the outputs are

01 or 10. This guarantees the self-checking property of the parity

checker [24]. The proposed encoder is illustrated in Fig. 2 for the

code with k = 16 and t = 1.

The proposed circuit can detect any error that affects an odd

number of c

i

bits. For a general code, in most cases there is logic

sharing among the computations of the c

i

bits [18]. This means

that an error may propagate to more than one c

i

bit, and if the

number of bits affected is even, then the error is not detected by

the proposed scheme. To avoid this issue, the computation of each

c

i

bit can be done separately. This, however, increases the circuit

area of the encoder as no logic sharing is allowed. Another option is

to control the logic in such a way that errors can only propagate

to an odd number of outputs. This would also increase the cost

compared to an unrestricted implementation. Additionally, even if

the error propagates to an odd number of outputs, the delay of each

path can be different. This may cause registering of only some of the

output errors at the clock edge.

For OLS codes, as discussed in the previous section a pair of data

bits shares at most one parity check. This guarantees that there is

no logic sharing among the computation of the c

i

bits. Therefore,

the proposed technique detects all errors that affect a single circuit

node.

For the syndrome computation, the parity prediction can be imple-

mented by checking that the following two equations take the same

value

r

1

= s

1

s

2

s

3

s

2t m

(5)

r

2

= c

1

c

2

c

3

c

2t m

(6)

where s

i

are the computed syndrome bits. The proposed circuit is

shown in Fig. 3 for the code with k = 16 and t = 1.

For syndrome computation, the input code space is only a subset

of the possible 2

k+2t m

input congurations as only up to t errors are

considered. This subset is given by the valid OLS codewords and the

non-valid OLS codewords that are at a Hamming distance of t or less

from a valid codeword. Those correspond to the input congurations

in which there are no errors or at most t errors on the d

i

inputs such

that the errors can be corrected.

The output code space of the OLS syndrome computation is

composed by the outputs given by (5) and (6) satisfying r

1

= r

2

,

while the output error space is the complement of the output code

space.

The fault-secure property for the syndrome computation is easily

demonstrated for the faults in F by observing that the circuits that

compute r

1

and r

2

do not share any gate and both circuits are only

composed of XOR gates. Therefore, a single fault could propagate

to only one of the outputs, producing an output on the output error

space.

To prove the self-testing property for the syndrome computation,

suppose that a fault occurs in one of the gates computing (5). If the

input conguration is a valid OLS codeword, all the syndrome bits

are 0, detecting all stuck-at-1 faults in the XOR gates computing (5).

Instead, if the input is a non-OLS codeword that is affected by a t

or less errors, some syndrome bits are 1, allowing the detection of

a stuck-at-0 faults in the XOR gates computing (5). Finally, suppose

that a fault occurs in one of the gates computing (6). Since any

combination of the 2tm check bits is allowed, any fault can be

activated and the error propagated to the output r

2

.

For OLS codes, the cost of the encoder and syndrome computation

in terms of the number of two-input XOR gates can be easily

calculated (note that for the calculations an l input XOR gate is

c

1

SYNDROME COMPUTATI ON

c

2

c

3

c

4

c

5

c

6 c

7 c8

s

1

s

2 s

3

s

4

s

5

s

6 s

7

s

8

c1 c2 c

3

c

4

c

5

c

6 c

7

c

8

r

2

r

1

d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11d12d13d14

d15d

16

d1 d5 d9 d13 d2 d6 d10d14

d3 d7 d11d15 d4 d8

d12d

16

Fig. 3. Proposed self-checking syndrome computation for OLS code with

k = 16 and t = 1.

TABLE I

OVERHEAD OF PROPOSED CED FOR SEC-OLS CODES

k m Encoder Syndrome

16 4 29.17% 43.75%

64 8 13.39% 23.44%

256 16 6.46% 12.11%

assumed to be equivalent to l 1 two-input XOR gates). For a code

with k = m

2

and that can correct t errors, there are 2tm parity check

bits and the computation of each of them requires m 1 two input

XOR gates. Therefore, the encoder requires 2tm(m 1) two-input

XOR gates. For the syndrome computation, an additional XOR gate is

needed for each parity check bit, giving a total of 2tm

2

two-input XOR

gates. The proposed method requires 2tm1 two-input XOR gates

for the encoder and 4tm-2 two-input XOR gates for the syndrome

computation. This means that the overhead required to implement

our method for the encoder is

o

encoder

=

(2tm1)

(2tm(m 1))

(7)

and for the syndrome computation is

o

syndrome

=

(4tm 2)

(2tm

2

)

. (8)

For large values of m, the rst equation can be approximated by

1/m and the second by 2/m. This shows that as the block size of the

code k = m

2

grows, the overhead becomes smaller and independent

of t . This is illustrated in Table I, where the overheads predicted by

(7) and (8) are illustrated for t = 1 and different values of k.

The overhead in terms of delay is signicant as the proposed parity

computation is done over the results of the encoder or syndrome

computation. This means that the delay of the new logic adds directly

to the encoding or syndrome computation delay. However, the effect

on the memory access time can be minimized by noting that for the

encoder the error checking can be done in parallel with the writing

of the data into the memory. Then if an error is detected, the data is

encoded and written again. For the syndrome computation, the error

detection can be performed in parallel with the majority logic voting

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 21, NO. 12, DECEMBER 2013 2337

TABLE II

LAYOUT AREA FOR ENCODER (in m

2

)

k m Unprotected With CED Overhead

16 4 184.6 236.2 27.9%

64 8 847.0 948.7 12.0%

256 16 3594.1 3820.1 6.2%

TABLE III

LAYOUT AREA FOR SYNDROME COMPUTATION (in m

2

)

k m Unprotected With CED Overhead

16 4 237.7 344.1 45.1%

64 8 951.1 1176.4 23.6%

256 16 3804.4 4276.8 12.4%

TABLE IV

DELAY ESTIMATES FOR ENCODER (in ns)

k m Unprotected With CED Overhead

16 4 1.26 1.65 30%

64 8 1.52 2.01 28%

256 16 1.71 2.41 40%

and the error correction such that again, the impact on access time

is minimized.

Finally, it is worth noting that the overhead of implementing the

proposed technique for other codes is much larger. This is because

the CED check becomes more complex and also because logic

sharing must be avoided in the parity check computation.

IV. EVALUATION

The proposed CED mechanisms have been implemented in

VHDL for codes with t = 1 and the values of k used in

Table I. The designs have been implemented for the 45-nm OSU

free PDK standard cell library [25] using synopsys design com-

piler for the synthesis and cadence encounter for placement and

routing.

To evaluate the area overhead, synthesis was run with maximum

effort on area optimization and then place and route was done to

obtain the circuit layout. The area of the circuit layouts for the

encoder is shown in Table II and for the syndrome computation is

shown in Table III. The overhead required to implement our proposed

technique is also shown in the tables. It can be observed that the

results are in good agreement with the analytical estimates presented

in Table I.

To evaluate the impact on delay, synthesis was run with

maximum effort on delay optimization. The results are shown in

Tables IV and V. It can be observed that the proposed scheme

introduces a signicant delay. This is expected from the discussion

in the previous section. However, as explained there, the impact on

memory access time can be minimized by performing error checking

in parallel with the writing of the data for the encoder. For the

syndrome computation, the checking can be done in parallel with

the majority voting and error correction.

It was mentioned in the previous sections that the proposed

approach was not effective for other codes. This is in part because

to ensure the detection of errors no logic sharing among the parity

bits computation can be allowed. This results in a signicant area

increase. As an example, the encoder for a parity extended Hamming

code with k = 32 was implemented with and without logic sharing.

TABLE V

DELAY ESTIMATES FOR SYNDROME COMPUTATION (in ns)

k m Unprotected With CED Overhead

16 4 1.32 1.75 32%

64 8 1.54 2.05 33%

256 16 1.75 2.42 38%

The area overhead of avoiding logic sharing was 35%. The cost of the

checker is also larger for Hamming. In this particular case, the total

overhead for the proposed scheme was over 80%. This conrms that

the proposed checker is not effective in a general case and relies on

the properties of OLS codes to achieve an efcient implementation.

V. CONCLUSION

In this brief, a CED technique for OLS codes encoders and

syndrome computation was proposed. The proposed technique took

advantage of the properties of OLS codes to design a parity prediction

scheme that could be efciently implemented and detects all errors

that affect a single circuit node. The technique was evaluated for

different word sizes, which showed that for large words the overhead

is small. This is interesting as large word sizes are used, for

example, in caches for which OLS codes have been recently proposed

[13]. The proposed error checking scheme required a signicant

delay; however, its impact on access time could be minimized.

This was achieved by performing the checking in parallel with

the writing of the data in the case of the encoder and in parallel

with the majority voting and error correction in the case of the

decoder.

In a general case, the proposed scheme required a much larger

overhead as most ECCs did not have the properties of OLS codes.

This limited the applicability of the proposed CED scheme to OLS

codes. The availability of low overhead error detection techniques

for the encoder and syndrome computation is an additional reason

to consider the use of OLS codes in high-speed memories and

caches.

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pp. 173174.

Oscillation and Transition Tests for Synchronous

Sequential Circuits

Katherine Shu-Min Li

AbstractIn this brief, we propose an oscillation-ring test methodology

for synchronous sequential circuits under the scan test environment. This

approach provides the following features: 1) it is at-speed testing, which

makes delay defects detectable; 2) the automatic test pattern generation is

much easier, and the test set is usually smaller; and 3) test responses are

directly observable at primary outputs and, thus, it greatly reduces the

communication bandwidth between the automatic test equipment and

the circuit under test. A modied scan register design supporting the

oscillation-ring test is presented and an effective oscillation test generation

algorithm for the proposed test scheme is given. Experimental results on

LGSyn91 benchmarks show that the proposed test method achieves high

fault coverage with a smaller number of test vectors.

Index TermsAt-speed test, oscillation test, scan design, synchronous

sequential circuit.

I. INTRODUCTION

Decreasing feature sizes and increasing clock speeds have com-

bined to dramatically alter the defect effects. Recent evidence indi-

cates that delay defects can no longer be ignored [1]. The detection

of delay faults requires at-speed test techniques, which creates signal

transitions to be captured at normal speed. In the past, it was typically

accomplished with functional patterns, but it was undesirable mainly

due to the cost consideration. Scan-based test techniques [2] offer

a viable alternative for at-speed testing. However, there are many

complicating factors that use slow scan-based tests for stuck-at faults

to delay test delay faults. Thus, a cost-effective test methodology for

the at-speed test is desirable, and it is the motivation of this brief.

Sequential testing is difcult due to the lack of controllability and

observability in internal storage elements. Sequential automatic test

pattern generation (ATPG) is much more complicated [3], and it may

not be able to achieve high fault coverage with sequential testing.

The scan-based designs are the most popular design for testability

(DFT) technique for testing sequential circuits. However, scan tests

are usually carried out in lower speed, and thus they are mainly

targeted for stuck-at faults.

An oscillation ring is a closed loop with an odd number of signal

inversions. If the circuit under test (CUT) is fault-free, an oscillation

signal appears on the ring. Otherwise, the CUT is deemed faulty. The

oscillation-based test is an efcient and effective method to detect

faults in a circuit or a device. It has been applied to test analog

circuits [4], digital circuits [5], and system-level interconnects [6].

We propose an oscillation test methodology for sequential testing

in this brief. The proposed method modies storage elements such

that oscillation signals can be generated according to the functional

and timing specications of the CUT. This approach provides the

following features; 1) in this architecture, testing is conducted at-

speed, which makes delay defects detectable; 2) test vectors can

be directly derived from the nite-state machine (FSM) model,

Manuscript received January 23, 2012; revised July 20, 2012 and

September 16, 2012; accepted November 25, 2012. Date of publica-

tion January 11, 2013; date of current version October 14, 2013. This

work was supported in part by the National Science Council of Taiwan,

under Grant NSC-98-2221-E-110-060-MY2, Grant NSC-99-2220-E-110-009,

Grant 99-EC-17-A-01-S1-104, and Grant NSC-100-2221-E-110-087.

The author is with the Department of Computer Science and Engineer-

ing, National Sun Yat-Sen University, Kaohsiung 80424, Taiwan (e-mail:

smli@cse.nsysu.edu.tw).

Color versions of one or more of the gures in this paper are available

online at http://ieeexplore.ieee.org.

Digital Object Identier 10.1109/TVLSI.2012.2230654

1063-8210 2013 IEEE

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