ASIC IMPLEMENTATION OF DIGITAL BASEBAND PROCESSOR OF

WRAN (IEE802.22)



A report of project phase-1
Submitted by
IPPILI SURAYYA
Under the guidance of
Prof..R.M.PATRIKAR


Department of Electronics Engineering
Visvesvaraya National Institute of Technology
Nagpur 440010 (India).




ABSTRACT:
The WRAN system uses vacant TV channels to provide wireless data communication over a distance up to 100km
at the rate of 4.54-22.69Mbps in Regional areas without causing interference to incumbent users. WRAN operates in
frequency bands 58-862MHz.OFDMA Transmitter is used in physical layer for transmission of binary data which is
coming from MAC layer. In the transmitter side random bit generator is used for testing of operation of transmitter
instead of interfacing with MAC layer. In the Channel Coding Scrambler and BCC are operating at frequencies
between 4.54-22.69MHZ. Bit interleaver is operating at frequency twice of scrambler operating frequency.
Constellation mapping is used for Digital modulation of data for different data rates different modulations are used
like QPSK, 16-QAM, 64-QAM so a MUX is used at the transmitter to select the modulation type according to
modulation index. The total available bandwidth is divided into 2048 sub carriers so 2048 IFFT used at the
transmitter to assign data onto the 2048 subcarriers.
Verilog HDL is used to code all digital blocks for FPGA implementation through XILINX ISE14.2. functional
simulation is done using ModelSim. The functional simulation for all the digital modules in the transmitter is done
by applying test bench.
In this report WRAN introduction, IEEE802.22 physical layer, implementation of blocks in OFDMA transmitter are
included.
INTRODUCTION:

This chapter will give an idea about the WRAN/IEEE 802.22 technology.
The Wireless Regional Area Networks (WRANs) standard has been developed to operate primarily in low
population density areas in order to provide broadband access to data networks. The WRAN systems will use vacant
channels in the VHF and UHF bands allocated to the Television Broadcasting Service in the frequency range
between 54 MHz and 862 MHz while avoiding interference to the broadcast incumbents in these bands. A typical
application can be the coverage of the rural area around a village.[1]

Figure 1-IEEE 802.22 WRAN cell base station and user terminals



Parameters

Specification
Frequency range 54~862 MHz
a

Channel bandwidth 6, 7, or 8 MHz
Data rate 4.54 to 22.69 Mbit/s
Payload modulation QPSK, 16-QAM, 64-QAM
Multiple Access OFDMA
FFT Size (N
FFT
) 2048
Cyclic Prefix Modes 1/4, 1/8, 1/16, 1/32
Duplex TDD



T
CP


SYM

IEEE 802.22 Physical Layer

Specifications of PHY:

The PHY specification is based on an orthogonal frequency division multiple access (OFDMA) scheme where
information modulated on orthogonal subcarriers using Inverse Fourier Transforms.
















Table-1 Standard specifications of PHY layer of WRAN[1]



OFDMA Symbol Format:
Time Domain Description:
The time-domain signal is generated by taking the inverse Fourier transform of the length N
FFT
vector. The
vector is formed by taking the constellation mapper output and inserting pilot and guard tones. At the
receiver, the time domain signal is transformed to the frequency domain representation by using a Fourier
transform.
Let T
FFT
represent the time duration of the IFFT output signal. The OFDM symbol is formed by inserting a
cyclic prefix of time duration T
CP
resulting in a symbol duration of T
SYM
= T
FFT
+
T
CP
.






T
T
FFT


Figure-2 OFDM symbol format[1]

Frequency Domain Description:
In the frequency domain, an OFDM symbol is defined in terms of its subcarriers. The subcarriers are
classified as:
1) Data subcarriers,
2) Pilot subcarriers,
3) Guard and Null (including DC) subcarriers.
The classification is based on the functionality of the subcarriers. The total number of subcarriers is
determined by the FFT/IFFT size. The pilot subcarriers are distributed across the bandwidth. All the
remaining guard/Null subcarriers carry no energy and are located at the center frequency of the channel (DC
subcarrier) and at both edges of the channel (guard subcarriers).





Data Sub-carriers Pilot Sub-Carriers Guard/Null Sub-carriers

Figure 2:Distribution of various sub-carriers over total band width.


Functional Block Diagram of OFDMA:



Figure 3 Functional Block Diagram of OFDMA

Random bit generator:
Random bit generator is to generate the data to test the operation transmitter. It is
Implemented by LFSR.It will generates bits at required rate by simply changing the operating frequency (clock
frequency) of LFSR.

Channel coding:
Channel coding is used to encrypt the data so that other users cant understand it and to provide
mechanism of self-correcting errors at the receiver without giving request to retransmit the data. It includes data
scrambling, binary convolutional coding (as FEC), bit interleaver and constellation mapping. The scrambling process
is to encode the message at the transmitter to make the message understandable at the receiver not equipped with
appropriate descrambling. FEC is used for controlling errors in data transmission over noisy communication channel
by correcting error without. The bit interleaver is used for avoiding burst errors.


Figure 4 Channel coding process

Data scrambling:

The data scrambler is single bit processing module. The data generated by LFSR is first processed by Pseudo
random bit generator (PRBS) of size 15bit. Initially PRBS is initialized with 011011100010101, starting with the
MSB on the left. This initialization vector used as secret key for Descrambling.


Forward Error correction:
The 1/2 binary convolutional code is the proposed FEC method by standard IEEE 802.22.
Binary convolutional coding:
1/2 binary convolutional encoder is a single bit processing module. The constraint length of this
coder is equal to7 and its generator polynomials are 171
o
and 133
o
for outputs A and B respectively. Figure
shows graphical description of the generator polynomials. Output A and output B represent the first
and second output bits respectively of this encoder.Interleaving of this output data done by using turbo-like
Interleaving Algorithm.


Figure-5 Rate: 1/2 convolutional coder with generator polynomials 171o, 133o.


Constellation mapping:
The output of the bit interleaver is entered serially to the constellation mapper. The input data to
the mapper is first divided into groups of number of coded bits per carrier, i.e., N
CBPC
bits and then converted into
complex numbers representing QPSK, 16-QAM or 64-QAM constellation points. The mapping for QPSK, 16-
QAM and 64-QAM is performed according to Gray-coding constellation mapping. The complex value number is
scaled by a modulation dependent normalization factor K
MOD
.


Table 2: Number of coded bit per carrier and normalization factor for different modulation constellations

Sub-carrier allocator:
The subcarrier allocator assigns the data constellations to the corresponding sub-
channels according to the subcarrier allocation method.


Pilot inserter:
The pilot inserter assigns pilots at fixed positions in the frequency domain within each OFDM data
symbol. Pilots can support the synchronization, channel estimation and tracking process.
IFFT:
Here we are using 2048 point IFFT for assigning data on 2048 orthogonal sub carriers.

Cyclic prefix inserter:
It is to prevent inter-symbol interference (ISI) eventually caused by the channel delay spread, the OFDM symbol is
extended by a cyclic prefix that contains the same waveform as the corresponding ending part of the symbol. Finally,
the OFDM signal is transferred to the RF transmission modules via a digital-to-analog converter.

Receiver Block diagram:



Figure 6: Receiver block diagram for the OFDMA

The OFDM receiver roughly implements the same operations as performed by the transmitter but in reverse order.
In addition to the data processing, synchronization and channel estimation must be performed at the receiver.

Implementation:

IEEE802.22 Baseband transmitter:
In this section there are RTL schematics and Pin description of implemented modules of transmitter included
to give brief description of functionality of modules.

Random Bit Generator: The random bit generator has start pin as enable signal when start is high for 1 clock
cycle the bit generator initialized with initialization vector and it will generate the random bits till next rising edge
comes in start. The bits generated at the rate of clock frequency.The output of bitgenerator is given to the input of
Scrambler.




Scrambler: This is single bit processing module. The scrambler has clock, reset, detain and data out pins. When
reset is high the scrambler is initialized with 0110111000100101. It will produce the data at the same rate the data
is entering.

BCC: BCC is a single bit processing module, It has clk, in, start, and output pins of single bit width. Start is
acting as reset pin for BCC. It will produce the output at bit rate twice of input by adding redundant bits. The clk
signal which is used in scrambler and RBG is given as clock signal to BCC.




Bit Interleaver: It is a single bit processing module having inputs clk, data in, reset. The clock input having
frequency twice of operating clk of scrambler and BCC. When reset is low, the interleaver will give interleaved data
at output. Here the interleaver is Designed using concept of Micro programmed control unit.


Channel coding: It is a single bit processing module. Total channel codding module having scrambler, BCC and
interleaver. It is having two clock inputs clk and clkby2. Clkby2 for scrambler and BCC, clk for interleaver. The
clk having frequency twice of clkby2. When reset is low the channel coder will encodes the data and produce the
output at the rate of twice of the input data rate.






Work to be done:

Implementation of Remaining modules in Transmitter (Constellation mapping, sub-carrier
allocation, IFFT).
Implementation of Complete Receiver Block Diagram
Complete ASIC Implementation of OFDMA Transceiver till GDSII file using Synopsys Design
Compiler and Cadence SOC encounter Tools.
Looking at the issues of IEEE 802.22 MAC LAYER.








References:

1. Cognitive Wireless RAN Medium Access Control (MAC) and Physical Layer (PHY) Specifications: policies and
procedures for operation in TV bands IEEE std 802.22 2011.

2. A reference Joaquin Garcia Rene cumplido,on the design of an FPGA-based OFDM Modulatorproceedings of
international conference on reconfiguarable computing and FPGAsator 2005.

3. Khaled sobhaihi,akram hammoudeh,David scammel FPGA Implementation of OFDM Transceiver for a 60Ghz wirelesss
Mobile Radio SystemIEEE computer society 2010 International conference on reconfigurable computing.

4. Article on Hardware implementation of bit interleaver for the IEEE 802.22 standard by Mehdi Ahmadi, Ali Azarpeyvand,
and Seid Mehdi Fakhraie School of Electrical and Computer Engineering,University of Tehran, Tehran, Iran.