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Xiaoyan Cheng
, Tao Yin
, Qisong Wu
, Yiping Jia
, and Haigang Yang
, Member, IEEE

System on Programmable Chip Research Department,
Institute of Electronics, Chinese Academy of Sciences, Beijing, China
The University of Chinese Academy of Sciences, Beijing, China
Corresponding Author:

A Field-Programmable Analog Array (FPAA) architecture
designed for intelligent sensory application is presented,
which consists of high performance and high flexible Con-
figurable Analog Blocks (CABs). The CAB is developed to
realize both continuous-time and discrete-time circuits for
achieving optimal performance in different applications. In
addition to employ coarse-grained reconfigurable CAB in
FPAA, a fine-grained reconfigurable amplifier in the CAB
is utilized to maximize programmability and flexibility. The
precision of the analog processing is enhanced by employ-
ing fat-tree interconnection network topology to minimize
the number of switches used in FPAA and using correlated
double sampling (CDS) techniques to suppress the offset
and noise. The FPAA is designed and implemented in
SMIC 0.18m CMOS process with a 3.3 V supply voltage.
An instrumental amplifier and a capacitive sensor signal
readout circuit are taken as application examples. The rela-
tive precision and dynamic range of the analog processing
are 97.6% and 119dB respectively.

With advancements of silicon technologies and microma-
chined transducers, more and more intelligent sensory chips
have appeared recently in automotive industries, smart
house/industry automation and biological recordings [1-3].
These intelligent chips often integrate high density pro-
grammable digital IPs , analog front-end circuitry, a MCU
core with peripherals and bus interconnections in a mono-
lithic chip for powerful performance. In digital domain, the
digital IPs often takes FPGA design methodology as a time
and cost efficient solution for most designers. However, in
analog domain, to meet the demand of a variety of sensor
interfaces, most microsystems have integrated various data
channels for various sensor signal acquisition and a wide
range of analog function modules such as signal conditioni-

Fig.1. A new design methodology based on FPAA for
Intelligent Sensory Chip
ng circuits, filters and AD/DA converters in the analog
front-end circuitry. These analog modules are usually fixed
and cannot adapt to different applications. This methodolo-
gy often cost large chip area and long design cycle time.
Analog systems able to cope with a wide spectrum of appli-
cations and interface circuits for versatile sensors with
smaller chip area and lower design cost become challenges
for most IC designers.
In this paper, we adopt Field-Programmable Analog Ar-
ray (FPAA) design methodology to substitute for the tradi-
tional design method in Analog Front-End block as shown
in Fig.1. The FPAA is composed of Configurable Analog
Blocks (CABs), IO interface blocks, interconnection net-
work and SPI configuration interface. As a new and effi-
cient solution for analog functions to fast prototyping,
FPAA design methodology can drastically reduce the costs
and time-to-market for system platform design. However,
the functions of most FPAA are limited to the basic analog
signal processing like the filter processing by far, rarely
designed for the sensor signal processing. To not only per-
form basic analog signal processing functions but also inter-
face different sensor signals in minutes, we present a new
FPAA to meet the demand.
This paper is organized as follows: the details of operat-
ing principle and implementation of FPAA are described in
Section 2 and Section 3, the results and application exam-
ples are demonstrated in Section4. In Section 5, the conclu-
sions are drawn.
*Research Supported by the CAS/SAFEA International Part-
nership Program for Creative Research Teams, National
High Technology Research and Develop Program of China
(2012AA012301) and National Science and Technology Ma-
jor Project of China (2013ZX03006004)
978-1-4799-0004-6/13/$31.00 2013 IEEE

Fig.2. The high-level architecture of FPAA with 4x4 CABs

The detailed architecture of FPAA is shown in Fig.2,
which is composed of 4x4 homogenous coarse-grained
CABs. The interconnection network of FPAA adopts fat-
tree type [4] which is a hierarchical network with the prop-
erty of area universality. Comparing with other intercon-
nection networks like crossbar and meshes, fat-tree is suit-
able for reconfigurable analog system. Almost a simple
analog function can be built by a few small analog blocks,
so there is no need to use the crossbar type to interconnect
all CABs, which has a area growth rate of O(N
) causing a
large delay due to parasitic capacitances from numbers of
connection switches. The types and scales of interconnec-
tion switch matrix (SM) are divided by the hierarchies of
FPAA shown in the Fig.2, including SMa, SMb, SMc and
SMd types. The symbol n in the label of Fig.2 represents
the number of channels output from CABs or matrices.
The FPAA outputs 4n channels to next stage for larger
scale or to the external interface directly.
To reduce the parasitic capacitance at the interface be-
tween I/Os and the CABs, the I/Os of the FPAA are not
designed as universal I/Os for all CABs, and are mainly
classified into three categories, including analog I/O (I/O
A), digital I/O (I/O D) and sensory I/O (In S) as shown in
Fig.2 for different signals delivering. The I/O D and I/O A
are respectively composed of programmable digital buffer
and programmable analog buffer to reduce interconnection
delay and isolate the pad capacitance. The signal from sen-
sors are directly connecting the channels of the local CABs
through the In_S I/O blocks, which is composed by CMOS
switch matrices, in which each switch has about 100
equivalent resistive value at common mode voltage varying
from 0~3.3V when it is turned on.





Fig.3. The architecture and local interconnections of CAB
The architecture of coarse-grained high performance and
high flexible CAB is shown in Fig.3. The CAB is compose-
d of two high flexible Sub_Cells and one comparator for
mixed signal functions. The sub-cells communicate with
comparator, analog I/O and reference sources by local in-
terconnections. Adopting local interconnections are used to
minimize the parasitic capacitances for better performance.
The Non_overlap_clock block can provide the two
Sub_Cells and comparator with 2 MHz, 1 MHz, 500 KHz
and 250 KHz non_overlap clock signals for discrete-mode
processing. The reference input block provides voltage ref-
erence and current reference to the CAB. Configuration
Registers for better connectivity is built in each CAB and
composed by shift registers to configure the connectivity of
the local interconnection network and to program the func-
tionality of the CABs.
3.1. The Architecture of Sub-cell
Fig.4 shows the architecture of sub-cell in the CAB , which
consists of a fined-grained reconfigurable amplifier with
passive components, two programmable SC cells (Cin1 and
Cin2) and differential correlated double sampling (CDS)
capacitors( C
and C
). The sub-cell can work under
continuous-mode or discrete-mode through reconfigura-
tions. Each programmable SC cell with four programmable
switches can be easily configured by two configuration bits
for four working modes: totally off, capacitor on, positive
resistor and negative resistor modes respectively. The
switches in programmable SC cells can be static configured
by shift registers or dynamic configured by non_overlap
The FPAA is capable of interfacing with different kinds
of sensor signals such as voltage, current, resistance and
capacitive signals. The sensor signals are sensitive to noise
and offset of the circuits, so the accuracy tolerance and dy-
namic range will be the key challenges to the sensor condi-
tioning circuits design. In this FPAA, for voltage and cur-
rent sensing, we adopt continuous-mode instrumentation
amplifier and transimpedance amplifier with a programma-
ble gain to reduce the nonideal effect of the switches such
as switch noise and clock charge injection compared with
the discrete mode. For meeting accuracy of capacitive sens-

Fig.4. The schematic of Sub-Cell with CDS techniques
or signals readout circuits, the full differential SC charge
amplifier is used to amplify micro capacitive signal in dis-
crete mode. For better noise performance and larger dynam-
ic range, we adopt the CDS [5] techniques to suppress the
offset and 1/f noise, and suppress the common mode noise
and clock charge injection by using full differential circuits.
3.2. Configurations of Core Amplifier
The core block in the Sub_Cell is the configurable amplifier
as shown in the Fig.5, which is consisted of folded-cascode
stage with rail to rail (R-R) input for large dynamic range
and classAB output stage. The architecture of R-R input
stage referenced [6] ensure constant slew rate over the en-
tire input common voltage range without consuming much
more power consumption comparing traditional 3xcurrent
mirror method. The R-R input stage can be configured as a
rail to rail input or common PMOS input stage by the con-
trol bit R as shown in the Fig.5.
There are mainly three kinds of configurations. For out-
put style configuration, the amplifier can be configured as
classAB single-ended output operation amplifier or as a
folded-cascode OTA with differential output. The output
configuration is controlled by the control bit S as shown
in the Fig.4 and the Fig.5. For performance configuration,
the GBW and the power consumption of amplifier can be
adjusted by programming biasing current sources (Ibias).
The simulation results of performances of configured clas-
sAB single-ended output operation amplifier are listed in
the Table I. For application configuration, the amplifier
assisted by passive components can not only be configured
as one stage amplifier, integrator, differentiator, adder, sub-
tracter or first order filters and so on , but also as TIA or
part of instrumentation amplifier for sensory processing.

Fig.5. The reconfigurable rail to rail input amplifier
Table 1. Performance of rail to rail reconfigurable
amplifier in single-ended output configuration
with 32pF||800 load
(Technology: 0.18um CMOS, V
= 3.3 V)
Bias Current(uA) 2.5 5 10 20
DC Gain(dB) 83 84 83 80
GBW(MHz) 8.5 9 16 26
Phase Margin() 73 82 75 64
Noise(nV/Hz)@1KHz 132 112 100 93
THD (dB)@(V
55 66 76 81
Power Consumption (mA) 0.73 0.83 1 1.3

The FPAA was implemented in a 0.18-um standard CMOS
technology at 3.3V power supply. To validate the proposed
FPAA, different applications circuits were mapped into the
FPAA and simulation results were extracted. These circuits
have been mainly chosen to characterize the FPAA for
sensory circuits due to the length of paper.
4.1. Implementation of Voltage Sensing Interface Cir-
cuit and Simulation Results
The voltage sensing interface circuit implemented by com-
mon three op-amps Instrumentation Amplifier (IA) can be
mapped into two CABs. The resistance value of Rout in the
Fig.4 can be programmed among 1~25 unit resistor. In the
simulation circuits, we set appropriate resistances for each
resistors in the IA to meet Vout=25Vin ideally. The fre-
quency of input signal is 10 KHz.
The curve fitting function of IA simulation results
shown in Fig.6 can be expressed as:
Vout =25.61Vin+1mV (2)
From the equation, we can get the relative precision of
micro voltage readout circuits is about 97.6% shown in
Fig.6. The deviation in slope is mainly caused by pro-
gramming switches connected in the resistors and can be
improved by reducing the equivalent resistance value of
switches. The differential input range of the analog signal
can be 1.65 1 V, for relative precision greater than
97.6%. The maximum input dynamic range can be
reached to 1.651.45V.

Fig.6. Simulation results of transfer function of micro
voltage readout circuit
4.2. Implementation of Capacitive Sensing Interface
Circuit and Simulation Results
The micro capacitive sensing interface circuit is built by
switched capacitor amplifier. The reference capacitors C
and C
shown in Fig.7 (a) are implemented with Cin1 and
Cin2 separately in a CAB shown in Fig.2. The reference
capacitors can be programmed between 0 and 32 units of
capacitance to adapt large input sensor capacitor range.
The output of capacitive sensing circuit is:

= ,

where C is (Cs
)/2. The circuit is capable of convert-
ing sensing capacitance from -2p to 2p with a nonlinearity
distortion less than 0.9 as shown in Fig.7(b), and with a
V-C gain of 0.315mV/fF. The minimum detectable capa-
citance of the readout circuitry reaches 8.3aF within 100Hz
sensor bandwidth, and the linearity range is 119dB. 1
and 2 are non_overlap clock, the 1d and 2d are the
delay of the 1 and 2 respectively.

This work presents a wide dynamic range and high preci-
sion FPAA for intelligent sensory applications which em-
ploys fat-tree interconnection network and high perfor-
mance IO interfaces. The coarse grained CABs combined
fine-grained reconfigurable core amplifier in this FPAA
can work under continuous-mode and discrete-mode to
maximize the flexibility and efficiency of the FPAA. In
order to achieve large dynamic range in the discrete mode,
FPAA adopted the CDS techniques and full differential
configuration for the high accurate capacitive sensing cir-
cuits. Through the above application demonstration, this
FPAA has been validated that it is an efficient solution for
the fast prototyping of intelligent sensory applications. The
FPAA can also process most of basic analog signal
processing functions on demand.

Fig.7. (a) Mapping of the micro capacitor sensing inter-
face circuit into two CABs

Fig.7. (b) Linearity performance of the capacitive
sensing interface circuit.

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