Problem 10.1
This problem explores in more detail the characteristics of the constantgm
reference. Refer to Figure 10.3.
Rather than choosing m=4, consider simply making m very large. In the limit,
the transconductance approaches a value that is twice what is obtain when m=4.
Show this formally by deriving an expression for the transconductance of M
1
if the
M
2
is S times wide as M
1
. To simply the derivation, neglect body effect and assume
that the PMOS mirror is an ideal 1:1 mirror.
I
REFN
Startup
Network
M
1
M
2
R
2
I
REFP
V
DD
Figure 10.13 Basic constantg
m
reference
Solution:
M
4
M
3
M
2
M
1
I
REF
I
out
(W/L)
P
(W/L)
P
(W/L)
N
S(W/L)
N
R
S
(a) From current mirror M
1
M
2
, we have
V
GS1
=V
GS2
+I
out
R
S
and assume V
th1
=V
th2
,
where ( )
2
1 1
1
2
1
th GS ox n REF
V V
L
W
C I

.

\

= and ( )
2
2 2
1
1
2
out n ox GS th
S
W
I C V V
L
 
=

\ .
1 1 2 2
1 1
2 2
out REF
GS th GS out S th out S
n ox n ox
I I
V V V I R V I R
W W
C C
L L
S
= + = + = + +
   
 
\ . \ .
2
1 2
1 1
2 2
out REF
th th out S
n ox n ox
I I
V V I R
W
C
L
S
W
C
L
+ = + +
   
 
\ . \ .
1 1
2 2
out REF
out S
n ox n ox
I I
I R
W W
C C
L L
S
= +
   
 
\ . \ .
(1)
(b) From current mirror M
3
M
4
, we have
V
GS3
=V
GS4
and assume V
th3
=V
th4
, where
( )
2
3 3
3
2
1
th GS ox p out
V V
L
W
C I

.

\

= and ( )
2
4 4
1
2
1
th GS ox p REF
V V
L
W
C I

.

\

=
3
2 2
3
3 3
2 2

.

\

+ = =

.

\

+ =
L
W
C
I
V V
L
W
C
I
V V
ox p
REF
th GS
ox p
out
th GS
3 3
2 2

.

\

=

.

\

L
W
C
I
L
W
C
I
ox p
REF
ox p
out
REF out
I I = (2)
Substitution of Eq.(2) into Eq.(1), we have
1 1
2 2
out out
out S
n ox n ox
I I
I R
W W
C C
L L
S
= +
   
 
\ . \ .
1
2 1
1
out
out S
n ox
I
I R
W S
C
L
 
=


 
\ .

\ .
1
2 1
1
out S
n ox
S
I R
W
C
L
 
=


 
\ .

\ .
3
2
2
1
2 1 1
1
out
S
n ox
S
I
W R
C
L
 
=


 
\ .

\ .
As expected, the current is independent of the supply voltage (but still a function
of process and temperature)
2
1
2
2
1
2
2
1
2 1
1
4 1
2 1
m
n ox out
S
n ox out
S
g
W
C I
L R
W
C I
L S R
S
 
 
=



\ .
\ .
 
 
=



\ .
\ .
2
2
1 2
1
4 1
m
S
S
g
R
 

\ .
=
1
1
2 1
m
S
S
g
R
 

\ .
=
Case 1: S=4, we have
1
1
1
2 1
2 1
4
1 2
m
S S S
g
R R R
 
 


\ . \ .
= = =
Case 2: S, we have
1
1
2 1
2
lim
m
S
S S
S
g
R R
 

\ .
= =
The assumption V
th1
=V
th2
introduces some error in the foregoing calculation
because of the sources of M
1
and M
2
are at difference voltage.
The transconductance of M
1
is determined geometric ratio only, independent of
powersupply voltage, process parameter, temperature, or any other parameters with
large variability.
4
The constant g
m
circuit exhibits little supply dependence if channellength
modulation is negligible. For this reason, relatively long channels are used for all of
the transistors in the circuit.
Problem 10.2
In the improved constantgm reference of Figure 10.14, investigate the effect of
PMOS mirror error caused nonzero output conduction. Model the PMOS devices as
square law; assume that they are ideal except for a channellength modulation of
0.1V
1
. Derive a general expression for the transconductance of M
1
, no longer
assuming that M
3
s V
g
, precisely equals the V
1
of M
1
.
M
2
R
2
I
REFP
+
_
I
REFN
Startup
Network
M
1
M
3
I
bias3
Figure 10.14 Improved constantg
m
reference
Solution:
M
2
R
2
I
REFP
+
_
I
REFN
Startup
Network
M
1
M
3
I
bias3
Figure 10.14 Improved constantg
m
reference
V
GS1
V
GS3 (W/L)
1
S(W/L)
1
Solution:
Let I
bias3
=I
REFN
=I
REFP
5
1 3 2 GS GS
V V I R = +
1 3 2 2
1 3
2 2
GS th GS th
n ox n ox
I I
V V V I R V I R
W W
C C
L L
= + = + = + +
   
 
\ . \ .
2
1 1
2 2
th th
n ox n ox
I I
V
S
V I R
W W
C C
L L
+ = + +
   
 
\ . \ .
2
1 1
2 2
n ox n ox
I I
I R
W W
C C
L
S
L
= +
   
 
\ . \ .
(1)
2
1
2 1
1
n ox
I
I R
W S
C
L
 
=


 
\ .

\ .
2
1
2 1
1
n ox
I R
W S
C
L
 
=


 
\ .

\ .
2
2
2
1
2 1 1
1
n ox
I
W R S
C
L
 
=


 
\ .

\ .
As expected, the current is independent of the supply voltage (but still a function
of process and temperature)
2
1
2
2
1 2
2
2
1 2
2 1
1
4 1
2 1
m
n ox
n ox
g
W
C I
L R S
W
C I
L R S
 
 
=



\ .
\ .
 
 
=



\ .
\ .
2
2
1 2
2
1
4 1
m
S
g
R
 

\ .
=
6
1
2
1
2 1
m
S
g
R
 

\ .
=
The assumption V
th1
=V
th2
introduces some error in the foregoing calculation
because of the sources of M
1
and M
2
are at difference voltage.
The transconductance of M
1
is determined geometric ratio only, independent of
powersupply voltage, process parameter, temperature, or any other parameters with
large variability.
The constant g
m
circuit exhibits little supply dependence if channellength
modulation is negligible. For this reason, relatively long channels are used for all of
the transistors in the circuit.
7
Problem 10.3
Using the simple circuit of the first problem, select device sizes and resistor
value to produce an output current sink of 250uA and a transconductance of 1mS at
300K. Use the level3 device parameters from Chapter 5 and simulate with SPICE
to verify that the design works as desired.
Problem 10.4
The equations for the CMOScompatible bandgap reference do not take finite
pnp into account. Unfortunately, typical values for of such transistors are often
below 10. Rederive the expression for the output voltage including .
Problem 10.5
In this problem, we consider the settling behavior of a nonideal voltage
reference in response to a transient disturbance. Consider the popular circuit shown
in Figure 10.15. Assume that each transistor is 10um wide and that V
DD
is 3V. Use
the level3 device model given in Chapter 5.
(a) Choose Iref to make the output voltage 1V.
(b) What is the lowfrequency incremental output resistance
(c) Now consider what happen if the reference voltage must drive a total load of
3 pF and if a disturbance happens to bump the output voltage to 1.5V in 1ns
(e.g. with a fastacting current source). Calculate the settling time to 1% of
the original value of 1V (you may neglect body effect in your hand
calculations) and verify your answer with SPICE. Explain discrepancy
quantitatively.
M
2
M
1
V
DD
V
REF
Figure 10.15 V
gs
based voltage reference
Solution:
Problem 10.6
8
In lowvoltage circuits, it becomes difficult or impractical to use ordinary
cascade structures to increase the output resistance of current sources. Alternative
cascading techniques can be used to reduce the voltage required, however. An
example is sketched in Figure 10.16.
M
1
M
4
M
2
M
5
M
3
I
out
Figure 10.16 Lowheadroom cascode
V
BIAS
In this circuit, M
1
establishes a bias voltage for the gates of M
4
and M
5
. A
typical rule thumb is to make M
1
about 1/4 the width of all the other transistors.
However, one can place the design of this circuit on a more rational basis. If we call
S the ratio W/L, assume that S
2
=S
3
=n
2
S
4
=n
2
S
5
=S, where n>1.
Assume zero output conductance in saturation and neglect body effect. Derive
explicitly the condition on S
1
in terms of S and n so that M
2
and M
3
are biased on
edge of saturation. You may assume squarelaw behavior.
Solution:
I
bias
W/[Ln
2
]
W[/L(n+1)
2
]
W/L W/L
M
5
M
4
M
3
M
2
M
1
I
out
=I
in I
bias
W/L
I
out
=I
in
W/L
I
bias
M
5
M
4
M
3
M
2
M
1
I
bias
W[/L(n+1)
2
]
W/[Ln
2
] W/[Ln
2
] W/[Ln
2
]
The reason for including M
4
is to lower the drainsource voltage (V
ds2
) of
M
2
so that it is matched to the drainsource voltage (V
ds3
) of M
3
.
( )
( )
( ) ( )
( ) ( )( ) ( )
1 5 2
2 2
1 2 2
1 2
1 1
2 2
1
1 1
D D D
n ox GS th n ox GS th
GS th GS th eff
I I I
W
W
L
C V V C V V
L
n
V V n V V n V
= =
(
(
(
=
(
(
+
(
= + = +
9
The voltage at the gate of M
5
5 1 G GS
V V =
The minimum drain voltage of M
5
must satisfies V
D5
V
G5
V
th
( )
5 5 1
1
D G th GS th eff
V V V V V n V > = = +
In the ideal circuit design in the above Figure, the transistors M
2
and M
4
are
biased exactly at the transition point between the saturation and nonsaturation
regions. The analysis has neglected the body effect, so threshold voltages will not be
exactly equal. In an actual circuit design, therefore, the size of M
1
will be made
slightly smaller to ensure transistors are biased in the saturation region. (Perhaps, the
size of M
2
is W/5L).
Problem 10.7
Repeat the previous problem for shortchannel devices, expressing your answer
in part in terms of E
sat
. Note in particular that shortchannel effects are helpful here
because the saturation voltage diminishes, allowing operation at lower supply voltage.
Solution:
Problem 10.8
Another lowheadroom current source is shown in Figure 10.17. Assume for
simplicity that all widths are equal. Determine an expression for R that guarantees
that both M
1
and M
2
are in saturation. Assume longchannel behavior, and neglect
body effect and channellength modulation.
10
R
I
REF
M
2
M
1
M
4
M
3
I
out
Figure 10.17 Alternative lowheadroom cascode current source
Solution:
Question: How to get a HighSwing current mirror?
Answer: Let the gate voltage of M
4
is V
th
+2V
eff
Add a dc level shift V
th
between the gates of M
3
and M
4
.
M
2
M
1
I
REF
I
OUT
R
OUT
V
OUT
M
4
M
3
+
V
th
+V
eff

+
V
eff

+
V
th
+V
eff

+
V
eff

I
OUT
V
OUT
V
MIN
2V
eff
2V
th
+2V
eff
V
th
Importance: The gate voltae of M
4
is V
th
+2V
eff
Find V
G3
V
G3
=V
GS1
+V
GS3
=2(V
th
+V
eff
)
Find V
G4
V
G4
=V
G3
V
th
=2(V
th
+V
eff
)V
th
=V
th
+2V
eff
Find V
DS2
V
DS2
=V
G4
V
GS4
= (V
th
+2V
eff
)(V
th
+V
eff
)=V
eff
Find minimumV
DS4
The minimum drainsource V
DS
voltage that keeps M4 at the active region is V
eff
11
V
DS4
V
eff
Find minimum V
OUT
V
DS4
=V
DS2
+V
DS4
(V
eff
)+V
eff
=2V
eff
If the gate voltage of M
4
is V
th
+2V
eff
, then you can get the highswing current
mirror.
SelfBiased highswing cascode current source
M
2
M
4
M
3
M
1
R
I
REF
V
OUT
+
V
T
+V
ON

V
T
+V
ON
+
V
ON

V
T
+2V
ON
i
OUT
Problem 10.9
A variation on the constantgm bias cell avoids error due to backgate bias (body
effect) by forcing the source terminals of both NMOS devices to be at the same
potential; see Figure 10.18. Show that the output current is determined only by
transistor geometry and resistor value. As before, ignore body effect and assume
zero output conductance and identical transistors (except for M
4
), which is S times as
wide as the others). Show that the transconductance of M
5
depends only on
geometry and the reference resistor R.
M
1
M
2
M
3
M
4
M
5
I
out
Figure 10.18. Alternative constantg
m
reference
R
W/L S(W/L)
12
Solution:
Case 1: Assume the gain of opamp is infinite and M
3
and M
4
are operated in the
subthreshold region, we have V+=V
exp 1 exp
exp
GS th DS
D t
T T
GS th
D t
T
V V V W
I I
L nV V
V V W
I I
L nV
(    
=
(  
\ . \ .
 
~

\ .
Paul Gray pp.67 Eq.(1.252)
4
ln
GS th T
t
I
V V nV
W
S I
L
(
(
( ~ +
 
(

(
\ .
4
ln
GS th T
t
I
V V nV
W
I
L
(
(
( ~ +
 
(

(
\ .
4 3 GS GS
I R V V + =
ln ln
th T th T
t t
I I
I R V nV V nV
W W
S I I
L L
( (
( (
( ( + + = +
   
( (
 
( (
\ . \ .
ln ln ln
T T T
t t t
I I I
I R nV nV nV
W W W
S I I S I
L L L
( ( (
( ( (
( ( ( + =
     
( ( (
  
( ( (
\ . \ . \ .
ln
t
T
t
I
W
I
L
I R nV
I
W
S I
L
(
(
 
(

\ .
(
=
(
(
 
(

(
\ .
( ) ln
T
nV S
I
R
= ,where V
T
is the thermal voltage
Warning: n is dependent of process and V
T
also is dependent on
temperature.
Case 2: Assume the gain of opamp is infinite and M
3
and M
4
are operated in the
saturation region, we have V+=V
13
4 3 GS GS
I R V V + =
2 2
th th
n ox n ox
I I
I R V V
W W
C C
L L
S
( (
( (
( (
+ =
    ( (
 
( (
\ . \ .
2 2
n ox n ox
I I
I R
W W
L
S C C
L
+ =
   
 
\ . \ .
2 2
n ox n ox
I I
I R
W W
C C
L L
S
=
   
 
\ . \ .
2 1
1
n ox
I
I R
W
S
C
L
 
=

 
\ .

\ .
2 1
1
n ox
I R
W
S
C
L
 
=

 
\ .

\ .
2
2
2 1
1
n ox
I R
W
S
C
L
(
(
 
(
=

  (
\ .

(
\ .
2
2
2 1
1
n ox
I R
W
S
C
L
 
=

 
\ .

\ .
2
2
2 1
1
n ox
W
S
C
L
I
R
 

 
\ .

\ .
=
2
2
1
2 1
n ox
S
I
W
C R
L
 

\ .
=
 

\ .
Warning:
n ox
C is dependent on process.
Problem 10.10
(a) In the circuit of the previous problem, does the polarity of the opamp
matter? Explain qualitatively why it most certainly does, and how it behaves if the
14
polarity is incorrect.
(b) To answer (a) most quantitatively, derive an explicit expression for the
loop transmission of the circuit by breaking the loop at the output of the opamp,
driving the commongate connection of M
1
and M
2
, and observing what comes back
from the opamp output. Watch your signs?
Problem 10.11
Selfbiased circuits abound in this chapter, and we have alluded to the necessity
of startup circuits without actually showing any specific example. Consider the
bandgap reference circuit of Figure 10.19 as an example. Assume that the core of
the bandgap has 100uA of current flowing in each branch.
Q
1
R
1
=6.07K
Q
2
R
2
=6.7K
M
1
I
out
M
4
M
3
M
2
M
9
M
6
M
7
M
8
M
5
u
n
C
ox
=100uA/V
2
u
p
C
ox
=40uA/V
2
V
tN
=0.6V
V
tp
=0.9V
V
BE1
=0.713V
V
BE2
=0.650V
Figure 10.19 CMOS bandgap reference with startup circuit example
Solution:
15
Q
1
R
1
=6.07K
Q
2
R
2
=6.7K
M
1
I
out
M
4
M
3
M
2
M
9
M
6
M
7
M
8
M
5
Step 1
Q
1
R
1
=6.07K
Q
2
R
2
=6.7K
M
1
I
out
M
4
M
3
M
2
M
9
M
6
M
7
M
8
M
5
Step 2
Q
1
R
1
=6.07K
Q
2
R
2
=6.7K
M
1
I
out
M
4
M
3
M
2
M
9
M
6
M
7
M
8
M
5
Step 3
Q
1
R
1
=6.07K
Q
2
R
2
=6.7K
M
1
I
out
M
4
M
3
M
2
M
9
M
6
M
7
M
8
M
5
Step 4
16
Problem 10.12 please visit the following website
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