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Waqar Ahmad

Department of Electrical Engineering


VLSI Design
Lecture 3
(CMOS Fabrication and Layout)
Wafer Preparation
VLSI
Design
2
Photolithography
Used to print desired patterns on wafer
The feature size directly depends on the wavelength of your
lithographic system
UV light
Reticle field size
20 mm 15mm,
4 die per field
5:1 reduction lens
Wafer
Image exposure on
wafer 1/5 of reticle
field
4 mm 3 mm,
4 die per exposure
Serpentine
stepping
pattern
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Design
3
oxidation
optical
mask
process
step
photoresist coating photoresist
removal (ashing)
spin, rinse, dry
acid etch
photoresist
stepper exposure
development
Typical operations in a single
photolithographic cycle (from [Fullman]).
Photo-Lithographic Process
VLSI
Design
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Fabricating one transistor
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Design
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Oxidation
(Field oxide)
Silicon substrate
Silicon dioxide Silicon dioxide
oxygen
Photoresist
Develop
oxide oxide
Photoresist
Coating
photoresist photoresist
Mask-Wafer
Alignment and Exposure
Mask
UV light
Exposed
Photoresist
exposed
photoresist
exposed
photoresist
G
S D
Active
Regions
top nitride
S D
G
silicon nitride silicon nitride
Nitride
Deposition
Contact
holes
S D
GG
Contact
Etch
Ion
Implantation
ox
D
G
Scanning
ion beam
S
Metal
Deposition and
Etch
drain
S D
GG
Metal
contacts
Polysilicon
Deposition
polysilicon polysilicon
Silane gas
Dopant gas
Oxidation
(Gate oxide)
gate oxide gate oxide
oxygen
Photoresist
Remove
oxide oxide
Ionized oxygen gas
Oxide
Etch
photoresist photoresist
oxide oxide
Ionized CF
4
gas
Polysilicon
Mask and Etch
oxide oxide
Ionized CCl
4
gas
CMOS Fabrication
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Design
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CMOS transistors are fabricated on silicon wafer
Lithography process similar to printing press
On each step, different materials are deposited or etched
Easiest to understand by viewing both top and cross-section
of wafer in a simplified manufacturing process
CMOS Top View
n+
p
Gate Source Drain
bulkSi
SiO
2
Polysilicon
n+
SiO
2
n
Gate Source Drain
bulk Si
Polysilicon
p+ p+
7
Inverter Cross-section
Typically use p-type substrate for nMOS transistors
Requires n-well for body of pMOS transistors
n+
p substrate
p+
n well
A
Y
GND
V
DD
n+ p+
SiO
2
n+ diffusion
p+ diffusion
polysilicon
metal1
nMOS transistor pMOS transistor
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Design
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Well and Substrate Taps
Substrate must be tied to GND and n-well to V
DD
Metal to lightly-doped semiconductor forms poor
connection called Shottky Diode
Use heavily doped well and substrate contacts / taps
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Design
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Inverter Mask Set
Transistors and wires are defined by masks
Cross-section taken along dashed line
GND V
DD
Y
A
substrate tap
well tap
nMOS transistor pMOS transistor
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Design
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Detailed Mask Views
Six masks
n-well
Polysilicon
n+ diffusion
p+ diffusion
Contact
Metal
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Design
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CMOS Process at a Glance
Define active areas
Etch and fill trenches
Implant well regions
Deposit and pattern
polysilicon layer
Implant source and drain
regions and substrate contacts
Create contact and via windows
Deposit and pattern metal layers
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Design
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Patterning of SiO2
Si-substrate
Si-substrate
Si-substrate
(a) Silicon base material
(b) After oxidation and deposition
of negative photoresist
(c) Stepper exposure
Photoresist
SiO
2
UV-light
Patterned
optical mask
Exposed resist
SiO
2
Si-substrate
Si-substrate
Si-substrate
SiO
2
SiO
2
(d) After development and etching of resist,
chemical or plasma etch of SiO
2
(e) After etching
(f) Final result after removal of resist
Hardened resist
Hardened resist
Chemical or plasma
etch
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Design
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Photolithography
Step 1 n-well Formation
Step 2 Active Region Formation
Step 3 Polysilicon Gate
Step 4 p-type and n-type diffusion
Step 5 Metal Contact Formation
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Design
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1.1 Oxidation & Photoresist
Form N-Well regions
Grow oxide
Deposit photoresist
Two types
Positive Tone
The area exposed to
light dissolves
(softens)
Negative Tone
The area exposed to
light remains
(hardens)
Layout view
Cross section view
p-type substrate
NWELL mask
NWELL mask
oxide
photoresist
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Design
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1.2 Lithography
Form N-Well regions
Grow oxide
Deposit photoresist
Pattern photoresist
NWELL Mask
expose only n-well areas
Layout view
Cross section view
p-type substrate
NWELL mask
NWELL mask
oxide
photoresist
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Design
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1.3 Etch
Form N-Well regions
Grow oxide
Deposit photoresist
Pattern photoresist
NWELL Mask
expose only n-well areas
Etch oxide
Etch oxide with hydrofluoric
acid (HF)
Only attacks oxide where
resist has been exposed
Remove photoresist
Use mixture of acids called
piranah etch
Necessary so resist doesnt
melt in next step
Layout view
Cross section view
p-type substrate
oxide
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Design
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1.4 Well Formation
Form N-Well regions
Grow oxide
Deposit photoresist
Pattern photoresist
NWELL Mask
expose only n-well areas
Etch oxide
Remove photoresist
Diffuse n-type dopants
through oxide mask layer
Diffusion
Place wafer in furnace with
arsenic gas
Heat until As atoms diffuse
into exposed Si
Ion Implanatation
Blast wafer with beam of As
ions
Ions blocked by SiO2, only
enter exposed Si
Layout view
Cross section view
p-type substrate
n-well
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Design
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1.5 Strip Oxide
Form N-Well regions
Grow oxide
Deposit photoresist
Pattern photoresist
NWELL Mask
expose only n-well areas
Etch oxide
Remove photoresist
Diffuse n-type dopants
through oxide mask layer
Strip off the remaining
oxide using HF
Layout view
Cross section view
p-type substrate
n-well
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Design
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2.1 Spin Resist
Form Active Regions
Deposit SiN over wafer
Deposit photoresist
over SiN layer
ACTIVE mask
ACTIVE mask
SiN
photoresist
p-type substrate
n-well
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Design
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2.2 Masking for Diffusion
Form Active Regions
Deposit SiN over wafer
Deposit photoresist over
SiN layer
Pattern photoresist
*ACTIVE MASK
ACTIVE mask
SiN
photoresist
p-type substrate
n-well
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Design
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ACTIVE mask
2.3 Etching
Form Active Regions
Deposit SiN over wafer
Deposit photoresist over
SiN layer
Pattern photoresist
*ACTIVE MASK
Etch SiN in exposed
areas
leaves SiN mask which
blocks oxide growth
SiN
photoresist
p-type substrate
n-well
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Design
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ACTIVE mask
2.4 Oxide Growth
Form Active Regions
Deposit SiN over wafer
Deposit photoresist over SiN
layer
Pattern photoresist
*ACTIVE MASK
Etch SiN in exposed areas
leaves SiN mask which blocks
oxide growth
Remove photoresist
Grow Field Oxide
(FOX)
thermal oxidation
p-type substrate
n-well
FOX
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Design
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ACTIVE mask
2.5 Strip Oxide
Form Active Regions
Deposit SiN over wafer
Deposit photoresist over SiN
layer
Pattern photoresist
*ACTIVE MASK
Etch SiN in exposed areas
leaves SiN mask which blocks
oxide growth
Remove photoresist
Grow Field Oxide (FOX)
thermal oxidation
Remove SiN
p-type substrate
n-well
FOX
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Design
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ACTIVE mask
3.1 Thin Gate Oxide
Form Gate (Poly layer)
Grow thin Gate Oxide
over entire wafer
negligible effect on FOX
regions
gate oxide
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Design
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POLY mask
3.2 Deposit Poly & Photoresist
Form Gate (Poly layer)
Grow thin Gate Oxide
over entire wafer
negligible effect on FOX regions
Deposit Polysilicon
Chemical Vapor
Deposition (CVD) of
silicon layer
Place wafer in furnace
with Silane gas (SiH4)
Forms many small
crystals called polysilicon
Heavily doped to be good
conductor
Deposit Photoresist
gate oxide
POLY mask
POLY mask
polysilicon
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Design
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3.3 Lithography
Form Gate (Poly layer)
Grow thin Gate Oxide
over entire wafer
negligible effect on FOX regions
Deposit Polysilicon
Deposit Photoresist
Pattern Photoresist
*POLY MASK
Etch Poly in exposed
areas
Etch/remove Oxide
gate protected by poly
gate oxide
POLY mask
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Design
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POLY mask
3.4 Etch
Form Gate (Poly layer)
Grow thin Gate Oxide
over entire wafer
negligible effect on FOX
regions
Deposit Polysilicon
Deposit Photoresist
Pattern Photoresist
*POLY MASK
Etch Poly in exposed areas
Etch/remove Oxide
gate protected by poly
gate oxide
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Design
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POLY mask
4.1 Photoresist
Form pmos S/D
Cover with photoresist
PSELECT mask
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Design
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PSELECT mask
4.2 Masking
Form pmos S/D
Cover with photoresist
Pattern photoresist
*PSELECT MASK
PSELECT mask
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Design
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PSELECT mask
4.3 p-type doping
Form pmos S/D
Cover with photoresist
Pattern photoresist
*PSELECT MASK
Implant p-type dopants
P-diffusion forms pMOS
source, drain, and p-
substrate contact
Polysilicon is better than
metal for self-aligned gates
because it doesnt melt
during later processing
Remove photoresist
p+ dopant
p+ dopant
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Design
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PSELECT mask
4.4 Photoresist
Form nmos S/D
Cover with photoresist
NSELECT mask
p+ p+ p+
n
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Design
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NSELECT mask
4.5 Masking
Form nmos S/D
Cover with photoresist
Pattern photoresist
*NSELECT MASK
NSELECT mask
p+ p+ p+
n
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Design
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NSELECT mask
4.6 n-type doping
Form nmos S/D
Cover with photoresist
Pattern photoresist
*NSELECT MASK
Implant n-type dopants
N-diffusion forms nMOS
source, drain, and n-well
contact
Remove photoresist
n+ dopant
n+ dopant
p+ p+ p+
n
n+ n+ n+
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Design
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NSELECT mask
5.1 Spin Resist
Form Contacts
Deposit oxide
Deposit photoresist
CONTACT mask
p+ p+ p+
n
n+ n+ n+
CONTACT mask
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Design
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5.2 Masking
Form Contacts
Deposit oxide
Deposit photoresist
Pattern photoresist
*CONTACT Mask
One mask for both active
and poly contact shown
CONTACT mask
p+ p+ p+
n
n+ n+ n+
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Design
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CONTACT mask
5.3 Etch
Form Contacts
Deposit oxide
Deposit photoresist
Pattern photoresist
*CONTACT Mask
One mask for both active
and poly contact shown
Etch oxide
p+ p+ p+
n
n+ n+ n+
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Design
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CONTACT mask
5.4 Deposit Metal 1
Form Contacts
Deposit oxide
Deposit photoresist
Pattern photoresist
*CONTACT Mask
One mask for both active and
poly contact shown
Etch oxide
Remove photoresist
Deposit metal1
immediately after opening
contacts so no native oxide
grows in contacts
Planerize
make top level
p+ p+ p+
n
n+ n+ n+
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Design
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CONTACT mask
5.5 Further Metal Layers
Rest of metal layers
follow similarly
p+ p+ p+
n
n+ n+ n+
p-type substrate
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Design
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METAL2 mask
Metalization
Sputter on aluminum over whole wafer
Pattern to remove excess metal, leaving wires
Metal
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Design
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Advanced Metallization
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Design
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Advanced Metallization
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Design
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Twin-Well CMOS Process
Separate optimization of
NMOS and PMOS
Vth, body effect and channel
transconductance
Reduces unbalanced drain
parasitics
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Design
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Silicon-on-Insulator (SOI)
Insulating substrate instead of silicon
Improved speed and latch up susceptibility
Independent NMOS and PMOS creation
Higher integration density (no wells), avoidance of latch-up
problem and low parasitics
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Design
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Design Rules
and
Layout
Layout
Chips are specified with set of masks
Minimum dimensions of masks determine transistor size (and
hence speed, cost, and power)
Feature size f = distance between source and drain
Set by minimum width of polysilicon
Feature size improves 30% every 3 years or so
Normalize for feature size when describing design rules
Express rules in terms of = f/2
E.g. = 0.3 m in 0.6 m process
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Design
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p-substrate
n-well
n+
p+
Gate oxide
Gate (polysilicon)
Field Oxide
Insulated glass
Provide electrical isolation
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Design
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Layer Types
CMOS Process Layers Color Coding
Layer
Polysilicon
Well (p,n)
Active Area (n+)
Color Representation
Yellow
Green
Red
Metal1
Metal2
Blue
Magenta
Contact To Poly
Contact To Diffusion
Via
Black
Black
Black
Select (n+)
Green
Active Area (p+)
Beige
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Design
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Layers in 0.25 m CMOS process
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Design
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Two major approaches:
Micron rules: stated at micron resolution.
rules: simplified micron rules with limited scaling attributes.
Design rules represents a tolerance which insures very high
probability of correct fabrication
scalable design rules: lambda parameter
absolute dimensions (micron rules)
In reality, Design rules are determined by experience
VLSI
Design
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Design Rule Conventions
All minimum sizes and spacing specified in microns.
Rules don't have to be multiples of .
Can result in 50% reduction in area over based rules
Standard in industry.
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Design
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Micron Rules
Lambda-based (scalable CMOS) design rules define
scalable rules based on (which is half of the
minimum channel length)
Stick diagram is a draft of real layout, it serves as an
abstract view between the schematic and layout.
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Design
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Lambda-based Design Rules
Circuit designer in general want tighter, smaller layouts
for improved performance and decreased silicon area.
On the other hand, the process engineer wants design
rules that result in a controllable and reproducible
process.
All widths, spacing, and distances are written in the
form of = 0.5 X minimum drawn transistor length
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Design
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Lambda-based Design Rules Need
Design rules based on single parameter,
Simple for the designer
Wide acceptance
Minimum feature size is defined as 2
Prevents shorting, opens, contacts from slipping out of
area to be contacted
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Design
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Lambda-based Design Rules Advantages
Minimum width of PolySi and diffusion line = 2
Minimum width of Metal line = 3 as metal lines run over a
more uneven surface than other conducting layers to ensure
their continuity
2
Metal
Diffusion
Polysilicon
3
2
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Design
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Lambda-based Design Rules
PolySi PolySi space 2
Metal - Metal space 2
Diffusion Diffusion space 3. To avoid the possibility of their
associated regions overlapping and conducting current
2
Metal
Diffusion
Polysilicon
2
3
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Design
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Lambda-based Design Rules
Diffusion PolySi space . To prevent the lines overlapping to
form unwanted capacitor
Metal lines can pass over both diffusion and polySi without
electrical effect. Where no separation is specified, metal lines
can overlap or cross

Metal
Diffusion
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Design
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Lambda-based Design Rules
Metal lines can pass over both diffusion and polySi without
electrical effect
However, it is recommended practice to leave between a
metal edge and a polySi or diffusion line to which it is not
electrically connected

Metal
Polysilicon
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Design
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Lambda-based Design Rules
Vias and Contacts
1
2
1
Via
Metal to
Poly Contact
Metal to
Active Contact
1
2
5
4
3 2
2
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Design
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Design
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Lambda-based Design Rules Simplified
Wiring Tracks
A wiring track is the space required for a wire
4 width, 4 spacing from neighbor = 8 pitch
Transistors also consume one wiring track
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Design
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Well spacing
Wells must surround transistors by 6
Implies 12 between opposite transistor flavors
Leaves room for one wire track
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Design
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6
2
6
2
3
All device mask dimensions are based on multiples of , e.g., polysilicon minimum
width = 2. Minimum metal to metal spacing = 3
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Design
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Lambda-based Design Rules Example
Inverter Layout
Transistor dimensions specified as Width / Length
Minimum size is 4 / 2, sometimes called 1 unit
In f = 0.6 m process, this is 1.2 m wide, 0.6 m long
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Design
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Gate Layout
Layout can be very time consuming
Design gates to fit together nicely
Build a library of standard cells
Standard cell design methodology
V
DD
and GND should abut (standard height)
Adjacent gates should satisfy design rules
nMOS at bottom and pMOS at top
All gates include well and substrate contacts
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Design
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Example: Inverter
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Design
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CMOS Inverter Layout
A A
n
p-substrate Field
Oxide
p
+
n
+
In
Out
GND V
DD
(a) Layout
(b) Cross-Section along A-A
A
A
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Design
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Sticks Diagram
1
3
In
Out
V
DD
GND
Stick diagram of inverter
Dimensionless layout entities
Only topology is important
Final layout generated by
compaction program
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Design
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Example: 3-input NAND Layout
Horizontal N-diffusion and p-diffusion strips
Vertical polysilicon gates
Metal1 V
DD
rail at top
Metal1 GND rail at bottom
32 by 40
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Design
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Example: 3-input NAND Stick Diagrams
Stick diagrams help plan layout quickly
Need not be to scale
Draw with color pencils or dry-erase markers
c
A
V
DD
GND
Y
A
V
DD
GND
B C
Y
INV
metal1
poly
ndiff
pdiff
contact
NAND3
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Design
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Area Estimation
Estimate area by counting wiring tracks
Multiply by 8 to express in
32
40
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71
Example: O3AI Gate
Sketch a stick diagram for 4-input gate

( )
Y A B C D = + +
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72
Packaging
Packaging Requirements
Electrical: Low parasitics
Mechanical: Reliable and robust
Thermal: Efficient heat removal
Economical: Cheap
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Design
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Bonding Techniques
Lead Frame
Substrate
Die
Pad
Wire Bonding
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Design
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Tape-Automated Bonding (TAB)
(a) Polymer Tape with imprinted
(b) Die attachment using solder bumps.
wiring pattern.
Substrate
Die
Solder Bump
Film + Pattern
Sprocket
hole
Polymer film
Lead
frame
Test
pads
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Design
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Flip-Chip Bonding
Solder bumps
Substrate
Die
Interconnect
layers
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Design
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Package-to-Board Interconnect
(a) Through-Hole Mounting
(b) Surface Mount
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Design
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References
Contents of this lecture are courtesy of
Neil H. E. Weste
Nivedita Shettar
Jan M. Rabaey
A. Mason