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KARUR

Prepared by
T.Thamaraimanalan
Assistant Professor/ECE
VSBEC DE Lab Manual
CONTENTS
1. Design and implementation of Adders and Subtractors using logic gates.
2. Design and implementation of code converters using logic gates
i! BCD to e"cess#$ code and voice versa
ii! Binar% to gra% and vice#versa
$. Design and implementation of & bit binar% Adder' subtractor and BCD
adder using (C )&*$
&. Design and implementation of 2Bit Magnitude Comparator using logic
gates * Bit Magnitude Comparator using (C )&*+
+. Design and implementation of 1, bit odd'even parit% c-ec.er 'generator
using (C)&1*/.
,. Design and implementation of Multiple"er and De#multiple"er using
logic gates and stud% of (C)&1+/ and (C )&1+&
). Design and implementation of encoder and decoder using logic gates
and stud% of (C)&&+ and (C)&1&)
*. Construction and verification of & bit ripple counter and Mod#1/ ' Mod
12 0ipple counters
1. Design and implementation of $#bit s%nc-ronous up'do2n counter
1/. (mplementation of S(S34 S(534 5(S3 and 5(53 s-ift registers using
6lip# flops.
11. Design of e"periments 14 ,4 *4 1/ using Verilog 7DL.
5repared b%8 9.9-amaraimanalan. A5'ECE 2
VSBEC DE Lab Manual
5repared b%8 9.9-amaraimanalan. A5'ECE $
VSBEC DE Lab Manual
5repared b%8 9.9-amaraimanalan. A5'ECE &
VSBEC DE Lab Manual
EXPT NO. : DESIN O! ADDE" AND S#$T"ACTO"
DATE :
AI%:
9o design and construct -alf adder4 full adder4 -alf subtractor and full
subtractor circuits and verif% t-e trut- table using logic gates.
APPA"AT#S "E&#I"ED:
Sl.:o. C3M53:E:9 S5EC(6(CA9(3: ;9<.
1. A:D =A9E (C )&/* 1
2. >#30 =A9E (C )&*, 1
$. :39 =A9E (C )&/& 1
&. 30 =A9E (C )&$2 1
$. (C 90A(:E0 ?(9 # 1
&. 5A9C7 C30DS # 2$
T'EO"(:
'A)! ADDE":
A -alf adder -as t2o inputs for t-e t2o bits to be added and t2o
outputs one from t-e sum @ SA and ot-er from t-e carr% @ cA into t-e -ig-er
adder position. Above circuit is called as a carr% signal from t-e addition of
t-e less significant bits sum from t-e >#30 =ate t-e carr% out from t-e
A:D gate.
!#)) ADDE":
5repared b%8 9.9-amaraimanalan. A5'ECE +
VSBEC DE Lab Manual
A full adder is a combinational circuit t-at forms t-e arit-metic sum
of inputB it consists of t-ree inputs and t2o outputs. A full adder is useful to
add t-ree bits at a time but a -alf adder cannot do so. (n full adder sum
output 2ill be ta.en from >#30 =ate4 carr% output 2ill be ta.en from 30
=ate.
'A)! S#$T"ACTO":
9-e -alf subtractor is constructed using >#30 and A:D =ate. 9-e
-alf subtractor -as t2o input and t2o outputs. 9-e outputs are difference and
borro2. 9-e difference can be applied using >#30 =ate4 borro2 output can
be implemented using an A:D =ate and an inverter.
!#)) S#$T"ACTO":
9-e full subtractor is a combination of >#304 A:D4 304 :39 =ates.
(n a full subtractor t-e logic circuit s-ould -ave t-ree inputs and t2o outputs.
9-e t2o -alf subtractor put toget-er gives a full subtractor .9-e first -alf
subtractor 2ill be C and A B. 9-e output 2ill be difference output of full
subtractor. 9-e e"pression AB assembles t-e borro2 output of t-e -alf
subtractor and t-e second term is t-e inverted difference output of first >#
30.
)OIC DIA"A%:
5repared b%8 9.9-amaraimanalan. A5'ECE ,
VSBEC DE Lab Manual
'A)! ADDE"
T"#T' TA$)E:
A $ CA""( S#%
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S#% . A/$ 0 A$/ CA""( . A$
)OIC DIA"A%:
5repared b%8 9.9-amaraimanalan. A5'ECE )
VSBEC DE Lab Manual
!#)) ADDE"
!#)) ADDE" #SIN T1O 'A)! ADDE"
T"#T' TA$)E:
A $ C CA""( S#%
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S#% . A/$/C 0 A/$C/ 0 A$C/ 0 A$C
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VSBEC DE Lab Manual
,-%ap for CA""(:
CA""( . A$ 0 $C 0 AC
)OIC DIA"A%:
'A)! S#$T"ACTO"
T"#T' TA$)E:
A $ $O""O1 DI!!E"ENCE
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VSBEC DE Lab Manual
,-%ap for DI!!E"ENCE:

DI!!E"ENCE . A/$ 0 A$/
,-%ap for $O""O1:
$O""O1 . A/$
5repared b%8 9.9-amaraimanalan. A5'ECE 1/
VSBEC DE Lab Manual
)OIC DIA"A%:
!#)) S#$T"ACTO"
!#)) S#$T"ACTO" #SIN T1O 'A)! S#$T"ACTO":
T"#T' TA$)E:
A $ C $O""O1 DI!!E"ENCE
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VSBEC DE Lab Manual
,-%ap for Differen2e:
Differen2e . A/$/C 0 A/$C/ 0 A$/C/ 0 A$C
,-%ap for $orro3:
$orro3 . A/$ 0 $C 0 A/C
P"OCEED#"E:
i! Connections are given as per circuit diagram.
ii! Logical inputs are given as per circuit diagram.
iii! 3bserve t-e output and verif% t-e trut- table.
5repared b%8 9.9-amaraimanalan. A5'ECE 12
VSBEC DE Lab Manual
"ES#)T:
9-us -alf adder4 full adder4 -alf subtractor and full subtractor
circuits 2ere designed using logic gates and t-eir trut- table 2ere verified.
5repared b%8 9.9-amaraimanalan. A5'ECE 1$
VSBEC DE Lab Manual
EXPT NO. : DESIN AND I%P)E%ENTATION O! CODE CON4E"TO"S
DATE :
AI%:
9o design and implement &#bit
i! Binar% to gra% code converter
ii! =ra% to binar% code converter
iii! BCD to e"cess#$ code converter
iv! E"cess#$ to BCD code converter
APPA"AT#S "E&#I"ED:
Sl.:o. C3M53:E:9 S5EC(6(CA9(3: ;9<.
1. >#30 =A9E (C )&*, 1
2. A:D =A9E (C )&/* 1
$. 30 =A9E (C )&$2 1
&. :39 =A9E (C )&/& 1
+. (C 90A(:E0 ?(9 # 1
,. 5A9C7 C30DS # $+
T'EO"(:
9-e availabilit% of large variet% of codes for t-e same discrete
elements of information results in t-e use of different codes b% different
s%stems. A conversion circuit must be inserted bet2een t-e t2o s%stems if
eac- uses different codes for same information. 9-us4 code converter is a
circuit t-at ma.es t-e t2o s%stems compatible even t-oug- eac- uses
different binar% code.
9-e bit combination assigned to binar% code to gra% code. Since eac-
code uses four bits to represent a decimal digit. 9-ere are four inputs and
four outputs. =ra% code is a non#2eig-ted code.
9-e input variable are designated as B$4 B24 B14 B/ and t-e output
variables are designated as C$4 C24 C14 Co. from t-e trut- table4
5repared b%8 9.9-amaraimanalan. A5'ECE 1&
VSBEC DE Lab Manual
combinational circuit is designed. 9-e Boolean functions are obtained from
?#Map for eac- output variable.
A code converter is a circuit t-at ma.es t-e t2o s%stems compatible
even t-oug- eac- uses a different binar% code. 9o convert from binar% code
to E"cess#$ code4 t-e input lines must suppl% t-e bit combination of
elements as specified b% code and t-e output lines generate t-e
corresponding bit combination of code. Eac- one of t-e four maps represents
one of t-e four outputs of t-e circuit as a function of t-e four input variables.
A t2o#level logic diagram ma% be obtained directl% from t-e Boolean
e"pressions derived b% t-e maps. 9-ese are various ot-er possibilities for a
logic diagram t-at implements t-is circuit. :o2 t-e 30 gate 2-ose output is
CCD -as been used to implement partiall% eac- of t-ree outputs.
)OIC DIA"A%:
$INA"( TO "A( CODE CON4E"TO"
,-%ap for
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VSBEC DE Lab Manual

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T"#T' TA$)E:
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"A( CODE TO $INA"( CON4E"TO"
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VSBEC DE Lab Manual
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VSBEC DE Lab Manual
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T"#T' TA$)E:
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VSBEC DE Lab Manual
)OIC DIA"A%:
$CD TO EXCESS-5 CON4E"TO"
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VSBEC DE Lab Manual
,-%ap for E
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VSBEC DE Lab Manual
T"#T' TA$)E:
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VSBEC DE Lab Manual
)OIC DIA"A%:
EXCESS-5 TO $CD CON4E"TO"
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VSBEC DE Lab Manual
,-%ap for A:
A . X+ X6 0 X5 X= X+
,-%ap for $:
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VSBEC DE Lab Manual

,-%ap for C:
,-%ap for D:
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VSBEC DE Lab Manual
T"#T' TA$)E:
7 E;2ess < 5 Inp8t 7 $CD O8tp8t 7
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P"OCED#"E:
5repared b%8 9.9-amaraimanalan. A5'ECE 2)
VSBEC DE Lab Manual
i! Connections 2ere given as per circuit diagram.
ii! Logical inputs 2ere given as per trut- table
iii! 3bserve t-e logical output and verif% 2it- t-e trut- tables.
"ES#)T:
9-us t-e code convertors circuits 2ere designed using logic gates and
t-eir trut- table 2ere verified.
EXPT NO. : DESIN O! =-$IT ADDE" AND S#$T"ACTO"
5repared b%8 9.9-amaraimanalan. A5'ECE 2*
VSBEC DE Lab Manual
DATE :
AI%:
9o design and implement &#bit adder and subtractor using (C )&*$.
APPA"AT#S "E&#I"ED:
Sl.:o. C3M53:E:9 S5EC(6(CA9(3: ;9<.
1. (C (C )&*$ 1
2. E>#30 =A9E (C )&*, 1
$. :39 =A9E (C )&/& 1
$. (C 90A(:E0 ?(9 # 1
&. 5A9C7 C30DS # &/
T'EO"(:
= $IT $INA"( ADDE":
A binar% adder is a digital circuit t-at produces t-e arit-metic sum of
t2o binar% numbers. (t can be constructed 2it- full adders connected in
cascade4 2it- t-e output carr% from eac- full adder connected to t-e input
carr% of ne"t full adder in c-ain. 9-e augends bits of @AA and t-e addend bits
of @BA are designated b% subscript numbers from rig-t to left4 2it- subscript
/ denoting t-e least significant bits. 9-e carries are connected in c-ain
t-roug- t-e full adder. 9-e input carr% to t-e adder is C
/
and it ripples
t-roug- t-e full adder to t-e output carr% C
&
.
= $IT $INA"( S#$T"ACTO":
9-e circuit for subtracting A#B consists of an adder 2it- inverters4
placed bet2een eac- data input @BA and t-e corresponding input of full
adder. 9-e input carr% C
/
must be eDual to 1 2-en performing subtraction.
= $IT $INA"( ADDE"/S#$T"ACTO":
5repared b%8 9.9-amaraimanalan. A5'ECE 21
VSBEC DE Lab Manual
9-e addition and subtraction operation can be combined into one
circuit 2it- one common binar% adder. 9-e mode input M controls t-e
operation. E-en MF/4 t-e circuit is adder circuit. E-en MF14 it becomes
subtractor.
= $IT $CD ADDE":
Consider t-e arit-metic addition of t2o decimal digits in BCD4
toget-er 2it- an input carr% from a previous stage. Since eac- input digit
does not e"ceed 14 t-e output sum cannot be greater t-an 114 t-e 1 in t-e sum
being an input carr%. 9-e output of t2o decimal digits must be represented
in BCD and s-ould appear in t-e form listed in t-e columns.
ABCD adder t-at adds 2 BCD digits and produce a sum digit in BCD.
9-e 2 decimal digits4 toget-er 2it- t-e input carr%4 are first added in t-e top
& bit adder to produce t-e binar% sum.
PIN DIA"A% !O" IC >=?5:
)OIC DIA"A%:
=-$IT $INA"( ADDE"
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VSBEC DE Lab Manual
)OIC DIA"A%:
=-$IT $INA"( S#$T"ACTO"
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VSBEC DE Lab Manual
)OIC DIA"A%:
=-$IT $INA"( ADDE"/S#$T"ACTO"
5repared b%8 9.9-amaraimanalan. A5'ECE $2
VSBEC DE Lab Manual
5repared b%8 9.9-amaraimanalan. A5'ECE $$
VSBEC DE Lab Manual
T"#T' TA$)E:
5repared b%8 9.9-amaraimanalan. A5'ECE $&
Inp8t Data A Inp8t Data $ Addition S8btra2tion
A= A5 A6 A+ $= $5 $6 $+ C S= S5 S6 S+ $ D= D5 D6 D+
+ * * * * * + * * + * + * + * + + *
+ * * * + * * * + * * * * + * * * *
* * + * + * * * * + * + * * + * + *
* * * + * + + + * + * * * * + * + *
+ * + * + * + + + * * + * * + + + +
+ + + * + + + + + + * + * * + + + +
+ * + * + + * + + * + + + * + + * +
VSBEC DE Lab Manual
)OIC DIA"A%:
$CD ADDE"
, %AP
( . S= 9S5 0 S6:
5repared b%8 9.9-amaraimanalan. A5'ECE $+
VSBEC DE Lab Manual
T"#T' TA$)E:
$CD S#% CA""(
S= S5 S6 S+ C
* * * * *
* * * + *
* * + * *
* * + + *
* + * * *
* + * + *
* + + * *
* + + + *
+ * * * *
+ * * + *
+ * + * +
+ * + + +
+ + * * +
+ + * + +
+ + + * +
+ + + + +
P"OCED#"E:
i! Connections 2ere given as per circuit diagram.
ii! Logical inputs 2ere given as per trut- table
iii! 3bserve t-e logical output and verif% 2it- t-e trut- tables.
"ES#)T:
9-us t-e & bit binar% adder4 & bit binar% subtractor and BCD adder
2ere designed using logic gates and t-eir trut- table 2as verified.
5repared b%8 9.9-amaraimanalan. A5'ECE $,
VSBEC DE Lab Manual
EXPT NO. : DESIN AND I%P)E%ENTATION O! %ANIT#DE
CO%PA"ATO"
DATE :
AI%:
9o design and implement
i! 2 G bit magnitude comparator using basic gates.
ii! * G bit magnitude comparator using (C )&*+.
APPA"AT#S "E&#I"ED:
Sl.:o. C3M53:E:9 S5EC(6(CA9(3: ;9<.
1. A:D =A9E (C )&/* 2
2. >#30 =A9E (C )&*, 1
$. 30 =A9E (C )&$2 1
&. :39 =A9E (C )&/& 1
+. &#B(9 MA=:(9HDE
C3M5A0A930
(C )&*+ 2
,. (C 90A(:E0 ?(9 # 1
). 5A9C7 C30DS # $/
T'EO"(:
9-e comparison of t2o numbers is an operator t-at determine one
number is greater t-an4 less t-an or! eDual to t-e ot-er number. A
magnitude comparator is a combinational circuit t-at compares t2o numbers
A and B and determine t-eir relative magnitude. 9-e outcome of t-e
comparator is specified b% t-ree binar% variables t-at indicate 2-et-er AIB4
AFB or! AJB.
5repared b%8 9.9-amaraimanalan. A5'ECE $)
VSBEC DE Lab Manual
A F A
$
A
2
A
1
A
/

B F B
$
B
2
B
1
B
/

9-e eDualit% of t-e t2o numbers and B is displa%ed in a
combinational circuit designated b% t-e s%mbol AFB!.
9-is indicates A greater t-an B4 t-en inspect t-e relative magnitude of
pairs of significant digits starting from most significant position. A is / and
t-at of B is /.
Ee -ave AJB4 t-e seDuential comparison can be e"panded as
AIB F A$B
$
1
C >
$
A
2
B
2
1
C >
$
>
2
A
1
B
1
1
C >
$
>
2
>
1
A
/
B
/
1
AJB F A
$
1
B
$
C >
$
A
2
1
B
2
C >
$
>2A
1
1
B
1
C >
$
>
2
>
1
A
/
1
B
/

9-e same circuit can be used to compare t-e relative magnitude of
t2o BCD digits.
E-ere4 A F B is e"panded as4
A F B F A
$
C B
$
! A
2
C B
2
! A
1
C B
1
! A
/
C B
/
!

"
$
"
2
"
1
"
/

5repared b%8 9.9-amaraimanalan. A5'ECE $*
VSBEC DE Lab Manual
)OIC DIA"A%:
6 $IT %ANIT#DE CO%PA"ATO"
5repared b%8 9.9-amaraimanalan. A5'ECE $1
VSBEC DE Lab Manual
, %AP
5repared b%8 9.9-amaraimanalan. A5'ECE &/
VSBEC DE Lab Manual
T"#T' TA$)E
5repared b%8 9.9-amaraimanalan. A5'ECE &1
VSBEC DE Lab Manual
A+ A* $+ $* A @ $ A . $ A A $
* * * * * + *
* * * + * * +
* * + * * * +
* * + + * * +
* + * * + * *
* + * + * + *
* + + * * * +
* + + + * * +
+ * * * + * *
+ * * + + * *
+ * + * * + *
+ * + + * * +
+ + * * + * *
+ + * + + * *
+ + + * + * *
+ + + + * + *
PIN DIA"A% !O" IC >=?B:
5repared b%8 9.9-amaraimanalan. A5'ECE &2
VSBEC DE Lab Manual
)OIC DIA"A%:
? $IT %ANIT#DE CO%PA"ATO"
5repared b%8 9.9-amaraimanalan. A5'ECE &$
VSBEC DE Lab Manual
T"#T' TA$)E:
A $ A@$ A.$ AA$
* * * * * * * * * * * * * * * * * + *
* * * + * * * + * * * * * * * * + * *
* * * * * * * * * * * + * * * + * * +
P"OCED#"E:
i! Connections are given as per circuit diagram.
ii! Logical inputs are given as per circuit diagram.
5repared b%8 9.9-amaraimanalan. A5'ECE &&
VSBEC DE Lab Manual
iii! 3bserve t-e output and verif% t-e trut- table.
"ES#)T:
9-us t-e magnitude comparator circuit 2as designed using logic gates
and t-eir trut- table 2as verified.
EXPT NO. : +C $IT ODD/E4EN PA"IT( C'EC,E" /ENE"ATO"
DATE :
AI%:
9o design and implement 1, bit odd'even parit% c-ec.er generator
using (C )&1*/.
5repared b%8 9.9-amaraimanalan. A5'ECE &+
VSBEC DE Lab Manual
APPA"AT#S "E&#I"ED:
Sl.:o. C3M53:E:9 S5EC(6(CA9(3: ;9<.
1. :39 =A9E (C )&/& 1
1. (C )&1*/ 2
2. (C 90A(:E0 ?(9 # 1
$. 5A9C7 C30DS # $/
T'EO"(:
A parit% bit is used for detecting errors during transmission of binar%
information. A parit% bit is an e"tra bit included 2it- a binar% message to
ma.e t-e number is eit-er even or odd. 9-e message including t-e parit% bit
is transmitted and t-en c-ec.ed at t-e receiver ends for errors. An error is
detected if t-e c-ec.ed parit% bit doesnAt correspond to t-e one transmitted.
9-e circuit t-at generates t-e parit% bit in t-e transmitter is called a @parit%
generatorA and t-e circuit t-at c-ec.s t-e parit% in t-e receiver is called a
@parit% c-ec.erA.
(n even parit%4 t-e added parit% bit 2ill ma.e t-e total number is even
amount. (n odd parit%4 t-e added parit% bit 2ill ma.e t-e total number is odd
amount. 9-e parit% c-ec.er circuit c-ec.s for possible errors in t-e
transmission. (f t-e information is passed in even parit%4 t-en t-e bits
reDuired must -ave an even number of 1As. An error occur during
transmission4 if t-e received bits -ave an odd number of 1As indicating t-at
one bit -as c-anged in value during transmission.
PIN DIA"A% !O" IC >=+?*:
5repared b%8 9.9-amaraimanalan. A5'ECE &,
VSBEC DE Lab Manual
!#NCTION TA$)E:
INP#TS O#TP#TS
N8mber of 'iDh Data
Inp8ts 9I* < I>:
PE PO EE KO
E4EN + * + *
ODD + * * +
E4EN * + * +
ODD * + + *
X + + * *
X * * + +
)OIC DIA"A%:
+C $IT ODD/E4EN PA"IT( C'EC,E"
5repared b%8 9.9-amaraimanalan. A5'ECE &)
VSBEC DE Lab Manual
T"#T' TA$)E:
I> IC IB I= I5 I6 I+ I* I>/IC/IB/I=/I5/I6/++/ I*/ A2tiFe EE EO
* * * * * * * + * * * * * * * * + + *
* * * * * + + * * * * * * + + * * + *
* * * * * + + * * * * * * + + * + * +
)OIC DIA"A%:
+C $IT ODD/E4EN PA"IT( ENE"ATO"
5repared b%8 9.9-amaraimanalan. A5'ECE &*
VSBEC DE Lab Manual
T"#T' TA$)E:
I> IC IB I= I5 I6 I+ I* I> IC IB I= I5 I6 I+ I* A2tiFe EE EO
+ + * * * * * * + + * * * * * * + + *
+ + * * * * * * + + * * * * * * * * +
+ + * * * * * * * + * * * * * * * + *
P"OCED#"E:
i! Connections are given as per circuit diagram.
ii! Logical inputs are given as per circuit diagram.
5repared b%8 9.9-amaraimanalan. A5'ECE &1
VSBEC DE Lab Manual
iii! 3bserve t-e output and verif% t-e trut- table.
"ES#)T:
9-us t-e parit% c-ec.er and parit% generator circuit 2as designed
using logic gates and t-eir trut- table 2as verified.
EXPT NO. : DESIN AND I%P)E%ENTATION O! %#)TIP)EXE" AND
DE%#)TIP)EXE"
DATE :
AI%:
5repared b%8 9.9-amaraimanalan. A5'ECE +/
VSBEC DE Lab Manual
9o design and implement multiple"er and demultiple"er using logic
gates.
APPA"AT#S "E&#I"ED:
Sl.:o. C3M53:E:9 S5EC(6(CA9(3: ;9<.
1. $ ('5 A:D =A9E (C )&11 2
2. 30 =A9E (C )&$2 1
$. :39 =A9E (C )&/& 1
2. (C 90A(:E0 ?(9 # 1
$. 5A9C7 C30DS # $2
T'EO"(:
%#)TIP)EXE":
Multiple"er means transmitting a large number of information units
over a smaller number of c-annels or lines. A digital multiple"er is a
combinational circuit t-at selects binar% information from one of man% input
lines and directs it to a single output line. 9-e selection of a particular input
line is controlled b% a set of selection lines. :ormall% t-ere are 2
n
input line
and n selection lines 2-ose bit combination determine 2-ic- input is
selected.
DE%#)TIP)EXE":
9-e function of Demultiple"er is in contrast to multiple"er function. (t
ta.es information from one line and distributes it to a given number of
output lines. 6or t-is reason4 t-e demultiple"er is also .no2n as a data
distributor. Decoder can also be used as demultiple"er.
(n t-e 18 & demultiple"er circuit4 t-e data input line goes to all of t-e
A:D gates. 9-e data select lines enable onl% one gate at a time and t-e data
on t-e data input line 2ill pass t-roug- t-e selected gate to t-e associated
data output line.
5repared b%8 9.9-amaraimanalan. A5'ECE +1
VSBEC DE Lab Manual
$)OC, DIA"A% !O" =:+ %#)TIP)EXE":
!#NCTION TA$)E:
S+ S* INP#TS (
* * D* G D* S+/ S*/
* + D+ G D+ S+/ S*
+ * D6 G D6 S+ S*/
+ + D5 G D5 S+ S*
( . D* S+/ S*/ 0 D+ S+/ S* 0 D6 S+ S*/ 0 D5 S+ S*
CI"C#IT DIA"A% !O" %#)TIP)EXE":
5repared b%8 9.9-amaraimanalan. A5'ECE +2
VSBEC DE Lab Manual
T"#T' TA$)E:
S+ S* ( . O#TP#T
* * D*
* + D+
+ * D6
+ + D5
$)OC, DIA"A% !O" +:= DE%#)TIP)EXE":
5repared b%8 9.9-amaraimanalan. A5'ECE +$
VSBEC DE Lab Manual
!#NCTION TA$)E:
S+ S* INP#T
* * X G D* . X S+/ S*/
* + X G D+ . X S+/ S*
+ * X G D6 . X S+ S*/
+ + X G D5 . X S+ S*
( . X S+/ S*/ 0 X S+/ S* 0 X S+ S*/ 0 X S+ S*
)OIC DIA"A% !O" DE%#)TIP)EXE":
5repared b%8 9.9-amaraimanalan. A5'ECE +&
VSBEC DE Lab Manual
T"#T' TA$)E:
INP#T O#TP#T
S+ S* I/P D* D+ D6 D5
5repared b%8 9.9-amaraimanalan. A5'ECE ++
VSBEC DE Lab Manual
* * * * * * *
* * + + * * *
* + * * * * *
* + + * + * *
+ * * * * * *
+ * + * * + *
+ + * * * * *
+ + + * * * +
PIN DIA"A% !O" IC >=+B*:


PIN DIA"A% !O" IC >=+B=:
5repared b%8 9.9-amaraimanalan. A5'ECE +,
VSBEC DE Lab Manual
P"OCED#"E:
i! Connections are given as per circuit diagram.
ii! Logical inputs are given as per circuit diagram.
iii! 3bserve t-e output and verif% t-e trut- table.
"ES#)T:
9-us t-e multiple"er and de#multiple"er circuit 2as designed using
logic gates and t-eir trut- table 2as verified.
EXPT NO. : DESIN AND I%P)E%ENTATION O! ENCODE AND
DECODE"
5repared b%8 9.9-amaraimanalan. A5'ECE +)
VSBEC DE Lab Manual
DATE :
AI%:
9o design and implement encoder and decoder using logic gates.
APPA"AT#S "E&#I"ED:
Sl.:o. C3M53:E:9 S5EC(6(CA9(3: ;9<.
1. $ ('5 :A:D =A9E (C )&1/ 2
2. 30 =A9E (C )&$2 $
$. :39 =A9E (C )&/& 1
2. (C 90A(:E0 ?(9 # 1
$. 5A9C7 C30DS # 2)
T'EO"(:
ENCODE":
An encoder is a digital circuit t-at perform inverse operation of a
decoder. An encoder -as 2
n
input lines and n output lines. (n encoder t-e
output lines generates t-e binar% code corresponding to t-e input value. (n
octal to binar% encoder it -as eig-t inputs4 one for eac- octal digit and t-ree
output t-at generate t-e corresponding binar% code. (n encoder it is assumed
t-at onl% one input -as a value of one at an% given time ot-er2ise t-e circuit
is meaningless. (t -as an ambiguila t-at 2-en all inputs are Lero t-e outputs
are Lero. 9-e Lero outputs can also be generated 2-en D/ F 1.
DECODE":
A decoder is a multiple input multiple output logic circuit 2-ic-
converts coded input into coded output 2-ere input and output codes are
different. 9-e input code generall% -as fe2er bits t-an t-e output code. Eac-
input code 2ord produces a different output code 2ord i.e t-ere is one to one
mapping can be e"pressed in trut- table. (n t-e bloc. diagram of decoder
5repared b%8 9.9-amaraimanalan. A5'ECE +*
VSBEC DE Lab Manual
circuit t-e encoded information is present as n input producing 2
n
possible
outputs. 2
n
output values are from / t-roug- out 2
n
G 1.
PIN DIA"A% !O" IC >==B:
$CD TO DECI%A) DECODE":
PIN DIA"A% !O" IC >=+=>:
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VSBEC DE Lab Manual
)OIC DIA"A% !O" ENCODE":
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VSBEC DE Lab Manual
T"#T' TA$)E:
INP#T O#TP#T
(+ (6 (5 (= (B (C (> A $ C
+ * * * * * * * * +
* + * * * * * * + *
* * + * * * * * + +
* * * + * * * + * *
* * * * + * * + * +
* * * * * + * + + *
* * * * * * + + + +
)OIC DIA"A% !O" DECODE":
5repared b%8 9.9-amaraimanalan. A5'ECE ,1
VSBEC DE Lab Manual
T"#T' TA$)E:
INP#T O#TP#T
E A $ D* D+ D6 D5
+ * * + + + +
* * * * + + +
* * + + * + +
* + * + + * +
* + + + + + *
P"OCED#"E:
i! Connections are given as per circuit diagram.
5repared b%8 9.9-amaraimanalan. A5'ECE ,2
VSBEC DE Lab Manual
ii! Logical inputs are given as per circuit diagram.
iii! 3bserve t-e output and verif% t-e trut- table.
"ES#)T:
9-us t-e encoder and decoder circuit 2as designed using logic gates
and t-eir trut- table 2as verified.
EXPT NO. : CONST"#CTION AND 4E"I!ICATION O! = $IT
"IPP)E CO#NTE" AND %OD +*/%OD +6 "IPP)E CO#NTE"
DATE :
AI%:
5repared b%8 9.9-amaraimanalan. A5'ECE ,$
VSBEC DE Lab Manual
9o design and verif% & bit ripple counter mod 1/' mod 12 ripple
counter.
APPA"AT#S "E&#I"ED:
Sl.:o. C3M53:E:9 S5EC(6(CA9(3: ;9<.
1. M? 6L(5 6L35 (C )&), 2
2. :A:D =A9E (C )&// 1
$. (C 90A(:E0 ?(9 # 1
&. 5A9C7 C30DS # $/
T'EO"(:
A counter is a register capable of counting number of cloc. pulse
arriving at its cloc. input. Counter represents t-e number of cloc. pulses
arrived. A specified seDuence of states appears as counter output. 9-is is t-e
main difference bet2een a register and a counter. 9-ere are t2o t%pes of
counter4 s%nc-ronous and as%nc-ronous. (n s%nc-ronous common cloc. is
given to all flip flop and in as%nc-ronous first flip flop is cloc.ed b% e"ternal
pulse and t-en eac- successive flip flop is cloc.ed b% ; or ; output of
previous stage. A soon t-e cloc. of second stage is triggered b% output of
first stage. Because of in-erent propagation dela% time all flip flops are not
activated at same time 2-ic- results in as%nc-ronous operation.
PIN DIA"A% !O" IC >=>C:
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VSBEC DE Lab Manual
)OIC DIA"A% !O" = $IT "IPP)E CO#NTE":
5repared b%8 9.9-amaraimanalan. A5'ECE ,+
VSBEC DE Lab Manual
T"#T' TA$)E:
C), &A &$ &C &D
* * * * *
+ + * * *
6 * + * *
5 + + * *
= * * + *
B + * + *
C * + + *
> + + + *
? * * * +
H + * * +
+* * + * +
5repared b%8 9.9-amaraimanalan. A5'ECE ,,
VSBEC DE Lab Manual
++ + + * +
+6 * * + +
+5 + * + +
+= * + + +
+B + + + +
)OIC DIA"A% !O" %OD - +* "IPP)E CO#NTE":
T"#T' TA$)E:
C), &A &$ &C &D
* * * * *
+ + * * *
6 * + * *
5repared b%8 9.9-amaraimanalan. A5'ECE ,)
VSBEC DE Lab Manual
5 + + * *
= * * + *
B + * + *
C * + + *
> + + + *
? * * * +
H + * * +
+* * * * *
)OIC DIA"A% !O" %OD - +6 "IPP)E CO#NTE":
T"#T' TA$)E:
C), &A &$ &C &D
* * * * *
+ + * * *
6 * + * *
5 + + * *
= * * + *
B + * + *
C * + + *
> + + + *
? * * * +
H + * * +
+* * + * +
++ + + * +
5repared b%8 9.9-amaraimanalan. A5'ECE ,*
VSBEC DE Lab Manual
+6 * * * *
P"OCED#"E:
i! Connections are given as per circuit diagram.
ii! Logical inputs are given as per circuit diagram.
iii! 3bserve t-e output and verif% t-e trut- table.
"ES#)T:
9-us t-e & bit ripple counter and mod 1/ ripple counter circuit 2as
designed using logic gates and t-eir trut- table 2as verified.
5repared b%8 9.9-amaraimanalan. A5'ECE ,1
VSBEC DE Lab Manual
EXPT NO. : DESIN AND I%P)E%ENTATION O! 5 $IT S(NC'"ONO#S
#P AND DO1N CO#NTE"
DATE :
AI%:
9o design and implement $ bit s%nc-ronous up and do2n counter.
APPA"AT#S "E&#I"ED:
Sl.:o. C3M53:E:9 S5EC(6(CA9(3: ;9<.
1. M? 6L(5 6L35 (C )&), 2
2. $ ('5 A:D =A9E (C )&11 1
$. 30 =A9E (C )&$2 1
&. >30 =A9E (C )&*, 1
+. :39 =A9E (C )&/& 1
,. (C 90A(:E0 ?(9 # 1
). 5A9C7 C30DS # $+
T'EO"(:
A counter is a register capable of counting number of cloc. pulse
arriving at its cloc. input. Counter represents t-e number of cloc. pulses
arrived. An up'do2n counter is one t-at is capable of progressing in
increasing order or decreasing order t-roug- a certain seDuence. An up'do2n
counter is also called bidirectional counter. Hsuall% up'do2n operation of
t-e counter is controlled b% up'do2n signal. E-en t-is signal is -ig- counter
goes t-roug- up seDuence and 2-en up'do2n signal is lo2 counter follo2s
reverse seDuence.
5repared b%8 9.9-amaraimanalan. A5'ECE )/
VSBEC DE Lab Manual
)OIC DIA"A%:
T"#T' TA$)E:
C), &
A
&
$
&
C
&
N
* / / / /
+ / / / 1
6 / /
1
/
5 / /
1
1
= / 1 / /
B / 1 / 1
C / 1 1 /
> / 1 1 1
? 1 / / /
H 1 / / 1
+* 1 / 1 /
++ 1 / 1 1
+6 1 1 / /
+5 1 1
/
1
+= 1 1
1
/
+B 1 1 1 1
)OIC DIA"A% !O" DO1N CO#NTE"
5repared b%8 9.9-amaraimanalan. A5'ECE )1
VSBEC DE Lab Manual
T"#T' TA$)E
Clo2I O8tp8t
/ ////
1 ///1
2 //1/
$ //11
& /1//
+ /1/1
, /11/
) /111
* 1///
1 1//1
1/ 1/1/
11 1/11
12 11//
1$ 11/1
1& 111/
1+ 1111
P"OCED#"E:
5repared b%8 9.9-amaraimanalan. A5'ECE )2
VSBEC DE Lab Manual
i! Connections are given as per circuit diagram.
ii! Logical inputs are given as per circuit diagram.
iii! 3bserve t-e output and verif% t-e trut- table.
"ES#)T:
9-us Hp counter and Do2n counter 2as designed successfull% using
(C )&), and its trut- table 2as verified successfull%.
5repared b%8 9.9-amaraimanalan. A5'ECE )$
VSBEC DE Lab Manual
EXPT NO. : DESIN AND I%P)E%ENTATION O! S'I!T "EISTE"
DATE :
AI%:
9o design and implement
i! Serial in serial out
ii! Serial in parallel out
iii! 5arallel in serial out
iv! 5arallel in parallel out
APPA"AT#S "E&#I"ED:
Sl.:o. C3M53:E:9 S5EC(6(CA9(3: ;9<.
1. D 6L(5 6L35 (C )&)& 2
2. 30 =A9E (C )&$2 1
$. (C 90A(:E0 ?(9 # 1
&. 5A9C7 C30DS # $+
T'EO"(:
A register is capable of s-ifting its binar% information in one or bot-
directions is .no2n as s-ift register. 9-e logical configuration of s-ift
register consist of a D#6lip flop cascaded 2it- output of one flip flop
connected to input of ne"t flip flop. All flip flops receive common cloc.
pulses 2-ic- causes t-e s-ift in t-e output of t-e flip flop. 9-e simplest
possible s-ift register is one t-at uses onl% flip flop. 9-e output of a given
flip flop is connected to t-e input of ne"t flip flop of t-e register. Eac- cloc.
pulse s-ifts t-e content of register one bit position to rig-t.
PIN DIA"A%:
5repared b%8 9.9-amaraimanalan. A5'ECE )&
VSBEC DE Lab Manual
)OIC DIA"A%:
SE"IA) IN SE"IA) O#T:
T"#T' TA$)E:
5repared b%8 9.9-amaraimanalan. A5'ECE )+
VSBEC DE Lab Manual
C),
Serial in Serial o8t
+ + *
6 * *
5 * *
= + +
B X *
C X *
> X +
)OIC DIA"A%:
SE"IA) IN PA"A))E) O#T:
T"#T' TA$)E:
C), DATA
O#TP#T
&
A
&
$
&
C
&
D
+ + + * * *
6 * * + * *
5 * * * + +
= + + * * +
)OIC DIA"A%:
PA"A))E) IN SE"IA) O#T:
5repared b%8 9.9-amaraimanalan. A5'ECE ),
VSBEC DE Lab Manual
T"#T' TA$)E:
C), &5 &6 &+ &* O/P
* + * * + +
+ * * * * *
6 * * * * *
5 * * * * +
)OIC DIA"A%:
PA"A))E) IN PA"A))E) O#T:
T"#T' TA$)E:
C),
DATA INP#T O#TP#T
D
A
D
$
D
C
D
D
&
A
&
$
&
C
&
D
5repared b%8 9.9-amaraimanalan. A5'ECE ))
VSBEC DE Lab Manual
+ + * * + + * * +
6 + * + * + * + *
P"OCED#"E:
i! Connections are given as per circuit diagram.
ii! Logical inputs are given as per circuit diagram.
iii! 3bserve t-e output and verif% t-e trut- table.
"ES#)T:
9-us t-e various s-ift registers 2ere designed successfull% using flip#
flops and t-eir trut- tables 2ere verified successfull%.
EXPT NO. : DESIN AND SI%#)ATION O! CO%$INATIONA) AND
SE&#ENTIA) CI"C#ITS
DATE :
5repared b%8 9.9-amaraimanalan. A5'ECE )*
VSBEC DE Lab Manual
AI%:
9o design and simulate
i! Adder and Subtractor
ii! Multiple"er and De#multiple"er
iii! 0ipple counter
iv! S-ift registers
TOO)S "E&#I"ED
>(L(:> Soft2are
Modelsim simulator
P"OCED#"E
Erite and dra2 t-e Digital logic s%stem.
Erite t-e Verilog 7DL code for above s%stem.
3pen proNect navigator
Select 6ile :e2 proNect
=ive t-e file name and press ne"t
=ive t-e entit% name and select Verilog 7DL module and press ne"t
=ive t-e inputs and outputs and specif% input or output or in#out and
select ne"t
9-en give finis- and t-e entit% and t-e arc-itecture details appear b%
itself
Enter t-e Verilog 7DL code in after arc-itecture.
C-ec. t-e s%nta" and simulate t-e above Verilog 7DL code using
ModelSim or >ilin"! and verif% t-e output 2aveform as obtained.
Verif% t-e grap- 2it- t-e trut- table
P"O"A%
'A)! ADDE"
5repared b%8 9.9-amaraimanalan. A5'ECE )1
VSBEC DE Lab Manual
module -alfOadderinO"4 inO%4 outOsum4 outOcarr%!B
input inO"B
input inO%B
output outOsumB
output outOcarr%B
"or outOsum4 inO"4 inO%!B
and outOcarr%4 inO"4 inO%!B
end moduleB
!#)) ADDE"
module fullOadder"4 %4 L4 sum4 carr%!B
input "B
input %B
output sumB
output carr%B
2ire a4 b4 cB
"or sum4 "4 %4 L!B
and a4 "4 %!B
and b4 %4 L!B
and c4 L4 "!B
or carr%4 a4 b4 c!B
end moduleB
'A)! S#$T"ACTO"
module -alfOsubtractor "4 %4 diff4 borro2!B
input "B
5repared b%8 9.9-amaraimanalan. A5'ECE */
VSBEC DE Lab Manual
input %B
output diffB
output borro2B
2ire %barB
not %bar4 %!B
"or diff4 "4 %!B
and borro24 "4 %bar!B
end moduleB
%#)TIP)EXE"
module mu"O& to 1 %4 (14 (24 ($4 (&4 S/4 S1!B
input (14 (24 ($4 (&4 S/4 S1B
output %B
2ire S1bar4 S/bar4 a4 b4 c4 dB
not S1bar4 S1!B
not S/bar4 S/!B
and a4 S1bar4 S/bar4 (1!B
and b4 S1bar4 S/4 (2!B
and c4 S14 S/bar4 ($!B
and d4 S14 S/4 (&!B
or %4 a4 b4 c4 d!B
end moduleB
DE-%#)TIP)EXE"
module mu"O& to 1 <14 <24 <$4 <&4 (4 S/4 S1!B
input (4 S/4 S1B
5repared b%8 9.9-amaraimanalan. A5'ECE *1
VSBEC DE Lab Manual
output <14 <24 <$4 <&B
2ire S1bar4 S/barB
not S1bar4 S1!B
not S/bar4 S/!B
and <14 S1bar4 S/bar4 (!B
and <24 S1bar4 S/4 (!B
and <$4 S14 S/bar4 (!B
and <&4 S14 S/4 (!B
or %4 a4 b4 c4 d!B
end moduleB
"IPP)E CO#NTE"
module counter count4 load4 in4 cl.4 clr4 a4 c!B
input count4 load4 cl.4 clrB
input P$8/Q inB
output cB
output P$8/Q aB
reg P$8/Q aB
assign c F count R Sload R a F F &Ab1111!B
al2a%s T posedge CL? or negedge clr!
if Sclr! A F &Ab////B
else if load! a F inB
else if count! a F a C 1Ab1B
else a F aB
end moduleB
SISO S'I!T "EISTE"
module s-ift cl.4 SE4 S(4 S3!B
input SE4 S(B
output S3B
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VSBEC DE Lab Manual
reg P$8/Q tempB
al2a%s T posedge cl.!
begin
if SE!
begin
temp F temp JJ 1B
tempP/Q F S(B
endB
begin
assign S3 F temp P$QB
end moduleB
SIPO S'I!T "EISTE"
module s-ift cl.4 SE4 S(4 53!B
input SE4 S(B
output 53 P$8/QB
reg P$8/Q tempB
al2a%s T posedge cl.!
begin
if SE!
begin
temp F Utemp P28/Q4 S(VB
endB
begin
assign 53 F tempB
end moduleB
5repared b%8 9.9-amaraimanalan. A5'ECE *$
VSBEC DE Lab Manual
"ES#)T:
9-us t-e simulation of adders4 subtractors4 multiple"er4 de#
multiple"er4 ripple counter4 s-ift registers using >(L(:> soft2are and
simulated t-eir circuit using modelsim simulator.
5repared b%8 9.9-amaraimanalan. A5'ECE *&