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A Symmetric Diagonal Driver Transistor SRAM Cell
with Imbalance Suppression Technology for Stable Low Voltage Operation
S . Horiba, T. Takahashi, H. Ohkubo, K. Noda, F. Hayashi, T. Uchida
T. Yokoyama, K. Ando, T. Yoshida, T. Hashimoto and T. Shimizu
ULSI Device Development Laboratories, NEC Corporation
1120. Shimokuzawa, Sagamihara, Kanagawa 229, Japan

Abstract easily formed even on a planarized interlayer dielectric. The


A symmetiic diagonal driver transistor (SDDT) cell has been resistance of a 0.3vm bit-line contact could be reduced to one-
dcveloped for low voltage SRAM operation which exhibits high seventh of that of a polysilicon pad contact [4],as shown in Fig.4.
alignment tolerance. This new symmetric cell layout substantially By fully planaiizing the g r o u n d - h e , as shown in Fig.5, the ground-
suppresses the imbalance in a pair of cell transistor characteristics line resistance could be reduced to 24 CLkell, which is one-third of
and, combined with silicon nitiide self-aligned contact (Si?N,-SAC) that with no planarization.
and low rcsistance groond-line structures, results in a minimum
operation voltage of 1.9V, which is 0.3V lower than that of the Transistor characteristics
conventional split word line cell. The resistance of the ground-line, which is connected to the
source of the driver transistor, strongly affects the drain current
Introduction difference between a pair of driver transistors in a cell (AId), as
As the supply voltage (Vcc) decreases in high density SRAMs, shown in Fig.6. The low ground-line resistance of 24 CL/cell,
the imbalance in a pair of ccll transistors becomes a serious problem attained as a rcsult of the mesh ground-line and interlayer dielectric
for stable low voltage operation. In order to reduce this problem, planarization, can reduce A I d down to 3pA. Figure 7 shows the
several split word-line :SRAM cell structures have been proposed measured A I d for three types of cell structures with 0 . l p m offset
[ 1,2]. Thesc technologies can theoretically balance the alignment. The average value of A I d decreases by one half upon
characteristics in a pair of ccll transistors through symmetrical changing the layout from the conventional cell to the SDDT cell
pattern layout. They cannot. however, prevent the imbalance caused because of its large alignment margin. Moreover, the average value
by channcl area pattern deformation due to lithographic of A Id becomes almost zero by adopting the Si3N4-SAC
misalignmcnt bctwecn the active region and gate electrodes. In technology in addition to the SDDT layout. This can be attributed to
addition, misalignment of a contact hole with respect to the gate the reduction of the source resistance imbalance, because the
electrode and a large grlound-line resistance can further increase the distance from the gate edge to the g r o u n d - h e contact hole is
electrical characteristics imbalance between a pair of cell transistors. defined by the thickness of the sidewall spacers in the SAC
In this work. a new symmetric layout cell having high technology.
misalignment tolerance 'combined with Si3N4-SACand low ground- Memory cell stability
line resistance technologies is proposed for high speed and stable In order to estimate the efficiency of the above-mentioned layout
low voltage SRAM operation. and technologies for cell stability, the static noise margin (S.N.M.)
was simulated, as shown in Fig.8. When the minimum operation
Memory cell layout voltage (Vcc,,) is defined as the supply voltage at S.N.M.=OV,
Figure I shows layouts of (a) a conventional split word-line cell Vcc,, of the SDDT cell with SAC and low resistance ground-line
[11 and (b) the SDDT cell designed with 0.3pm rule. In the split structures is 0.3V lower than that of the conventional cell. Figure 9
word-line cell, when misalignment occurs between the gate shows the dependence of fail bit number on Vcc measured in the
electrodes and the active region patterns, as depicted with the 64Kbit test SRAMs. For the conventional cell, fail bits appear at
dashcd lines in Fig.1, the channcl area of one of the pair of driver Vcc=2.2V and increase gradually with decreasing Vcc. On the other
transistors changes. This causes an imbalance between the transistor hand, Fail bits for the SDDT cell with SAC and low resistance
pair. On thc othcr hand, the channel area in the SDDT cell docs not technologies increase sharply at Vcc=1.9V. Thus in the case of
change within 0.2pm misalignment, which is sufficiently large for Vcc=2.5V. the SDDT technology provides a wider voltage margin
the alignment accuracy of optical lithography. In the SDDT cell, the for stable operation.
bit line length is 16% shorter and the bit line pitch is 2 0 8 wider than
those of the split word line cell in almost the same cell area. As a Conclusions
rcsult, thc bit-line resistance and the bit-line to bit-line capacitance An SDDT cell with high alignment tolerance has been developed
can be reduced by 16% and 4 5 8 . respectively. for low voltage SRAM operation. The SDDT cell with Si3N4-SAC
and low resistance ground-line technologies has demonstrated
Process technology effective suppression of the imbalance in a pair of cell transistor
64Kbit test SRAMs have been fabricated using 3-level poly and characteristics. Stable low voltage operation has been confirmed
2-level aluminum wirings and 0.3pm CMOS technology. The first through electrical tests of a 64Kbit SRAM. This SDDT cell
polycide layer is used for the MOSFET gate electrode. The second tcchnology is promising for low voltage and high speed SRAMs
polycide layer is used for the g r o u n d - h e . The third polysilicon layer with high process-fluctuation immunity.
is employed as the high-resistance load and the Vcc linc. The bit-line
contact is filled with a tungsten plug. Figure 2 is a plane view SEM Acknowledgment
photograph showing tlhe SDDT cell after polycide gate electrode The authors would like to thank Drs. M. Kamoshida, K. Okada,
formation. N. Endo, S. Ohya, N. Kasai and J. M. Drynan for their continuous
The Si3N4-SACtechnology has been adapted to both the ground- encouragement and helpful discussions, and Messrs. H. Kawamoto
linc contact and thc bit-line contact which can eliminate the source and T. Shinmura for their contribution to device fabrication.
or drain resistance fluctuation caused by the misalignment. Figure 3 References
shows a cross-sectional SEM photograph of the Si3N4-SAC [l] H.Ohkub et al., TEDM Tech.Dig., p.481(1991)
structure. Thc top and sides of the gate electrode were covered with 121 K.1tahashi et al., IEDM Tech.Dig., p.477(1991)
a Si3N4 film. followed by high SiOz:Si3N, selectivity etching [3]. [3] K. Harashima et al., hoc. Symp. on Dry Process, p. 247(1994)
With this technology, the bit-line and ground-line contacts can be 141T.Yamanaka et al., IEDM Tech.Dig.,p.477(1990)

144 0-7803-3342-X:/96/$5.0001996 IEEE 1996 Symposium on VLSl Technology Digest of Technical Papers

Authorized licensed use limited to: University of Central Florida. Downloaded on October 26, 2008 at 00:13 from IEEE Xplore. Restrictions apply.
---without misalignment Mesh ground-line
I n

B i t-1 ine 1.Opm


(a) (b) Fig 2 A plane view SEM photograph showing
Fig. 1 Cell layouts. (a) the conventional split xvord-line cell and the SDDT cell after gate electrode formation.
(b) the SDDT cell.

D o plysilicon pad conlac


5 600
1
c? 400
m
$ 200
0

0
02 03 04 05 06 7
Contact Size (vm)

(a) O5pm (b) O 5 p Fig. 4 Dependence of bit-line contact


Fig 3 Cross scctional SEM photographs showing features of (a) ground- resistance on bit-line contact diameter for
line contact opening and (b) a bit-line contact with tungsten plug Si3N4 SAC and polysilicon pad contacts.

I I I J
15 - - Driver transistor -
0 Accesstianslstor -
10 I
0 -
9 !
5
A
:
- 0
51
-10 -
- - I

-15 -
-20 I I I

O.5pni Fig. 7 Drain current difference,AId, between pair transistors in a


Fig' ' Cross-sectional
SDDT cell along the bit-line.
photograph Of the
cell. for three types of cell structures. The gate electrode pattem is
aligned to the active area nith 0 . l p m offset. Dots indicate averaged
values of45 dice/wafer.

40 , , . , . 100000

.
SDDTcelltSAC
A SDDTceIl+SAC 10000 grwnd line
cM"e"fl0nal cell

2 100
L

10

Ground-line resistance ( Q k e l l )
w-4 Supply voltage (V)
15 2
Supply voltage (V)
25

Fig 6 Relationship betwcen AId and Fig 8 Dependence of static noise margin Fig. 9 Dependence of faif bit number
ground-line resistance Solid line S.N M. for three t y e s of cell structures on on Vcc, measured in 64Kbit test
indicates simulated data by SPICE VCC. simulated by SPICE [ground-line SRAMs.
and dots are measured data. resistance= 0 : 24 62 /cell. ~ > m80 : Q /cell]

1996 Symposium on VLSl Technology Digest of Technical Papers 145

Authorized licensed use limited to: University of Central Florida. Downloaded on October 26, 2008 at 00:13 from IEEE Xplore. Restrictions apply.